## @file
#
#  Copyright (c) 2021-2022, Rockchip Limited. All rights reserved.
#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
#
#  SPDX-License-Identifier: BSD-2-Clause-Patent
#
##

[Defines]
  DEC_SPECIFICATION              = 0x00010005
  PACKAGE_NAME                   = RockchipPkg
  PACKAGE_GUID                   = 633b6754-2c95-11ec-b78c-f42a7dcb925d
  PACKAGE_VERSION                = 0.1

[Includes]
  Include

[Protocols]
  gUniNorFlashProtocolGuid = { 0x86F305EA, 0xDFAC, 0x4A6B, { 0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA } }
  gRockchipI2cDemoProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b } }
  gRk860xRegulatorProtocolGuid = { 0xb9ef9018, 0x2096, 0x4bf5, { 0x94, 0xb2, 0x70, 0x32, 0xb9, 0xa9, 0xa4, 0x29 } }
  gRockchipCrtcProtocolGuid = { 0xC128406A, 0x99D9, 0x11EC, { 0x99, 0x27, 0xF4, 0x2A, 0x7D, 0xCB, 0x92, 0x5D } }
  gRockchipConnectorProtocolGuid = { 0x50439CB6, 0x9B85, 0x11EC, { 0x95, 0x73, 0xF4, 0x2A, 0x7D, 0xCB, 0x92, 0x5D } }
  gOhciDeviceProtocolGuid = { 0x54bce5e6, 0xbaae, 0x488a, { 0x82, 0x67, 0xc0, 0x85, 0x7f, 0xb4, 0xe8, 0x05 } }
  gRockchipI2cMasterProtocolGuid = { 0x7b4af789, 0x43d2, 0x44a5, { 0xa0, 0xb3, 0x3f, 0xa5, 0xde, 0xd7, 0xa1, 0x27 } }
  gRockchipPlatformConfigAppliedProtocolGuid = { 0xdf0e9b10, 0xcbd6, 0x496f, { 0x83, 0xd6, 0xef, 0xbb, 0x96, 0x9c, 0xe5, 0x3d } }
  gDpPhyProtocolGuid = { 0xb4bcf881, 0xc8b3, 0x46d7, { 0xaf, 0xbe, 0x5a, 0x2d, 0x94, 0x9d, 0x93, 0xc3 } }
  gPca95xxProtocolGuid = { 0x7e91391b, 0xa23c, 0x4a51, { 0x9d, 0xf7, 0xf6, 0x74, 0xef, 0x1d, 0x51, 0x1b } }
  gRockchipDsiPanelProtocolGuid = { 0x07a5d05c, 0x3216, 0x49fc, { 0xb4, 0x22, 0x28, 0x9d, 0x38, 0xd5, 0xdf, 0x7e } }

[Guids]
  gRockchipTokenSpaceGuid = { 0xc620b83a, 0x3175, 0x11ec, { 0x95, 0xb4, 0xf4, 0x2a, 0x7d, 0xcb, 0x92, 0x5d } }
  gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } }
  gShellI2cDemoHiiGuid = { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce, 0x7b, 0x91, 0x7f, 0x5f, 0x2f } }
  gRockchipEventResetGuid = { 0x4ecbd617, 0xc2a6, 0x4d4c, { 0x80, 0x4e, 0x53, 0x38, 0x3b, 0x98, 0x7d, 0x75 } }
  gRockchipEventPlatformBmAfterConsoleGuid = { 0xf1272c11, 0xb418, 0x40ca, { 0x88, 0x26, 0x11, 0x94, 0xd7, 0xb7, 0x30, 0x4a } }

[PcdsFixedAtBuild]
  gRockchipTokenSpaceGuid.PcdProcessorName|"Unknown"|VOID*|0x00000001
  gRockchipTokenSpaceGuid.PcdPlatformName|"Unknown"|VOID*|0x00000002
  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Unknown"|VOID*|0x00000003
  gRockchipTokenSpaceGuid.PcdBoardName|"Unknown"|VOID*|0x00000004
  gRockchipTokenSpaceGuid.PcdBoardVendorName|"Unknown"|VOID*|0x00000005
  gRockchipTokenSpaceGuid.PcdProductUrl|"Unknown"|VOID*|0x00000006
  gRockchipTokenSpaceGuid.PcdMemoryVendorName|"Unknown"|VOID*|0x00000007
  gRockchipTokenSpaceGuid.PcdFamilyName|"Unknown"|VOID*|0x00000008
  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"Unknown"|VOID*|0x00000009

  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x0 }|VOID*|0x02000001
  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x02000002
  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ 0x0 }|VOID*|0x02000003
  gRockchipTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x02000004
  gRockchipTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x02000005
  gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x0 }|VOID*|0x02000007
  gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x0 }|VOID*|0x02000008
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x0 }|VOID*|0x02000009
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0 }|VOID*|0x0200000A
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 0x0 }|VOID*|0x0200000B
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ 0x0 }|VOID*|0x0200000C
  gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ 0x0 }|VOID*|0x0200000D
  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0|UINT8|0x0200000E

  gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress|0x0|UINT32|0x40000030
  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken|FALSE|BOOLEAN|0x40000031

  gRockchipTokenSpaceGuid.PcdDwcSdhciBaseAddress|0x0|UINT32|0x40000035
  gRockchipTokenSpaceGuid.PcdDwcSdhciForceHighSpeed|FALSE|BOOLEAN|0x40000036
  gRockchipTokenSpaceGuid.PcdDwcSdhciDisableHs400|FALSE|BOOLEAN|0x40000037

  gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0|UINT32|0x21200002

  gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0|UINT32|0x50000060
  gRockchipTokenSpaceGuid.PcdNumEhciController|0|UINT32|0x50000061
  gRockchipTokenSpaceGuid.PcdEhciSize|0|UINT32|0x50000062
  gRockchipTokenSpaceGuid.PcdOhciSize|0|UINT32|0x50000063

  gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ 0x0 }|VOID*|0x50000069
  gRockchipTokenSpaceGuid.PcdDwc3Size|0|UINT32|0x50000071

  gRockchipTokenSpaceGuid.FspiBaseAddr|0|UINT64|0x21200003
  gRockchipTokenSpaceGuid.CruBaseAddr|0|UINT64|0x21200008

  gRockchipTokenSpaceGuid.PcdNvStoragePreferSpiFlash|FALSE|BOOLEAN|0x21200009

  gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0|UINT32|0x32000001
  gRockchipTokenSpaceGuid.PcdEdpId|0|UINT32|0x32000003
  gRockchipTokenSpaceGuid.PcdHdmiId|0|UINT32|0x32000004
  gRockchipTokenSpaceGuid.PcdHdmiDDCI2CPinMux|0|UINT32|0x32000005

  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase|0x0010f000|UINT64|0x00001000
  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize|0x100|UINT32|0x00001001
  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSmcId|0x82000010|UINT32|0x00010002

  gRockchipTokenSpaceGuid.PcdPca9555Address|0|UINT8|0x03000001
  gRockchipTokenSpaceGuid.PcdPca9555Bus|0|UINT8|0x03000002
