From d4d925fd799bdc0eb4826bb67f4211354868452c Mon Sep 17 00:00:00 2001 From: hornet Date: Sat, 30 Nov 2024 08:11:08 +0500 Subject: [PATCH] finished project outline, added two walkthrough sections, included local copies of some sources --- README.md | 173 +- .../.github/workflows/build.yml | 106 + .../.github/workflows/nightly.yml | 41 + .../.github/workflows/release.yml | 28 + local/UEFI/edk2-rk3588-master/.gitignore | 13 + local/UEFI/edk2-rk3588-master/.gitmodules | 16 + local/UEFI/edk2-rk3588-master/README.md | 376 ++ local/UEFI/edk2-rk3588-master/build.sh | 252 + .../edk2-rk3588-master/configs/RK3588.conf | 3 + .../edk2-rk3588-master/configs/aio-3588q.conf | 3 + .../edk2-rk3588-master/configs/blade3.conf | 3 + .../edk2-rk3588-master/configs/edge2.conf | 3 + .../configs/fydetab-duo.conf | 3 + .../UEFI/edk2-rk3588-master/configs/h88k.conf | 3 + .../configs/indiedroid-nova.conf | 3 + .../edk2-rk3588-master/configs/itx-3588j.conf | 3 + .../edk2-rk3588-master/configs/nanopc-t6.conf | 3 + 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local/freebsd/bsdinstall_files/search.min.js create mode 100644 local/freebsd/bsdinstall_files/theme-chooser.min.js diff --git a/README.md b/README.md index 163e3d5..0fda7de 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,174 @@ # wirecat -fuck your phone - PDA based on OrangePi 5 Plus \ No newline at end of file +fuck your phone - PDA based on OrangePi 5 Plus + +## quick FAQ & overview + +>what the fuck is this? + +wirecat is a project i thought about for a long time - building your own portable device with all the functionality you need, tailored to your specific needs, and of course - the one that looks cool. + +> why wirecat? + +just a cool name. also, the amount of interface ports on opi5+ is sure impressive for a SBC, so it's kinda fitting. + +> why FreeBSD? + +the only OS i could find that would satisfy my needs of running properly on this piece of hardware and not being a piece of dead shit. none of the linux distros would do, since unfortunately as of 11/2024 there is not a single systemd-free distro that works properly. trust me, i've tried several(void, alpine, artix, gentoo, etc.) + +> what kind of functionality does it have? + +it is a fully capable ARM computer running a UNIX-compliant system - the only limit is your schizo level. but in short - it can do everything what a smartphone/laptop can do, taking desktop functionality as granted - connect and utilize cellular network, work with RFID/NFC devices, even used as an electronic recon system(if you have an SDR)! sounds cool, doesn't it? + +> SDR? what is that? + +software-defined radio. an auxillary device that can be used to discover the electromagnetic(radio) spectrum around it, receive or transmit on certain radio frequency with certain types of modulation, depending on your SDR specs. for my own i used RTL-SDRv3, since it's cheap and i've had it for years. a reasonable choice for beginners in RF field, though better alternatives exist as of now, but those have a higher price tag(HackRF One, for example). + +> specs? + +OrangePi 5 Plus: +- CPU: octa-core Rockchip RK3588 64-bit ARM processor(aarch64, 4x Cortex-A55 + 4x Cortex-A72, upo to 2.4GHz) +- RAM: dual-channel 16GB LPDDR4X* +- GPU: Mali-610 ARM +- storage: 1x NVME M.2 MSI Spectrum Z390 SSD 240GB(system), 1x eMMC 256GB(secondary storage) +- wireless: 1x RTL8862BE(PCIE+USB) wireless network adapter(Wi-Fi 6/BT 5 capable), 1x Sierra Wireless AIrprime EM7455 M.2 key cellular/GPS module with USB adapter +- ethernet: 2x Realtek 2.5Gbps Ethernet adapters +battery: +- cells: 6x Samsung INR18650-35E 18650 batteries, 3500mAh +- BMS: chinkshit 22,5W BMS, QuickCharge 3.0/4.0, 2x USB, 1x microUSB, 1x USB-C, 1x USB-C(charge only) +auxillary: +- cellular: Sierra Wireless Airprime EM7455, GSM/LTE/GPS, 1x SIM card slot, 3x U.FL male antenna connector +- RFID/NFC: RFID-RC522 module +- display: 5" FHD HDMI touchscreen display(many options, acquisition in progress) +- keyboard: mini-keyboard, wireless capable(many options, acquisition in progress) +software: +- operating system: FreeBSD 14.1-RELEASE aarch64 +- video drivers: Panfrost/drm-510 + +## walkthrough(WIP) + +walkthrough on how to assemble your own variation of wirecat is divided into following sections: +1. hardware assembly +2. OS installation +3. software installation(WIP) +4. chassis assembly(WIP) + +full list of parts and tools needed for building will be in the end of this document + +### hardware assembly + +BATTERY ASSEMBLY + +hardware required: +- 6x battery cells +- BMS board +- wiring(i recommend 16AWG) +- 18650 battery slots(any kind, just make sure they are connected in parallel) +tools required: +- soldering iron +- wire stripper/knife +- multimeter +- isolation tape +- two-side duct tape(optional) + +step-by-step: + +0. prepare the wiring, measure the length and strip the ends for soldering +1. connect the 18650 battery slots in parallel so you have a single 6-piece battery block +2. solder the positive and negative terminals according to their respective locations on the BMS board(marked by B+ and B- accordingly) +3. check connections with multimeter, then properly isolate the terminals with isolation nape or in any other suitable way(thermal glue, epoxy, etc.) +4. OPTIONAL: use two-way duct tape to secure the BMS board on the top/side of the battery block +5. this BMS plate has a thermal resistor, place it right on one of the battery cells and secure with tape +6. insert the battery cells +7. put the battery assembly to charge + +congrats! the battery block is ready! + +ORANGEPI 5 PLUS + +hardware required: +- OrangePi 5 Plus +- eMMC chip +- cooler/radiator kit +- M.2 SSD +tools required: +- screwdriver + +>>note: i know 99% of people can manage this without any instructions, but anyway +step-by-step: + +0. prepare all your stuff, watch out for small components getting lost! +1. unpack the M.2 SSD, install it just like any other one in the back M.2 2280 slot +2. unpack the eMMC, install into the designated slot +3. unpack the coller/radiator kit, remove the back cover to expose the thermal sticky pads, install to their respective places + +probably the easiest part, nonetheless - way to go! + +RFID/NFC MODULE WIRING(WIP) + +### OS installation + +depending on your OS, instructions may not be suitable for your system of choice. only FreeBSd installation will be covered here. known other operating systems with some level of Orange Pi 5 Plus support: +- Orange Pi OS(full, vendor-provided) +- Armbian(partial) +- BredOS(full) +- Armtix(barely) + +tools required: +- flashing/burning software(dd/Rufus/balenaEtcher/etc.) +- SD card + +PART 1 - UEFI INSTALLATION VIA JUMPER OS + +0. prepare your tools +1. pick any OS image you want, vendor-provided ones are a good option +2. flash the image onto an SD card +3. insert the SD card and boot up Orange Pi 5 Plus +4. once logged in, follow [guide in this repo](https://github.com/edk2-porting/edk2-rk3588) to install UEFI firmware [local copy of guide and UEFI image](./local/UEFI) + +now you should have a working UEFI installed, after rebooting the I/O status light will blink blue instead of green + +PART 2 - FREEBSD INSTALLATION + +tools required: +- flashing/burning software(dd/Rufus/balenaEtcher/etc.) +- SD card or USB flash drive + +0. prepare your tools, download the OS image from [here](https://download.freebsd.org/releases/ISO-IMAGES/14.1/FreeBSD-14.1-RELEASE-arm64-aarch64-memstick.img) +1. flash the image onto the storage device +2. insert the storage device into the SD card slot/USB port +3. power on the OrangePi 5 Plus, enter the BIOS +4. select the storage medium and boot +5. FreeBSD installation here is not really any different from any other platform, pretty intuitive as well, nonetheless i will leave [this guide](https://docs.freebsd.org/en/books/handbook/bsdinstall/) here [(local copy)](./local/freebsd/bsdinstall.html) + +NOTE: as of 11/2024, the current version of FreeBSD 14.1-RELEASE does not come with the drivers for wireless card, so for network connectivity you will need to use either an Ethernet cable or USB tethering via your smartphone until then + +congratulations, now you should have a working FreeBSD installation running! + +### software installation(WIP) + +### chassis assembly(WIP) + +## list of parts and tools(WIP) + +PARTS + +- OrangePi 5 Plus 16GB kit(32GB version is available for purchase as of 11/2024) - i recommend the option with the cooling/radiator kit, wireless card and 265GB eMMC card +- M.2 2280 SSD +- RFID-RC522 module +- Sierra Wireless Airprime EM7455 module with USB adapter +- RTL-SDRv3 software-defined radio +- 5" FHD HDMI touchscreen display +- 6x 18650 batteries - you can alter the battery assembly design to your needs, i just went full blast on this one +- 3x 2-piece parallel 18650 battery slots - you can get whatever combination you want, according to your battery aseembly configuration +- 16AWG wiring - you will probably need like 20cm of it at most, suit yourself :3 +- signal wires - can find those almost anywhere +- HDMI cable +- USB-C cable + +TOOLS +- soldering iron and soldering neccessities(flux, solder, cleaning kit, etc.) +- screwdriver +- wire stripper +- isolation tape +- two-way duct tape(optional) \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/.github/workflows/build.yml b/local/UEFI/edk2-rk3588-master/.github/workflows/build.yml new file mode 100644 index 0000000..65a5fa2 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/.github/workflows/build.yml @@ -0,0 +1,106 @@ +name: Build +on: + push: + paths-ignore: + - '**.md' + branches: + - master + pull_request: + paths-ignore: + - '**.md' + branches: + - master + workflow_call: + inputs: + build-configs: + type: string + required: true + workflow_dispatch: + +jobs: + build: + runs-on: ubuntu-latest + strategy: + matrix: + PLATFORM: + - rock-5b + - rock-5a + - rock-5-itx + - orangepi-5 + - orangepi-5plus + - indiedroid-nova + - fydetab-duo + - roc-rk3588s-pc + - itx-3588j + - aio-3588q + - station-m3 + - r58x + - r58-mini + - edge2 + - nanopi-r6c + - nanopi-r6s + - nanopc-t6 + - blade3 + - h88k + CONFIGURATION: ${{ fromJSON(format('[{0}]', inputs.build-configs || '"Debug"')) }} + steps: + - name: Checkout + uses: actions/checkout@v4 + with: + submodules: recursive + + - name: Install dependencies + shell: bash + run: | + sudo apt-get update && \ + sudo apt-get install -y \ + acpica-tools \ + binutils-aarch64-linux-gnu \ + build-essential \ + device-tree-compiler \ + gettext \ + git \ + gcc-aarch64-linux-gnu \ + libc6-dev-arm64-cross \ + python3 \ + python3-pyelftools + + - name: Get version tag + id: get_version_tag + shell: bash + run: echo "version=$(git describe --tags --always)" >> $GITHUB_OUTPUT + + - name: Set up Secure Boot default keys + run: | + mkdir keys + # We don't really need a usable PK, so just generate a public key for it and discard the private key + openssl req -new -x509 -newkey rsa:2048 -subj "/CN=Rockchip Platform Key/" -keyout /dev/null -outform DER -out keys/pk.cer -days 7300 -nodes -sha256 + curl -L https://go.microsoft.com/fwlink/?LinkId=321185 -o keys/ms_kek.cer + curl -L https://go.microsoft.com/fwlink/?linkid=321192 -o keys/ms_db1.cer + curl -L https://go.microsoft.com/fwlink/?linkid=321194 -o keys/ms_db2.cer + curl -L https://uefi.org/sites/default/files/resources/dbxupdate_arm64.bin -o keys/arm64_dbx.bin + + - name: Build platform + shell: bash + run: | + export EDK2_SECUREBOOT_FLAGS=" \ + -D DEFAULT_KEYS=TRUE \ + -D PK_DEFAULT_FILE=keys/pk.cer \ + -D KEK_DEFAULT_FILE1=keys/ms_kek.cer \ + -D DB_DEFAULT_FILE1=keys/ms_db1.cer \ + -D DB_DEFAULT_FILE2=keys/ms_db2.cer \ + -D DBX_DEFAULT_FILE1=keys/arm64_dbx.bin \ + -D SECURE_BOOT_ENABLE=TRUE" + + export EDK2_BUILD_FLAGS=" \ + ${EDK2_SECUREBOOT_FLAGS}" + + ./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}} --edk2-flags "${EDK2_BUILD_FLAGS}" + mv RK3588_NOR_FLASH.img ${{matrix.PLATFORM}}_UEFI_${{matrix.CONFIGURATION}}_${{steps.get_version_tag.outputs.version}}.img + + - name: Upload artifact + uses: actions/upload-artifact@v4 + with: + name: ${{matrix.PLATFORM}} UEFI ${{matrix.CONFIGURATION}} image + path: ./*.img + if-no-files-found: error diff --git a/local/UEFI/edk2-rk3588-master/.github/workflows/nightly.yml b/local/UEFI/edk2-rk3588-master/.github/workflows/nightly.yml new file mode 100644 index 0000000..ec78c82 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/.github/workflows/nightly.yml @@ -0,0 +1,41 @@ +name: Nightly +run-name: Nightly build +on: + schedule: + - cron: "0 0 * * *" + +jobs: + prepare: + runs-on: ubuntu-latest + permissions: + actions: write + steps: + - name: Delete previous cancelled runs + uses: Mattraks/delete-workflow-runs@v2 + with: + retain_days: 0 + keep_minimum_runs: 0 + delete_workflow_pattern: ${{ github.workflow }} + delete_run_by_conclusion_pattern: cancelled + + - name: Check for new commits + id: check-new-commits + uses: adriangl/check-new-commits-action@v1 + with: + seconds: 86400 # One day in seconds + branch: 'master' + + - name: Cancel action if no new commits + if: ${{ steps.check-new-commits.outputs.has-new-commits != 'true' }} + uses: andymckay/cancel-action@0.3 + + - name: Wait for cancellation + if: ${{ steps.check-new-commits.outputs.has-new-commits != 'true' }} + shell: bash + run: while true; do echo "Waiting for job to be cancelled"; sleep 5; done + + build_for_nightly: + needs: prepare + uses: ./.github/workflows/build.yml + with: + build-configs: '"Debug", "Release"' diff --git a/local/UEFI/edk2-rk3588-master/.github/workflows/release.yml b/local/UEFI/edk2-rk3588-master/.github/workflows/release.yml new file mode 100644 index 0000000..a37dbc4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/.github/workflows/release.yml @@ -0,0 +1,28 @@ +name: Release +on: + push: + tags: + - '*' + +jobs: + build_for_release: + uses: ./.github/workflows/build.yml + with: + build-configs: '"Debug", "Release"' + + release: + runs-on: ubuntu-latest + needs: build_for_release + permissions: + contents: write + steps: + - name: Download all workflow run artifacts + uses: actions/download-artifact@v4 + + - name: Create release + uses: softprops/action-gh-release@v2 + with: + draft: true + prerelease: false + files: "*/*Release*.img" + fail_on_unmatched_files: true diff --git a/local/UEFI/edk2-rk3588-master/.gitignore b/local/UEFI/edk2-rk3588-master/.gitignore new file mode 100644 index 0000000..d805189 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/.gitignore @@ -0,0 +1,13 @@ +boot-*.img +uefi-*.img +uefi-*.img.gz +workspace +*.dll +ramdisk +.cache +.vscode +*.dts +*.swp +*.rej +*.orig +*_FLASH.img diff --git a/local/UEFI/edk2-rk3588-master/.gitmodules b/local/UEFI/edk2-rk3588-master/.gitmodules new file mode 100644 index 0000000..be3edcc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/.gitmodules @@ -0,0 +1,16 @@ +[submodule "edk2"] + path = edk2 + url = https://github.com/tianocore/edk2.git +[submodule "edk2-non-osi"] + path = edk2-non-osi + url = https://github.com/tianocore/edk2-non-osi.git +[submodule "edk2-platforms"] + path = edk2-platforms + url = https://github.com/tianocore/edk2-platforms.git +[submodule "misc/rkbin"] + path = misc/rkbin + url = https://github.com/rockchip-linux/rkbin.git +[submodule "arm-trusted-firmware"] + path = arm-trusted-firmware + url = https://github.com/worproject/arm-trusted-firmware + branch = rk3588 diff --git a/local/UEFI/edk2-rk3588-master/README.md b/local/UEFI/edk2-rk3588-master/README.md new file mode 100644 index 0000000..49edc63 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/README.md @@ -0,0 +1,376 @@ +# EDK2 UEFI firmware for Rockchip RK3588 platforms +This repository contains an UEFI firmware implementation based on EDK2 for various RK3588 boards. + +# Supported platforms +- [Radxa ROCK 5B](https://radxa.com/products/rock5/5b/) +- [Radxa ROCK 5A](https://radxa.com/products/rock5/5a/) +- [Radxa ROCK 5 ITX](https://radxa.com/products/rock5/5itx/) +- [Orange Pi 5](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html) +- [Orange Pi 5 Plus](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-plus.html) +- [ameriDroid Indiedroid Nova](https://indiedroid.us) +- [Fydetab Duo](https://fydetabduo.com/) +- [Firefly AIO-3588Q](https://en.t-firefly.com/product/industry/aio3588q) +- [Firefly ITX-3588J](https://en.t-firefly.com/product/industry/itx3588j) +- [Firefly ROC-RK3588S-PC](https://en.t-firefly.com/product/industry/rocrk3588spc) +- [StationPC Station M3](https://www.stationpc.com/product/stationm3) +- [Mekotronics R58X](https://www.mekotronics.com/h-pd-75.html) +- [Mekotronics R58 Mini](https://www.mekotronics.com/h-pd-76.html) +- [Khadas Edge2](https://www.khadas.com/edge2) +- [Mixtile Blade 3](https://www.mixtile.com/blade-3) +- [FriendlyELEC NanoPC T6](https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6) +- [FriendlyELEC NanoPi R6C](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6C) +- [FriendlyELEC NanoPi R6S](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6S) +- [Hinlink H88K](http://www.hinlink.com) + +# Supported OSes +## In ACPI mode +| OS | Version | Tested/supported hardware | Notes | +| --- | --- | --- | --- | +| Windows | 11 | [Status](https://github.com/worproject/Rockchip-Windows-Drivers#hardware-support-status) || +| NetBSD | 10 | Display, UART, USB, PCIe (incl. NVME), SATA, eMMC, GMAC Ethernet || +| VMware ESXi Arm Fling | >= 1.12 | Display, USB | * PCIe devices will hang at boot, need to disable in settings or leave the ports empty.
* GMAC Ethernet gets detected but does not work. | +| Linux | tested Ubuntu 22.04, kernel 5.15.0-75-generic | Display, UART, USB, PCIe (incl. NVME & Ethernet), SATA | For full hardware functionality, use a kernel with RK3588 support and switch to Device Tree mode. | + +> [!NOTE] +> ACPI support is only being developed and tested against Windows. There are no plans to further improve functionality for other OSes. Consider using Device Tree instead (where applicable, for instance Linux). + +## In Device Tree mode +| OS | Version | Tested/supported hardware | Notes | +| --- | --- | --- | --- | +| Rockchip SDK Linux | 5.10 legacy, tested with [Armbian rk3588-live-iso](https://github.com/amazingfate/rk3588-live-iso) | Platform-dependent, most peripherals work. | If using a different kernel, see [Device Tree configuration](#device-tree-configuration). | + +# Supported peripherals in UEFI + +> [!NOTE] +> Applicable to all platforms unless otherwise noted. +> +> Only devices relevant to the firmware itself (not OS) are listed below. + +| Device | Status | Notes | +| --- | --- | --- | +| USB 3 / 2.0 / 1.1 | 🟢 Working | Host-mode only, USB 3 devices connected to a Type-C port only work in one orientation. | +| PCIe 3.0 (RK3588) | 🟢 Working | No bifurcation support | +| PCIe 2.1 | 🟢 Working | | +| SATA | 🟢 Working | | +| SD/eMMC | 🟢 Working | | +| HDMI output | 🟡 Partial | Single display with mode limited at 1080p 60 Hz | +| DisplayPort output (USB-C) | 🟡 Partial | Mode fixed at 1080p 60 Hz, only works in one orientation of the Type-C port. Some displays may not work regardless. | +| eDP output | 🟡 Partial | Disabled, requires manual configuration depending on the platform and panel. | +| DSI output | 🟢 Working | Only enabled on Fydetab Duo. Requires manual configuration depending on the platform and panel. | +| GMAC Ethernet | 🔴 Not working | Only brought-up for OS usage | +| Realtek PCIe Ethernet | 🟢 Working | Some platforms don't have MAC addresses set, networking may not work in that case. | +| UART | 🟢 Working | UART2 console available at 1500000 baud rate | +| GPIO | 🟡 Partial | Only read, write and alt function supported | +| I2C | 🟢 Working | | +| SPI | 🟢 Working | | +| PWM | 🟢 Working | | +| SPI NOR Flash | 🟢 Working | | +| HYM8563 real-time clock | 🟢 Working | | +| RNG | 🟢 Working | | +| Cooling fan | 🟢 Working | Supported on most platforms. Fan connector where present, otherwise available at the GPIO header for 3-pin PWM fans (do *not* connect 2-pin fans there!):
* Orange Pi 5: `GPIO4_B2`
* Indiedroid Nova: `GPIO4_B4` | +| Status LED | 🟢 Working | | +| Voltage regulators (RK806, RK860) | 🟢 Working | | +| FUSB302 USB Type-C Controller | 🔴 Not working | Required for PD negotiation and connector orientation switching | + +# Getting started +## 1. Requirements +* One of the [supported devices](#supported-platforms). +* Storage for the firmware: SPI NOR flash (included with some devices), SD card or eMMC. +* Quality power supply that can provide at least 15 W. Depending on the peripherals you use, more may be needed. + + Note: on Mixtile Blade 3, a fixed voltage *higher than* 5V must be supplied. The board cannot power any external peripherals if the input voltage is just 5V. USB-PD negotiation is not supported by firmware. +* HDMI or DisplayPort (USB-C) screen capable of at least 1080p 60Hz. +* Optionally, if display is not available or for debugging purposes, an UART adapter capable of 1500000 baud rate (e.g. USB CH340, CP2104). + +## 2. Download the firmware image +The latest version can be obtained from . + +If your platform is not yet supported, using an image meant for another device is **not** recommended. Although they are generally similar, voltage setup can happen to be different and you may risk damaging the board. External peripherals are unlikely to work either. + +## 3. Flash the firmware +UEFI can be flashed to either a SPI NOR flash, SD card or eMMC module: +* For removable SD or eMMC (easiest), you can simply use balenaEtcher, RPi Imager or dd. +* For SPI NOR or soldered eMMC, instructions can be found at: . + + In short, you can flash the image from Linux booted on the device or by using RKDevTool on another computer. The latter requires entering Maskrom mode on the device. The way to do this slightly varies across platforms, refer to your vendor documentation. + +**Warning:** these operations will erase data on the storage device. Make a backup first! + +If you wish to have both UEFI and an OS on the same SD or eMMC device: flash UEFI first, then create any additional partitions without touching the first, reserved one. Steps for updating the firmware in this case can be found [here](#updating-the-firmware). + +Note: Using SPI NOR (if present) is recommeded, as it leaves the other storage options free for other purposes. Additionally, SD/eMMC will limit the firmware's ability to access its own storage (variable store) when an OS is running. This feature is mostly used by OS installers to create the boot menu options, it is not mandatory. + +## 4. Connect peripherals and power on the device +If the flashing process has been done correctly, you should see the status LED blinking (if present), and shortly after, the platform's boot logo with a progress bar at the bottom on the connected display. + +At this stage, you can press Esc to enter the firmware setup, F1 to launch the UEFI Shell, or, provided you also have an UEFI bootloader/app on a storage device, you can let the system automatically run that, which is the default behavior if no action is taken. + +Check the [Supported OSes](#supported-oses) and [Supported peripherals in UEFI](#supported-peripherals-in-uefi) sections to see what's currently possible with this firmware. + +Also check the configuration options described below, some of which may need to be changed depending on the OS used. + +If you experience any issues, please see the [Troubleshooting](#troubleshooting) section. + +# Configuration settings +The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using the UI configuration menu (under `Device Manager` -> `Rockchip Platform Configuration`). + +Configuration through the user interface is fairly straightforward and help/navigation information is provided around the menus. + +## Tips +* CPU clocks are set to 816 MHz (boot default) on platforms without a cooling fan included. If you have adequate cooling, go to the configuration menu -> `CPU Performance` and set all Cluster Presets to `Maximum`. + +## Device Tree configuration +For rich Linux support, it is recommended to enable Device Tree mode. You can do so by going to the configuration menu -> `ACPI / Device Tree` and setting `Config Table Mode` to `Device Tree`. + +By default, the firmware installs a [DTB compatible with (most) Rockchip SDK Linux 5.10 legacy kernel variants](https://github.com/edk2-porting/edk2-rk3588/tree/master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree). + +### Custom Device Tree Blob (DTB) override and overlays +It is also possible to provide a custom DTB and overlays. To enable this, go to the configuration menu -> `ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`. + +The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases this will be the first FAT32 EFI System Partition. + +* The base DTB must be located at `\dtb\base\.dtb`. + +* The overlays can be placed in: + * `\dtb\overlays` - will be applied first, regardless of the platform. + * `\dtb\overlays\` - will be applied only to the specified platform. + + and must have the `.dtbo` extension. + +The paths above are relative to the root of the file system. That is, the `dtb` directory must not be placed in a sub-directory. + +`` can be: +| Name | Platform | +| --------------------------------------- | ----------------------------- | +| `rk3588-rock-5b` | ROCK 5B | +| `rk3588s-rock-5a` | ROCK 5A | +| `rk3588-rock-5-itx` | ROCK 5 ITX | +| `rk3588s-orangepi-5` | Orange Pi 5 | +| `rk3588-orangepi-5-plus` | Orange Pi 5 Plus | +| `rk3588s-9tripod-linux` | Indiedroid Nova | +| `rk3588s-fydetab-duo` | Fydetab Duo | +| `rk3588-firefly-aio-3588q` | Firefly AIO-3588Q | +| `itx-3588j` | Firefly ITX-3588J | +| `roc-rk3588s-pc` | ROC-RK3588S-PC / Station M3 | +| `rk3588-blueberry-edge-v12-linux` | R58X (v1.2) | +| `rk3588-blueberry-minipc-linux` | R58 Mini | +| `rk3588s-khadas-edge2` | Edge2 | +| `rk3588-blade3-v101-linux` | Blade 3 | +| `rk3588-nanopc-t6` | NanoPC T6 | +| `rk3588s-nanopi-r6c` | NanoPi R6C | +| `rk3588s-nanopi-r6s` | NanoPi R6S | +| `rk3588-hinlink-h88k` | H88K | + +In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB. + +The firmware applies some fix-ups to its own DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied to a custom base DTB - overlays must be used instead. + +If the application of an overlay fails (e.g. due to it being invalid in regard to the base DTB), all overlays are discarded, including those that got applied up to that point. + +If the custom base DTB is invalid, the firmware-provided one will be passed to the OS instead. + +This entire process is logged to the [serial console](#advanced-troubleshooting). There's currently no other way to see potential errors. + +# Updating the firmware +If the storage is only used for UEFI and nothing else, simply download the latest image and flash it as described in the [Getting started](#getting-started) section. + +If it is also used by an OS and has additional partitions, only part of the image needs to be applied. This can be done with the `dd` tool: +```bash +dd if=FIRMWARE.img of=DESTINATION bs=512 skip=64 seek=64 conv=notrunc +``` + +`FIRMWARE.img` is the firmware image for your platform. E.g. `edge2_UEFI_Release_v0.8.img`. + +`DESTINATION` is the destination storage that you wish to update the firmware on. E.g. `/dev/sdb`. + +Here we skip the GPT and copy the firmware starting at offset 0x8000 (`64` blocks * `512` bytes block size) until its end. See [Flash layout](#flash-layout) for more details. + +# Troubleshooting + +> [!IMPORTANT] +> First of all, make sure your device can only possibly load the UEFI firmware and nothing else. +> +> **U-Boot must not present on either SPI NOR, SD or eMMC, otherwise it could take precedence and cause hidden issues.** + +Below you can find some basic debugging information. If none of this helps, please see the [Advanced troubleshooting](#advanced-troubleshooting) section. + +## Meaning of the Status LED +If your device has an activity LED, the firmware will blink it in different patterns to indicate the current system status. + +1. Immediately after power on, the LED should start pulsing quickly. This indicates that the firmware is initializing. + +2. After initialization (usually takes less than 5 seconds), the LED will switch to a short pulsing every 2 seconds or so. This indicates that the firmware is ready and waiting for user action or the countdown to boot automatically. The display output should also be enabled at this point. + +3. When the firmware boots an OS and is about to exit, the LED will stop blinking. + +If the LED: +* does not light up after power on, this means the firmware has not managed to load up at all. +* gets stuck in either on or off state after blinking a few times and never recovers, something went wrong and the firmware has crashed or frozen. + + Note that it is only expected to stop as described at point 3) above. + +## Common issues +### Nothing shows up on the screen +Make sure you've flashed the firmware correctly and that it is the version designed for your device. In most cases this is the culprit. + +Assuming the firmware loads fine: +* The display must support a resolution of at least 1080p at 60 Hz. +* If you're using HDMI and the system has two ports, only one will work. Try both. +* If you're using USB-C to DisplayPort, only one orientation of the USB-C connector will work. Check both. + +If you are not able to get any display output, the only way to interact with UEFI is via the [serial console](#advanced-troubleshooting). + +### Configuration settings do not get saved +This has been observed in cases where U-Boot was still present on another boot device (SD, eMMC or SPI NOR). This is not a supported scenario. The solution is to unplug or erase devices that may have other firmware on them. + +What's happening: +1. Board loads U-Boot from a storage device that has higher priority (let's say eMMC). +2. That U-Boot image in turn loads UEFI and its settings from another device with lower priority (let's say SD). +3. UEFI cannot accurately determine to which device it belongs. The parameter used to verify this points to eMMC (U-Boot), while UEFI actually got loaded from SD. +4. Consequently, UEFI mistakenly saves the user settings to eMMC. On reboot, U-Boot loads UEFI and the original/unchanged settings from SD and the cycle repeats. + +### USB 3 devices do not work +* Try a different port. +* If you're using USB-C, 3.0 devices will only work in one orientation of the connector. Check both. +* Make sure the power supply and cable are good. + +### Networking does not work +* Only Realtek PCIe and USB controllers are supported. Native Gigabit provided by RK3588 isn't. + +* Some boards with Realtek NICs do not have a MAC address set at factory and will show-up as being all zeros in UEFI, possibly preventing the adapter from obtaining an IP address. + + You can easily fix this by writing the MAC address manually: + + 1. Boot into Linux and open up a terminal. The commands below apply to Armbian with legacy kernel. + + 2. Install the headers for your kernel version: + ```bash + sudo apt install -y linux-headers-legacy-rk35xx + ``` + + 3. Clone Realtek PGTool and build the driver: + ```bash + git clone https://github.com/redchenjs/rtnicpg + cd rtnicpg + make + ``` + + 4. Unload all Realtek modules and load the driver built above: + ```bash + sudo rmmod pgdrv + sudo ./pgload.sh + ``` + Note: make sure there aren't any remaining Realtek modules loaded after this, except for the new `pgdrv`.
If you have `r8125` built-in, you might have to reboot with `initcall_blacklist=rtl8125_init_module` as a kernel parameter (in Grub). + + 5. Burn a MAC address into the eFuses: + + For only one NIC: + ```bash + sudo ./rtnicpg-aarch64-linux-gnu /efuse /nodeid 00E04C001234 + ``` + For two or more: + ```bash + sudo ./rtnicpg-aarch64-linux-gnu /efuse /# 1 /nodeid 00E04C001234 + sudo ./rtnicpg-aarch64-linux-gnu /efuse /# 2 /nodeid 00E04C001235 + ``` + `00E04C001234` is an example address. You can generate random and unique ones using: + + **Note:** the number of eFuses is limited, thus MAC addresses can only be changed a few times. + +## Advanced troubleshooting +The firmware will log detailed information to the serial console when using a debug version. See the [release notes](https://github.com/edk2-porting/edk2-rk3588/releases) for details on how to obtain this version. + +1. The debug image needs to be flashed in place of the existing one. + +2. Connect the **UART2** RX, TX and GND pins on your device (check vendor documentation) to the UART adapter on your other computer. + +3. Open up a serial terminal (`PuTTY` on Windows, `stty` on Linux) set to 1500000 baud rate and 8n1 (default). + +4. Power on the device. + +You should be able to see many debug messages being printed to the console. If that's not the case, double check the connections (swap RX/TX), make sure the adapter is functional and configured correctly. + +The logs should give an insight of what's going on. If you need help analyzing them, feel free to open an issue ticket. + +# Reporting issues +You can open issues related to UEFI at . + +Please include as many details as possible: expected behavior, what actually happens, steps to reproduce, [serial logs](#advanced-troubleshooting), etc. + +Also check the existing issues in case yours might be already reported. + +# Building +The firmware can only be built on Linux currently. For Windows use WSL. + +1. Install required packages: + + For Ubuntu/Debian: + ```bash + sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu acpica-tools python3-pyelftools uuid-dev python-is-python3 device-tree-compiler + ``` + For Arch Linux: + ```bash + sudo pacman -Syu + sudo pacman -S git base-devel gcc dtc aarch64-linux-gnu-binutils aarch64-linux-gnu-gcc aarch64-linux-gnu-glibc python python-pyelftools iasl --needed + ``` + +2. Clone the repository: + ```bash + git clone https://github.com/edk2-porting/edk2-rk3588.git --recursive + cd edk2-rk3588 + ``` + +3. Build UEFI (ROCK 5B for example, check [list of platform configs](https://github.com/edk2-porting/edk2-rk3588/tree/master/configs)): + ```bash + ./build.sh --device rock-5b --release Release # (or Debug) + ``` + +If you get build errors, it is very likely that you're still missing some dependencies. The list of packages above is not complete and depending on the distro you may need to install additional ones. In most cases, looking up the error messages on the internet will point you at the right packages. + +# Notes + +## Flash layout +| Address | Size | Desc | File | +| ---------- | ---------- | --------------------- | ---------------------- | +| 0x00000000 | 0x00004400 | GPT Table | rk3588_spi_nor_gpt.img | +| 0x00008000 | | IDBlock | idblock.bin | +| 0x00100000 | 0x00500000 | BL33_AP_UEFI FV | ${DEVICE}_EFI.itb | +| 0x007C0000 | 0x00010000 | NV_VARIABLE_STORE | | +| 0x007D0000 | 0x00010000 | NV_FTW_WORKING | | +| 0x007E0000 | 0x00010000 | NV_FTW_SPARE | | + +The variable store is not included in the flash image, in order to prevent overwriting it and to maintain the user settings across updates. + +The firmware expects these exact offsets, do not change them. + +## Memory Map +| Address | Size | Desc | File | +| ---------- | --------- | --------------------- | ------------------- | +| 0x00040000 | | ATF | bl31_0x00040000.bin | +| 0x000f0000 | | ATF | bl31_0x000f0000.bin | +| 0x00200000 | 0x00500000 | UEFI FV | BL33_AP_UEFI.Fv | +| 0x007C0000 | 0x00010000 | NV_VARIABLE_STORE | | +| 0x007D0000 | 0x00010000 | NV_FTW_WORKING | | +| 0x007E0000 | 0x00010000 | NV_FTW_SPARE | | +| 0x08400000 | | OP-TEE | bl32.bin | +| 0xff100000 | | ATF (PMU_MEM) | bl31_0xff100000.bin | + +## Licenses +Most of the UEFI code is licensed under the default EDK2 license, which is [BSD-2-Clause-Patent](https://github.com/tianocore/edk2/blob/master/License.txt). + +Some non-critical components have been ported from Rockchip's U-Boot fork and are licensed as **GPL-2.0-or-later**: +* UsbDpPhy +* DwDpLib + +The files in `edk2-rockchip-non-osi` are licensed as **GPL-2.0-only**. + +The license for some of the blobs in the `misc/rkbin/` directory can be found at: . Note that it also contains binaries built from open-source projects such as U-Boot (SPL), Arm Trusted Firmware and OP-TEE, having a different license. + +## Community +* Hack w/ Rockchip Telegram: +* Windows on R Discord: + +## Credits & alternatives +This firmware is based on Rockchip's initial efforts at . + +For RK356x, check out the Quartz64-UEFI project at https://github.com/jaredmcneill/quartz64_uefi, from which we also reused some code. diff --git a/local/UEFI/edk2-rk3588-master/build.sh b/local/UEFI/edk2-rk3588-master/build.sh new file mode 100755 index 0000000..e472005 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/build.sh @@ -0,0 +1,252 @@ +#!/bin/bash + +function _help(){ + echo + echo "Build EDK2 for Rockchip RK3588 platforms." + echo + echo "Usage: build.sh [options]" + echo + echo "Options:" + echo " -d, --device DEV Build for DEV, or 'all'." + echo " -r, --release MODE Release mode for building, default is 'DEBUG', 'RELEASE' alternatively." + echo " -t, --toolchain TOOLCHAIN Set toolchain, default is 'GCC'." + echo " --open-tfa ENABLE Use open-source TF-A submodule. Default: ${OPEN_TFA}" + echo " -C, --clean Clean workspace and output." + echo " -D, --distclean Clean up all files that are not in repo." + echo " --tfa-flags \"FLAGS\" Flags appended to open TF-A build process." + echo " --edk2-flags \"FLAGS\" Flags appended to the EDK2 build process." + echo " -h, --help Show this help." + echo + exit "${1}" +} + +function _error() { echo "${@}" >&2; exit 1; } + +function _build_idblock() { + echo " => Building idblock.bin" + pushd ${WORKSPACE} + + FLASHFILES="FlashHead.bin FlashData.bin FlashBoot.bin" + rm -f rk35*_spl_loader_*.bin idblock.bin rk35*_ddr_*.bin rk35*_usbplug*.bin UsbHead.bin ${FLASHFILES} + + DDRBIN_RKBIN=$(grep '^FlashData' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-) + SPL_RKBIN=$(grep '^FlashBoot' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-) + + DDRBIN="${ROOTDIR}/misc/rkbin/${DDRBIN_RKBIN}" + + # + # SPL v1.13 has broken SD card support! + # Use v1.12 instead. + # + # SPL="${ROOTDIR}/misc/rkbin/${SPL_RKBIN}" + SPL="${ROOTDIR}/misc/rk3588_spl_v1.12.bin" + + # Create idblock.bin + ${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -n rk3588 -T rksd -d ${DDRBIN}:${SPL} idblock.bin + + popd + echo " => idblock.bin build done" +} + +function _build_fit() { + echo " => Building FIT" + pushd ${WORKSPACE} + + BL31_RKBIN=$(grep '^PATH=.*_bl31_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-) + BL32_RKBIN=$(grep '^PATH=.*_bl32_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-) + + BL31="${ROOTDIR}/misc/rkbin/${BL31_RKBIN}" + BL32="${ROOTDIR}/misc/rkbin/${BL32_RKBIN}" + + if [ ${OPEN_TFA} == 1 ]; then + BL31="${ROOTDIR}/arm-trusted-firmware/build/${TFA_PLAT}/${RELEASE_TYPE,,}/bl31/bl31.elf" + fi + + rm -f bl31_0x*.bin ${WORKSPACE}/BL33_AP_UEFI.Fv ${SOC_L}_${DEVICE}_EFI.its + + ${ROOTDIR}/misc/extractbl31.py ${BL31} + if [ ! -f bl31_0x000f0000.bin ]; then + # Not used but FIT expects it. + touch bl31_0x000f0000.bin + fi + + cp ${BL32} ${WORKSPACE}/bl32.bin + cp ${ROOTDIR}/misc/${SOC_L}_spl.dtb ${WORKSPACE}/${DEVICE}.dtb + cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/BL33_AP_UEFI.Fv ${WORKSPACE}/ + cat ${ROOTDIR}/misc/uefi_${SOC_L}.its | sed "s,@DEVICE@,${DEVICE},g" > ${SOC_L}_${DEVICE}_EFI.its + ${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -f ${SOC_L}_${DEVICE}_EFI.its -E ${DEVICE}_EFI.itb + + popd + echo " => FIT build done" +} + +function _pack_image() { + _build_idblock + _build_fit + + echo " => Building 8MB NOR FLASH IMAGE" + cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img + + # GPT at 0x0, size:0x4400 + dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img + # idblock at 0x8000 + dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=32 + # FIT Image at 0x100000 + dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024 + cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/ +} + +function _build(){ + local DEVICE="${1}"; shift + + # + # Grab platform parameters + # + if [ -f "configs/${DEVICE}.conf" ] + then source "configs/${DEVICE}.conf" + else _error "Device configuration not found" + fi + if [ -f "configs/${SOC}.conf" ] + then source "configs/${SOC}.conf" + else _error "SoC configuration not found" + fi + typeset -l SOC_L="$SOC" + + rm -f "${OUTDIR}/RK35*_NOR_FLASH.img" + + # + # Build TF-A + # + if [ ${OPEN_TFA} == 1 ]; then + pushd arm-trusted-firmware + + if [ ${RELEASE_TYPE} == "DEBUG" ]; then + DEBUG=1 + else + DEBUG=0 + fi + + make PLAT=${TFA_PLAT} DEBUG=${DEBUG} all ${TFA_FLAGS} + + popd + fi + + # + # Build EDK2 + # + [ -d "${WORKSPACE}/Conf" ] || mkdir -p "${WORKSPACE}/Conf" + + export GCC_AARCH64_PREFIX="${CROSS_COMPILE}" + export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}" + export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-platforms:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/edk2-rockchip-non-osi:${ROOTDIR}/edk2-non-osi:${ROOTDIR}" + + make -C "${ROOTDIR}/edk2/BaseTools" + source "${ROOTDIR}/edk2/edksetup.sh" + + build \ + -s \ + -n 0 \ + -a AARCH64 \ + -t "${TOOLCHAIN}" \ + -p "${ROOTDIR}/${DSC_FILE}" \ + -b "${RELEASE_TYPE}" \ + -D FIRMWARE_VER="${GIT_COMMIT}" \ + ${EDK2_FLAGS} + + # + # Compile final image + # + _pack_image + + echo "Build done: RK3588_NOR_FLASH.img" +} + +function _clean() { rm --one-file-system --recursive --force "${OUTDIR}"/workspace "${OUTDIR}"/RK3588_*.img; } +function _distclean() { if [ -d .git ]; then git clean -xdf; else _clean; fi; } + +# +# Default variables +# +typeset -l DEVICE +typeset -u RELEASE_TYPE +DEVICE="" +RELEASE_TYPE=DEBUG +TOOLCHAIN=GCC +OPEN_TFA=1 +TFA_FLAGS="" +EDK2_FLAGS="" +CLEAN=false +DISTCLEAN=false +OUTDIR="${PWD}" + +# +# Get options +# +OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,clean,distclean,help" -n build.sh -- "${@}") || _help $? +eval set -- "${OPTS}" +while true; do + case "${1}" in + -d|--device) DEVICE="${2}"; shift 2 ;; + -r|--release) RELEASE_TYPE="${2}"; shift 2 ;; + -t|--toolchain) TOOLCHAIN="${2}"; shift 2 ;; + --open-tfa) OPEN_TFA="${2}"; shift 2 ;; + --tfa-flags) TFA_FLAGS="${2}"; shift 2 ;; + --edk2-flags) EDK2_FLAGS="${2}"; shift 2 ;; + -C|--clean) CLEAN=true; shift ;; + -D|--distclean) DISTCLEAN=true; shift ;; + -h|--help) _help 0; shift ;; + --) shift; break ;; + *) break ;; + esac +done +if [[ -n "${@}" ]]; then + echo "Invalid additional arguments '${@}'" + _help 1 +fi + +if "${DISTCLEAN}"; then _distclean; exit "$?"; fi +if "${CLEAN}"; then _clean; exit "$?"; fi + +[ -z "${DEVICE}" ] && _help 1 +[ -f "configs/${DEVICE}.conf" ] || [ "${DEVICE}" == "all" ] || _error "Device configuration not found" + +# +# Get machine architecture +# +MACHINE_TYPE=$(uname -m) + +# Fix-up possible differences in reported arch +if [ ${MACHINE_TYPE} == 'arm64' ]; then + MACHINE_TYPE='aarch64' +elif [ ${MACHINE_TYPE} == 'amd64' ]; then + MACHINE_TYPE='x86_64' +fi + +if [ ${MACHINE_TYPE} != 'aarch64' ]; then + export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}" +fi + +GIT_COMMIT="$(git describe --tags --always)" || GIT_COMMIT="unknown" + +export WORKSPACE="${OUTDIR}/workspace" +[ -d "${WORKSPACE}" ] || mkdir "${WORKSPACE}" + +ROOTDIR="$(realpath "$(dirname "$0")")" +cd "${ROOTDIR}" || exit 1 + +# Exit on first error +set -e + +if [ "${DEVICE}" == "all" ] +then + for i in configs/*.conf; do + DEV="$(basename "$i" .conf)" + if [ "${DEV}" != "RK3588" ] + then + echo "Building ${DEV}" + _build "${DEV}" + fi + done +else + _build "${DEVICE}" +fi diff --git a/local/UEFI/edk2-rk3588-master/configs/RK3588.conf b/local/UEFI/edk2-rk3588-master/configs/RK3588.conf new file mode 100644 index 0000000..9af38af --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/RK3588.conf @@ -0,0 +1,3 @@ +MINIALL_INI=RK3588MINIALL.ini +TRUST_INI=RK3588TRUST.ini +TFA_PLAT=rk3588_reference_pmic diff --git a/local/UEFI/edk2-rk3588-master/configs/aio-3588q.conf b/local/UEFI/edk2-rk3588-master/configs/aio-3588q.conf new file mode 100644 index 0000000..f394772 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/aio-3588q.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc +PLATFORM_NAME=AIO-3588Q +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/blade3.conf b/local/UEFI/edk2-rk3588-master/configs/blade3.conf new file mode 100644 index 0000000..aec306d --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/blade3.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Mixtile/Blade3/Blade3.dsc +PLATFORM_NAME=Blade3 +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/edge2.conf b/local/UEFI/edk2-rk3588-master/configs/edge2.conf new file mode 100644 index 0000000..46efa16 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/edge2.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc +PLATFORM_NAME=Edge2 +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/fydetab-duo.conf b/local/UEFI/edk2-rk3588-master/configs/fydetab-duo.conf new file mode 100644 index 0000000..07d32af --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/fydetab-duo.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc +PLATFORM_NAME=FydetabDuo +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/h88k.conf b/local/UEFI/edk2-rk3588-master/configs/h88k.conf new file mode 100644 index 0000000..cb71fdc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/h88k.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc +PLATFORM_NAME=H88K +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/indiedroid-nova.conf b/local/UEFI/edk2-rk3588-master/configs/indiedroid-nova.conf new file mode 100644 index 0000000..e625278 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/indiedroid-nova.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc +PLATFORM_NAME=IndiedroidNova +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/itx-3588j.conf b/local/UEFI/edk2-rk3588-master/configs/itx-3588j.conf new file mode 100644 index 0000000..f7c6aa9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/itx-3588j.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc +PLATFORM_NAME=ITX-3588J +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/nanopc-t6.conf b/local/UEFI/edk2-rk3588-master/configs/nanopc-t6.conf new file mode 100644 index 0000000..4661e0c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/nanopc-t6.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc +PLATFORM_NAME=NanoPC-T6 +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/nanopi-r6c.conf b/local/UEFI/edk2-rk3588-master/configs/nanopi-r6c.conf new file mode 100644 index 0000000..9901a4a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/nanopi-r6c.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc +PLATFORM_NAME=NanoPi-R6C +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/nanopi-r6s.conf b/local/UEFI/edk2-rk3588-master/configs/nanopi-r6s.conf new file mode 100644 index 0000000..428af0e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/nanopi-r6s.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc +PLATFORM_NAME=NanoPi-R6S +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/orangepi-5.conf b/local/UEFI/edk2-rk3588-master/configs/orangepi-5.conf new file mode 100644 index 0000000..d33b89b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/orangepi-5.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc +PLATFORM_NAME=OrangePi5 +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/orangepi-5plus.conf b/local/UEFI/edk2-rk3588-master/configs/orangepi-5plus.conf new file mode 100644 index 0000000..10eaf0a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/orangepi-5plus.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.dsc +PLATFORM_NAME=OrangePi5Plus +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/r58-mini.conf b/local/UEFI/edk2-rk3588-master/configs/r58-mini.conf new file mode 100644 index 0000000..d62060e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/r58-mini.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc +PLATFORM_NAME=R58-Mini +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/r58x.conf b/local/UEFI/edk2-rk3588-master/configs/r58x.conf new file mode 100644 index 0000000..06fe1bb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/r58x.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc +PLATFORM_NAME=R58X +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/roc-rk3588s-pc.conf b/local/UEFI/edk2-rk3588-master/configs/roc-rk3588s-pc.conf new file mode 100644 index 0000000..52ee539 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/roc-rk3588s-pc.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc +PLATFORM_NAME=ROC-RK3588S-PC +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/rock-5-itx.conf b/local/UEFI/edk2-rk3588-master/configs/rock-5-itx.conf new file mode 100644 index 0000000..56dbf4e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/rock-5-itx.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc +PLATFORM_NAME=ROCK5ITX +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/rock-5a.conf b/local/UEFI/edk2-rk3588-master/configs/rock-5a.conf new file mode 100644 index 0000000..60aed61 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/rock-5a.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc +PLATFORM_NAME=ROCK5A +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/rock-5b.conf b/local/UEFI/edk2-rk3588-master/configs/rock-5b.conf new file mode 100644 index 0000000..cef4eb6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/rock-5b.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.dsc +PLATFORM_NAME=ROCK5B +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/rock-5bplus.conf b/local/UEFI/edk2-rk3588-master/configs/rock-5bplus.conf new file mode 100644 index 0000000..4bdd94a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/rock-5bplus.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc +PLATFORM_NAME=ROCK5BPlus +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/configs/station-m3.conf b/local/UEFI/edk2-rk3588-master/configs/station-m3.conf new file mode 100644 index 0000000..232df39 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/configs/station-m3.conf @@ -0,0 +1,3 @@ +DSC_FILE=edk2-rockchip/Platform/StationPC/StationM3/StationM3.dsc +PLATFORM_NAME=StationM3 +SOC=RK3588 diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md new file mode 100644 index 0000000..716d477 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md @@ -0,0 +1,20 @@ +# Rockchip Platform Device Trees +## Sources +* + * Updated to `rk-6.1-rkr1` branch, currently called `vendor` branch in armbian/build + +* roc-rk3588s-pc: + +* itx-3588j: + (note: in the dtb given here, the builtin bootargs in the source above were commented out + before building. Not sure if that was a necessary step - SS) + +* rk3588-firefly-aio-3588q: + +* rk3588-rock-5b-plus: + +* rk3588s-fydetab-duo: + (note: dtb taken from the `noble` branch which is based on the rockchip 6.1 rkr3 bsp kernel) + +## License +SPDX-License-Identifier: GPL-2.0-only diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/itx-3588j.dtb b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/itx-3588j.dtb new file mode 100644 index 0000000000000000000000000000000000000000..7b2e01690bf6c1a91833b6aa1d15e39753443293 GIT binary patch literal 168063 zcmeEv37lm`b^g8Gv+pwu11jQUQ3svJ^fGJQ+F=nCbp+gqrg{C|>*?q8^61yyGeb}t zL<5Qf#tk)!LJ|>0#SJ$c1rY@m;|7U|Ym6vK$X`Sg0sr53>Qvpj%iFqpz=itt?b=SA zbLyN^r|MSSd*5x#ANbFp4RH<$l-`%@;+qV2*WxPB%yf0sw*qdj;%aRZV0o%{RwGV7YY7n=1w~P*(a|*r7}9X_ZR>mgoWWsp;oRjO}xu-J!NCDR_V!?iq)Zg zU93Q`btids-KI+FmLYwb*4buk!}6C#<#U8XTBUEWRPO0QKmmfS zo3eGi@w$Tm^Vb{86GP?k(egy!V7Yt10kAFWUmdG2#_A72{ly!rmC@qF`0&PE)yfzc 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    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..48b6d03 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl @@ -0,0 +1,53 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C7" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI4" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PA7 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host2.asl") + + Scope (I2C7) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.Modules.fdf.inc new file mode 100644 index 0000000..edfaed1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-9tripod-linux.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc new file mode 100644 index 0000000..6d55c3a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc @@ -0,0 +1,116 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = IndiedroidNova + PLATFORM_VENDOR = Ameridroid + PLATFORM_GUID = 247fa541-ba0c-478e-ba76-4e00450f7f11 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # No status LED on this platform. + DEFINE RK_STATUS_LED_ENABLE = FALSE + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Indiedroid Nova" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"ameriDroid" + gRockchipTokenSpaceGuid.PcdFamilyName|"Indiedroid" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://indiedroid.us" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-9tripod-linux" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x7 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..0cef780 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,296 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + /* Do not override, set by earlier boot stages. */ +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + break; + case 4: + GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3 + break; + case 5: + GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0 + GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0 + break; + case 6: + GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3 + GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* Set GPIO4 PA5 output high to enable USB-C VBUS */ + GpioPinWrite (4, GPIO_PIN_PA5, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset to gpio output mode */ + if(Segment == PCIE_SEGMENT_PCIE20L2) { // RTL8111 + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* nothing to power on */ +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER2, + .ChannelID = PWM_CHANNEL3, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM2_CH3 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (4, GPIO_PIN_PB4, 0xB); // PWM11_IR_M1 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + // No controllable LEDs on this platform +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + // No controllable LEDs on this platform +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + GpioPinSetFunction(4, GPIO_PIN_PA7, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc new file mode 100644 index 0000000..656ef89 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc new file mode 100644 index 0000000..a09f125 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc @@ -0,0 +1,31 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = AIO-3588Q + PLATFORM_VENDOR = Firefly + PLATFORM_GUID = 400f8259-7664-47df-b375-8ba262e4867e + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + + # + # Platform based on AIO-3588Q board + # +!include Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc new file mode 100644 index 0000000..e14a3e8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc @@ -0,0 +1,134 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # PCA9555 GPIO extender support + # I2C location configured by PCDs below. + # + DEFINE RK_PCA9555_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"AIO-3588Q" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly" + gRockchipTokenSpaceGuid.PcdFamilyName|"AIO" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/core/icore3588q" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"aio-3588q" + + # I2C + # i2c0: pc9202@3c, rk8602@42, rk8603@43 + # i2c1: rk8602@42 (npu) + # i2c3: es8388@11, XC7160b@1b, gc2053b@37, gc2093b@7e + # i2c6: pca9555@20, pca9555@21, fusb302@22, hym8563@51 + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x42, 0x11, 0x51, 0x20, 0x21, 0x22 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x3, 0x6, 0x6, 0x6, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + gRockchipTokenSpaceGuid.PcdPca9555Address|0x21 + gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x47 + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x4f + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf + + # Hack to enable use of PCA9555 during PCIe initialization. + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { + + RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf + } diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..21b5dea --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl @@ -0,0 +1,55 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C3" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC4 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac0.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C3) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..8c130ad --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,460 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +EFI_STATUS +EFIAPI +GetPca9555Protocol ( + IN OUT PCA95XX_PROTOCOL **Pca95xxProtocl + ) +{ + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + UINTN HandleCount; + + /* Locate Handles of all PCA95XX_PROTOCOL producers */ + Status = gBS->LocateHandleBuffer (ByProtocol, + &gPca95xxProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__)); + return Status; + } + + DEBUG ((DEBUG_INFO, + "%a: got %d PCA95XX_PROTOCOLs\n", + __FUNCTION__, + HandleCount)); + + /* + * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute + * the consumer is not obliged to call CloseProtocol. + */ + Status = gBS->OpenProtocol (HandleBuffer[0], + &gPca95xxProtocolGuid, + (VOID **)Pca95xxProtocl, + HandleBuffer[0], + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + + return Status; +} + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + /* Do not override, set by earlier boot stages. */ +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 0: + /* gmac0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_RXD2, GMAC0_RXD3 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; // GMAC0_RXCLK, GMAC0_TXD2, GMAC0_TXD3, GMAC0_TXCLK + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_TXD0, GMAC0_TXD1 + BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; // GMAC0_TXEN, GMAC0_RXD0, GMAC0_RXD1 + BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; // GMAC0_RXDV_CRS, GMAC0_MCLKINOUT + BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; // GMAC0_MDC, GMAC0_MDIO + + /* phy0 reset */ + GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT); + break; + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */ + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */ + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */ + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */ + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 0: + /* phy0 reset */ + GpioPinWrite (3, GPIO_PIN_PC7, !Enable); + break; + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB7, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); // I2C0_SCL_M2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); // I2C0_SDA_M2 + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PD4, 9); // I2C1_SCL_M2 + GpioPinSetFunction(0, GPIO_PIN_PD5, 9); // I2C1_SDA_M2 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); // I2C3_SCL_M0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); // I2C3_SDA_M0 + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); // I2C6_SCL_M0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); // I2C6_SDA_M0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + /* On Firefly AIO-3588Q this is controlled via the PCA9555. */ + Status = GetPca9555Protocol(&Pca95xxProtocol); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "UsbPortPowerEnable failed to get PCA9555! (%d)\n", Status)); + } else { + /* USB-C */ + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 12, /* vbus5v0_typec_pwr_en */ + GPIO_MODE_OUTPUT_0 + ); + + gBS->Stall(1200000); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 12, /* vbus5v0_typec_pwr_en */ + GPIO_MODE_OUTPUT_1 + ); + + /* other USB stuff */ + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 5, /* vcc5v0_host */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 4, /* vcc_hub_reset */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 6, /* vcc_hub3_reset */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 7, /* vcc5v0_host3 */ + GPIO_MODE_OUTPUT_1 + ); + } +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); // PCIE30X4_PERSTN_M1 + GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); // vcc3v3_pcie30 + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PC6, Enable); // vcc3v3_pcie30 + break; + case PCIE_SEGMENT_PCIE20L0: + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + switch (Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); // PCIE30X4_PERSTN_M1 + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (1, GPIO_PIN_PB4, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + Status = GetPca9555Protocol(&Pca95xxProtocol); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "PciePeReset(L2) failed to get PCA9555! (%d)\n", Status)); + } else { + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 14, /* PCA_IO1_6 */ + Enable ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1 + ); + } + break; + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER3, + .ChannelID = PWM_CHANNEL3, + .PeriodNs = 50000, + .DutyNs = 50000, + .Polarity = FALSE, +}; // PWM15 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (1, GPIO_PIN_PC6, 0xB); // PWM15_IR_M2 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + GpioPinWrite (3, GPIO_PIN_PB2, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PB2, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); // headphone enable + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetFunction (1, GPIO_PIN_PC4, 0); // headphone detect +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..8becb63 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,38 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Protocols] + gPca95xxProtocolGuid + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf new file mode 100644 index 0000000..6c686c3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf @@ -0,0 +1,42 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Protocols] + gPca95xxProtocolGuid + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c + +# Hack to enable use of PCA9555 during PCIe initialization. +[Depex] + gPca95xxProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.bmp 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protocol. + + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    + Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..1a55cb5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..0fa03f6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl @@ -0,0 +1,41 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac0.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc new file mode 100644 index 0000000..1af29d9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc @@ -0,0 +1,19 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2023, Shimrra Shai +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/itx-3588j.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc new file mode 100644 index 0000000..272e886 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc @@ -0,0 +1,34 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2023, Shimrra Shai +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ITX-3588J + PLATFORM_VENDOR = Firefly + PLATFORM_GUID = db88a604-ec99-4d39-84d4-af4fa5b5e757 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + + # + # Platform based on ITX-3588J board + # +!include Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc + + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc new file mode 100644 index 0000000..2cb3d96 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc @@ -0,0 +1,120 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2023, Shimrra Shai +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # PCA9555 GPIO extender support + # I2C location configured by PCDs below. + # + DEFINE RK_PCA9555_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"ITX-3588J" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly" + gRockchipTokenSpaceGuid.PcdFamilyName|"ITX" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/industry/itx3588j" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"itx-3588j" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x21, 0x22 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + gRockchipTokenSpaceGuid.PcdPca9555Address|0x21 + gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x45 + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42 + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..cea6bd3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,511 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +EFI_STATUS +EFIAPI +GetPca9555Protocol ( + IN OUT PCA95XX_PROTOCOL **Pca95xxProtocl + ) +{ + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + UINTN HandleCount; + UINTN Index; + + /* Locate Handles of all PCA95XX_PROTOCOL producers */ + Status = gBS->LocateHandleBuffer (ByProtocol, + &gPca95xxProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__)); + return Status; + } + + DEBUG ((DEBUG_INFO, + "%a: got %d PCA95XX_PROTOCOLs\n", + __FUNCTION__, + HandleCount)); + + /* + * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute + * the consumer is not obliged to call CloseProtocol. + */ + Status = gBS->OpenProtocol (HandleBuffer[0], + &gPca95xxProtocolGuid, + (VOID **)Pca95xxProtocl, + HandleBuffer[0], + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + + return Status; +} + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 0: + /* gmac0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; + + /* phy0 reset */ + GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT); + break; + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */ + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */ + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */ + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */ + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 0: + /* phy0 reset */ + GpioPinWrite (3, GPIO_PIN_PC7, !Enable); + break; + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB7, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + /* io mux M2 */ + PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300; + PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030; + break; + case 1: + /* io mux */ + //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990; + //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880; + break; + case 2: + /* io mux */ + BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000; + BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009; + PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000; + PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + break; + case 3: + break; + case 4: + break; + case 5: + break; + case 6: + /* io mux M0 */ + BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000; + BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009; + PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000; + PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + /* On Firefly ITX-3588J this is controlled via the PCA9555. */ + Status = GetPca9555Protocol(&Pca95xxProtocol); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status)); + } else { + /* USB-C */ + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 12, /* vbus5v0_typec_pwr_en */ + GPIO_MODE_OUTPUT_0 + ); + + gBS->Stall(1200000); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 12, /* vbus5v0_typec_pwr_en */ + GPIO_MODE_OUTPUT_1 + ); + + /* other USB stuff */ + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 5, /* vcc5v0_host */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 4, /* vcc_hub_reset */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 6, /* vcc_hub3_reset */ + GPIO_MODE_OUTPUT_1 + ); + + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 7, /* vcc5v0_host3 */ + GPIO_MODE_OUTPUT_1 + ); + } +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + if(Segment == PCIE_SEGMENT_PCIE30X4) { + /* reset */ + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + /* vcc3v3_pcie30 */ + GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE30X4) { + /* vcc3v3_pcie30 */ + GpioPinWrite (2, GPIO_PIN_PC5, Enable); + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE30X4) { + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER2, + .ChannelID = PWM_CHANNEL3, + .PeriodNs = 50000, + .DutyNs = 50000, + .Polarity = TRUE, +}; // PWM2_CH3 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + Status = GetPca9555Protocol(&Pca95xxProtocol); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status)); + } else { + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 11, /* vcc_fan_pwr_en */ + GPIO_MODE_OUTPUT_1 + ); + } +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + Status = GetPca9555Protocol(&Pca95xxProtocol); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status)); + } else { + /* (SS) NB: (TBA?) It doesn't *appear* we can regulate the fan speed, + * only power up/down, but I could be wrong + */ + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 11, /* vcc_fan_pwr_en */ + (Percentage > 0) ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0 + ); + } +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Activate power LED only */ + GpioPinWrite (1, GPIO_PIN_PB3, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PB3, GPIO_PIN_OUTPUT); + +#if 0 + /* Red off, Green for status, Blue for power */ + GpioPinWrite (3, GPIO_PIN_PB2, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); + GpioPinWrite (3, GPIO_PIN_PC0, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT); + GpioPinWrite (1, GPIO_PIN_PD5, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PD5, GPIO_PIN_OUTPUT); +#endif +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + /* (SS) does not seem to work and causes errors on I2C complaining + * about something being too high + */ +#if 0 + EFI_STATUS Status = EFI_SUCCESS; + PCA95XX_PROTOCOL *Pca95xxProtocol; + + /* On Firefly ITX-3588J this is controlled via the PCA9555. */ + Status = GetPca9555Protocol(&Pca95xxProtocol); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status)); + } else { + Pca95xxProtocol->GpioProtocol.Set( + &Pca95xxProtocol->GpioProtocol, + 3, /* user_led */ + Enable ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0 + ); + } +#endif +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..8becb63 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,38 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Protocols] + gPca95xxProtocolGuid + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..2815d7f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl @@ -0,0 +1,53 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C3" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PA6 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host2.asl") + + Scope (I2C3) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..5a66f79 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,368 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + + /* phy1 reset */ + GpioPinSetDirection (0, GPIO_PIN_PD3, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 1: + /* phy1 reset */ + GpioPinWrite (0, GPIO_PIN_PD3, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0 + break; + case 4: + GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3 + break; + case 5: + break; + case 6: + GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3 + GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* Enable USB-C VBUS */ + GpioPinWrite (1, GPIO_PIN_PB1, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PB1, GPIO_PIN_OUTPUT); + + // + // Power cycle vcc5v0_host as some USB 3.0 devices won't enumerate + // during boot otherwise. + // + GpioPinSetDirection (1, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + GpioPinWrite (1, GPIO_PIN_PB6, FALSE); + gBS->Stall (1200000); + GpioPinWrite (1, GPIO_PIN_PB6, TRUE); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + if(Segment == PCIE_SEGMENT_PCIE20L2) { // M.2 M Key + /* reset */ + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + /* vcc3v3_pcie20 */ + GpioPinSetDirection (1, GPIO_PIN_PD7, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + /* vcc3v3_pcie20 */ + GpioPinWrite (1, GPIO_PIN_PD7, Enable); + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER2, + .ChannelID = PWM_CHANNEL3, + .PeriodNs = 50000, + .DutyNs = 50000, + .Polarity = TRUE, +}; // PWM2_CH3 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (3, GPIO_PIN_PD5, 0xB); // PWM11_IR_M3 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Red off, Green for status, Blue for power */ + GpioPinWrite (3, GPIO_PIN_PB2, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); + GpioPinWrite (3, GPIO_PIN_PC0, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT); + GpioPinWrite (1, GPIO_PIN_PD5, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PD5, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PC0, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + GpioPinSetFunction(1, GPIO_PIN_PA6, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.Modules.fdf.inc new file mode 100644 index 0000000..783d147 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/roc-rk3588s-pc.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc new file mode 100644 index 0000000..555b9d2 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc @@ -0,0 +1,45 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ROC-RK3588S-PC + PLATFORM_VENDOR = Firefly + PLATFORM_GUID = d6741299-c347-4115-9f1a-1207fdf16ab0 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + + # + # Platform based on ROC-RK3588S-PC board + # +!include Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"ROC-RK3588S-PC" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly" + gRockchipTokenSpaceGuid.PcdFamilyName|"ROC" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/industry/rocrk3588spc" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"roc-rk3588s-pc" diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc new file mode 100644 index 0000000..b3dc9a9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc @@ -0,0 +1,107 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdBoardName|"ROC-RK3588S-PC" + gRockchipTokenSpaceGuid.PcdBoardVendorName|"Firefly" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2, 0x3 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x2 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x43 + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.bmp b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.bmp new file mode 100644 index 0000000000000000000000000000000000000000..bd5021dd0b29323c80d7645879353e7be82a9f73 GIT binary patch literal 148634 zcmeI52e{P4+JNc3cj>+N-h1!eMp3YV0*9)opj^F*UKB;)Dn(HNvHdDuIp@#>lrB|3 ziqcd-iqb(8{og|*hLqWCHk;i&ne#-MOeRyl%)C40n{Qfnnb|s3ilo1~{8yg;{x4;U z6r=e!Wr_m)U->IlHARY~|8D&CUGlKJ!XbgeP0QVovHVv`KuRF`B@hk_$T*RJWMTAI ze)~C0lQCW90@-tv%9pF$Ejh~;$XOjWJvo@yl%LNkUUqpyJ_?1 zZ|n5V13f++*(YI~T3dQ98r9|9p)IH0Sz~DHf(^^0%a+lNG-VtSlz{qerNdnbgo%a4 z+g5ffpLB8TRJ?{0y1SBMkB{Th=g6c>v3MKTij%Ea9$n;)Z?hK3RrTKH9pAd&e!;se ze6aS&_PNU25~<^i$rr;Z0sCKDh73vqVPaviR+WOvh9EFwJv%k4{-a$5k=TFK?So-P z78Yw&(S8hqkiFx_W-FT8PI1Ix7zo!I(T+Z!XX5uooe^DWFX8{?YruO8hiY&|SNF9nq??tuY7u9}Dc!ARx~v&=k=wk5SnXyFRzH28 z#BsHTw}pSmhhnyRxu4aLnO8t2D=Q`1R|WH|HCGzYSQ{8RQX-q#kijA?0ksN*&(UYe zIIiAYiDP@2T}h9whv}1ylpQ@_As}fq>89RHP#@937&&*vLT&$hcTlOQfdh__nF`f) z&eV79IGl}y?7;xRu3z!w`uY6HgQtGj zef+x}$M>u`u<7%?D;IwAzgITRd-AJShpu?K?~+H_$H%o=JgjZ}a9GiCc#q{c!2-KCX=VzmuKGUaM z@4CzmGMdhiD+|MCCJ6J_D$WdOiz#=oxU7AJA$GYw*LQy1Rv&-*izq2Zx|PfH?MOiT z83Vd|CXVft5J#sCCf&AV{J2#w%=mi2XM2`!`eDbx(?9%j@yw;GSFZhe?ax2|{43-? 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All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl new file mode 100755 index 0000000..405ac5e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl @@ -0,0 +1,44 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + // include ("Usb3Host2.asl") + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..f27cee8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,354 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0 + break; + case 4: + break; + case 5: + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */ + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + + /* Set GPIO4 PC6 output high to power the 4G/LTE module */ + GpioPinWrite (4, GPIO_PIN_PC6, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); + + /* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */ + GpioPinWrite (1, GPIO_PIN_PD2, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable on-board LED1\n")); + // GpioPinWrite (2, GPIO_PIN_PC0, TRUE); + // GpioPinSetDirection (2, GPIO_PIN_PC0, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L0: // rtl8152b + GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L1: // m.2 a+e key + GpioPinSetDirection (4, GPIO_PIN_PC2, GPIO_PIN_OUTPUT); + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L2: //rtl8152b + GpioPinSetDirection (4, GPIO_PIN_PA4, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* output high to enable power */ + + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (2, GPIO_PIN_PC5, Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (4, GPIO_PIN_PC2, Enable); + break; + case PCIE_SEGMENT_PCIE20L2: + break; + default: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (4, GPIO_PIN_PB3, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (4, GPIO_PIN_PA2, !Enable); + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinWrite (4, GPIO_PIN_PA4, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (2, GPIO_PIN_PB7, FALSE); + GpioPinSetDirection (2, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (2, GPIO_PIN_PB7, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + GpioPinSetFunction(1, GPIO_PIN_PC4, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..ec569ea --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,34 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.Modules.fdf.inc new file mode 100644 index 0000000..25edcdb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-nanopc-t6.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc new file mode 100644 index 0000000..926b9a4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc @@ -0,0 +1,116 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Molly Sophia +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = NanoPC-T6 + PLATFORM_VENDOR = FriendlyElec + PLATFORM_GUID = e5022309-24e1-46e0-9d40-dcbc7293e609 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"NanoPC T6" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"FriendlyElec" + gRockchipTokenSpaceGuid.PcdFamilyName|"NanoPi 6" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-nanopc-t6" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # NanoPC T6 has two 2.5 GBE wired to the first two PCIE2 ports, while the third one is wired to m.2 a+e key + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..63c8600 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl @@ -0,0 +1,39 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588S", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + //include ("Spi.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..6525824 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,342 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB7, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0 + break; + case 4: + break; + case 5: + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* Set GPIO4 PB5 (USB_HOST_PWREN) output high to power USB ports */ + GpioPinWrite (4, GPIO_PIN_PB5, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT); + + /* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */ + GpioPinWrite (1, GPIO_PIN_PD2, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable on-board LED WAN\n")); + // GpioPinWrite (1, GPIO_PIN_PC2, TRUE); + // GpioPinSetDirection (1, GPIO_PIN_PC2, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable on-board LED LAN\n")); + // GpioPinWrite (1, GPIO_PIN_PC3, TRUE); + // GpioPinSetDirection (1, GPIO_PIN_PC3, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable on-board LED1\n")); + // GpioPinWrite (1, GPIO_PIN_PC4, TRUE); + // GpioPinSetDirection (1, GPIO_PIN_PC4, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE20L1: // RTL8152BG + // GPIO1_A7_u - PCIE20x1_1_PERSTn_M2 + GpioPinSetDirection (1, GPIO_PIN_PA7, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L2: // M.2 SSD + // GPIO3_D1_d - PCIE20X1_2_PERSTN_M0 + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* nothing to power on */ +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (1, GPIO_PIN_PA7, !Enable); + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (1, GPIO_PIN_PC1, FALSE); + GpioPinSetDirection (1, GPIO_PIN_PC1, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (1, GPIO_PIN_PC1, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..ec569ea --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,34 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.Modules.fdf.inc new file mode 100644 index 0000000..67fe4d8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.Modules.fdf.inc @@ -0,0 +1,19 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2023, Sergey Tyuryukanov +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6c.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc new file mode 100644 index 0000000..268a600 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc @@ -0,0 +1,114 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Molly Sophia +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2023, Sergey Tyuryukanov +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = NanoPi-R6C + PLATFORM_VENDOR = FriendlyElec + PLATFORM_GUID = e5022309-24e1-46e0-9d40-dcbc7293e609 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"NanoPi R6C" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"FriendlyElec" + gRockchipTokenSpaceGuid.PcdFamilyName|"NanoPi" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-nanopi-r6c" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl new file mode 100755 index 0000000..4caa5d5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/AcpiTables/Dsdt.asl @@ -0,0 +1,39 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host2.asl") + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..403a082 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,329 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + /* Do not override, set by earlier boot stages. */ +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB7, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0 + break; + case 4: + break; + case 5: + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* Set GPIO4 PB5 (USB_HOST_PWREN) output high to power USB ports */ + GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PB5, TRUE); + + /* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */ + GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + GpioPinWrite (1, GPIO_PIN_PD2, TRUE); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* found info from nanopi r6s dtb */ + switch(Segment) { + case PCIE_SEGMENT_PCIE20L1: // rtl8152b + // PCIE20x1_1_PERSTn_M2 + GpioPinSetDirection (1, GPIO_PIN_PA7, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L2: // rtl8152b + // PCIE20x1_2_PERSTn_M0 + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* nothing to power on */ +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE20L1: // rtl8152b + GpioPinWrite (1, GPIO_PIN_PA7, !Enable); + break; + case PCIE_SEGMENT_PCIE20L2: // rtl8152b + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (1, GPIO_PIN_PC1, FALSE); + GpioPinSetDirection (1, GPIO_PIN_PC1, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (1, GPIO_PIN_PC1, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..ec569ea --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,34 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.Modules.fdf.inc new file mode 100644 index 0000000..6b82ba7 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6s.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc new file mode 100644 index 0000000..fb28705 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc @@ -0,0 +1,112 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Molly Sophia +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = NanoPi-R6S + PLATFORM_VENDOR = FriendlyElec + PLATFORM_GUID = 4a2e5415-53e2-48b5-9a4f-3b34d9e8ef6f + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"NanoPi R6S" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"FriendlyElec" + gRockchipTokenSpaceGuid.PcdFamilyName|"NanoPi 6" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6S" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-nanopi-r6s" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..689c760 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/AcpiTables/Dsdt.asl @@ -0,0 +1,60 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C7" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC0 + +// +// WORKAROUND: +// SDMMC may be unreliable at UHS-I speeds. +// +#define SDMMC_CAP_DDR50 0 +#define SDMMC_CAP_SDR50 0 +#define SDMMC_CAP_SDR104 0 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host2.asl") + + Scope (I2C7) { + include ("Es8388.asl") + } + } +} diff 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All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.Modules.fdf.inc new file mode 100644 index 0000000..25791fc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023-2024, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # TODO: Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-fydetab-duo.dtb + } + + # Splash screen logo + INF $(PLATFORM_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc new file mode 100644 index 0000000..9604b88 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc @@ -0,0 +1,113 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023-2024, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = FydetabDuo + PLATFORM_VENDOR = FydeInnovations + PLATFORM_GUID = de3232fb-1716-4f63-a8fe-67a623ae5297 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # No HDMI output on this platform + DEFINE RK_DW_HDMI_QP_ENABLE = FALSE + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Fydetab Duo" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Fyde Innovations" + gRockchipTokenSpaceGuid.PcdFamilyName|"Fydetab" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://fydetabduo.com/" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-fydetab-duo" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x50, 0x51, 0x11 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6, 0x7 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # SD card detect signal is inverted + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(PLATFORM_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/CsotDsiPanel.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/CsotDsiPanel.c new file mode 100644 index 0000000..f0bedf1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/CsotDsiPanel.c @@ -0,0 +1,171 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include + +STATIC UINT8 mCsotDsiInitSequence[] = { + 0x0a, 0x31, 0x58, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x0A, 0x00, 0x06, 0x40, 0x00, 0x28, 0x06, 0x40, 0x06, 0x40, 0x02, 0x00, 0x04, 0x21, 0x00, 0x20, 0x05, 0xD0, 0x00, 0x16, 0x00, 0x0C, 0x02, 0x77, 0x00, 0xDA, 0x18, 0x00, 0x10, 0xE0, 0x03, 0x0C, 0x20, 0x00, 0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B, 0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, 0x40, 0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8, 0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6, 0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0x74, + 0x39, 0x00, 0x06, 0xB9, 0x83, 0x12, 0x1A, 0x55, 0x00, + 0x39, 0x00, 0x03, 0x51, 0x08, 0x00, + 0x39, 0x00, 0x02, 0x53, 0x24, + 0x39, 0x00, 0x1D, 0xB1, 0x1C, 0x6B, 0x6B, 0x27, 0xE7, 0x00, 0x1B, 0x12, 0x20, 0x20, 0x2D, 0x2D, 0x1F, 0x33, 0x31, 0x40, 0xCD, 0xFF, 0x1A, 0x05, 0x15, 0x98, 0x00, 0x88, 0xF9, 0xFF, 0xFF, 0xCF, + 0x39, 0x00, 0x12, 0xB2, 0x00, 0x6A, 0x40, 0x00, 0x00, 0x14, 0x6E, 0x40, 0x73, 0x02, 0x80, 0x21, 0x21, 0x00, 0x00, 0x10, 0x27, + 0x39, 0x00, 0x2D, 0xB4, 0x64, 0x00, 0x08, 0x7F, 0x08, 0x7F, 0x00, 0x62, 0x01, 0x72, 0x01, 0x72, 0x00, 0x60, 0x00, 0x00, 0x0A, 0x08, 0x00, 0x29, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xFF, 0x14, 0x00, 0x00, 0x0F, 0x0F, 0x2D, 0x2D, + 0x39, 0x00, 0x04, 0xB6, 0x8F, 0x8F, 0x03, + 0x39, 0x00, 0x03, 0xBC, 0x06, 0x02, + 0x39, 0x00, 0x07, 0xC0, 0x34, 0x34, 0x44, 0x00, 0x08, 0xD8, + 0x39, 0x00, 0x06, 0xC9, 0x00, 0x1E, 0x80, 0xA5, 0x01, + 0x39, 0x00, 0x07, 0xCB, 0x00, 0x13, 0x38, 0x00, 0x0B, 0x27, + 0x39, 0x00, 0x02, 0xCC, 0x02, + 0x39, 0x00, 0x02, 0xD1, 0x07, + 0x39, 0x00, 0x29, 0xD3, 0x00, 0xC0, 0x08, 0x08, 0x08, 0x04, 0x04, 0x04, 0x14, 0x02, 0x07, 0x07, 0x07, 0x31, 0x13, 0x12, 0x12, 0x12, 0x03, 0x03, 0x03, 0x32, 0x10, 0x11, 0x00, 0x11, 0x32, 0x10, 0x03, 0x00, 0x03, 0x32, 0x10, 0x03, 0x00, 0x03, 0x00, 0x00, 0xFF, 0x00, + 0x39, 0x00, 0x31, 0xD5, 0x19, 0x19, 0x18, 0x18, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, 0x07, 0x07, 0x00, 0x00, 0x01, 0x01, 0x18, 0x18, 0x40, 0x40, 0x20, 0x20, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x18, 0x18, 0x2F, 0x2F, 0x31, 0x31, 0x2F, 0x2F, 0x31, 0x31, 0x18, 0x18, 0x41, 0x41, 0x41, 0x41, + 0x39, 0x00, 0x31, 0xD6, 0x40, 0x40, 0x18, 0x18, 0x05, 0x05, 0x04, 0x04, 0x03, 0x03, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00, 0x07, 0x07, 0x06, 0x06, 0x18, 0x18, 0x19, 0x19, 0x20, 0x20, 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x18, 0x18, 0x2F, 0x2F, 0x31, 0x31, 0x2F, 0x2F, 0x31, 0x31, 0x18, 0x18, 0x41, 0x41, 0x41, 0x41, + 0x39, 0x00, 0x40, 0xE1, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 0x0A, 0x00, 0x06, 0x40, 0x00, 0x28, 0x06, 0x40, 0x06, 0x40, 0x02, 0x00, 0x04, 0x21, 0x00, 0x20, 0x05, 0xD0, 0x00, 0x16, 0x00, 0x0C, 0x02, 0x77, 0x00, 0xDA, 0x18, 0x00, 0x10, 0xE0, 0x03, 0x0C, 0x20, 0x00, 0x06, 0x0B, 0x0B, 0x33, 0x0E, 0x1C, 0x2A, 0x38, 0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7B, 0x7D, 0x7E, 0x01, 0x02, 0x01, 0x00, 0x09, + 0x39, 0x00, 0x0C, 0xE7, 0x06, 0x14, 0x14, 0x1A, 0x23, 0x38, 0x00, 0x23, 0x5D, 0x02, 0x02, + 0x39, 0x00, 0x02, 0xBD, 0x01, + 0x39, 0x00, 0x04, 0xB1, 0x01, 0x23, 0x00, + 0x39, 0x00, 0x25, 0xD8, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, 0x20, 0x00, 0x02, 0x22, 0x00, 0x00, + 0x39, 0x00, 0x1A, 0xE1, 0x40, 0x09, 0xBE, 0x19, 0xFC, 0x19, 0xFA, 0x19, 0xF8, 0x1A, 0x38, 0x1A, 0x78, 0x1A, 0xB6, 0x2A, 0xF6, 0x2B, 0x34, 0x2B, 0x74, 0x3B, 0x74, 0x6B, 0xF4, + 0x39, 0x00, 0x0D, 0xE7, 0x02, 0x00, 0x40, 0x01, 0x84, 0x13, 0xBE, 0x14, 0x48, 0x00, 0x04, 0x26, + 0x39, 0x00, 0x08, 0xCB, 0x1F, 0x55, 0x03, 0x28, 0x0D, 0x08, 0x0A, + 0x39, 0x00, 0x02, 0xBD, 0x02, + 0x39, 0x00, 0x0D, 0xD8, 0xAF, 0xFF, 0xFA, 0xFA, 0xBF, 0xEA, 0xAF, 0xFF, 0xFA, 0xFA, 0xBF, 0xEA, + 0x39, 0x00, 0x23, 0xE7, 0x01, 0x05, 0x01, 0x03, 0x01, 0x03, 0x04, 0x02, 0x02, 0x24, 0x00, 0x24, 0x81, 0x02, 0x40, 0x00, 0x29, 0x60, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x39, 0x00, 0x02, 0xBD, 0x03, + 0x39, 0x00, 0x19, 0xD8, 0xAA, 0xAA, 0xAA, 0xAB, 0xBF, 0xEA, 0xAA, 0xAA, 0xAA, 0xAB, 0xBF, 0xEA, 0xAF, 0xFF, 0xFA, 0xFA, 0xBF, 0xEA, 0xAF, 0xFF, 0xFA, 0xFA, 0xBF, 0xEA, + 0x39, 0x00, 0x03, 0xE1, 0x01, 0x3F, + 0x39, 0x00, 0x02, 0xBD, 0x00, + 0x39, 0x00, 0x2F, 0xE0, 0x00, 0x13, 0x30, 0x36, 0x40, 0x78, 0x8B, 0x94, 0x95, 0x97, 0x94, 0x94, 0x91, 0x8F, 0x8F, 0x8B, 0x8A, 0x8C, 0x8E, 0xA6, 0xB7, 0x4D, 0x7F, 0x00, 0x13, 0x30, 0x36, 0x40, 0x78, 0x8B, 0x94, 0x95, 0x97, 0x94, 0x94, 0x91, 0x8F, 0x8F, 0x8B, 0x8A, 0x8C, 0x8E, 0xA6, 0xB7, 0x4D, 0x7F, + 0x39, 0x00, 0x05, 0xBA, 0x70, 0x03, 0xA8, 0x92, + 0x39, 0x00, 0x25, 0xD8, 0xEA, 0xAA, 0xAA, 0xAE, 0xAA, 0xAF, 0xEA, 0xAA, 0xAA, 0xAE, 0xAA, 0xAF, 0xE0, 0x00, 0x0A, 0x2E, 0x80, 0x2F, 0xE0, 0x00, 0x0A, 0x2E, 0x80, 0x2F, 0xE0, 0x00, 0x0A, 0x2E, 0x80, 0x2F, 0xE0, 0x00, 0x0A, 0x2E, 0x80, 0x2F, + 0x39, 0x00, 0x02, 0xBD, 0x00, + 0x39, 0x00, 0x02, 0xC1, 0x01, + 0x39, 0x00, 0x02, 0xBD, 0x01, + 0x39, 0x00, 0x3B, 0xC1, 0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x1F, 0x23, 0x27, 0x2B, 0x2F, 0x33, 0x37, 0x3B, 0x3F, 0x43, 0x47, 0x4B, 0x52, 0x5A, 0x62, 0x69, 0x71, 0x79, 0x81, 0x89, 0x91, 0x98, 0xA1, 0xA9, 0xB1, 0xB9, 0xC1, 0xCA, 0xD2, 0xDA, 0xE3, 0xEA, 0xF4, 0xF8, 0xF9, 0xFB, 0xFD, 0xFF, 0x16, 0xA4, 0x44, 0x16, 0x90, 0xE7, 0xF9, 0x71, 0xA0, 0xF3, 0x1F, 0x40, + 0x39, 0x00, 0x02, 0xBD, 0x02, + 0x39, 0x00, 0x3B, 0xC1, 0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0x24, 0x28, 0x2D, 0x31, 0x35, 0x39, 0x3D, 0x41, 0x45, 0x49, 0x4D, 0x55, 0x5D, 0x65, 0x6D, 0x75, 0x7D, 0x85, 0x8D, 0x94, 0x9C, 0xA4, 0xAC, 0xB4, 0xBC, 0xC4, 0xCC, 0xD4, 0xDC, 0xE4, 0xEC, 0xF4, 0xF8, 0xFA, 0xFC, 0xFE, 0xFF, 0x06, 0xAA, 0xFC, 0x5B, 0xFF, 0xFF, 0xA4, 0xF9, 0x86, 0xF9, 0x55, 0x40, + 0x39, 0x00, 0x02, 0xBD, 0x03, + 0x39, 0x00, 0x3B, 0xC1, 0x00, 0x04, 0x07, 0x0B, 0x0F, 0x13, 0x17, 0x1B, 0x1F, 0x23, 0x27, 0x2C, 0x30, 0x33, 0x38, 0x3C, 0x40, 0x44, 0x48, 0x4C, 0x53, 0x5B, 0x63, 0x6B, 0x72, 0x7A, 0x82, 0x89, 0x91, 0x99, 0xA1, 0xA9, 0xB1, 0xB9, 0xC1, 0xC9, 0xD1, 0xDA, 0xE2, 0xEA, 0xF3, 0xF6, 0xF9, 0xFA, 0xFE, 0xFF, 0x0F, 0x9A, 0xFC, 0x31, 0x40, 0xE4, 0xFB, 0xE9, 0xA3, 0xD9, 0x77, 0x00, + 0x39, 0x00, 0x02, 0xBD, 0x02, + 0x39, 0x00, 0x02, 0xBF, 0x72, + 0x39, 0x00, 0x02, 0xBD, 0x00, + 0x39, 0x00, 0x08, 0xBF, 0xFD, 0x00, 0x80, 0x9C, 0x10, 0x00, 0x80, + 0x39, 0x00, 0x02, 0xE9, 0xDE, + 0x39, 0x00, 0x04, 0xB1, 0xCC, 0x03, 0x00, + 0x39, 0x00, 0x02, 0xE9, 0x3F, + 0x39, 0x00, 0x07, 0xD0, 0x07, 0xC0, 0x08, 0x03, 0x11, 0x00, + 0x39, 0x00, 0x03, 0xB0, 0x00, 0x00, + 0x39, 0x00, 0x02, 0xE9, 0xCF, + 0x39, 0x00, 0x02, 0xBA, 0x03, + 0x39, 0x00, 0x02, 0xE9, 0x3F, + // 0x39, 0x00, 0x04, 0xB9, 0x83, 0x12, 0x1A, + // 0x39, 0x00, 0x02, 0xC7, 0x00, + // 0x39, 0x00, 0x02, 0xCF, 0xFF, + + 0x39, 0x00, 0x01, 0x11, + 0x39, 0x00, 0x01, 0x29, +}; + +EFI_STATUS +EFIAPI +CsotDsiPanelPrepare ( + IN ROCKCHIP_DSI_PANEL_PROTOCOL *This + ) +{ + /* vcc_lcd_en_pin */ + GpioPinWrite (4, GPIO_PIN_PA3, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PA3, GPIO_PIN_OUTPUT); + MicroSecondDelay (5 * 1000); + + /* avdd_lcd_gpio */ + GpioPinWrite (3, GPIO_PIN_PA7, TRUE); + GpioPinSetDirection (3, GPIO_PIN_PA7, GPIO_PIN_OUTPUT); + MicroSecondDelay (5 * 1000); + + /* avee_lcd_gpio */ + GpioPinWrite (3, GPIO_PIN_PA6, TRUE); + GpioPinSetDirection (3, GPIO_PIN_PA6, GPIO_PIN_OUTPUT); + MicroSecondDelay (5 * 1000); + + MicroSecondDelay (120 * 1000); + + /* lcd_rst_gpio (inverted) */ + GpioPinWrite (3, GPIO_PIN_PC6, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); + MicroSecondDelay (120 * 1000); + + /* lcd_rst_gpio (inverted) */ + GpioPinWrite (3, GPIO_PIN_PC6, TRUE); + MicroSecondDelay (120 * 1000); + + return EFI_SUCCESS; +} + +STATIC ROCKCHIP_DSI_PANEL_PROTOCOL mCsotDsiPanel = { + .DsiId = 0, + .DsiLaneRate = 676000, + .DsiLanes = 4, + .DsiFlags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET, + .DsiFormat = MIPI_DSI_FMT_RGB888, + .DscEnable = TRUE, + .SliceWidth = 1600, + .SliceHeight = 40, + .VersionMajor = 1, + .VersionMinor = 1, + + .InitSequence = mCsotDsiInitSequence, + .InitSequenceLength = ARRAY_SIZE (mCsotDsiInitSequence), + + .NativeMode = { + .CrtcId = 2, + .OscFreq = 275000000, + .Horizontal = { + .Resolution = 1600, + .Sync = 20, + .BackPorch = 40, + .FrontPorch = 60 + }, + .Vertical = { + .Resolution = 2560, + .Sync = 4, + .BackPorch = 18, + .FrontPorch = 112 + }, + .HsyncActive = 0, + .VsyncActive = 0, + .DenActive = 0, + .ClkActive = 0, + .VpsConfigModeID = 1 + }, + + .Prepare = CsotDsiPanelPrepare, +}; + +EFI_STATUS +EFIAPI +AttachCsotDsiPanel ( + VOID + ) +{ + EFI_HANDLE Handle = NULL; + + return gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gRockchipDsiPanelProtocolGuid, + &mCsotDsiPanel, + NULL + ); +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..1e85741 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,306 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + /* Do not override, set by earlier boot stages. */ +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + GpioPinSetFunction(3, GPIO_PIN_PB7, 9); //i2c3_scl_m1 + GpioPinSetFunction(3, GPIO_PIN_PC0, 9); //i2c3_sda_m1 + break; + case 4: + GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3 + break; + case 5: + GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3 + break; + case 6: + GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3 + GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset to gpio output mode */ + if(Segment == PCIE_SEGMENT_PCIE20L2) { // AP6275P Wi-Fi + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + + /* wifi_poweren_gpio */ + GpioPinSetDirection (0, GPIO_PIN_PC7, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + /* wifi_poweren_gpio */ + GpioPinWrite (0, GPIO_PIN_PC7, Enable); + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + } +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + GpioPinWrite (3, GPIO_PIN_PC2, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PC2, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PC2, Enable); +} + +extern +EFI_STATUS +EFIAPI +AttachCsotDsiPanel ( + VOID + ); + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + /* vcc_5v0_en */ + GpioPinWrite (4, GPIO_PIN_PA2, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + + GpioPinSetFunction(1, GPIO_PIN_PC0, 0); //jdet + + /* spk-con-gpio */ + GpioPinWrite (4, GPIO_PIN_PA5, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + + AttachCsotDsiPanel(); +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..4f05c41 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FydeInnovations/FydetabDuo/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,41 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + TimerLib + UefiBootServicesTableLib + +[Protocols] + gRockchipDsiPanelProtocolGuid + +[Sources.common] + RockchipPlatformLib.c + CsotDsiPanel.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.bmp 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b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.c new file mode 100644 index 0000000..2255b11 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.c @@ -0,0 +1,144 @@ +/** @file + Logo DXE Driver, install Edkii Platform Logo protocol. + + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    + Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl new file mode 100755 index 0000000..bfc7343 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/AcpiTables/Dsdt.asl @@ -0,0 +1,54 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C7" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD5 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac0.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C7) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/H88K.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/H88K.Modules.fdf.inc new file mode 100644 index 0000000..22f88e6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/H88K.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-hinlink-h88k.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc new file mode 100644 index 0000000..3a14a38 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc @@ -0,0 +1,121 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2022, Xilin Wu +# Copyright (c) 2023, Jianfeng Liu +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = H88K + PLATFORM_VENDOR = Hinlink + PLATFORM_GUID = 5ecd3024-77d5-47a2-8293-a963ac878d48 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"H88K" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Hinlink" + gRockchipTokenSpaceGuid.PcdFamilyName|"H88K" + gRockchipTokenSpaceGuid.PcdProductUrl|"http://www.hinlink.com/" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-hinlink-h88k" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2, 0x7 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x2 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44 + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..ff8a81e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,386 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 0: + /* gmac0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; + + /* phy0 reset */ + GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 0: + /* phy0 reset */ + GpioPinWrite (4, GPIO_PIN_PB3, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PB5, 9); //i2c1_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PB6, 9); //i2c1_sda_m0 + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0 + break; + case 4: + GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0 + GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0 + break; + case 5: + GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0 + GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0 + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */ + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + /* Set GPIO4 PB0 (USB_HUB_PWREN) output high to power USB ports */ + GpioPinSetDirection (4, GPIO_PIN_PA6, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PA6, FALSE); + MicroSecondDelay (100); + GpioPinWrite (4, GPIO_PIN_PA6, TRUE); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + GpioPinSetDirection (3, GPIO_PIN_PD5, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinSetDirection (0, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* output high to enable power */ + + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (3, GPIO_PIN_PD5, Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + break; + default: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (0, GPIO_PIN_PB0, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (4, GPIO_PIN_PA2, !Enable); + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinWrite (4, GPIO_PIN_PA5, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (3, GPIO_PIN_PB7, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PB7, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..015b7cf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Hinlink/H88K/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + TimerLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.c new file mode 100644 index 0000000..25e877c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.c @@ -0,0 +1,341 @@ +/** @file + * + * Khadas MCU platform driver + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "KhadasMcuDxe.h" + +STATIC CONST EFI_GUID I2cGuid = I2C_GUID; + +STATIC +EFI_STATUS +EFIAPI +KhadasMcuRead ( + IN CONST KHADAS_MCU_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length + ) +{ + EFI_STATUS Status; + EFI_I2C_REQUEST_PACKET *RequestPacket; + UINTN RequestPacketSize; + KHADAS_MCU_CONTEXT *KhadasMcuContext = KHADAS_MCU_FROM_PROTOCOL (This); + + ASSERT (KhadasMcuContext != NULL); + ASSERT (KhadasMcuContext->I2cIo != NULL); + + RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION) * 2; + RequestPacket = AllocateZeroPool (RequestPacketSize); + if (RequestPacket == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + RequestPacket->OperationCount = 2; + + RequestPacket->Operation[0].Flags = 0; + RequestPacket->Operation[0].LengthInBytes = RegAddressLength; + RequestPacket->Operation[0].Buffer = RegAddress; + + RequestPacket->Operation[1].Flags = I2C_FLAG_READ; + RequestPacket->Operation[1].LengthInBytes = Length; + RequestPacket->Operation[1].Buffer = Buffer; + + Status = KhadasMcuContext->I2cIo->QueueRequest (KhadasMcuContext->I2cIo, 0, NULL, RequestPacket, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: error %d during transmission\n", __func__, Status)); + } + + FreePool (RequestPacket); + + return Status; +} + +STATIC +EFI_STATUS +EFIAPI +KhadasMcuWrite ( + IN CONST KHADAS_MCU_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length + ) +{ + EFI_STATUS Status; + EFI_I2C_REQUEST_PACKET *RequestPacket; + UINTN RequestPacketSize; + UINT8 *Data; + UINT16 Index; + KHADAS_MCU_CONTEXT *KhadasMcuContext = KHADAS_MCU_FROM_PROTOCOL (This); + + ASSERT (KhadasMcuContext != NULL); + ASSERT (KhadasMcuContext->I2cIo != NULL); + + RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION); + RequestPacket = AllocateZeroPool (RequestPacketSize); + if (RequestPacket == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Data = AllocateZeroPool (RegAddressLength + Length); + if (Data == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + for (Index = 0; Index < RegAddressLength; Index++) { + Data[Index] = RegAddress[Index] & 0xff; + } + + for (Index = RegAddressLength; Index < RegAddressLength + Length; Index++) { + Data[Index] = Buffer[Index - RegAddressLength] & 0xff; + } + + RequestPacket->OperationCount = 1; + + RequestPacket->Operation[0].Flags = 0; + RequestPacket->Operation[0].LengthInBytes = RegAddressLength + Length; + RequestPacket->Operation[0].Buffer = Data; + + Status = KhadasMcuContext->I2cIo->QueueRequest (KhadasMcuContext->I2cIo, 0, NULL, RequestPacket, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: error %d during transmission\n", __func__, Status)); + } + + FreePool (Data); + FreePool (RequestPacket); + + return Status; +} + +STATIC +EFI_STATUS +EFIAPI +KhadasMcuReadRegister ( + IN CONST KHADAS_MCU_PROTOCOL *This, + IN UINT8 Address, + OUT UINT8 *Value + ) +{ + return KhadasMcuRead (This, &Address, sizeof (UINT8), Value, sizeof (UINT8)); +} + +STATIC +EFI_STATUS +EFIAPI +KhadasMcuWriteRegister ( + IN CONST KHADAS_MCU_PROTOCOL *This, + IN UINT8 Address, + IN UINT8 Value + ) +{ + return KhadasMcuWrite (This, &Address, sizeof (UINT8), &Value, sizeof (UINT8)); +} + +STATIC +EFI_STATUS +EFIAPI +KhadasMcuSetFanSpeedPercentage ( + IN KHADAS_MCU_PROTOCOL *This, + IN UINT8 Percentage + ) +{ + return KhadasMcuWriteRegister (This, MCU_CMD_FAN_STATUS_CTRL_REGv2, + MIN (Percentage, 100)); +} + +EFI_DRIVER_BINDING_PROTOCOL mDriverBindingProtocol = { + KhadasMcuSupported, + KhadasMcuStart, + KhadasMcuStop +}; + +EFI_STATUS +EFIAPI +KhadasMcuSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status; + EFI_I2C_IO_PROTOCOL *TmpI2cIo; + UINT8 KhadasMcuAddress; + UINT8 KhadasMcuBus; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &TmpI2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + + KhadasMcuAddress = PcdGet8 (PcdKhadasMcuAddress); + KhadasMcuBus = PcdGet8 (PcdKhadasMcuBus); + + Status = EFI_UNSUPPORTED; + + if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) && + TmpI2cIo->DeviceIndex == I2C_DEVICE_INDEX(KhadasMcuBus, KhadasMcuAddress)) { + DEBUG ((DEBUG_INFO, "%a: attached to Khadas MCU device\n", __func__)); + Status = EFI_SUCCESS; + } + + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +KhadasMcuStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status; + KHADAS_MCU_CONTEXT *KhadasMcuContext; + KHADAS_MCU_PROTOCOL *KhadasMcuProtocol; + + KhadasMcuContext = AllocateZeroPool (sizeof(KHADAS_MCU_CONTEXT)); + if (KhadasMcuContext == NULL) { + DEBUG ((DEBUG_ERROR, "%a: context allocation failed\n", __func__)); + return EFI_OUT_OF_RESOURCES; + } + + KhadasMcuContext->ControllerHandle = ControllerHandle; + KhadasMcuContext->Signature = KHADAS_MCU_SIGNATURE; + + KhadasMcuProtocol = &KhadasMcuContext->KhadasMcuProtocol; + KhadasMcuProtocol->SetFanSpeedPercentage = KhadasMcuSetFanSpeedPercentage; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &KhadasMcuContext->I2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: failed to open I2cIo\n", __func__)); + FreePool (KhadasMcuContext); + return EFI_UNSUPPORTED; + } + + Status = gBS->InstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gKhadasMcuProtocolGuid, KhadasMcuProtocol, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: failed to install KHADAS_MCU_PROTOCOL\n", __func__)); + goto fail; + } + + return Status; + +fail: + FreePool (KhadasMcuContext); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +KhadasMcuStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ) +{ + EFI_STATUS Status; + KHADAS_MCU_PROTOCOL *KhadasMcuProtocol; + KHADAS_MCU_CONTEXT *KhadasMcuContext; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gKhadasMcuProtocolGuid, + (VOID **) &KhadasMcuProtocol, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + KhadasMcuContext = KHADAS_MCU_FROM_PROTOCOL(KhadasMcuProtocol); + + gBS->UninstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gKhadasMcuProtocolGuid, &KhadasMcuContext->KhadasMcuProtocol, + &gEfiDriverBindingProtocolGuid, &mDriverBindingProtocol, + NULL + ); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + FreePool (KhadasMcuContext); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +KhadasMcuDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiDriverBindingProtocolGuid, &mDriverBindingProtocol, + NULL + ); + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.h new file mode 100644 index 0000000..b3f2d2e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.h @@ -0,0 +1,64 @@ +/** @file + * + * Khadas MCU platform driver + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __KHADAS_MCU_DXE_H__ +#define __KHADAS_MCU_DXE_H__ + +#include + +#define KHADAS_MCU_SIGNATURE SIGNATURE_32 ('K', 'M', 'C', 'U') + +#define I2C_GUID \ + { \ + 0xadc1901b, 0xb83c, 0x4831, { 0x8f, 0x59, 0x70, 0x89, 0x8f, 0x26, 0x57, 0x1e } \ + } + +typedef struct { + UINT32 Signature; + EFI_HANDLE ControllerHandle; + EFI_I2C_IO_PROTOCOL *I2cIo; + KHADAS_MCU_PROTOCOL KhadasMcuProtocol; +} KHADAS_MCU_CONTEXT; + +#define KHADAS_MCU_FROM_IO(a) CR (a, KHADAS_MCU_CONTEXT, I2cIo, KHADAS_MCU_SIGNATURE) +#define KHADAS_MCU_FROM_PROTOCOL(a) CR (a, KHADAS_MCU_CONTEXT, KhadasMcuProtocol, KHADAS_MCU_SIGNATURE) + +// +// Registers & fields +// https://docs.khadas.com/products/sbc/edge2/hardware/edge2-boot-flow +// +#define MCU_CMD_FAN_STATUS_CTRL_REGv2 0x8A + +EFI_STATUS +EFIAPI +KhadasMcuSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +KhadasMcuStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +KhadasMcuStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ); + +#endif // __KHADAS_MCU_DXE_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.inf new file mode 100644 index 0000000..5a852c4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/KhadasMcuDxe/KhadasMcuDxe.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Khadas MCU platform driver +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = KhadasMcuDxe + FILE_GUID = a9d195e1-85a0-426f-b364-413e6d2350a7 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = KhadasMcuDxeInitialize + +[Sources.common] + KhadasMcuDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/Khadas/KhadasPkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + PcdLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[Protocols] + gEfiI2cIoProtocolGuid ## CONSUMES + gEfiDriverBindingProtocolGuid ## PRODUCES + gKhadasMcuProtocolGuid ## PRODUCES + +[Pcd] + gKhadasTokenSpaceGuid.PcdKhadasMcuAddress + gKhadasTokenSpaceGuid.PcdKhadasMcuBus + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.bmp b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.bmp new file mode 100644 index 0000000000000000000000000000000000000000..2ba1e15f5b42ecc2b2f0b6cd2d7cf95f92fbf541 GIT binary patch literal 330318 zcmeI5d5|2{VTWh$UG05oSF2qCLL52}21^2QNP;y;fRT-4kc5O00vU5#++a%}u!IGO zLmb8jhJa%r#<;LCad3jMIgE&Hd{E`TQ%U)+RHZ6avGZqsN}Jx^p6;HWK3~s#TO;V1 z>3+xeUVr_r?m6@PwKG~uhyIr7-?934V?(JlU;i3PqlZ5J|Gy&_mr95J@dp72KmY;| zfB*y_009U<00Izz00bZa0SG_<0uX=z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U< z00Izz00bZa0SG_<0uX=z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz00bZa z0SG_<0uX=z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz00bZa0SG_<0uX=z z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz00bZa0SG_<0uX=z1Rwwb2tWV= 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z009U<00Izz00bZa0SG_<0uX=z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz z00bZa0SG_<0uX=z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz00bZa0SG_< z0uX=z1Rwwb2tWV=5P$##AOHafKmY;|fB*y_009U<00Izz00bZa0SG_<0uX=z1Rwwb U2tWV=5P$##AOHafWJ%!v0FOTSq5uE@ literal 0 HcmV?d00001 diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.c new file mode 100644 index 0000000..2255b11 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.c @@ -0,0 +1,144 @@ +/** @file + Logo DXE Driver, install Edkii Platform Logo protocol. + + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    + Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..725b2a7 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/AcpiTables/Dsdt.asl @@ -0,0 +1,53 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8316" +#define BOARD_CODEC_I2C "\\_SB.I2C3" +#define BOARD_CODEC_I2C_ADDR 0x10 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD3 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host2.asl") + + Scope (I2C3) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Edge2.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Edge2.Modules.fdf.inc new file mode 100644 index 0000000..f802319 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Edge2.Modules.fdf.inc @@ -0,0 +1,21 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-khadas-edge2.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf + + # Khadas MCU Support + INF $(VENDOR_DIRECTORY)/Drivers/KhadasMcuDxe/KhadasMcuDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc new file mode 100644 index 0000000..59b8c57 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc @@ -0,0 +1,120 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Edge2 + PLATFORM_VENDOR = Khadas + PLATFORM_GUID = 584a4095-9cf3-46ea-a9b5-8d55ccd11da0 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Edge2" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Khadas" + gRockchipTokenSpaceGuid.PcdFamilyName|"Edge" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.khadas.com/edge2" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-khadas-edge2" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x18, 0x10 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2, 0x2, 0x3 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x2 + gKhadasTokenSpaceGuid.PcdKhadasMcuAddress|0x18 + gKhadasTokenSpaceGuid.PcdKhadasMcuBus|0x2 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf + + # Khadas MCU Support + $(VENDOR_DIRECTORY)/Drivers/KhadasMcuDxe/KhadasMcuDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..9162eb1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,383 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +STATIC VOID *mKhadasMcuEventRegistration; +STATIC KHADAS_MCU_PROTOCOL *mKhadasMcu; +STATIC UINT8 mTargetFanSpeed; + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0 + break; + case 4: + GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3 + break; + case 5: + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* Set VCC_5V0_PWREN_H */ + GpioPinWrite (4, GPIO_PIN_PA2, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + + /* Set USB_HOST_PWREN_H */ + GpioPinWrite (1, GPIO_PIN_PB1, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PB1, GPIO_PIN_OUTPUT); + + /* Set TYPEC0_PWR_EN */ + GpioPinWrite (3, GPIO_PIN_PA4, TRUE); + GpioPinSetDirection (3, GPIO_PIN_PA4, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset to gpio output mode */ + if(Segment == PCIE_SEGMENT_PCIE20L2) { // AP6275P Wi-Fi + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + + /* wifi_poweren_gpio */ + GpioPinSetDirection (0, GPIO_PIN_PC4, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + /* wifi_poweren_gpio */ + GpioPinWrite (0, GPIO_PIN_PC4, Enable); + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + } +} + +STATIC +VOID +KhadasMcuRegistrationEventHandler ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_HANDLE Handle; + UINTN BufferSize; + EFI_STATUS Status; + + BufferSize = sizeof (EFI_HANDLE); + Status = gBS->LocateHandle ( + ByRegisterNotify, + NULL, + mKhadasMcuEventRegistration, + &BufferSize, + &Handle); + if (EFI_ERROR (Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG ((DEBUG_WARN, "%a: Failed to locate gKhadasMcuProtocol. Status=%r\n", + __func__, Status)); + } + return; + } + + Status = gBS->HandleProtocol (Handle, + &gKhadasMcuProtocolGuid, (VOID **) &mKhadasMcu); + ASSERT_EFI_ERROR (Status); + + PwmFanSetSpeed (mTargetFanSpeed); + + gBS->CloseEvent (Event); +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + EfiCreateProtocolNotifyEvent ( + &gKhadasMcuProtocolGuid, + TPL_CALLBACK, + KhadasMcuRegistrationEventHandler, + NULL, + &mKhadasMcuEventRegistration); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + UINT32 Percentage + ) +{ + mTargetFanSpeed = (UINT8) Percentage; + + // + // If the protocol is installed, set the speed now. + // Otherwise it will be set by KhadasMcuRegistrationEventHandler + // when ready. + // + if (mKhadasMcu != NULL) { + mKhadasMcu->SetFanSpeedPercentage (mKhadasMcu, mTargetFanSpeed); + } +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Red off, Green for status, Blue for power */ + GpioPinWrite (4, GPIO_PIN_PB4, FALSE); + GpioPinSetDirection (4, GPIO_PIN_PB4, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PB2, FALSE); + GpioPinSetDirection (4, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PB3, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (4, GPIO_PIN_PB2, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + GpioPinSetFunction(1, GPIO_PIN_PD3, 0); //jdet + GpioPinSetFunction(1, GPIO_PIN_PD0, 0); //spk_con +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..e36cc27 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Edge2/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,40 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + Platform/Khadas/KhadasPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + UefiLib + UefiBootServicesTableLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c + +[Protocols] + gKhadasMcuProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Include/Protocol/KhadasMcu.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Include/Protocol/KhadasMcu.h new file mode 100644 index 0000000..86365e3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/Include/Protocol/KhadasMcu.h @@ -0,0 +1,30 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __KHADAS_MCU_H__ +#define __KHADAS_MCU_H__ + +#define KHADAS_MCU_PROTOCOL_GUID \ + { 0x162d2a6e, 0x33af, 0x4ca5, { 0xaa, 0x68, 0xbc, 0xd3, 0xb2, 0x4c, 0xca, 0xf5 } } + +typedef struct _KHADAS_MCU_PROTOCOL KHADAS_MCU_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *KHADAS_MCU_SET_FAN_SPEED_PERCENTAGE) ( + IN KHADAS_MCU_PROTOCOL *This, + IN UINT8 Percentage + ); + +struct _KHADAS_MCU_PROTOCOL { + KHADAS_MCU_SET_FAN_SPEED_PERCENTAGE SetFanSpeedPercentage; +}; + +extern EFI_GUID gKhadasMcuProtocolGuid; + +#endif // __KHADAS_MCU_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/KhadasPkg.dec b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/KhadasPkg.dec new file mode 100644 index 0000000..2a1027a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Khadas/KhadasPkg.dec @@ -0,0 +1,26 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = KhadasPkg + PACKAGE_GUID = 7a5b60db-89a8-4749-b4e7-e093197595c2 + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[Protocols] + gKhadasMcuProtocolGuid = { 0x162d2a6e, 0x33af, 0x4ca5, { 0xaa, 0x68, 0xbc, 0xd3, 0xb2, 0x4c, 0xca, 0xf5 } } + +[Guids] + gKhadasTokenSpaceGuid = { 0x2f92c2cf, 0x0e93, 0x45c9, { 0xae, 0x30, 0x38, 0x46, 0x4d, 0x3f, 0xde, 0x8a } } + +[PcdsFixedAtBuild] + gKhadasTokenSpaceGuid.PcdKhadasMcuAddress|0|UINT8|0x00000001 + gKhadasTokenSpaceGuid.PcdKhadasMcuBus|0|UINT8|0x00000002 diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/Logo.bmp b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/Logo.bmp new file mode 100644 index 0000000000000000000000000000000000000000..de9b4f39f73864eae7cb6106803c2301a3553206 GIT binary patch literal 224526 zcmeI52Vh=R`Tz6IjApb=(j?7(lQ+qm*+D6zh0;$qP@sS~Q5mkE3W5j@P*KD! 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All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..1f72ac9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/AcpiTables/Dsdt.asl @@ -0,0 +1,40 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac0.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..616a2bc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,341 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 0: + /* gmac0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; + + /* phy0 reset */ + GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 0: + /* phy0 reset */ + GpioPinWrite (4, GPIO_PIN_PB3, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + break; + case 4: + break; + case 5: + GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3 + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* Enable USB-C VBUS */ + GpioPinWrite (4, GPIO_PIN_PA7, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PA7, GPIO_PIN_OUTPUT); + + /* Enable USB HOST VBUS */ + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset to gpio output mode */ + if(Segment == PCIE_SEGMENT_PCIE20L0) { // AP6275P Wi-Fi + GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT); + + /* wifi_poweren_gpio */ + GpioPinSetDirection (1, GPIO_PIN_PB1, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L0) { + /* wifi_poweren_gpio */ + GpioPinWrite (1, GPIO_PIN_PB1, Enable); + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L0) { + GpioPinWrite (1, GPIO_PIN_PB4, !Enable); + } +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Power button LED used as status indicator */ + GpioPinWrite (3, GPIO_PIN_PB7, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PB7, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..ec569ea --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,34 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.Modules.fdf.inc new file mode 100644 index 0000000..6317171 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-blueberry-minipc-linux.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc new file mode 100644 index 0000000..aa27f79 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc @@ -0,0 +1,124 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = R58-Mini + PLATFORM_VENDOR = Mekotronics + PLATFORM_GUID = b01621cc-69a0-419f-9f37-aadfbb5db256 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # This board lacks an SD card slot. + DEFINE RK_SD_ENABLE = FALSE + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"R58 Mini" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Mekotronics" + gRockchipTokenSpaceGuid.PcdFamilyName|"R58" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.mekotronics.com/h-pd-76.html" + gRockchipTokenSpaceGuid.PcdBoardName|"MINI-PC-RK3588-4D32-V1.0" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-blueberry-minipc-linux" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # PCI Express 3.0 support flags and default values + # + gRK3588TokenSpaceGuid.PcdPcie30Supported|FALSE + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0, 0x1, 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..9e6f782 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/AcpiTables/Dsdt.asl @@ -0,0 +1,55 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C3" +#define BOARD_CODEC_I2C_ADDR 0x10 +#define BOARD_CODEC_GPIO "\\_SB.GPI3" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PB2 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac0.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C3) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..354433c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,384 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 0: + /* gmac0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; + + /* phy0 reset */ + GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT); + break; + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + + /* phy1 reset */ + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 0: + /* phy0 reset */ + GpioPinWrite (4, GPIO_PIN_PB3, !Enable); + break; + case 1: + /* phy1 reset */ + GpioPinWrite (4, GPIO_PIN_PA2, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0 + break; + case 4: + break; + case 5: + GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3 + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* Enable USB-C VBUS */ + GpioPinWrite (4, GPIO_PIN_PA7, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PA7, GPIO_PIN_OUTPUT); + + /* Enable USB HOST VBUS */ + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: // M.2 M Key + /* reset */ + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + /* vcc3v3_pcie30 */ + GpioPinSetDirection (1, GPIO_PIN_PC4, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L0: // AP6275P Wi-Fi + /* reset */ + GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT); + + /* wifi_poweren_gpio */ + GpioPinSetDirection (1, GPIO_PIN_PB1, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + /* vcc3v3_pcie30 */ + GpioPinWrite (1, GPIO_PIN_PC4, Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + /* wifi_poweren_gpio */ + GpioPinWrite (1, GPIO_PIN_PB1, Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (1, GPIO_PIN_PB4, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Power button LED used as status indicator */ + GpioPinWrite (3, GPIO_PIN_PB7, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PB7, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + GpioPinSetFunction(3, GPIO_PIN_PB2, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..ec569ea --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,34 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/R58X.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/R58X.Modules.fdf.inc new file mode 100644 index 0000000..56deaa1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/R58X.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-blueberry-edge-v12-linux.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc new file mode 100644 index 0000000..0236229 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc @@ -0,0 +1,126 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = R58X + PLATFORM_VENDOR = Mekotronics + PLATFORM_GUID = d947cf02-21c1-4a39-9c80-55969396f733 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"R58X" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Mekotronics" + gRockchipTokenSpaceGuid.PcdFamilyName|"R58" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.mekotronics.com/h-pd-75.html" + gRockchipTokenSpaceGuid.PcdBoardName|"EDGE-RK3588-4D32-V1.2" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-blueberry-edge-v12-linux" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x10 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x3 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # Disable HS400 for now, otherwise eMMC is unusable. + gRockchipTokenSpaceGuid.PcdDwcSdhciDisableHs400|TRUE + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0, 0x1, 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x44 + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42 + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..2221309 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/AcpiTables/Dsdt.asl @@ -0,0 +1,40 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Blade3.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Blade3.Modules.fdf.inc new file mode 100644 index 0000000..31670cb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Blade3.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-blade3-v101-linux.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Blade3.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Blade3.dsc new file mode 100644 index 0000000..92ba5f8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Blade3.dsc @@ -0,0 +1,109 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Blade3 + PLATFORM_VENDOR = Mixtile + PLATFORM_GUID = 6058aec7-9db7-4fdf-a2ce-19f58631071d + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # No status LED on this platform. + DEFINE RK_STATUS_LED_ENABLE = FALSE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Blade 3" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Mixtile" + gRockchipTokenSpaceGuid.PcdFamilyName|"Blade" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.mixtile.com/blade-3/" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-blade3-v101-linux" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 } + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..9ab05e9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,345 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2 + break; + case 2: + break; + case 3: + break; + case 4: + GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0 + GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0 + break; + case 5: + GpioPinSetFunction(1, GPIO_PIN_PB6, 9); //i2c5_scl_m3 + GpioPinSetFunction(1, GPIO_PIN_PB7, 9); //i2c5_sda_m3 + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* vbus5v0_typec0 (data-only port) */ + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + + /* vbus5v0_typec1 (PD + data port) */ + // Won't enable 5V on VBUS for now, unsure if it's okay + // to do it when voltage > 5V is already supplied to this port. + // + // GpioPinWrite (4, GPIO_PIN_PA3, TRUE); + // GpioPinSetDirection (4, GPIO_PIN_PA3, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: // U.2 + /* reset */ + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + /* vcc3v3_pcie30 */ + GpioPinSetDirection (1, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L0: // ASM1182e (-> 2x RTL8125) + /* reset */ + GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L1: + /* reset */ + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (1, GPIO_PIN_PB2, Enable); + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (1, GPIO_PIN_PB4, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (4, GPIO_PIN_PA2, !Enable); + break; + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER2, + .ChannelID = PWM_CHANNEL0, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM2_CH0 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (3, GPIO_PIN_PD0, 0xB); // PWM8_M2 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + // No controllable LEDs on this platform +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + // No controllable LEDs on this platform +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Blade3/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/Logo.bmp b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/Logo.bmp new file mode 100644 index 0000000000000000000000000000000000000000..8f8677b1aeb214759f40b561ab3d194d4ab6ad57 GIT binary patch literal 172854 zcmeHQho2Qix&>yK#LS({1SaPki4r6yK|nx2L_|asL=aRE5F|>Js00xSN)iJiySnS{ z({+Qo;qB_ar@rUD-9P0WY`1ATRDIQ5H_Y(O?~2vc)fG z>hRycdiLnC4*&1jBOm`7e=|4s=yCJENd5KAPMAF@Z_nDA3okdneWX?Cb7FhLgyA{F zp2qd+F}N-L#T6BAA8Ao)1%=-^+Intx!?ODeit`eP&2ceCfDvE>x-80j?U!_PbDi^9rJT!$TEBR!{hv2F|L?=jC+8N3TjaZp03*N%bX^1n zG>0x9Qa)#JGU}q4g<=pA6MAl2Rpoq8Dd)=J)@#SwzJ0&b;O8Gc=omLBUED6;Wds-j zMxZMqkeU*=Z(WTNL%J5mt~fhGa=0;dbgt{ON|~1rw|;SD zC0loK-}o*gzz8q`v4%iNK@tv)mA0?0g*QD}(K{XrD5AgR4;H&VtCV^5XzSnJzHRet zQ1o9ew$_y;i<;+qi~u9R2y`6;diLz`%;HiddUP%P=Kkioiaz3TcQ%DC9SnNJjm`6? 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All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Mixtile/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.bmp b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.bmp new file mode 100644 index 0000000000000000000000000000000000000000..7292827f6c0130f698d045288fcb6d9dc0fdfe41 GIT binary patch literal 116534 zcmeI5hrdBz0pC6f`ARNpx9Bdpx6~FA_@XVQDYZ1Vpn36M-ok9q6yjE z^s-r#OcV&-xv7r9sWxcwDK>1DF0@4!N`Ah#^n3AxTUXR@hQz$KGkvO7khTU)BDVC z2KN4C;FWg=UVV3P-+O~Y!-GTb5AGlNOM2fy@&`Whzx^-$srRX0c0KUzjvb$?J#BOO zyknE46_by6lMUl!X=U%zzfLU&dr?IFw`s$plZ|?l58uX%9@Mf}tWNeFEa{p%`A9f< zFfQqyXB|3GHxzfnjywLbAd#Fr1e{EmCW@zZKk#k$oX5}m2}MPd-^}zb89GPYRTmDaw;8M zlAWDJUVUv_UQbS&lKbY}x`DwRc=>kQ-(-X$Hgy6*c{kSR4@XK1+jiYF5#<#|NC$pk8j#D??kHhpgnyUKbVeWzm4 z$&+awav#@3QAzc&m+I0whg}gt>bKwi=9COL2Nn{0O6{7PdiVSy$fS*Xo%ZdY#cHM? zVOuEW0Qn{j2+6|oLym8`ZtuX$e;xN#5Eg)*$9`PDb_X_FlV-MJBAP6(Zrk!&*S%kF zIRBpV`NtJj)&=Ph(J96zHOF1qdhRo!W~@R#qf z>C(qoAYBiP{aAL;tw zH{F{l#-S71CbaI1t>Y^enMg~_#s#b5lJ*(-y@z;1-?sT<6K}e50i%I^?{cVl6Fon3 zlZCk=Lo;Llk^`$|xaP!b@^f)Gp)M-v+5K-hK+#bbk%_xx>d(2uN&GzfZ8>i|`OB%r zk~Io6UAjBZmdF^mg;h;`&;225q?#JYra;Rz&yUSP-lW)B`kwpU)Etfr1)8sVI&T)r z2%tqJy?dsPq4DIHkYwe{l1Uc!JpQ9``L5y)Iy8*j6u~pXLvH{0q9G^DTUqjO?Wvpd zVaase|90GY%jOkkXt?X%Z`7TBYuU^d$+9X>0v9*+R2+7C^Obx0p8ah;p|=11s$(wk z#3*Mn+irO+Unq)XwDH3GSPLPDH=^f6&73bd4i3FnHtVPm2xhfv{o3t$K}b|l4eRbg z?HQRm7_)TV`Ncdz_HRXXsaP(N@iow}eDTS7K|dVJu-Vi=fJ6c#Ew}D82Z_KjibD`a~AP3io10;0+8nKSu6;3w}0CVo=(0hgqM&Oc( zIF)nwI_?ZZ!xe{~8hf5~bv z?gw(2T6N|n5y-O<*5on~iW<7cX?3`VEt`8x&XTI_)=y-|#2RDCoMqyA9{Z7d*2XU< zSzeQy>jk@;WH9?+EySx{by=ULV2XO_*?QxvS`gIN$+$RmAgu3x=wI7!`xFc}Vl)L^;#(R-fKocRQ~<-A z_^m9x)Itd*2JL?MdqJ3{!rB(g-|i{ny8P0C!}KB>yEmMP1hup$5WbhrTpkKW954hJ zC@Mm=jZ!(0w2s12sRyng!8;+4S?x*J_dRdWwye0RH#j_5smXUDsHHK1(~V`x9Nvc% zVZ8vO_o-i*jueK4z8J25@1Olt-HNGTuQ4a~ATfP_w{LwzjD?R~G?;0Hubv5}hL|{!K{C@222K!6OQQ3hufaja0k-kthXf?t zP~vo@Zd=^k$F)d|6*EXYKEmu!qBkvx+>6~=d(w4UFta=9y!$KhBkdqSliexxsHMGD z4#tlHcPm1C>_26*j^ITU(P#Wbd}7AN$>tE79YLA&A|o z(b7btR&H9)A^N6TOHV{m5M+y!fDh6FPpXq-Veg0jUBF|)qyaul^sm>$kUO0&KVrh= z=%lKKzPca$jv!m)1jcU>uFh)c5rqqQkj|?shb^7fyFhe~9zuH+p!_`M|=Vy z$Gofg612o;F`?_>=$2tCoql-OMWLuKOSRcy6*VIlwOs#UX}v`BX==LsLy-Y6(2yHs ze4Oz5F#wv?W$TTv2=EBbq-zwk@^TCxD>j{hKgF#B>03;cCBuEw0BDiBMEor#Byxf` zI3oj~ZpgMJph6|6>+)5*=0?%2WndCs2(1QNl%kmw14T=KwFzEdKo~O7wmB}di}pn0 z&B6`7%w7@g%UvOKP9i~UT`_wofI{~WxIyLebHqTA6Xgp|2t1(CiYScxU;OXLc-RdI zg>4kbniH-T5cWR#vw~!yVmQ>>RY#nsmRWG)5FPSRLBObuia`}c=r-cNg+OFH#SmF6 zDqnD-pj_kx^J5fb6mB>)3h;bmZYL5=mpx%uLtaxh+t)d;?Us*=-gwH|DDZUN@qvF5 z!$nJA(3TrdleS#{ax@I&R#~t{mL-aC1fDbOV8qZ^7FIX9YZf(h$~-9cPwqN;a|m@W zlPg-fY|hbop$gv{ihKEv5DgF1YvD%@-2(m5m^x`_n0tq#3zTy1_mUddKj5gw&xUjF z6qw>mQ5VWxbU*4H#}he=Tn#gSfhks~a*??-29;vaI0=~e!peGcaQgQQ=c4N=&5j)h z{KwH;A}f76@BZpo@5#b}SKsxV3R#$5(m7jVg5JxTU97JC1q2B&KZbSoQZRy^)Qymt z9hT814Obi4;Bi|2Vmm)sQR@e}?2*!RdFr-J<+fWtnKg22(YT}#+;=dh1z>orxk37U zjeb;DRQGG|%t+#;q4435Q!uroBA`i z@qnZyQBq0;oo$uBQI`0D7a`xW1JDPX5^xIP@bD^(0H&geE(3O^JJj7Y-7*Xp_Ow_c%D|aHqB6#}MpS{CVq#6(j zn#(=QX*L>h_m!8`h-%qdr@R|2*B5DYPn2@dh#XnT&Cx82V?-T0QB>C!5OQ}ldPc2g zi$j^-_)0nlY-kALfaeC-l>^N*vMnj_hlYEf_^FHvvjK}4&74FQj>vu5>5iSBw>@z% zUFrYuUql7l*IDLeMG*~X`BC}=V3pQ;^2bU;(Ke)W6omnn=dS(D2#@?_PVmLeD z&T&+T@RMM}C^J35h@FWKE(C}Gl)6dhyqSgCD# zOJwqq5Flgu``@?uLS6$dKQ@;iJ@V3pE0l$sYH^^l(E`FZy zUobKlllDIObC0po>xZp?bEduRDqsv#WO>|a-&uy~b?#Dzx12$wfYKJz* zjR$A4-_o-Q$w_2KY(QQoNQ)eguCQ~ECyj|>yT-srj&4)E(h8c*1d6tv2_9W^!{*2- ztZAkng3x>Rfd3KxQ`XyQlI0%KSzO}0>&I9%oYb03cwlh#Z-e^|Rv&Y*gLvX6d>&S| zeuE;cK?<+7e~^8GJV|SdY|#gZQhd(rZ_M&w9`P+i3u^1IE0>-jslRuxuZvtL~|K|-f6O1>8oazIKrG>pNS+s(|#~>^I|ISFq19i+P8lW zp&Yj!PD6MW6kGChE5hT2Yp7?pfQO-qJj1ZX@LZM~w^(!%*mT0FN2r2m&q(7f=XYv* zf)_j!iBk138^$D@GD>M_PB8tf?I?v1tT;sTX=4ZY!OhQ8HX$g%eh$+t%M>b?o+=DuftFOTJwMnxtg zr!md873Ng*0?w7kLa?sj4}aeq&XM~l`;mPD!oMPN(V^rVc-S^KX3?b!s5%O>`(;d6Mq@22#-Fr5NLdr3t6cQ4_ zb1c71I2dacxK#i^yr*&X6ui9%9) zA;@p;&Aw)guA3qNaLKm2l^+rbMLEyPLe0oE4KbZ(9d{-MCidbDf@#1y1d(tL6h9}; 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z7?XFNcLev12}jY%h7gummDAfASI%V*f?Kuj+%If2r}l=u!og~?5qT2ei+B)4Yt`(| z`V}+LPhmUJd)4s+H?5hueeIlk&&N2F3p5&Q)KyDg-(vrD7#VZdxARf(Q*+_dSE1OL Md*6jHRs{wB4{j`#9{>OV literal 0 HcmV?d00001 diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.c new file mode 100644 index 0000000..2255b11 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.c @@ -0,0 +1,144 @@ +/** @file + Logo DXE Driver, install Edkii Platform Logo protocol. + + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    + Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl new file mode 100755 index 0000000..796403d --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/AcpiTables/Dsdt.asl @@ -0,0 +1,53 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S1_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C6" +#define BOARD_CODEC_I2C_ADDR 0x10 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD5 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + // include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host2.asl") + + Scope (I2C6) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..6a1b49d --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,332 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 850000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + /* This is not configured in the OrangePi5's Linux device tree + RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 1100000), */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + /* The OPi is officially configured for the 837500 voltage, but is still marked as avdd_0v75_s0 in the schematic and Linux device tree. rockchip says this voltage is set to improve HDMI stability. */ + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 837500), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + /* Do not override, set by earlier boot stages. */ +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB2, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + break; + case 4: + GpioPinSetFunction(3, GPIO_PIN_PA6, 9); //i2c4_scl_m0 + GpioPinSetFunction(3, GPIO_PIN_PA5, 9); //i2c4_sda_m0 + break; + case 5: + break; + case 6: + GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3 + GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* Set GPIO3 PC0 (TYPEC_EN) output high to power Type-C/USB2.0 ports */ + GpioPinWrite (3, GPIO_PIN_PC0, TRUE); + GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable green led\n")); + // GpioPinWrite (1, GPIO_PIN_PA2, TRUE); + // GpioPinSetDirection (1, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset to gpio output mode */ + if(Segment == PCIE_SEGMENT_PCIE20L2) { // M.2 M Key + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* nothing to power on */ +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER3, + .ChannelID = PWM_CHANNEL2, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM3_CH2 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (4, GPIO_PIN_PB2, 0xB); // PWM14_M1 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (1, GPIO_PIN_PA2, FALSE); + GpioPinSetDirection (1, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (1, GPIO_PIN_PA2, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + + GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.Modules.fdf.inc new file mode 100644 index 0000000..f6b4446 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-orangepi-5.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc new file mode 100644 index 0000000..b481ad9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc @@ -0,0 +1,122 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Willzen Zou +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = OrangePi5 + PLATFORM_VENDOR = OrangePi + PLATFORM_GUID = e6443926-7196-4fc4-9554-91fc1fb34256 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Orange Pi 5" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Orange Pi" + gRockchipTokenSpaceGuid.PcdFamilyName|"Orange Pi 5" + gRockchipTokenSpaceGuid.PcdProductUrl|"http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-orangepi-5" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x10 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42 + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S1Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl new file mode 100644 index 0000000..1d767aa --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/AcpiTables/Dsdt.asl @@ -0,0 +1,53 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8388" +#define BOARD_CODEC_I2C "\\_SB.I2C7" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD3 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + + Scope (I2C7) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..15f4a9e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,385 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2 + break; + case 2: + break; + case 3: + GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0 + break; + case 4: + break; + case 5: + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* vcc5v0_host_en */ + GpioPinWrite (3, GPIO_PIN_PB7, TRUE); + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + + /* typec5v_pwren */ + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: // M.2 M Key + /* reset */ + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + /* vcc3v3_pcie30 */ + GpioPinSetDirection (2, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L0: // M.2 A+E Key + /* reset */ + GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + /* vcc3v3_pcie2x1l0 */ + GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L1: // RTL8125B + /* reset */ + GpioPinSetDirection (3, GPIO_PIN_PB3, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L2: // RTL8125B + /* reset */ + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + break; + default: + break; + } + if (Segment == PCIE_SEGMENT_PCIE20L1 || Segment == PCIE_SEGMENT_PCIE20L2) { + /* vcc3v3_pcie_eth */ + GpioPinSetDirection (3, GPIO_PIN_PB4, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (2, GPIO_PIN_PB6, Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (2, GPIO_PIN_PC5, Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + case PCIE_SEGMENT_PCIE20L2: + /* Yes, disabling one would disable the other as well. */ + GpioPinWrite (3, GPIO_PIN_PB4, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (4, GPIO_PIN_PA5, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (3, GPIO_PIN_PB3, !Enable); + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinWrite (4, GPIO_PIN_PA2, !Enable); + break; + default: + break; + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER0, + .ChannelID = PWM_CHANNEL3, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM0_CH3 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (3, GPIO_PIN_PB2, 0xB); // PWM3_IR_M1 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (3, GPIO_PIN_PA6, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PA6, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PA6, Enable); +} + +VOID +EFIAPI +PlatformWiFiEnable ( + IN BOOLEAN Enable + ) +{ + // WiFi - enable + GpioPinWrite (0, GPIO_PIN_PC4, Enable); + GpioPinSetDirection (0, GPIO_PIN_PC4, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + PlatformWiFiEnable (TRUE); + + GpioPinSetFunction(1, GPIO_PIN_PD3, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.Modules.fdf.inc new file mode 100644 index 0000000..ce5cea1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-orangepi-5-plus.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.dsc new file mode 100644 index 0000000..99b4b3f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.dsc @@ -0,0 +1,119 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = OrangePi5Plus + PLATFORM_VENDOR = OrangePi + PLATFORM_GUID = 6bb03dd4-c246-474a-851c-70ea24a89e43 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Orange Pi 5 Plus" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Orange Pi" + gRockchipTokenSpaceGuid.PcdFamilyName|"Orange Pi 5" + gRockchipTokenSpaceGuid.PcdProductUrl|"http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-plus.html" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-orangepi-5-plus" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x7 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43, 0x11 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/Logo.bmp b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/Logo.bmp new file mode 100644 index 0000000000000000000000000000000000000000..ea4577218879f4797ea8d736b6abd9a0610285d0 GIT binary patch literal 218470 zcmeI532;vPXtyZhhea+kAw-|w9M z=k~eheCML!Ge@T+HGF=Be>>sd6QQJ}JMsTeQfvHI`Q)`qN^1C*9}*w|5+DH*AOR8} z0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq5+DH*AOR8}0TLhq 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zk^l*i011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg z011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!) z36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@kN^pg011!)36KB@ hkN^pg011!)36KB@kN^pg011!)36KB@kU;DZ_ + Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl new file mode 100755 index 0000000..044007e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/AcpiTables/Dsdt.asl @@ -0,0 +1,53 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8316" +#define BOARD_CODEC_I2C "\\_SB.I2C7" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC4 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + include ("Gmac1.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host2.asl") + + Scope (I2C7) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..955ee56 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,330 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + /* Do not override, set by earlier boot stages. */ +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + /* Do not override, set by earlier boot stages. */ +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + switch (Id) { + case 1: + /* gmac1 iomux */ + BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; + BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; + BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; + + /* phy1 reset */ + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + break; + default: + break; + } +} + +VOID +EFIAPI +GmacIoPhyReset ( + UINT32 Id, + BOOLEAN Enable + ) +{ + switch (Id) { + case 1: + /* phy1 reset */ + GpioPinWrite (3, GPIO_PIN_PB7, !Enable); + break; + default: + break; + } +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + break; + case 2: + GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0 + break; + case 3: + break; + case 4: + break; + case 5: + break; + case 6: + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + + /* vcc5v0_host */ + GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PB5, TRUE); + + /* vcc_5v0 */ + GpioPinSetDirection (4, GPIO_PIN_PA3, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PA3, TRUE); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + // Set reset and power IO to gpio output mode + GpioPinSetDirection (0, GPIO_PIN_PC5, GPIO_PIN_OUTPUT); + GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT); + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + /* output high to enable power */ + GpioPinWrite (0, GPIO_PIN_PC5, Enable); + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + if(Segment == PCIE_SEGMENT_PCIE20L2) { + GpioPinWrite (3, GPIO_PIN_PD1, !Enable); + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER0, + .ChannelID = PWM_CHANNEL3, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM0_CH3 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (3, GPIO_PIN_PB2, 0xB); // PWM3_IR_M1 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (3, GPIO_PIN_PD5, FALSE); + GpioPinSetDirection (3, GPIO_PIN_PD5, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (3, GPIO_PIN_PD5, Enable); +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + GpioPinSetFunction(1, GPIO_PIN_PC4, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.Modules.fdf.inc new file mode 100644 index 0000000..653ba21 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-rock-5a.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc new file mode 100644 index 0000000..e41ca62 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc @@ -0,0 +1,115 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Molly Sophia +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ROCK5A + PLATFORM_VENDOR = Radxa + PLATFORM_GUID = 34bba9d2-8903-4403-969c-1a51b7c05f63 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # RK3588S-based platform + # +!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"ROCK 5 Model A" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Radxa" + gRockchipTokenSpaceGuid.PcdFamilyName|"ROCK 5" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.radxa.com/Rock5/hardware/5a" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-rock-5a" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x11 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x7 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + + # + # GMAC + # + gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x3a + gRK3588TokenSpaceGuid.PcdGmac1RxDelay|0x3e + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl new file mode 100755 index 0000000..bfdd8cf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl @@ -0,0 +1,54 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8316" +#define BOARD_CODEC_I2C "\\_SB.I2C7" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD5 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C7) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..2b49a67 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,384 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2 + break; + case 2: + break; + case 3: + break; + case 4: + GpioPinSetFunction(2, GPIO_PIN_PB5, 9); //i2c4_scl_m1 + GpioPinSetFunction(2, GPIO_PIN_PB4, 9); //i2c4_sda_m1 + break; + case 5: + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */ + GpioPinWrite (4, GPIO_PIN_PB0, TRUE); + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable blue led\n")); + // GpioPinWrite (0, GPIO_PIN_PB7, TRUE); + // GpioPinSetDirection (0, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 1); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 1); // PCIE30x1_0_{CLKREQN,WAKEN,PERSTN}_M1 + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinSetDirection (3, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 0); // PCIE20x1_2_{CLKREQN,WAKEN,PERSTN}_M0 + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* output high to enable power */ + + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (1, GPIO_PIN_PA4, Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (1, GPIO_PIN_PD2, Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + break; + default: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: // m.2 a+e key + GpioPinWrite (4, GPIO_PIN_PA5, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: // rtl8125b + GpioPinWrite (3, GPIO_PIN_PB0, !Enable); + break; + default: + break; + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER0, + .ChannelID = PWM_CHANNEL1, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM0_CH1 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (0, GPIO_PIN_PC0, 0x3); // PWM1_M0 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (0, GPIO_PIN_PB7, FALSE); + GpioPinSetDirection (0, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (0, GPIO_PIN_PB7, Enable); +} + +VOID +EFIAPI +PlatformPcieWiFiEnable ( + IN BOOLEAN Enable + ) +{ + // WiFi - enable + GpioPinWrite (0, GPIO_PIN_PC4, Enable); + GpioPinSetDirection (0, GPIO_PIN_PC4, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PA2, Enable); + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + + // bluetooth - enable + GpioPinWrite (3, GPIO_PIN_PD5, Enable); + GpioPinSetDirection (3, GPIO_PIN_PD5, GPIO_PIN_OUTPUT); + GpioPinWrite (3, GPIO_PIN_PA6, Enable); + GpioPinSetDirection (3, GPIO_PIN_PA6, GPIO_PIN_OUTPUT); + +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + PlatformPcieWiFiEnable(TRUE); + GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.Modules.fdf.inc new file mode 100644 index 0000000..9182ecb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-rock-5b.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.dsc new file mode 100644 index 0000000..efacaa1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.dsc @@ -0,0 +1,120 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2022, Xilin Wu +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ROCK5B + PLATFORM_VENDOR = Radxa + PLATFORM_GUID = cb957236-be75-4077-aa31-0c3eae75c09c + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"ROCK 5 Model B" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Radxa" + gRockchipTokenSpaceGuid.PcdFamilyName|"ROCK 5" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.radxa.com/Rock5/hardware/5b" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-rock-5b" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x7 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/AcpiTables/Dsdt.asl new file mode 100755 index 0000000..bfdd8cf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/AcpiTables/Dsdt.asl @@ -0,0 +1,54 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8316" +#define BOARD_CODEC_I2C "\\_SB.I2C7" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD5 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C7) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..67f5984 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,395 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2 + break; + case 2: + break; + case 3: + break; + case 4: + GpioPinSetFunction(2, GPIO_PIN_PB5, 9); //i2c4_scl_m1 + GpioPinSetFunction(2, GPIO_PIN_PB4, 9); //i2c4_sda_m1 + break; + case 5: + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* Set GPIO1 PA1 (USB_HOST_PWREN) output high to power USB ports */ + GpioPinWrite (1, GPIO_PIN_PA1, TRUE); + GpioPinSetDirection (1, GPIO_PIN_PA1, GPIO_PIN_OUTPUT); + /* Set GPIO2 PB6 (USB_TYPEC_PWREN) output high to power USB ports */ + GpioPinWrite (2, GPIO_PIN_PB6, TRUE); + GpioPinSetDirection (2, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable blue led\n")); + // GpioPinWrite (0, GPIO_PIN_PB7, TRUE); + // GpioPinSetDirection (0, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 1); + break; + case PCIE_SEGMENT_PCIE30X2: + GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 1); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 1); // PCIE30x1_0_{CLKREQN,WAKEN,PERSTN}_M1 + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinSetDirection (3, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 0); // PCIE20x1_2_{CLKREQN,WAKEN,PERSTN}_M0 + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* output high to enable power */ + + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + /* fall through */ + case PCIE_SEGMENT_PCIE30X2: + GpioPinWrite (1, GPIO_PIN_PA4, Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (1, GPIO_PIN_PD2, Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: + break; + default: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE30X2: + GpioPinWrite (4, GPIO_PIN_PB0, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: // m.2 a+e key + GpioPinWrite (4, GPIO_PIN_PA5, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + break; + case PCIE_SEGMENT_PCIE20L2: // rtl8125b + GpioPinWrite (3, GPIO_PIN_PB0, !Enable); + break; + default: + break; + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER0, + .ChannelID = PWM_CHANNEL1, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM0_CH1 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (0, GPIO_PIN_PC0, 0x3); // PWM1_M0 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (0, GPIO_PIN_PB7, FALSE); + GpioPinSetDirection (0, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (0, GPIO_PIN_PB7, Enable); +} + +VOID +EFIAPI +PlatformPcieWiFiEnable ( + IN BOOLEAN Enable + ) +{ + // WiFi - enable + GpioPinWrite (0, GPIO_PIN_PC4, Enable); + GpioPinSetDirection (0, GPIO_PIN_PC4, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PA2, Enable); + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + + // bluetooth - enable + GpioPinWrite (3, GPIO_PIN_PD5, Enable); + GpioPinSetDirection (3, GPIO_PIN_PD5, GPIO_PIN_OUTPUT); + +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + PlatformPcieWiFiEnable(TRUE); + GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.Modules.fdf.inc new file mode 100644 index 0000000..0a6cd9e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-rock-5b-plus.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc new file mode 100644 index 0000000..c463f24 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc @@ -0,0 +1,122 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2022, Xilin Wu +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2024, Yun Dou +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ROCK5BPlus + PLATFORM_VENDOR = Radxa + PLATFORM_GUID = b3a14308-f25c-4b69-9387-47e0de34e3b7 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"ROCK 5 Model B Plus" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Radxa" + gRockchipTokenSpaceGuid.PcdFamilyName|"ROCK 5" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://docs.radxa.com/en/rock5/rock5b" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-rock-5bp" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x7 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdPcie30PhyModeDefault|0 # NANBNB + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/AcpiTables/AcpiTables.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/AcpiTables/AcpiTables.inf new file mode 100644 index 0000000..35d333b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/AcpiTables/AcpiTables.inf @@ -0,0 +1,58 @@ +#/** @file +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2019-2021, ARM Limited. All rights reserved. +# Copyright (c) Microsoft Corporation. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + RK_COMMON_ACPI_DIR = Silicon/Rockchip/RK3588/AcpiTables + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + Dsdt.asl + $(RK_COMMON_ACPI_DIR)/Madt.aslc + $(RK_COMMON_ACPI_DIR)/Fadt.aslc + $(RK_COMMON_ACPI_DIR)/Gtdt.aslc + $(RK_COMMON_ACPI_DIR)/Spcr.aslc + $(RK_COMMON_ACPI_DIR)/Mcfg.aslc + $(RK_COMMON_ACPI_DIR)/Dbg2.aslc + $(RK_COMMON_ACPI_DIR)/Pptt.aslc + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/AcpiTables/Dsdt.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/AcpiTables/Dsdt.asl new file mode 100755 index 0000000..bfdd8cf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/AcpiTables/Dsdt.asl @@ -0,0 +1,54 @@ +/** @file + * + * Differentiated System Definition Table (DSDT) + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define BOARD_I2S0_TPLG "i2s-jack" + +#define BOARD_AUDIO_CODEC_HID "ESSX8316" +#define BOARD_CODEC_I2C "\\_SB.I2C7" +#define BOARD_CODEC_I2C_ADDR 0x11 +#define BOARD_CODEC_GPIO "\\_SB.GPI1" +#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PD5 + +DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP ", "RK3588 ", 2) +{ + Scope (\_SB_) + { + include ("DsdtCommon.asl") + + include ("Cpu.asl") + + include ("Pcie.asl") + include ("Sata.asl") + include ("Emmc.asl") + include ("Sdhc.asl") + include ("Dma.asl") + // include ("Gmac.asl") + include ("Gpio.asl") + include ("I2c.asl") + include ("Uart.asl") + // include ("Spi.asl") + + include ("I2s.asl") + + include ("Usb2Host.asl") + include ("Usb3Host0.asl") + include ("Usb3Host1.asl") + include ("Usb3Host2.asl") + + Scope (I2C7) { + include ("Es8388.asl") + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.c new file mode 100644 index 0000000..53941d4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.c @@ -0,0 +1,388 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct regulator_init_data rk806_init_data[] = { + /* Master PMIC */ + RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000), + //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000), + + RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000), + RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000), + + RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000), + RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000), + + /* No dual PMICs on this platform */ +}; + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ) +{ + /* sdmmc0 iomux (microSD socket) */ + BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3 + BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET +} + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ) +{ + /* sdhci0 iomux (eMMC socket) */ + BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3 + BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7 +} + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON59 0x03EC +#define CRU_CLKSEL_CON78 0x0438 + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ) +{ + /* io mux */ + //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888; + //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008; + PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110; + PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080); +} + +VOID +EFIAPI +Rk806Configure ( + VOID + ) +{ + UINTN RegCfgIndex; + + RK806Init(); + + for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++) + RK806RegulatorInit(rk806_init_data[RegCfgIndex]); +} + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ) +{ + struct regulator_init_data Rk806CpuLittleSupply = + RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts); + + RK806RegulatorInit(Rk806CpuLittleSupply); +} + +VOID +EFIAPI +NorFspiIomux ( + VOID + ) +{ + /* io mux */ + MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78, + (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6)); +#define FSPI_M1 +#if defined(FSPI_M0) + /*FSPI M0*/ + BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0 + BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0 +#elif defined(FSPI_M1) + /*FSPI M1*/ + BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1 + BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1 +#else + /*FSPI M2*/ + BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2] + BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2 + BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2 +#endif +} + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ) +{ + /* No GMAC here */ +} + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ) +{ + UINTN BaseAddr = (UINTN) CruBase; + + MmioWrite32(BaseAddr + 0x087C, 0x0E000000); +} + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ) +{ + switch (id) { + case 0: + GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2 + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PD4, 9); //i2c1_scl_m2 + GpioPinSetFunction(0, GPIO_PIN_PD5, 9); //i2c1_sda_m2 + break; + case 2: + break; + case 3: + break; + case 4: + GpioPinSetFunction(2, GPIO_PIN_PB5, 9); //i2c4_scl_m1 + GpioPinSetFunction(2, GPIO_PIN_PB4, 9); //i2c4_sda_m1 + break; + case 5: + break; + case 6: + GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0 + GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0 + break; + case 7: + GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0 + GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0 + break; + default: + break; + } +} + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ) +{ + DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n")); + /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */ + GpioPinWrite (3, GPIO_PIN_PB7, TRUE); + GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); + + // DEBUG((DEBUG_INFO, "Trying to enable blue led\n")); + // GpioPinWrite (0, GPIO_PIN_PB7, TRUE); + // GpioPinSetDirection (0, GPIO_PIN_PB7, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ) +{ + MmioWrite32(0xfd5d0008, 0x20000000); + MmioWrite32(0xfd5d4008, 0x20000000); + MmioWrite32(0xfd5d8008, 0x20000000); + MmioWrite32(0xfd5dc008, 0x20000000); + MmioWrite32(0xfd7f0a10, 0x07000700); + MmioWrite32(0xfd7f0a10, 0x07000000); +} + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ) +{ + /* Set reset and power IO to gpio output mode */ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); + GpioPinSetDirection (1, GPIO_PIN_PA4, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 1); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT); + GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 1); // PCIE30x1_0_{CLKREQN,WAKEN,PERSTN}_M1 + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT); + GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT); + break; + case PCIE_SEGMENT_PCIE20L2: + GpioPinSetDirection (3, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); + // PciePinmuxInit(Segment, 0); // PCIE20x1_2_{CLKREQN,WAKEN,PERSTN}_M0 + break; + default: + break; + } +} + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + /* output high to enable power */ + + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (1, GPIO_PIN_PA4, Enable); + break; + case PCIE_SEGMENT_PCIE20L0: + GpioPinWrite (1, GPIO_PIN_PD2, Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (1, GPIO_PIN_PD2, Enable); + break; + case PCIE_SEGMENT_PCIE20L2: + break; + default: + break; + } +} + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ) +{ + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + GpioPinWrite (4, GPIO_PIN_PB6, !Enable); + break; + case PCIE_SEGMENT_PCIE20L0: // m.2 a+e key + GpioPinWrite (4, GPIO_PIN_PA5, !Enable); + break; + case PCIE_SEGMENT_PCIE20L1: + GpioPinWrite (4, GPIO_PIN_PA2, !Enable); + break; + case PCIE_SEGMENT_PCIE20L2: // rtl8125b + GpioPinWrite (3, GPIO_PIN_PB0, !Enable); + break; + default: + break; + } +} + +PWM_DATA pwm_data = { + .ControllerID = PWM_CONTROLLER0, + .ChannelID = PWM_CHANNEL1, + .PeriodNs = 4000000, + .DutyNs = 4000000, + .Polarity = FALSE, +}; // PWM0_CH1 + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ) +{ + GpioPinSetFunction (4, GPIO_PIN_PB2, 0xb); // PWM14_M1 + RkPwmSetConfig (&pwm_data); + RkPwmEnable (&pwm_data); +} + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ) +{ + pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100; + RkPwmSetConfig (&pwm_data); +} + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ) +{ + /* Status indicator */ + GpioPinWrite (0, GPIO_PIN_PC0, FALSE); + GpioPinSetDirection (0, GPIO_PIN_PC0, GPIO_PIN_OUTPUT); +} + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ) +{ + GpioPinWrite (0, GPIO_PIN_PC0, Enable); +} + +VOID +EFIAPI +PlatformPcieWiFiEnable ( + IN BOOLEAN Enable + ) +{ + // WiFi - enable + GpioPinWrite (0, GPIO_PIN_PC4, Enable); + GpioPinSetDirection (0, GPIO_PIN_PC4, GPIO_PIN_OUTPUT); + GpioPinWrite (4, GPIO_PIN_PA0, Enable); + GpioPinSetDirection (4, GPIO_PIN_PA0, GPIO_PIN_OUTPUT); + + // bluetooth - enable + GpioPinWrite (4, GPIO_PIN_PC5, Enable); + GpioPinSetDirection (4, GPIO_PIN_PC5, GPIO_PIN_OUTPUT); + GpioPinWrite (2, GPIO_PIN_PC5, Enable); + GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT); + +} + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ) +{ + // Configure various things specific to this platform + PlatformPcieWiFiEnable(TRUE); + GpioPinSetFunction(1, GPIO_PIN_PD5, 0); //jdet +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.inf new file mode 100644 index 0000000..b0ca955 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/Library/RockchipPlatformLib/RockchipPlatformLib.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RockchipPlatformLib + FILE_GUID = 5178fa86-2fec-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RockchipPlatformLib + RKPLATLIB_COMMON_DIR = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + CruLib + GpioLib + PWMLib + +[Sources.common] + RockchipPlatformLib.c + $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.Modules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.Modules.fdf.inc new file mode 100644 index 0000000..f9c5770 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.Modules.fdf.inc @@ -0,0 +1,18 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + # ACPI Support + INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Device Tree Support + FILE FREEFORM = gDtPlatformDefaultDtbFileGuid { + SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-rock-5-itx.dtb + } + + # Splash screen logo + INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc new file mode 100644 index 0000000..8e4df6c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc @@ -0,0 +1,126 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2022, Xilin Wu +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ROCK5ITX + PLATFORM_VENDOR = Radxa + PLATFORM_GUID = cb957236-be75-4077-aa31-0c3eae75c09c + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Silicon/Rockchip/RK3588/RK3588.fdf + RK_PLATFORM_FVMAIN_MODULES = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc + + # + # HYM8563 RTC support + # I2C location configured by PCDs below. + # + DEFINE RK_RTC8563_ENABLE = TRUE + + # + # RK3588-based platform + # +!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc + +################################################################################ +# +# Library Class section - list of all Library Classes needed by this Platform. +# +################################################################################ + +[LibraryClasses.common] + RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"ROCK 5 ITX" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Radxa" + gRockchipTokenSpaceGuid.PcdFamilyName|"ROCK 5" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://docs.radxa.com/rock5/rock5itx" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-rock-5-itx" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 ,0x22} + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x7 } + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) } + gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51 + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6 + + # + # HDMI1 Display + # + gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE) + + # + # USB/DP Combo PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 } + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 } + + # + # I2S + # + gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE + + # + # On-Board fan output + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE + + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +################################################################################ +[Components.common] + # ACPI Support + $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf + + # Splash screen logo + $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.bmp b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.bmp new file mode 100644 index 0000000000000000000000000000000000000000..0499e1884c34cdaa622dd0097900ccc99ec74789 GIT binary patch literal 106738 zcmeHQd3+Q_zK4*6BtQtcPjVmRo|yy*ceun0&qYA-K;(*mipV0X?y4-vO$Y=Kk^4{) z5f4yw)xFf+eQ$lfJ)erVoCzQ^6ZWt7t*)6)r>ncCy2AvRDLxHU_tf#LZ+-jMzu&K_ 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a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.c new file mode 100644 index 0000000..2255b11 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.c @@ -0,0 +1,144 @@ +/** @file + Logo DXE Driver, install Edkii Platform Logo protocol. + + Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    + Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_IMAGE_ID ImageId; + EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute; + INTN OffsetX; + INTN OffsetY; +} LOGO_ENTRY; + +STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx; +STATIC EFI_HII_HANDLE mHiiHandle; +STATIC LOGO_ENTRY mLogos[] = { + { + IMAGE_TOKEN (IMG_LOGO), + EdkiiPlatformLogoDisplayAttributeCenter, + 0, + 0 + } +}; + +/** + Load a platform logo image and return its data and attributes. + + @param This The pointer to this protocol instance. + @param Instance The visible image instance is found. + @param Image Points to the image. + @param Attribute The display attributes of the image returned. + @param OffsetX The X offset of the image regarding the Attribute. + @param OffsetY The Y offset of the image regarding the Attribute. + + @retval EFI_SUCCESS The image was fetched successfully. + @retval EFI_NOT_FOUND The specified image could not be found. +**/ +STATIC +EFI_STATUS +EFIAPI +GetImage ( + IN EDKII_PLATFORM_LOGO_PROTOCOL *This, + IN OUT UINT32 *Instance, + OUT EFI_IMAGE_INPUT *Image, + OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute, + OUT INTN *OffsetX, + OUT INTN *OffsetY + ) +{ + UINT32 Current; + + if (Instance == NULL || Image == NULL || + Attribute == NULL || OffsetX == NULL || OffsetY == NULL) { + return EFI_INVALID_PARAMETER; + } + + Current = *Instance; + if (Current >= ARRAY_SIZE (mLogos)) { + return EFI_NOT_FOUND; + } + + (*Instance)++; + *Attribute = mLogos[Current].Attribute; + *OffsetX = mLogos[Current].OffsetX; + *OffsetY = mLogos[Current].OffsetY; + + return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle, + mLogos[Current].ImageId, Image); +} + +STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = { + GetImage +}; + +/** + Entrypoint of this module. + + This function is the entrypoint of this module. It installs the Edkii + Platform Logo protocol. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + +**/ +EFI_STATUS +EFIAPI +InitializeLogo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HANDLE Handle; + + Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, + (VOID **) &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL, + (VOID **) &mHiiImageEx); + ASSERT_EFI_ERROR (Status); + + // + // Retrieve HII package list from ImageHandle + // + Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid, + (VOID **) &PackageList, ImageHandle, NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "HII Image Package with logo not found in PE/COFF resource section\n")); + return Status; + } + + // + // Publish HII package list to HII Database. + // + Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL, + &mHiiHandle); + if (!EFI_ERROR (Status)) { + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL); + } + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.idf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.idf new file mode 100644 index 0000000..c2d9096 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/Logo.idf @@ -0,0 +1,10 @@ +// @file +// Platform Logo image definition file. +// +// Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +// Copyright (c) 2022 Rockchip Electronics Co. Ltd. +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// + +#image IMG_LOGO Logo.bmp diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/LogoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/LogoDxe.inf new file mode 100644 index 0000000..e7a35de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/Drivers/LogoDxe/LogoDxe.inf @@ -0,0 +1,48 @@ +## @file +# The default logo bitmap picture shown on setup screen. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
    +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LogoDxe + FILE_GUID = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeLogo +# +# This flag specifies whether HII resource section is generated into PE image. +# + UEFI_HII_RESOURCE_SECTION = TRUE + +[Sources] + Logo.bmp + Logo.c + Logo.idf + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiHiiDatabaseProtocolGuid ## CONSUMES + gEfiHiiImageExProtocolGuid ## CONSUMES + gEfiHiiPackageListProtocolGuid ## PRODUCES CONSUMES + gEdkiiPlatformLogoProtocolGuid ## PRODUCES + +[Depex] + gEfiHiiDatabaseProtocolGuid AND + gEfiHiiImageExProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/StationM3/StationM3.dsc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/StationM3/StationM3.dsc new file mode 100644 index 0000000..17dd5f8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/StationPC/StationM3/StationM3.dsc @@ -0,0 +1,52 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = StationM3 + PLATFORM_VENDOR = StationPC + PLATFORM_GUID = c292d925-29ff-4327-9ed9-517c9d921840 + PLATFORM_VERSION = 0.2 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + VENDOR_DIRECTORY = Platform/$(PLATFORM_VENDOR) + PLATFORM_DIRECTORY = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + + # + # Platform based on ROC-RK3588S-PC board + # +!include Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdPlatformName|"Station M3" + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Station PC" + gRockchipTokenSpaceGuid.PcdFamilyName|"Station M" + gRockchipTokenSpaceGuid.PcdProductUrl|"https://www.stationpc.com/product/stationm3" + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"roc-rk3588s-pc" + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX) diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.c new file mode 100644 index 0000000..2bae038 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.c @@ -0,0 +1,356 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. +Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +*******************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +CONST CHAR16 ShellI2cDemoFileName[] = L"I2cDemoTestShellCommand"; +EFI_HANDLE ShellI2cDemoHiiHandle = NULL; + +STATIC CONST SHELL_PARAM_ITEM ParamList[] = { + {L"read", TypeFlag}, + {L"write", TypeFlag}, + {L"list", TypeFlag}, + {L"help", TypeFlag}, + {NULL , TypeMax} + }; + +/** + Return the file name of the help text file if not using HII. + + @return The string pointer to the file name. +**/ +STATIC +CONST CHAR16* +EFIAPI +ShellCommandGetManFileNameI2cDemo ( + VOID + ) +{ + return ShellI2cDemoFileName; +} + +STATIC +VOID +Usage ( + VOID + ) +{ + Print (L"I2C DEMO TEST commands:\n" + "i2cdemo [read] [write] [list] [][

    ] [] [] [] [] \n" + "All modes except 'list' require Address, Length and Chip set.\n\n" + "read - read from i2cdemo device\n" + "write - write Data to i2cdemo device\\n" + "list - list available i2cdemo devices\n\n" + "Bus - I2C bus address\n" + "Address - i2cdemo bus address\n" + "Length - data byte length to read/write\\n" + "RegAddress - address in i2cdemo to read/write\n" + "RegAddressLength - address in i2cdemo length\n" + "Data - data byte to be written\n" + "Examples:\n" + "List devices:\n" + " i2cdemo list\n" + "Read 2 bytes from address 0x10 in chip 0x51@bus2:\n" + " i2cdemo read 2 0x51 2 0x10 1\n" + "Fill 16 bytes with 0xab at address 0x0 in chip 0x57:\n" + " i2cdemo write 2 0x51 1 0x10 1 0x00\n" + ); +} + +STATIC +EFI_STATUS +I2cDemoList ( + ) +{ + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + UINTN ProtocolCount; + ROCKCHIP_I2CDEMO_PROTOCOL *I2cDemoProtocol; + UINTN i; + Status = gBS->LocateHandleBuffer ( ByProtocol, + &gRockchipI2cDemoProtocolGuid, + NULL, + &ProtocolCount, + &HandleBuffer + ); + if (ProtocolCount == 0) { + Print (L"0 devices found.\n"); + } else { + Print (L"%u devices found: ", ProtocolCount); + } + + for (i = 0; i < ProtocolCount; i++) { + Status = gBS->OpenProtocol ( + HandleBuffer[i], + &gRockchipI2cDemoProtocolGuid, + (VOID **) &I2cDemoProtocol, + gImageHandle, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL ); + Print (L"0x%x at bus %d\n", I2C_DEVICE_ADDRESS(I2cDemoProtocol->Identifier), + I2C_DEVICE_BUS(I2cDemoProtocol->Identifier)); + Status = gBS->CloseProtocol ( HandleBuffer[i], + &gRockchipI2cDemoProtocolGuid, + gImageHandle, + NULL ); + } + Print (L"\n"); + return Status; +} + +STATIC +EFI_STATUS +I2cDemoLocateProtocol ( + IN UINT32 Identifier, + OUT EFI_HANDLE *FoundHandle, + OUT ROCKCHIP_I2CDEMO_PROTOCOL **FoundI2cDemoProtocol + ) +{ + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + UINTN ProtocolCount; + ROCKCHIP_I2CDEMO_PROTOCOL *I2cDemoProtocol; + UINTN i; + Status = gBS->LocateHandleBuffer ( ByProtocol, + &gRockchipI2cDemoProtocolGuid, + NULL, + &ProtocolCount, + &HandleBuffer + ); + if (EFI_ERROR(Status)) { + return Status; + } + for (i = 0; i < ProtocolCount; i++) { + Status = gBS->OpenProtocol ( + HandleBuffer[i], + &gRockchipI2cDemoProtocolGuid, + (VOID **) &I2cDemoProtocol, + gImageHandle, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL ); + + if (I2cDemoProtocol->Identifier == Identifier) { + *FoundI2cDemoProtocol = I2cDemoProtocol; + *FoundHandle = HandleBuffer[i]; + return EFI_SUCCESS; + } + Status = gBS->CloseProtocol ( HandleBuffer[i], + &gRockchipI2cDemoProtocolGuid, + gImageHandle, + NULL ); + } + *FoundI2cDemoProtocol = NULL; + + return EFI_UNSUPPORTED; +} + +SHELL_STATUS +EFIAPI +ShellCommandRunI2cDemo ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + LIST_ENTRY *CheckPackage; + CHAR16 *ProblemParam; + CONST CHAR16 *ValueStr; + UINTN Bus, Address, XferLength, RegAddress, RegAddressLength, Source; + UINT8 *Buffer; + BOOLEAN ReadMode, WriteMode; + EFI_HANDLE Handle, ProtHandle; + ROCKCHIP_I2CDEMO_PROTOCOL *I2cDemoProtocol = NULL; + UINTN HandleSize, i; + UINTN TxData; + + Handle = NULL; + Source = 0; + HandleSize = 2 * sizeof (EFI_HANDLE); + + Status = gBS->LocateHandle (ByProtocol, &gRockchipI2cDemoProtocolGuid, NULL, + &HandleSize, &ProtHandle); + if (EFI_ERROR(Status)) { + Print (L"No I2cDemo protocol, connect I2C stack\n"); + Status = gBS->LocateHandle (ByProtocol, &gEfiI2cMasterProtocolGuid, NULL, + &HandleSize, &ProtHandle); + if (EFI_ERROR(Status)) { + Print (L"Failed to locate I2cMaster protocol, abort!\n"); + return SHELL_ABORTED; + } + Status = gBS->ConnectController (ProtHandle, NULL, NULL, TRUE); + if (EFI_ERROR(Status)) { + Print (L"Cannot connect I2C stack, abort!\n"); + return SHELL_ABORTED; + } + } + + Status = ShellInitialize (); + if (EFI_ERROR (Status)) { + Print (L"Error - failed to initialize shell\n"); + return SHELL_ABORTED; + } + + Status = ShellCommandLineParse (ParamList, &CheckPackage, &ProblemParam, TRUE); + if (EFI_ERROR (Status)) { + Print (L"Error - failed to parse command line\n"); + return SHELL_ABORTED; + } + + if (ShellCommandLineGetFlag (CheckPackage, L"list")) { + I2cDemoList(); + return SHELL_SUCCESS; + } + + if (ShellCommandLineGetFlag (CheckPackage, L"help")) { + Usage(); + return SHELL_SUCCESS; + } + + ReadMode = ShellCommandLineGetFlag (CheckPackage, L"read"); + WriteMode = ShellCommandLineGetFlag (CheckPackage, L"write"); + + if (!ReadMode && !WriteMode) { + Print (L"Not support mode given.\n"); + Usage(); + return SHELL_ABORTED; + } + + if (ShellCommandLineGetCount(CheckPackage) != 6 && ReadMode) { + Print (L"Not enough arguments given.\n"); + Usage(); + return SHELL_ABORTED; + } + + if (ShellCommandLineGetCount(CheckPackage) != 7 && WriteMode) { + Print (L"Not enough arguments given.\n"); + Usage(); + return SHELL_ABORTED; + } + + ValueStr = ShellCommandLineGetRawValue(CheckPackage, 1); + Bus = ShellHexStrToUintn (ValueStr); + + ValueStr = ShellCommandLineGetRawValue(CheckPackage, 2); + Address = ShellHexStrToUintn (ValueStr); + + ValueStr = ShellCommandLineGetRawValue(CheckPackage, 3); + XferLength = ShellHexStrToUintn (ValueStr); + + ValueStr = ShellCommandLineGetRawValue(CheckPackage, 4); + RegAddress = ShellHexStrToUintn (ValueStr); + + ValueStr = ShellCommandLineGetRawValue(CheckPackage, 5); + RegAddressLength = ShellHexStrToUintn (ValueStr); + + if (WriteMode) { + ValueStr = ShellCommandLineGetRawValue(CheckPackage, 6); + TxData = ShellHexStrToUintn (ValueStr); + } + + I2cDemoLocateProtocol (I2C_DEVICE_INDEX(Bus, Address), &Handle, &I2cDemoProtocol); + if (I2cDemoProtocol == NULL) { + Print (L"Failed to locate I2CDEMO protocol.\n"); + return SHELL_INVALID_PARAMETER; + } + + Buffer = AllocateZeroPool (XferLength); + if (Buffer == NULL) { + Status = SHELL_OUT_OF_RESOURCES; + Print (L"Error - out of resources.\n"); + goto out_close; + } + + if (ReadMode) { + Status = I2cDemoProtocol->Read(I2cDemoProtocol, (UINT8 *)&RegAddress, RegAddressLength, Buffer, XferLength); + if (!EFI_ERROR(Status)) { + Print (L"Read data[0 ~ %d]:", XferLength - 1); + for (i = 0; i Write(I2cDemoProtocol, (UINT8 *)&RegAddress, RegAddressLength, (UINT8 *)&TxData, XferLength); + } + + if (EFI_ERROR(Status)) { + Print (L"I2c Operation failed %d.\n", Status); + } else { + Print (L"I2c Operation successfully.\n"); + } + + Status = SHELL_SUCCESS; + + FreePool(Buffer); +out_close: + gBS->CloseProtocol ( Handle, + &gRockchipI2cDemoProtocolGuid, + gImageHandle, + NULL ); + + return Status; +} + +EFI_STATUS +EFIAPI +ShellI2cDemoTestLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + Print (L"~Filed to add Hii package\n"); + ShellI2cDemoHiiHandle = NULL; + + ShellI2cDemoHiiHandle = HiiAddPackages ( + &gShellI2cDemoHiiGuid, gImageHandle, + UefiShellI2cDemoLibStrings, NULL + ); + if (ShellI2cDemoHiiHandle == NULL) { + Print (L"Filed to add Hii package\n"); + return EFI_DEVICE_ERROR; + } + ShellCommandRegisterCommandName ( + L"i2cdemo", ShellCommandRunI2cDemo, ShellCommandGetManFileNameI2cDemo, 0, + L"i2cdemo", TRUE , ShellI2cDemoHiiHandle, STRING_TOKEN (STR_GET_HELP_I2CDEMO) + ); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +ShellI2cDemoTestLibDestructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + if (ShellI2cDemoHiiHandle != NULL) { + HiiRemovePackages (ShellI2cDemoHiiHandle); + } + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf new file mode 100644 index 0000000..8d669e3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf @@ -0,0 +1,45 @@ +# +# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = UefiShellI2cDemoLib + FILE_GUID = adf4b61c-2ca3-4e1a-9597-99282f5a4aa2 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 0.1 + LIBRARY_CLASS = NULL|UEFI_APPLICATION UEFI_DRIVER + CONSTRUCTOR = ShellI2cDemoTestLibConstructor + DESTRUCTOR = ShellI2cDemoTestLibDestructor + +[Sources] + I2cDemoTest.c + I2cDemoTest.uni + +[Packages] + MdePkg/MdePkg.dec + ShellPkg/ShellPkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + UefiLib + UefiBootServicesTableLib + MemoryAllocationLib + BaseLib + BaseMemoryLib + DebugLib + ShellCommandLib + ShellLib + UefiLib + UefiRuntimeServicesTableLib + PcdLib + +[Protocols] + gRockchipI2cDemoProtocolGuid + gEfiI2cMasterProtocolGuid + +[Guids] + gShellI2cDemoHiiGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.uni b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.uni new file mode 100644 index 0000000..e672dfc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.uni @@ -0,0 +1,49 @@ +/******************************************************************************* +Copyright (C) 2016 Marvell International Ltd. +Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +*******************************************************************************/ + +/=# +#langdef en-US "english" + +#string STR_GET_HELP_I2CDEMO #language en-US "" +".TH i2cdemo 0 "Basic I2CDEMO command."\r\n" +".SH NAME\r\n" +"Read/write data from/into I2cDemo Device memory\r\n" +".SH SYNOPSIS\r\n" +" \r\n" +"i2cdemo [read] [write] [list] [][
    ] [] []\r\n" +" [] []\r\n" +".SH OPTIONS\r\n" +" \r\n" +"All modes except 'list' require Address, Length and Chip set.\n\n" +"read - read from i2cdemo device\n" +"write - write Data to i2cdemo device\\n" +"list - list available i2cdemo devices\n\n" +"Bus - I2C bus address\n" +"Address - i2cdemo bus address\n" +"Length - data byte length to read/write\\n" +"RegAddress - address in i2cdemo to read/write\n" +"RegAddressLength - address in i2cdemo length\n" +"Data - data byte to be written\n" +"Examples:\n" +"List devices:\n" +" i2cdemo list\n" +" \r\n" +"EXAMPLES:\r\n" +"List devices:\r\n" +" i2cdemo list\r\n" +"Read 2 bytes from address 0x10 in chip 0x51@bus2:\n" +" i2cdemo read 2 0x51 2 0x10 1\n" +"Fill 16 bytes with 0xab at address 0x0 in chip 0x57:\n" +" i2cdemo write 2 0x51 1 0x10 1 0x00\n" +".SH RETURNVALUES\r\n" +" \r\n" +"RETURN VALUES:\r\n" +" SHELL_SUCCESS The action was completed as requested.\r\n" +" SHELL_ABORTED Error while processing command\r\n" + + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.c new file mode 100755 index 0000000..09edf64 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.c @@ -0,0 +1,417 @@ +/******************************************************************************* +Copyright (c) 2022, Rockchip Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +*******************************************************************************/ +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +UNI_NOR_FLASH_PROTOCOL *SpiFlashProtocol; + +CONST CHAR16 gShellSpiFlashFileName[] = L"ShellCommand"; +EFI_HANDLE gShellSfHiiHandle = NULL; + +STATIC CONST SHELL_PARAM_ITEM ParamList[] = { + {L"read", TypeFlag}, + {L"readfile", TypeFlag}, + {L"write", TypeFlag}, + {L"writefile", TypeFlag}, + {L"erase", TypeFlag}, + {L"update", TypeFlag}, + {L"updatefile", TypeFlag}, + {L"help", TypeFlag}, + {NULL , TypeMax} + }; + +typedef enum { + READ = 2, + READ_FILE = 4, + WRITE = 8, + WRITE_FILE = 16, + ERASE = 32, + UPDATE = 64, + UPDATE_FILE = 128, +} Flags; + +/** + Return the file name of the help text file if not using HII. + + @return The string pointer to the file name. +**/ +CONST CHAR16* +EFIAPI +ShellCommandGetManFileNameSpiFlash ( + VOID + ) +{ + + return gShellSpiFlashFileName; +} + +VOID +SfUsage ( + VOID + ) +{ + Print (L"\nBasic SPI command\n" + "sf [read | readfile | write | writefile | erase |" + "update | updatefile]" + "[
    | ] \n\n" + "Address - Address in RAM to store/load data\n" + "FilePath - Path to file to read/write data from/to\n" + "Offset - Offset from beginning of SPI flash to store/load data\n" + "Length - Number of bytes to send\n" + "Examples:\n" + "Check if there is response from SPI flash\n" + "Read 32 bytes from 0xe00000 of SPI flash into RAM at address 0x100000\n" + " sf read 0x100000 0xe00000 32\n" + "Read 0x20 bytes from 0x200000 of SPI flash into RAM at address 0x300000\n" + " sf read 0x300000 0x200000 0x20\n" + "Erase 0x10000 bytes from offset 0x100000 of SPI flash\n" + " sf erase 0x100000 0x100000\n" + "Write 16 bytes from 0x200000 at RAM into SPI flash at address 0x4000000\n" + " sf write 0x200000 0x4000000 16\n" + "Update 100 bytes from 0x100000 at RAM in SPI flash at address 0xe00000\n" + " sf update 0x100000 0xe00000 100\n" + "Read 0x3000 bytes from 0x0 of SPI flash into file fs2:file.bin\n" + " sf readfile fs2:file.bin 0x0 0x3000 \n" + "Update data in SPI flash at 0x3000000 from file Linux.efi\n" + " sf updatefile Linux.efi 0x3000000\n" + ); +} + +STATIC +EFI_STATUS +OpenAndPrepareFile ( + IN CHAR16 *FilePath, + SHELL_FILE_HANDLE *FileHandle + ) +{ + EFI_STATUS Status; + UINT64 OpenMode; + + OpenMode = EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE; + + Status = ShellOpenFileByName (FilePath, FileHandle, OpenMode, 0); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot open file\n"); + return Status; + } + + Status = FileHandleSetPosition(*FileHandle, 0); + + if (EFI_ERROR(Status)) { + Print (L"sf: Cannot set file position to first byte\n"); + ShellCloseFile (FileHandle); + return Status; + } + + return EFI_SUCCESS; +} + +SHELL_STATUS +EFIAPI +ShellCommandRunSpiFlash ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ +EFI_STATUS Status; + LIST_ENTRY *CheckPackage; + EFI_PHYSICAL_ADDRESS Address = 0, Offset = 0; + SHELL_FILE_HANDLE FileHandle = NULL; + UINTN ByteCount, I; + UINT64 FileSize; + UINT8 *Buffer = NULL, *FileBuffer = NULL; + CHAR16 *ProblemParam, *FilePath; + CONST CHAR16 *AddressStr = NULL, *OffsetStr = NULL; + CONST CHAR16 *LengthStr = NULL, *FileStr = NULL; + BOOLEAN AddrFlag = FALSE, LengthFlag = TRUE, FileFlag = FALSE; + UINT8 Flag = 0, CheckFlag = 0; + + Status = gBS->LocateProtocol ( + &gUniNorFlashProtocolGuid, + NULL, + (VOID **)&SpiFlashProtocol + ); + if (EFI_ERROR(Status)) { + Print (L"sf: Cannot locate SpiFlash protocol\n"); + return SHELL_ABORTED; + } + + // Parse Shell command line + Status = ShellInitialize (); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot initialize Shell\n"); + ASSERT_EFI_ERROR (Status); + return SHELL_ABORTED; + } + + Status = ShellCommandLineParse (ParamList, &CheckPackage, &ProblemParam, TRUE); + if (EFI_ERROR (Status)) { + Print (L"sf: Error while parsing command line\n"); + return SHELL_ABORTED; + } + + if (ShellCommandLineGetFlag (CheckPackage, L"help")) { + SfUsage(); + return EFI_SUCCESS; + } + + // Check flags provided by user + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"read") << 1); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"readfile") << 2); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"write") << 3); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"writefile") << 4); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"erase") << 5); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"update") << 6); + Flag |= (ShellCommandLineGetFlag (CheckPackage, L"updatefile") << 7); + + CheckFlag = Flag; + for (I = 0; CheckFlag; CheckFlag >>= 1) { + I += CheckFlag & 1; + if (I > 1) { + Print (L"sf: Too many flags\n"); + SfUsage(); + return SHELL_ABORTED; + } + } + + switch (Flag) { + case READ: + case WRITE: + case UPDATE: + AddressStr = ShellCommandLineGetRawValue (CheckPackage, 1); + OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2); + LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3); + AddrFlag = TRUE; + break; + case ERASE: + OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 1); + LengthStr = ShellCommandLineGetRawValue (CheckPackage, 2); + break; + case READ_FILE: + FileStr = ShellCommandLineGetRawValue (CheckPackage, 1); + OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2); + LengthStr = ShellCommandLineGetRawValue (CheckPackage, 3); + FileFlag = TRUE; + break; + case WRITE_FILE: + case UPDATE_FILE: + FileStr = ShellCommandLineGetRawValue (CheckPackage, 1); + OffsetStr = ShellCommandLineGetRawValue (CheckPackage, 2); + LengthFlag = FALSE; + FileFlag = TRUE; + break; + } + + // Read address parameter + if ((AddressStr == NULL) & AddrFlag) { + Print (L"sf: No address parameter!\n"); + return SHELL_ABORTED; + } else if (AddrFlag) { + Address = ShellHexStrToUintn (AddressStr); + if (Address == (UINTN)(-1)) { + Print (L"sf: Wrong address parameter\n"); + return SHELL_ABORTED; + } + } + + // Read offset parameter + if (OffsetStr == NULL) { + Print (L"sf: No offset Parameter!\n"); + return SHELL_ABORTED; + } else { + Offset = ShellHexStrToUintn (OffsetStr); + if (Offset < 0) { + Print (L"sf: Wrong offset parameter: %s", OffsetStr); + return SHELL_ABORTED; + } + } + + // Read length parameter + if ((LengthStr == NULL) & LengthFlag) { + Print (L"sf: No lenght parameter!\n"); + return SHELL_ABORTED; + } else if (LengthFlag) { + ByteCount = ShellStrToUintn (LengthStr); + if (ByteCount < 0) { + Print (L"sf: Wrong length parameter %s!\n", LengthStr); + return SHELL_ABORTED; + } + } + + if (FileFlag) { + // Read FilePath parameter + if (FileStr == NULL) { + Print (L"sf: No FilePath parameter!\n"); + return SHELL_ABORTED; + } else { + FilePath = (CHAR16 *) FileStr; + Status = ShellIsFile (FilePath); + // When read file into flash, file doesn't have to exist + if (EFI_ERROR (Status) && !(Flag & READ_FILE)) { + Print (L"sf: Wrong FilePath parameter!\n"); + return SHELL_ABORTED; + } + } + + Status = OpenAndPrepareFile (FilePath, &FileHandle); + if (EFI_ERROR(Status)) { + Print (L"sf: Error while preparing file\n"); + return SHELL_ABORTED; + } + + // Get file size in order to check correctness at the end of transfer + if (Flag & (WRITE_FILE | UPDATE_FILE)) { + Status = FileHandleGetSize (FileHandle, &FileSize); + if (EFI_ERROR (Status)) { + Print (L"sf: Cannot get file size\n"); + } + ByteCount = (UINTN) FileSize; + } + + FileBuffer = AllocateZeroPool ((UINTN) ByteCount); + if (FileBuffer == NULL) { + Print (L"sf: Cannot allocate memory\n"); + goto Error_Close_File; + } + + // Read file content and store it in FileBuffer + if (Flag & (WRITE_FILE | UPDATE_FILE)) { + Status = FileHandleRead (FileHandle, &ByteCount, FileBuffer); + if (EFI_ERROR (Status)) { + Print (L"sf: Read from file error\n"); + goto Error_Free_Buffer; + } else if (ByteCount != (UINTN) FileSize) { + Print (L"sf: Not whole file read. Abort\n"); + goto Error_Free_Buffer; + } + } + } + + Buffer = (UINT8 *)(UINTN)Address; + if (FileFlag) { + Buffer = FileBuffer; + } + + switch (Flag) { + case READ: + case READ_FILE: + Status = SpiFlashProtocol->Read (SpiFlashProtocol, Offset, Buffer, ByteCount); + break; + case ERASE: + Status = SpiFlashProtocol->Erase (SpiFlashProtocol, Offset, ByteCount); + break; + case WRITE: + case WRITE_FILE: + Status = SpiFlashProtocol->Write (SpiFlashProtocol, Offset, Buffer, ByteCount); + break; + case UPDATE: + case UPDATE_FILE: + Status = SpiFlashProtocol->Update (SpiFlashProtocol, Offset, Buffer, ByteCount); + break; + } + + if (EFI_ERROR (Status)) { + Print (L"sf: Error while performing spi transfer\n"); + return SHELL_ABORTED; + } + + switch (Flag) { + case ERASE: + Print (L"sf: %d bytes succesfully erased at offset 0x%x\n", ByteCount, + Offset); + break; + case WRITE: + case WRITE_FILE: + Print (L"sf: Write %d bytes at offset 0x%x\n", ByteCount, Offset); + break; + case UPDATE: + case UPDATE_FILE: + Print (L"sf: Update %d bytes at offset 0x%x\n", ByteCount, Offset); + break; + case READ: + Print (L"sf: Read %d bytes from offset 0x%x\n", ByteCount, Offset); + break; + case READ_FILE: + Status = FileHandleWrite (FileHandle, &ByteCount, FileBuffer); + if (EFI_ERROR(Status)) { + Print (L"sf: Error while writing into file\n"); + goto Error_Free_Buffer; + } + break; + } + + if (FileFlag) { + FreePool (FileBuffer); + + if (FileHandle != NULL) { + ShellCloseFile (&FileHandle); + } + } + + return EFI_SUCCESS; + +Error_Free_Buffer: + FreePool (FileBuffer); +Error_Close_File: + ShellCloseFile (&FileHandle); + return SHELL_ABORTED; +} + +EFI_STATUS +EFIAPI +ShellSpiFlashLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + gShellSfHiiHandle = NULL; + + gShellSfHiiHandle = HiiAddPackages ( + &gShellSfHiiGuid, gImageHandle, + UefiShellSpiFlashLibStrings, NULL + ); + if (gShellSfHiiHandle == NULL) { + return EFI_DEVICE_ERROR; + } + + ShellCommandRegisterCommandName ( + L"sf", ShellCommandRunSpiFlash, ShellCommandGetManFileNameSpiFlash, 0, + L"sf", TRUE , gShellSfHiiHandle, STRING_TOKEN (STR_GET_HELP_SF) + ); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +ShellSpiFlashLibDestructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + if (gShellSfHiiHandle != NULL) { + HiiRemovePackages (gShellSfHiiHandle); + } + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf new file mode 100644 index 0000000..b71014f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf @@ -0,0 +1,46 @@ +# +# Copyright (c) 2022, Rockchip Limited. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = UefiShellSpiFlashLib + FILE_GUID = 2f2dd8c9-221f-4acf-afe5-5897264c5774 + MODULE_TYPE = UEFI_APPLICATION + VERSION_STRING = 0.1 + LIBRARY_CLASS = NULL|UEFI_APPLICATION UEFI_DRIVER + CONSTRUCTOR = ShellSpiFlashLibConstructor + DESTRUCTOR = ShellSpiFlashLibDestructor + +[Sources] + SpiFlashCmd.c + SpiFlashCmd.uni + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + ShellPkg/ShellPkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + UefiLib + UefiBootServicesTableLib + MemoryAllocationLib + BaseLib + BaseMemoryLib + DebugLib + ShellCommandLib + ShellLib + UefiLib + UefiRuntimeServicesTableLib + PcdLib + HiiLib + FileHandleLib + +[Protocols] + gUniNorFlashProtocolGuid + +[Guids] + gShellSfHiiGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.uni b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.uni new file mode 100755 index 0000000..986785d --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.uni @@ -0,0 +1,50 @@ +/******************************************************************************* +Copyright (c) 2022, Rockchip Corporation. All rights reserved. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +*******************************************************************************/ + +/=# + +#langdef en-US "english" + +#string STR_GET_HELP_SF #language en-US "" +".TH sf 0 "Basic SPI flash command."\r\n" +".SH NAME\r\n" +"Read/write data from/into SPI flash.\r\n" +".SH SYNOPSIS\r\n" +" \r\n" +"sf [read | readfile | write | writefile | erase | \r\n" +" update | updatefile] \r\n" +".SH OPTIONS\r\n" +" \r\n" +" Length - Number of bytes to send\r\n" +" Address - Address in RAM to store/load data\r\n" +" Offset - Offset from beginning of SPI flash to store/load data\r\n" +" FilePath - Path to file to read data into or write/update data from \r\n" +".SH EXAMPLES\r\n" +" \r\n" +"EXAMPLES:\r\n" +"Check if there is response from SPI flash\r\n" +"Read 32 bytes from 0xe00000 of SPI flash into RAM at address 0x100000\r\n" +" sf read 0x100000 0xe00000 32\r\n" +"Read 0x20 bytes from 0x200000 of SPI flash into RAM at address 0x300000\r\n" +" sf read 0x300000 0x200000 0x20\r\n" +"Erase 0x10000 bytes from offset 0x100000 of SPI flash\r\n" +" sf erase 0x100000 0x100000\r\n" +"Write 16 bytes from 0x200000 at RAM into SPI flash at address 0x4000000\r\n" +" sf write 0x200000 0x4000000 16\r\n" +"Update 100 bytes from 0x100000 at RAM in SPI flash at address 0xe00000\r\n" +" sf update 0x100000 0xe00000 100\r\n" +"Read 0x3000 bytes from 0x0 of SPI flash into file fs2:file.bin\r\n" +" sf readfile fs2:file.bin 0x0 0x3000\r\n" +"Update data in SPI flash at 0x3000000 from file Linux.efi\r\n" +" sf update Linux.efi 0x3000000\r\n" +".SH RETURNVALUES\r\n" +" \r\n" +"RETURN VALUES:\r\n" +" SHELL_SUCCESS The action was completed as requested.\r\n" +" SHELL_ABORTED Error while processing command\r\n" + + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.c new file mode 100644 index 0000000..595d5ec --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.c @@ -0,0 +1,276 @@ +/** @file + * + * Synopsys DesignWare Cores SDHCI eMMC driver + * + * Copyright (c) 2017, Linaro, Ltd. All rights reserved.
    + * Copyright (c) 2022, Patrick Wildt + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include + +#include +#include + +#include "DwcSdhciDxe.h" + +#define EMMC_FORCE_HIGH_SPEED FixedPcdGetBool(PcdDwcSdhciForceHighSpeed) +#define EMMC_DISABLE_HS400 FixedPcdGetBool(PcdDwcSdhciDisableHs400) + +STATIC EFI_HANDLE mSdMmcControllerHandle; + +/** + Override function for SDHCI capability bits + + @param[in] ControllerHandle The EFI_HANDLE of the controller. + @param[in] Slot The 0 based slot index. + @param[in,out] SdMmcHcSlotCapability The SDHCI capability structure. + @param[in,out] BaseClkFreq The base clock frequency value that + optionally can be updated. + + @retval EFI_SUCCESS The override function completed successfully. + @retval EFI_NOT_FOUND The specified controller or slot does not exist. + @retval EFI_INVALID_PARAMETER SdMmcHcSlotCapability is NULL + +**/ +STATIC +EFI_STATUS +EFIAPI +EmmcSdMmcCapability ( + IN EFI_HANDLE ControllerHandle, + IN UINT8 Slot, + IN OUT VOID *SdMmcHcSlotCapability, + IN OUT UINT32 *BaseClkFreq + ) +{ + SD_MMC_HC_SLOT_CAP *Capability = SdMmcHcSlotCapability; + + if (SdMmcHcSlotCapability == NULL) { + return EFI_INVALID_PARAMETER; + } + if (ControllerHandle != mSdMmcControllerHandle) { + return EFI_NOT_FOUND; + } + + // + // Disable ADMA2 to avoid data corruption. + // This controller has the limitation that a single descriptor + // cannot cross 128 MB boundaries and must be split. + // This would require a patch in SdMmcPciHcDxe, but SDMA works + // fine for the time being. + // + Capability->Adma2 = 0; + + Capability->Hs400 = !EMMC_DISABLE_HS400; + + if (EMMC_FORCE_HIGH_SPEED) { + Capability->BaseClkFreq = 52; + Capability->Sdr50 = 0; + Capability->Ddr50 = 0; + Capability->Sdr104 = 0; + Capability->Hs400 = 0; + } + + return EFI_SUCCESS; +} + +/** + + Override function for SDHCI controller operations + + @param[in] ControllerHandle The EFI_HANDLE of the controller. + @param[in] Slot The 0 based slot index. + @param[in] PhaseType The type of operation and whether the + hook is invoked right before (pre) or + right after (post) + @param[in,out] PhaseData The pointer to a phase-specific data. + + @retval EFI_SUCCESS The override function completed successfully. + @retval EFI_NOT_FOUND The specified controller or slot does not exist. + @retval EFI_INVALID_PARAMETER PhaseType is invalid + +**/ +STATIC +EFI_STATUS +EFIAPI +EmmcSdMmcNotifyPhase ( + IN EFI_HANDLE ControllerHandle, + IN UINT8 Slot, + IN EDKII_SD_MMC_PHASE_TYPE PhaseType, + IN OUT VOID *PhaseData + ) +{ + SD_MMC_BUS_MODE *Timing; + UINTN MaxClockFreq; + UINT32 Value, i; + UINT32 TxClkTapNum; + + DEBUG ((DEBUG_INFO, "%a\n", __FUNCTION__)); + + if (ControllerHandle != mSdMmcControllerHandle) { + return EFI_SUCCESS; + } + + ASSERT (Slot == 0); + + switch (PhaseType) { + case EdkiiSdMmcInitHostPost: + /* + * Just before this Notification POWER_CTRL is toggled to power off + * and on the card. On this controller implementation, toggling + * power off also removes SDCLK_ENABLE (BIT2) from from CLOCK_CTRL. + * Since the clock has already been set up prior to the power toggle, + * re-add the SDCLK_ENABLE bit to start the clock. + */ + MmioOr16((UINT32) SD_MMC_HC_CLOCK_CTRL, CLOCK_CTRL_SDCLK_ENABLE); + break; + + case EdkiiSdMmcUhsSignaling: + if (PhaseData == NULL) { + return EFI_INVALID_PARAMETER; + } + + Timing = (SD_MMC_BUS_MODE *)PhaseData; + if (*Timing == SdMmcMmcHs400) { + /* HS400 uses a non-standard setting */ + MmioOr16((UINT32) SD_MMC_HC_HOST_CTRL2, HOST_CTRL2_HS400); + } + break; + + case EdkiiSdMmcSwitchClockFreqPost: + if (PhaseData == NULL) { + return EFI_INVALID_PARAMETER; + } + + Timing = (SD_MMC_BUS_MODE *)PhaseData; + switch (*Timing) { + case SdMmcMmcHs400: + case SdMmcMmcHs200: + MaxClockFreq = 200000000UL; + break; + case SdMmcMmcHsSdr: + case SdMmcMmcHsDdr: + MaxClockFreq = 52000000UL; + break; + default: + MaxClockFreq = 26000000UL; + break; + } + + DwcSdhciSetClockRate (MaxClockFreq); + + if (MaxClockFreq <= 52000000UL) { + MmioWrite32 (EMMC_DLL_CTRL, 0); + MmioWrite32 (EMMC_DLL_RXCLK, 0); + MmioWrite32 (EMMC_DLL_TXCLK, 0); + MmioWrite32 (EMMC_DLL_CMDOUT, 0); + MmioWrite32 (EMMC_DLL_STRBIN, EMMC_DLL_DLYENA | + EMMC_DLL_STRBIN_DELAY_NUM_SEL | + EMMC_DLL_STRBIN_DELAY_NUM_DEFAULT << EMMC_DLL_STRBIN_DELAY_NUM_OFFSET); + break; + } + + /* Switch to eMMC mode */ + MmioOr32 (EMMC_EMMC_CTRL, EMMC_CTRL_CARD_IS_EMMC); + + MmioWrite32(EMMC_DLL_CTRL, EMMC_DLL_CTRL_SRST); + gBS->Stall (1); + MmioWrite32(EMMC_DLL_CTRL, 0); + + MmioWrite32(EMMC_DLL_CTRL, EMMC_DLL_CTRL_START_POINT_DEFAULT | + EMMC_DLL_CTRL_INCREMENT_DEFAULT | EMMC_DLL_CTRL_START); + + for (i = 0; i < 500; i++) { + Value = MmioRead32(EMMC_DLL_STATUS0); + if (Value & EMMC_DLL_STATUS0_DLL_LOCK && + !(Value & EMMC_DLL_STATUS0_DLL_TIMEOUT)) { + break; + } + gBS->Stall (1); + } + + TxClkTapNum = EMMC_DLL_TXCLK_TAPNUM_DEFAULT; + + if (*Timing == SdMmcMmcHs400) { + TxClkTapNum = EMMC_DLL_TXCLK_TAPNUM_90_DEGREES; + + MmioWrite32 (EMMC_DLL_CMDOUT, EMMC_DLL_CMDOUT_SRC_CLK_NEG | + EMMC_DLL_CMDOUT_EN_SRC_CLK_NEG | + EMMC_DLL_DLYENA | + EMMC_DLL_CMDOUT_TAPNUM_90_DEGREES | + EMMC_DLL_TAPNUM_FROM_SW); + } + + MmioWrite32(EMMC_DLL_RXCLK, EMMC_DLL_DLYENA); + + MmioWrite32(EMMC_DLL_TXCLK, EMMC_DLL_DLYENA | + TxClkTapNum | EMMC_DLL_TAPNUM_FROM_SW | + EMMC_DLL_NO_INVERTER); + + MmioWrite32(EMMC_DLL_STRBIN, EMMC_DLL_DLYENA | + EMMC_DLL_STRBIN_TAPNUM_DEFAULT | EMMC_DLL_TAPNUM_FROM_SW); + break; + + default: + break; + } + return EFI_SUCCESS; +} + +STATIC EDKII_SD_MMC_OVERRIDE mSdMmcOverride = { + EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION, + EmmcSdMmcCapability, + EmmcSdMmcNotifyPhase, +}; + +EFI_STATUS +EFIAPI +DwcSdhciDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + DEBUG ((DEBUG_BLKIO, "%a\n", __FUNCTION__)); + + /* Start card on 375 kHz */ + DwcSdhciSetClockRate (375000UL); + + /* Configure pins */ + DwcSdhciSetIoMux (); + + /* Disable Command Conflict Check */ + MmioWrite32 (EMMC_HOST_CTRL3, 0); + + /* Disable DLL for identification */ + MmioWrite32 (EMMC_DLL_CTRL, 0); + MmioWrite32 (EMMC_DLL_RXCLK, 0); + MmioWrite32 (EMMC_DLL_TXCLK, 0); + MmioWrite32 (EMMC_DLL_STRBIN, 0); + + Status = RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeSdhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + &mSdMmcControllerHandle, + 1, + DWC_SDHCI_BASE, 0x10000); + ASSERT_EFI_ERROR (Status); + + Handle = NULL; + Status = gBS->InstallProtocolInterface (&Handle, + &gEdkiiSdMmcOverrideProtocolGuid, + EFI_NATIVE_INTERFACE, (VOID **)&mSdMmcOverride); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.h new file mode 100644 index 0000000..b0b8b02 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.h @@ -0,0 +1,97 @@ +/** @file + * + * Synopsys DesignWare Cores SDHCI eMMC driver + * + * Copyright (c) 2022, Patrick Wildt + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __DWCSDHCIDXE_H__ +#define __DWCSDHCIDXE_H__ + +#define DWC_SDHCI_BASE PcdGet32 (PcdDwcSdhciBaseAddress) + +#define SD_MMC_HC_CLOCK_CTRL (DWC_SDHCI_BASE + 0x2C) +#define SD_MMC_HC_HOST_CTRL2 (DWC_SDHCI_BASE + 0x3E) + +// eMMC Registers +#define EMMC_HOST_CTRL3 (DWC_SDHCI_BASE + 0x508) +#define EMMC_EMMC_CTRL (DWC_SDHCI_BASE + 0x52C) +#define EMMC_DLL_CTRL (DWC_SDHCI_BASE + 0x800) +#define EMMC_DLL_RXCLK (DWC_SDHCI_BASE + 0x804) +#define EMMC_DLL_TXCLK (DWC_SDHCI_BASE + 0x808) +#define EMMC_DLL_STRBIN (DWC_SDHCI_BASE + 0x80C) +#define EMMC_DLL_CMDOUT (DWC_SDHCI_BASE + 0x810) +#define EMMC_DLL_STATUS0 (DWC_SDHCI_BASE + 0x840) +#define EMMC_DLL_STATUS1 (DWC_SDHCI_BASE + 0x844) + +#define CLOCK_CTRL_SDCLK_ENABLE BIT2 + +#define HOST_CTRL2_HS400 (BIT2 | BIT1 | BIT0) + +#define EMMC_CTRL_CARD_IS_EMMC BIT0 + +#define EMMC_DLL_CTRL_SRST BIT1 +#define EMMC_DLL_CTRL_START BIT0 +#define EMMC_DLL_CTRL_START_POINT_DEFAULT (5 << 16) +#define EMMC_DLL_CTRL_INCREMENT_DEFAULT (2 << 8) + +#define EMMC_DLL_NO_INVERTER BIT29 +#define EMMC_DLL_DLYENA BIT27 +#define EMMC_DLL_TAPNUM_FROM_SW BIT24 + +#define EMMC_DLL_TXCLK_TAPNUM_DEFAULT (0x10 << 0) +#define EMMC_DLL_TXCLK_TAPNUM_90_DEGREES 0x9 + +#define EMMC_DLL_STRBIN_TAPNUM_DEFAULT (0x3 << 0) +#define EMMC_DLL_STRBIN_DELAY_NUM_SEL BIT26 +#define EMMC_DLL_STRBIN_DELAY_NUM_OFFSET 16 +#define EMMC_DLL_STRBIN_DELAY_NUM_DEFAULT 0x10 + +#define EMMC_DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 +#define EMMC_DLL_CMDOUT_SRC_CLK_NEG BIT28 +#define EMMC_DLL_CMDOUT_EN_SRC_CLK_NEG BIT29 + +#define EMMC_DLL_STATUS0_DLL_LOCK BIT8 +#define EMMC_DLL_STATUS0_DLL_TIMEOUT BIT9 + +typedef struct { + UINT32 TimeoutFreq : 6; // bit 0:5 + UINT32 Reserved : 1; // bit 6 + UINT32 TimeoutUnit : 1; // bit 7 + UINT32 BaseClkFreq : 8; // bit 8:15 + UINT32 MaxBlkLen : 2; // bit 16:17 + UINT32 BusWidth8 : 1; // bit 18 + UINT32 Adma2 : 1; // bit 19 + UINT32 Reserved2 : 1; // bit 20 + UINT32 HighSpeed : 1; // bit 21 + UINT32 Sdma : 1; // bit 22 + UINT32 SuspRes : 1; // bit 23 + UINT32 Voltage33 : 1; // bit 24 + UINT32 Voltage30 : 1; // bit 25 + UINT32 Voltage18 : 1; // bit 26 + UINT32 SysBus64V4 : 1; // bit 27 + UINT32 SysBus64V3 : 1; // bit 28 + UINT32 AsyncInt : 1; // bit 29 + UINT32 SlotType : 2; // bit 30:31 + UINT32 Sdr50 : 1; // bit 32 + UINT32 Sdr104 : 1; // bit 33 + UINT32 Ddr50 : 1; // bit 34 + UINT32 Reserved3 : 1; // bit 35 + UINT32 DriverTypeA : 1; // bit 36 + UINT32 DriverTypeC : 1; // bit 37 + UINT32 DriverTypeD : 1; // bit 38 + UINT32 DriverType4 : 1; // bit 39 + UINT32 TimerCount : 4; // bit 40:43 + UINT32 Reserved4 : 1; // bit 44 + UINT32 TuningSDR50 : 1; // bit 45 + UINT32 RetuningMod : 2; // bit 46:47 + UINT32 ClkMultiplier : 8; // bit 48:55 + UINT32 Reserved5 : 7; // bit 56:62 + UINT32 Hs400 : 1; // bit 63 +} SD_MMC_HC_SLOT_CAP; + +#endif // __DWCSDHCIDXE_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.inf new file mode 100644 index 0000000..56c5d91 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Synopsys DesignWare Cores SDHCI eMMC driver +# +# Copyright (c) 2014-2017, Linaro Limited. All rights reserved. +# Copyright (c) 2022, Patrick Wildt +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = DwcSdhciDxe + FILE_GUID = 4cd3a91b-990e-46a6-b609-9fa5d70d1f5f + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = DwcSdhciDxeInitialize + +[Sources.common] + DwcSdhciDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + DebugLib + IoLib + NonDiscoverableDeviceRegistrationLib + UefiBootServicesTableLib + DwcSdhciPlatformLib + +[Protocols] + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gEdkiiSdMmcOverrideProtocolGuid ## PRODUCES + gEfiCpuArchProtocolGuid + gEfiDevicePathProtocolGuid + +[Pcd] + gRockchipTokenSpaceGuid.PcdDwcSdhciBaseAddress + gRockchipTokenSpaceGuid.PcdDwcSdhciForceHighSpeed + gRockchipTokenSpaceGuid.PcdDwcSdhciDisableHs400 + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.c new file mode 100644 index 0000000..6d90461 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.c @@ -0,0 +1,306 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +*******************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "I2cDemoDxe.h" + +STATIC CONST EFI_GUID I2cGuid = I2C_GUID; + +EFI_DRIVER_BINDING_PROTOCOL gDriverBindingProtocol = { + I2cDemoSupported, + I2cDemoStart, + I2cDemoStop +}; + +EFI_STATUS +EFIAPI +I2cDemoSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + EFI_I2C_IO_PROTOCOL *TmpI2cIo; + UINT8 *I2cDemoAddresses; + UINT8 *I2cDemoBuses; + UINTN i; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &TmpI2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "I2cDemoSupported Error status: %d\n", Status)); + return EFI_UNSUPPORTED; + } + + /* get I2CDEMO devices' addresses from PCD */ + I2cDemoAddresses = PcdGetPtr (PcdI2cDemoAddresses); + I2cDemoBuses = PcdGetPtr (PcdI2cDemoBuses); + if (I2cDemoAddresses == 0) { + Status = EFI_UNSUPPORTED; + DEBUG((DEBUG_INFO, "I2cDemoSupported: I2C device found, but it's not I2CDEMO\n")); + goto out; + } + + Status = EFI_UNSUPPORTED; + for (i = 0; I2cDemoAddresses[i] != '\0'; i++) { + /* I2C guid must fit and valid DeviceIndex must be provided */ + if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) && + TmpI2cIo->DeviceIndex == I2C_DEVICE_INDEX(I2cDemoBuses[i], + I2cDemoAddresses[i])) { + DEBUG ((DEBUG_INFO, "I2cDemoSupported: attached to I2CDEMO device\n")); + Status = EFI_SUCCESS; + break; + } + } + +out: + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +I2cDemoRead ( + IN CONST ROCKCHIP_I2CDEMO_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length + ) +{ + EFI_I2C_REQUEST_PACKET *RequestPacket; + UINTN RequestPacketSize; + EFI_STATUS Status = EFI_SUCCESS; + I2CDEMO_CONTEXT *I2cDemoContext = I2CDEMO_SC_FROM_I2CDEMO(This); + + ASSERT(I2cDemoContext != NULL); + ASSERT(I2cDemoContext->I2cIo != NULL); + + RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION) * 2; + RequestPacket = AllocateZeroPool (RequestPacketSize); + if (RequestPacket == NULL) + return EFI_OUT_OF_RESOURCES; + + RequestPacket->OperationCount = 2; + + RequestPacket->Operation[0].Flags = 0; + RequestPacket->Operation[0].LengthInBytes = RegAddressLength; + RequestPacket->Operation[0].Buffer = RegAddress; + + RequestPacket->Operation[1].Flags = I2C_FLAG_READ; + RequestPacket->Operation[1].LengthInBytes = Length; + RequestPacket->Operation[1].Buffer = Buffer; + + Status = I2cDemoContext->I2cIo->QueueRequest(I2cDemoContext->I2cIo, 0, NULL, RequestPacket, NULL); + if (EFI_ERROR(Status)) + DEBUG((DEBUG_INFO, "I2cDemoTransfer: error %d during transmission\n", Status)); + + FreePool(RequestPacket); + + return Status; +} + +EFI_STATUS +EFIAPI +I2cDemoWrite ( + IN CONST ROCKCHIP_I2CDEMO_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length + ) +{ + EFI_I2C_REQUEST_PACKET *RequestPacket; + UINTN RequestPacketSize; + EFI_STATUS Status = EFI_SUCCESS; + I2CDEMO_CONTEXT *I2cDemoContext = I2CDEMO_SC_FROM_I2CDEMO(This); + UINT8 *Data; + UINT16 i; + + ASSERT(I2cDemoContext != NULL); + ASSERT(I2cDemoContext->I2cIo != NULL); + + RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION); + RequestPacket = AllocateZeroPool (RequestPacketSize); + if (RequestPacket == NULL) + return EFI_OUT_OF_RESOURCES; + + Data = AllocateZeroPool ( RegAddressLength + Length ); + if (Data == NULL) + return EFI_OUT_OF_RESOURCES; + + for (i = 0; i < RegAddressLength; i++) + Data[i] = RegAddress[i] & 0xff; + + for (i = RegAddressLength; i < RegAddressLength + Length; i++) + Data[i] = Buffer[i - RegAddressLength] & 0xff; + + RequestPacket->OperationCount = 1; + + RequestPacket->Operation[0].Flags = 0; + RequestPacket->Operation[0].LengthInBytes = RegAddressLength + Length; + RequestPacket->Operation[0].Buffer = Data; + + Status = I2cDemoContext->I2cIo->QueueRequest(I2cDemoContext->I2cIo, 0, NULL, RequestPacket, NULL); + if (EFI_ERROR(Status)) + DEBUG((DEBUG_INFO, "I2cDemoTransfer: error %d during transmission\n", Status)); + + FreePool(Data); + FreePool(RequestPacket); + + return Status; +} + +EFI_STATUS +EFIAPI +I2cDemoStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + I2CDEMO_CONTEXT *I2cDemoContext; + + I2cDemoContext = AllocateZeroPool (sizeof(I2CDEMO_CONTEXT)); + if (I2cDemoContext == NULL) { + DEBUG((DEBUG_ERROR, "I2cDemo: allocation fail\n")); + return EFI_OUT_OF_RESOURCES; + } + + I2cDemoContext->ControllerHandle = ControllerHandle; + I2cDemoContext->Signature = I2CDEMO_SIGNATURE; + I2cDemoContext->I2cDemoProtocol.Read = I2cDemoRead; + I2cDemoContext->I2cDemoProtocol.Write = I2cDemoWrite; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &I2cDemoContext->I2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "I2cDemo: failed to open I2cIo\n")); + FreePool(I2cDemoContext); + return EFI_UNSUPPORTED; + } + + I2cDemoContext->I2cDemoProtocol.Identifier = I2cDemoContext->I2cIo->DeviceIndex; + Status = gBS->InstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gRockchipI2cDemoProtocolGuid, &I2cDemoContext->I2cDemoProtocol, + NULL + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "I2cDemo: failed to install I2CDEMO protocol\n")); + goto fail; + } + + return Status; + +fail: + FreePool(I2cDemoContext); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +I2cDemoStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ) +{ + ROCKCHIP_I2CDEMO_PROTOCOL *I2cDemoProtocol; + EFI_STATUS Status; + I2CDEMO_CONTEXT *I2cDemoContext; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gRockchipI2cDemoProtocolGuid, + (VOID **) &I2cDemoProtocol, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + I2cDemoContext = I2CDEMO_SC_FROM_I2CDEMO(I2cDemoProtocol); + + gBS->UninstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gRockchipI2cDemoProtocolGuid, &I2cDemoContext->I2cDemoProtocol, + &gEfiDriverBindingProtocolGuid, &gDriverBindingProtocol, + NULL + ); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + FreePool(I2cDemoContext); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +I2cDemoInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiDriverBindingProtocolGuid, &gDriverBindingProtocol, + NULL + ); + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.h new file mode 100644 index 0000000..6b7f235 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.h @@ -0,0 +1,76 @@ +/******************************************************************************** +Copyright (c) 2021, Rockchip Limited. All rights reserved. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +*******************************************************************************/ + +#ifndef __I2CDEMO_H__ +#define __I2CDEMO_H__ + +#include + +#define I2CDEMO_SIGNATURE SIGNATURE_32 ('I', '2', 'C', 'D') + +#define MAX_BUFFER_LENGTH 64 + +#define I2C_GUID \ + { \ + 0xadc1901b, 0xb83c, 0x4831, { 0x8f, 0x59, 0x70, 0x89, 0x8f, 0x26, 0x57, 0x1e } \ + } + +typedef struct { + UINT32 Signature; + EFI_HANDLE ControllerHandle; + EFI_I2C_IO_PROTOCOL *I2cIo; + ROCKCHIP_I2CDEMO_PROTOCOL I2cDemoProtocol; +} I2CDEMO_CONTEXT; + +#define I2CDEMO_SC_FROM_IO(a) CR (a, I2CDEMO_CONTEXT, I2cIo, I2CDEMO_SIGNATURE) +#define I2CDEMO_SC_FROM_I2CDEMO(a) CR (a, I2CDEMO_CONTEXT, I2cDemoProtocol, I2CDEMO_SIGNATURE) + +EFI_STATUS +EFIAPI +I2cDemoSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +I2cDemoStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +I2cDemoStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ); + +EFI_STATUS +EFIAPI +I2cDemoRead ( + IN CONST ROCKCHIP_I2CDEMO_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length + ); + +EFI_STATUS +EFIAPI +I2cDemoWrite ( + IN CONST ROCKCHIP_I2CDEMO_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length + ); +#endif // __I2CDEMO_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf new file mode 100644 index 0000000..5681a14 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf @@ -0,0 +1,43 @@ +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = I2cDemoDxe + FILE_GUID = 59fc3843-d8d4-40aa-ae07-38967138509c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = I2cDemoInitialise + +[Sources.common] + I2cDemoDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEfiDriverBindingProtocolGuid + gEfiI2cIoProtocolGuid + gRockchipI2cDemoProtocolGuid + +[Pcd] + gRockchipTokenSpaceGuid.PcdI2cDemoAddresses + gRockchipTokenSpaceGuid.PcdI2cDemoBuses + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.c new file mode 100644 index 0000000..e8dbddf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.c @@ -0,0 +1,1036 @@ +/** @file + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "I2cDxe.h" + +#define RK_I2C_DUMPREG 1 + +STATIC CONST I2C_SPEC_VALUES StandardModeSpec = { + .MinLowNs = 4700, + .MinHighNs = 4000, + .MaxRiseNs = 1000, + .MaxFallNs = 300, +}; + +STATIC CONST I2C_SPEC_VALUES FastModeSpec = { + .MinLowNs = 1300, + .MinHighNs = 600, + .MaxRiseNs = 300, + .MaxFallNs = 300, +}; + +STATIC CONST I2C_SPEC_VALUES FastModeplusSpec = { + .MinLowNs = 500, + .MinHighNs = 260, + .MaxRiseNs = 120, + .MaxFallNs = 120, +}; + +STATIC I2C_DEVICE_PATH I2cDevicePathProtocol = { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(OFFSET_OF (I2C_DEVICE_PATH, End)), + (UINT8)(OFFSET_OF (I2C_DEVICE_PATH, End) >> 8), + }, + }, + EFI_CALLER_ID_GUID + }, + 0, // Instance + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof(EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } +}; + +STATIC +CONST I2C_SPEC_VALUES * +I2cGetSpec ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINT32 Speed + ) +{ + if (Speed == 1000) + return &FastModeplusSpec; + else if (Speed == 400) + return &FastModeSpec; + else + return &StandardModeSpec; +} + +STATIC +UINT32 +I2cRead ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINTN Off + ) +{ + ASSERT (I2cMasterContext != NULL); + return MmioRead32 (I2cMasterContext->BaseAddress + Off); +} + +STATIC +EFI_STATUS +I2cWrite ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINTN Off, + IN UINT32 Value + ) +{ + ASSERT (I2cMasterContext != NULL); + return MmioWrite32 (I2cMasterContext->BaseAddress + Off, Value); +} + +STATIC +VOID +I2cShowRegs ( + IN I2C_MASTER_CONTEXT *I2cMasterContex + ) +{ +#if RK_I2C_DUMPREG + UINTN i; + + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_con: 0x%08x\n", I2cRead(I2cMasterContex, I2C_CON))); + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_clkdiv: 0x%08x\n", I2cRead(I2cMasterContex, I2C_CLKDIV))); + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_mrxaddr: 0x%08x\n", I2cRead(I2cMasterContex, I2C_MRXADDR))); + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_mrxraddR: 0x%08x\n", I2cRead(I2cMasterContex, I2C_MRXRADDR))); + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_mtxcnt: 0x%08x\n", I2cRead(I2cMasterContex, I2C_MTXCNT))); + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_mrxcnt: 0x%08x\n", I2cRead(I2cMasterContex, I2C_MRXCNT))); + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_ien: 0x%08x\n", I2cRead(I2cMasterContex, I2C_IEN))); + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_ipd: 0x%08x\n", I2cRead(I2cMasterContex, I2C_IPD))); + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_fcnt: 0x%08x\n", I2cRead(I2cMasterContex, I2C_FCNT))); + for (i = 0; i < 8; i++) + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_txdata%d: 0x%08x\n", i, I2cRead(I2cMasterContex, I2C_TXDATA_BASE + 4 * i))); + for (i = 0; i < 8; i++) + DEBUG((DEBUG_INFO | DEBUG_LOAD, "i2c_rxdata%d: 0x%08x\n", i, I2cRead(I2cMasterContex,I2C_RXDATA_BASE + 4 * i))); +#endif +} + +STATIC +I2C_VERSION +I2cGetVersion( + IN I2C_MASTER_CONTEXT *I2cMasterContext + ) +{ + I2C_VERSION Version; + + Version = I2cRead(I2cMasterContext, I2C_CON) & I2C_CON_VERSION; + return Version >>= I2C_CON_VERSION_SHIFT; +} + +STATIC +VOID +EFIAPI +I2cVirtualAddressChangeNotify ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + I2C_MASTER_CONTEXT *I2cMasterContext = Context; + + EfiConvertPointer (0x0, (VOID **) &I2cMasterContext->BaseAddress); + EfiConvertPointer (0x0, (VOID **) &I2cMasterContext->I2cMaster.SetBusFrequency); + EfiConvertPointer (0x0, (VOID **) &I2cMasterContext->I2cMaster.Reset); + EfiConvertPointer (0x0, (VOID **) &I2cMasterContext->I2cMaster.StartRequest); +} + +EFI_STATUS +EFIAPI +I2cInitialiseController ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN UINT32 BusId, + IN BOOLEAN RuntimeSupport + ) +{ + EFI_STATUS Status; + I2C_MASTER_CONTEXT *I2cMasterContext; + I2C_DEVICE_PATH *DevicePath; + EFI_EVENT VirtualAddressChangeEvent = NULL; + + DEBUG ((DEBUG_VERBOSE, "I2cInitialiseController\n")); + DevicePath = AllocateCopyPool (sizeof(I2cDevicePathProtocol), + &I2cDevicePathProtocol); + if (DevicePath == NULL) { + DEBUG((DEBUG_ERROR, "I2cDxe: I2C device path allocation failed\n")); + return EFI_OUT_OF_RESOURCES; + } + DevicePath->Instance = BusId; + + if (RuntimeSupport) { + I2cMasterContext = AllocateRuntimeZeroPool (sizeof (I2C_MASTER_CONTEXT)); + } else { + I2cMasterContext = AllocateZeroPool (sizeof (I2C_MASTER_CONTEXT)); + } + + if (I2cMasterContext == NULL) { + DEBUG((DEBUG_ERROR, "I2cDxe: I2C master context allocation failed\n")); + return EFI_OUT_OF_RESOURCES; + } + I2cMasterContext->Signature = I2C_MASTER_SIGNATURE; + I2cMasterContext->I2cMaster.SetBusFrequency = I2cSetBusFrequency; + I2cMasterContext->I2cMaster.Reset = I2cReset; + I2cMasterContext->I2cMaster.StartRequest = I2cStartRequest; + I2cMasterContext->I2cEnumerate.Enumerate = I2cEnumerate; + I2cMasterContext->I2cBusConf.EnableI2cBusConfiguration = I2cEnableConf; + I2cMasterContext->RockchipI2cMaster.Bus = BusId; + I2cMasterContext->TclkFrequency = PcdGet32 (PcdI2cClockFrequency); + I2cMasterContext->BaseAddress = BaseAddress; + I2cMasterContext->Bus = BusId; + I2cMasterContext->RuntimeSupport = RuntimeSupport; + + if (RuntimeSupport) { + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + BaseAddress, + I2C_PERIPHERAL_SIZE, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: AddMemorySpace failed. Status=%r\n", + __FUNCTION__, Status)); + goto fail; + } + + Status = gDS->SetMemorySpaceAttributes ( + BaseAddress, + I2C_PERIPHERAL_SIZE, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: SetMemorySpaceAttributes failed. Status=%r\n", + __FUNCTION__, Status)); + goto fail; + } + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + I2cVirtualAddressChangeNotify, + I2cMasterContext, + &gEfiEventVirtualAddressChangeGuid, + &VirtualAddressChangeEvent); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to register for virtual address change. Status=%r\n", + __FUNCTION__, Status)); + goto fail; + } + } + + if (I2cGetVersion(I2cMasterContext) >= RkI2cVersion1) { + I2cAdapterBaudRate(I2cMasterContext, + PcdGet32 (PcdI2cBaudRate), + I2cMasterContext->TclkFrequency + ); + } else { + I2cCalBaudRate(I2cMasterContext, + PcdGet32 (PcdI2cBaudRate), + I2cMasterContext->TclkFrequency + ); + } + + Status = gBS->InstallMultipleProtocolInterfaces( + &I2cMasterContext->Controller, + &gEfiI2cMasterProtocolGuid, + &I2cMasterContext->I2cMaster, + &gEfiI2cEnumerateProtocolGuid, + &I2cMasterContext->I2cEnumerate, + &gEfiI2cBusConfigurationManagementProtocolGuid, + &I2cMasterContext->I2cBusConf, + &gRockchipI2cMasterProtocolGuid, + &I2cMasterContext->RockchipI2cMaster, + &gEfiDevicePathProtocolGuid, + (EFI_DEVICE_PATH_PROTOCOL *) DevicePath, + NULL); + + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "I2cDxe: Installing protocol interfaces failed!\n")); + goto fail; + } + + DEBUG ((DEBUG_INFO, "Succesfully installed controller %d at 0x%llx\n", BusId, I2cMasterContext->BaseAddress)); + return EFI_SUCCESS; + +fail: + if (VirtualAddressChangeEvent && RuntimeSupport) { + gBS->CloseEvent (VirtualAddressChangeEvent); + } + + FreePool(I2cMasterContext); + return Status; +} + +STATIC +VOID +EFIAPI +OnEndOfDxe ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN HandleCount; + UINTN Index; + + gBS->CloseEvent (Event); + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiI2cMasterProtocolGuid, + NULL, + &HandleCount, + &Handles + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_WARN, "%a: Couldn't locate gEfiI2cMasterProtocolGuid. Status=%r\n", + __func__, Status)); + return; + } + + for (Index = 0; Index < HandleCount; Index++) { + Status = gBS->ConnectController (Handles[Index], NULL, NULL, TRUE); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: ConnectController () failed. Status=%r\n", + __func__, Status)); + } + } + + gBS->FreePool (Handles); +} + +EFI_STATUS +EFIAPI +I2cInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_PHYSICAL_ADDRESS BaseAddress; + EFI_EVENT EndOfDxeEvent; + UINT8 *DeviceBusPcd; + UINT32 DeviceBusCount; + UINT8 *BusRuntimeSupport; + EFI_STATUS Status; + UINTN Index; + BOOLEAN ConfiguredBuses[I2C_COUNT] = {0}; + + DeviceBusPcd = PcdGetPtr (PcdI2cSlaveBuses); + DeviceBusCount = PcdGetSize (PcdI2cSlaveBuses); + BusRuntimeSupport = PcdGetPtr (PcdI2cSlaveBusesRuntimeSupport); + + /* Initialize enabled chips */ + for (Index = 0; Index < DeviceBusCount; Index++) { + if (DeviceBusPcd[Index] > I2C_COUNT - 1) { + DEBUG ((DEBUG_WARN, "I2cInitialise: invalid bus %d for DeviceBusPcd index %d. Skipping.\n", + DeviceBusPcd[Index], Index)); + continue; + } + + // + // PcdI2cSlaveBuses is used to map devices to their corresponding bus, + // which means we will be looping over duplicate entries when there's + // more than one device on a bus. Don't reinitialize in this case. + // + if (ConfiguredBuses[DeviceBusPcd[Index]]) { + DEBUG ((DEBUG_VERBOSE, "%a: Bus %d already configured. Skipping.\n", + __FUNCTION__, DeviceBusPcd[Index])); + continue; + } + ConfiguredBuses[DeviceBusPcd[Index]] = TRUE; + + BaseAddress = I2C_BASE (DeviceBusPcd[Index]); + + I2cIomux (DeviceBusPcd[Index]); + + Status = I2cInitialiseController( + ImageHandle, + SystemTable, + BaseAddress, + DeviceBusPcd[Index], + BusRuntimeSupport[Index] + ); + + if (EFI_ERROR(Status)) + return Status; + } + + Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + OnEndOfDxe, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +STATIC +VOID +I2cCalBaudRate ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINT32 Target, + IN UINT32 ClkRate + ) +{ + int Div, Divl, Divh; + + Div = DIV_ROUND_UP(ClkRate, Target * 8) - 2; + Divh = 0; + Divl = 0; + if (Div >= 0) { + Divl = Div / 2; + if (Div % 2 == 0) + Divh = Div / 2; + else + Divh = DIV_ROUND_UP(Div, 2); + } + + I2cWrite(I2cMasterContext, I2C_CLKDIV, I2C_CLKDIV_VAL(Divl, Divh)); +} + +STATIC +EFI_STATUS +I2cAdapterBaudRate ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINT32 Target, + IN UINT32 ClkRate + ) +{ + CONST I2C_SPEC_VALUES *Spec; + UINT32 MinTotalDiv, MinLowDiv, MinHighDiv, MinHoldDiv; + UINT32 LowDiv, HighDiv, ExtraDiv, ExtraLowDiv; + UINT32 MinLowNs, MinHighNs; + UINT32 StartSetup = 0; + UINT32 Speed; + + if (Target <= 100000 && Target >= 1000) { + StartSetup = 1; + Speed = 100; + } else if (Target <= 400000 && Target >= 100000) { + Speed = 400; + } else if (Target <= 1000000 && Target > 400000) { + Speed = 1000; + } else { + DEBUG ((DEBUG_ERROR, "invalid i2c speed : %d\n", Target)); + return EFI_INVALID_PARAMETER; + } + + Spec = I2cGetSpec(I2cMasterContext, Speed); + ClkRate = DIV_ROUND_UP(ClkRate, 1000); + Speed = DIV_ROUND_UP(Target, 1000); + + MinTotalDiv = DIV_ROUND_UP(ClkRate, Speed * 8); + + MinHighNs = Spec->MaxRiseNs + Spec->MinHighNs; + MinHighDiv = DIV_ROUND_UP(ClkRate * MinHighNs, 8 * 1000000); + + MinLowNs = Spec->MaxFallNs + Spec->MinLowNs; + MinLowDiv = DIV_ROUND_UP(ClkRate * MinLowNs, 8 * 1000000); + + MinHighDiv = (MinHighDiv < 1) ? 2 : MinHighDiv; + MinLowDiv = (MinLowDiv < 1) ? 2 : MinLowDiv; + + MinHoldDiv = MinHighDiv + MinLowDiv; + + if (MinHoldDiv >= MinTotalDiv) { + HighDiv = MinHighDiv; + LowDiv = MinLowDiv; + } else { + ExtraDiv = MinTotalDiv - MinHoldDiv; + ExtraLowDiv = DIV_ROUND_UP(MinLowDiv * ExtraDiv, + MinHoldDiv); + + LowDiv = MinLowDiv + ExtraLowDiv; + HighDiv = MinHighDiv + (ExtraDiv - ExtraLowDiv); + } + + HighDiv--; + LowDiv--; + + if (HighDiv > 0xffff || LowDiv > 0xffff) + return EFI_UNSUPPORTED; + + /* 1 for data hold/setup time is enough */ + I2cMasterContext->Config = I2C_CON_SDA_CFG(1) | I2C_CON_STA_CFG(StartSetup); + I2cWrite(I2cMasterContext, I2C_CLKDIV, (HighDiv << I2C_CLK_DIV_HIGH_SHIFT) | LowDiv); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +I2cSetBusFrequency ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN OUT UINTN *BusClockHertz + ) +{ + // + // Bus frequency is already set in the entry point. + // + // Note that this function is only called by some RTC drivers, + // the I2C I/O upper layer doesn't make any use of it yet. + // + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +I2cReset ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This + ) +{ + DEBUG((DEBUG_VERBOSE, "I2cReset\n")); + return EFI_SUCCESS; +} + +STATIC +VOID +I2cDisable ( + IN I2C_MASTER_CONTEXT *I2cMasterContext + ) +{ + DEBUG ((DEBUG_VERBOSE, "I2c I2cDisable.\n")); + + I2cWrite(I2cMasterContext, I2C_IEN, 0); + I2cWrite(I2cMasterContext, I2C_IPD, I2C_IPD_ALL_CLEAN); + I2cWrite(I2cMasterContext, I2C_CON, 0); +} + +/* + * enable and start at same time, Timeout is given in us. + */ +STATIC +EFI_STATUS +I2cStartEnable ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINT32 Con, + IN UINTN Timeout + ) +{ + DEBUG ((DEBUG_VERBOSE, "I2cStartEnable\n")); + + I2cWrite(I2cMasterContext, I2C_IPD, I2C_IPD_ALL_CLEAN); + I2cWrite(I2cMasterContext, I2C_IEN, I2C_STARTIEN); + I2cWrite(I2cMasterContext, I2C_CON, I2C_CON_EN | I2C_CON_START | Con |I2cMasterContext->Config); + + while (Timeout--) { + if (I2cRead(I2cMasterContext, I2C_IPD) & I2C_STARTIPD) { + I2cWrite(I2cMasterContext, I2C_IPD, I2C_STARTIPD); + break; + } + MicroSecondDelay(1); + } + if (Timeout <= 0) { + DEBUG ((DEBUG_ERROR, "I2C Send Start Bit Timeout\n")); + I2cShowRegs(I2cMasterContext); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2cStop ( + IN I2C_MASTER_CONTEXT *I2cMasterContext + ) +{ + int TimeOut = I2C_READY_TIMEOUT; + + DEBUG ((DEBUG_VERBOSE, "I2c Send Stop bit.\n")); + + I2cWrite(I2cMasterContext, I2C_IPD, I2C_IPD_ALL_CLEAN); + I2cWrite(I2cMasterContext, I2C_CON, I2C_CON_EN | I2C_CON_STOP |I2cMasterContext->Config); + I2cWrite(I2cMasterContext, I2C_IEN, I2C_CON_STOP); + + while (TimeOut--) { + if (I2cRead(I2cMasterContext, I2C_IPD) & I2C_STOPIPD) { + I2cWrite(I2cMasterContext, I2C_IPD, I2C_STOPIPD); + break; + } + MicroSecondDelay(1); + } + + if (TimeOut <= 0) { + DEBUG ((DEBUG_ERROR, "I2C Send Stop Bit Timeout\n")); + I2cShowRegs(I2cMasterContext); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2cReadOperation ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINTN SlaveAddress, + IN OUT UINT8 *Buf, + IN UINTN Length, + IN OUT UINTN *Read, + IN UINTN Snd, + IN UINTN Timeout + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + int TimeOut = I2C_TIMEOUT_US; + UINT8 *PBuf = Buf; + UINT32 BytesRemainLen = Length; + UINT32 BytesTranferedLen = 0; + UINT32 WordsTranferedLen = 0; + UINT32 Con = 0; + UINT32 RxData; + UINT32 i, j; + UINTN SndChunk = 0; + + DEBUG ((DEBUG_VERBOSE, "I2cRead: base_addr = 0x%x buf = %p, Length = %d\n", + I2cMasterContext->BaseAddress, Buf, Length)); + + /* If the second message for TRX read, resetting internal state. */ + if (Snd) { + I2cWrite(I2cMasterContext, I2C_CON, 0); + } + + I2cWrite(I2cMasterContext, I2C_MRXADDR, I2C_MRXADDR_SET(1, SlaveAddress << 1 | 1)); + + (*Read) = 0; + while (BytesRemainLen) { + if (BytesRemainLen > RK_I2C_FIFO_SIZE) { + Con = I2C_CON_EN; + BytesTranferedLen = 32; + } else { + /* + * The hw can read up to 32 bytes at a time. If we need + * more than one chunk, send an ACK after the last byte. + */ + Con = I2C_CON_EN | I2C_CON_LASTACK; + BytesTranferedLen = BytesRemainLen; + } + WordsTranferedLen = DIV_ROUND_UP(BytesTranferedLen, 4); + + /* + * make sure we are in plain RX mode if we read a second chunk; + * and first rx read need to send start bit. + */ + if (SndChunk) { + Con |= I2C_CON_MOD(I2C_MODE_RX); + I2cWrite(I2cMasterContext, I2C_CON, Con | I2cMasterContext->Config); + } else { + Con |= I2C_CON_MOD(I2C_MODE_TRX); + Status = I2cStartEnable(I2cMasterContext, Con, I2C_TIMEOUT_US); + if (EFI_ERROR(Status)) + goto out; + } + + I2cWrite(I2cMasterContext, I2C_IEN, I2C_MBRFIEN | I2C_NAKRCVIEN); + I2cWrite(I2cMasterContext, I2C_MRXCNT, BytesTranferedLen); + + while (TimeOut--) { + if (I2cRead(I2cMasterContext, I2C_IPD) & I2C_NAKRCVIPD) { + I2cWrite(I2cMasterContext, I2C_IPD, I2C_NAKRCVIPD); + Status = EFI_NO_RESPONSE; + goto out; + } + + if (I2cRead(I2cMasterContext, I2C_IPD) & I2C_MBRFIPD) { + I2cWrite(I2cMasterContext, I2C_IPD, I2C_MBRFIPD); + break; + } + MicroSecondDelay(1); + } + + if (TimeOut <= 0) { + DEBUG ((DEBUG_ERROR, "I2C Read Data Timeout\n")); + I2cShowRegs(I2cMasterContext); + Status = EFI_TIMEOUT; + goto out; + } + + for (i = 0; i < WordsTranferedLen; i++) { + RxData = I2cRead(I2cMasterContext, I2C_RXDATA_BASE + i * 4); + DEBUG ((DEBUG_VERBOSE, "I2c Read RXDATA[%d] = 0x%x\n", i, RxData)); + for (j = 0; j < 4; j++) { + if ((i * 4 + j) == BytesTranferedLen) { + break; + } + *PBuf++ = (RxData >> (j * 8)) & 0xff; + } + } + BytesRemainLen -= BytesTranferedLen; + SndChunk = 1; + (*Read) = BytesTranferedLen; + } + + Status = EFI_SUCCESS; + (*Read) = Length; + +out: + return (Status); +} + +STATIC +EFI_STATUS +I2cWriteOperation ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINTN SlaveAddress, + IN OUT CONST UINT8 *Buf, + IN UINTN Length, + IN OUT UINTN *Sent, + IN UINTN Timeout + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + int TimeOut = I2C_TIMEOUT_US; + CONST UINT8 *PBuf = Buf; + UINT32 BytesRemainLen = Length + 1; + UINT32 BytesTranferedLen = 0; + UINT32 WordsTranferedLen = 0; + UINT32 TxData; + UINT32 i, j; + UINTN Next = 0; + + DEBUG ((DEBUG_VERBOSE, "I2cWrite: base_addr = 0x%x buf = %p, Length = %d\n", + I2cMasterContext->BaseAddress, Buf, Length)); + + (*Sent) = 0; + + while (BytesRemainLen) { + if (BytesRemainLen > RK_I2C_FIFO_SIZE) { + BytesTranferedLen = 32; + } else { + BytesTranferedLen = BytesRemainLen; + } + WordsTranferedLen = DIV_ROUND_UP(BytesTranferedLen, 4); + + for (i = 0; i < WordsTranferedLen; i++) { + TxData = 0; + for (j = 0; j < 4; j++) { + if ((i * 4 + j) == BytesTranferedLen) { + break; + } + + if (i == 0 && j == 0 && PBuf == Buf) { + TxData |= (SlaveAddress << 1); + } else { + TxData |= (*PBuf++)<<(j * 8); + } + } + I2cWrite(I2cMasterContext, I2C_TXDATA_BASE + i * 4, TxData); + DEBUG ((DEBUG_VERBOSE, "I2c Write TXDATA[%d] = 0x%x\n", i, TxData)); + } + + /* If the write is the first, need to send start bit */ + if (!Next) { + Status = I2cStartEnable(I2cMasterContext, I2C_CON_EN | + I2C_CON_MOD(I2C_MODE_TX), I2C_TIMEOUT_US); + if (EFI_ERROR(Status)) { + goto out; + } + Next = 1; + } else { + I2cWrite(I2cMasterContext, I2C_CON, I2C_CON_EN | + I2C_CON_MOD(I2C_MODE_TX) | I2cMasterContext->Config); + } + + I2cWrite(I2cMasterContext, I2C_IEN, I2C_MBTFIEN | I2C_NAKRCVIEN); + I2cWrite(I2cMasterContext, I2C_MTXCNT, BytesTranferedLen); + + while (TimeOut--) { + if (I2cRead(I2cMasterContext, I2C_IPD) & I2C_NAKRCVIPD) { + I2cWrite(I2cMasterContext, I2C_IPD, I2C_NAKRCVIPD); + Status = EFI_NO_RESPONSE; + goto out; + } + if (I2cRead(I2cMasterContext, I2C_IPD) & I2C_MBTFIPD) { + I2cWrite(I2cMasterContext, I2C_IPD, I2C_MBTFIPD); + break; + } + MicroSecondDelay(1); + } + + if (TimeOut <= 0) { + DEBUG ((DEBUG_ERROR, "I2C Write Data Timeout\n")); + I2cShowRegs(I2cMasterContext); + Status = EFI_TIMEOUT; + goto out; + } + + BytesRemainLen -= BytesTranferedLen; + (*Sent) = BytesTranferedLen; + } + + (*Sent) = Length; + Status = EFI_SUCCESS; +out: + return (Status); +} + + +/* + * I2cStartRequest should be called only by I2cHost. + * I2C device drivers ought to use EFI_I2C_IO_PROTOCOL instead. + */ +STATIC +EFI_STATUS +I2cStartRequest ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN UINTN SlaveAddress, + IN EFI_I2C_REQUEST_PACKET *RequestPacket, + IN EFI_EVENT Event OPTIONAL, + OUT EFI_STATUS *I2cStatus OPTIONAL + ) +{ + UINTN Count = RequestPacket->OperationCount; + UINTN ReadMode; + UINTN Transmitted; + I2C_MASTER_CONTEXT *I2cMasterContext = I2C_SC_FROM_MASTER(This); + EFI_I2C_OPERATION *Operation; + EFI_STATUS Status = EFI_SUCCESS; + UINTN i; + BOOLEAN AtRuntime; + EFI_TPL Tpl; + + ASSERT (RequestPacket != NULL); + ASSERT (I2cMasterContext != NULL); + + AtRuntime = EfiAtRuntime (); + + // Events do not fire at runtime, so we can't support asynchronous requests. + if (AtRuntime && Event != NULL) { + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_VERBOSE, "I2cStartRequest.\n")); + + if (!AtRuntime) { + // Disable (timer) interrupts. + Tpl = gBS->RaiseTPL (TPL_HIGH_LEVEL); + } else if (I2cMasterContext->RuntimeSupport) { + // + // TO-DO: + // Implement some synchronization mechanism between this code path + // and the HLOS I2C driver, to prevent a race condition. + // + // See: https://github.com/edk2-porting/edk2-rk3588/issues/70 + // + } + + if (Count > 2 || ((Count == 2) && (RequestPacket->Operation->Flags & I2C_FLAG_READ))) { + DEBUG ((DEBUG_VERBOSE, "Not support more messages now, split them\n")); + return EFI_INVALID_PARAMETER; + } + + for (i = 0; i < Count; i++) { + Operation = &RequestPacket->Operation[i]; + ReadMode = Operation->Flags & I2C_FLAG_READ; + + if (Operation->Flags & I2C_FLAG_READ) { + /* If snd is true, it is TRX mode. */ + Status = I2cReadOperation ( I2cMasterContext, + SlaveAddress, + Operation->Buffer, + Operation->LengthInBytes, + &Transmitted, + i == 1, + I2C_TRANSFER_TIMEOUT); + Operation->LengthInBytes = Transmitted; + } else { + Status = I2cWriteOperation ( I2cMasterContext, + SlaveAddress, + Operation->Buffer, + Operation->LengthInBytes, + &Transmitted, + I2C_TRANSFER_TIMEOUT); + Operation->LengthInBytes = Transmitted; + } + + /* I2C transaction was aborted, so stop further transactions */ + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_VERBOSE, "I2cStartRequest: Failed at Count = %d\n", Count)); + break; + } + } + + I2cStop (I2cMasterContext); + I2cDisable (I2cMasterContext); + + if (!AtRuntime) { + gBS->RestoreTPL (Tpl); + } else if (I2cMasterContext->RuntimeSupport) { + // TO-DO: See above. + } + + if (I2cStatus != NULL) + *I2cStatus = EFI_SUCCESS; + if (Event != NULL) + gBS->SignalEvent(Event); + return EFI_SUCCESS; +} + +STATIC CONST EFI_GUID DevGuid = I2C_GUID; + +STATIC +EFI_STATUS +I2cAllocDevice ( + IN UINT8 SlaveAddress, + IN UINT8 Bus, + IN OUT CONST EFI_I2C_DEVICE **Device + ) +{ + EFI_STATUS Status; + EFI_I2C_DEVICE *Dev; + UINT32 *TmpSlaveArray; + EFI_GUID *TmpGuidP; + + Status = gBS->AllocatePool ( EfiBootServicesData, + sizeof(EFI_I2C_DEVICE), + (VOID **) &Dev ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "I2cDxe: I2C device memory allocation failed\n")); + return Status; + } + *Device = Dev; + Dev->DeviceIndex = SlaveAddress; + Dev->DeviceIndex = I2C_DEVICE_INDEX(Bus, SlaveAddress); + Dev->SlaveAddressCount = 1; + Dev->I2cBusConfiguration = 0; + Status = gBS->AllocatePool ( EfiBootServicesData, + sizeof(UINT32), + (VOID **) &TmpSlaveArray); + if (EFI_ERROR(Status)) { + goto fail1; + } + TmpSlaveArray[0] = SlaveAddress; + Dev->SlaveAddressArray = TmpSlaveArray; + + Status = gBS->AllocatePool ( EfiBootServicesData, + sizeof(EFI_GUID), + (VOID **) &TmpGuidP); + if (EFI_ERROR(Status)) { + goto fail2; + } + *TmpGuidP = DevGuid; + Dev->DeviceGuid = TmpGuidP; + + return EFI_SUCCESS; + +fail2: + FreePool(TmpSlaveArray); +fail1: + FreePool(Dev); + + return Status; +} + +/* + * It is called by I2cBus to enumerate devices on I2C bus. In this case, + * enumeration is based on PCD configuration - all Slave addresses specified + * in PCD get their corresponding EFI_I2C_DEVICE structures here. + * + * After enumeration succeeds, Supported() function of drivers that installed + * DriverBinding protocol is called. + */ +STATIC +EFI_STATUS +EFIAPI +I2cEnumerate ( + IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This, + IN OUT CONST EFI_I2C_DEVICE **Device + ) +{ + UINT8 *DevicesPcd; + UINT8 *DeviceBusPcd; + UINTN Index, NextIndex, DevCount; + UINT8 NextDeviceAddress; + I2C_MASTER_CONTEXT *I2cMasterContext = I2C_SC_FROM_ENUMERATE(This); + + DevCount = PcdGetSize (PcdI2cSlaveAddresses); + DevicesPcd = PcdGetPtr (PcdI2cSlaveAddresses); + DeviceBusPcd = PcdGetPtr (PcdI2cSlaveBuses); + if (*Device == NULL) { + for (Index = 0; Index < DevCount ; Index++) { + if (DeviceBusPcd[Index] != I2cMasterContext->Bus) + continue; + if (Index < DevCount) + I2cAllocDevice (DevicesPcd[Index], I2cMasterContext->Bus, Device); + + return EFI_SUCCESS; + } + } else { + /* Device is not NULL, so something was already allocated */ + for (Index = 0; Index < DevCount; Index++) { + if (DeviceBusPcd[Index] != I2cMasterContext->Bus) + continue; + if (DevicesPcd[Index] == I2C_DEVICE_ADDRESS((*Device)->DeviceIndex)) { + for (NextIndex = Index + 1; NextIndex < DevCount; NextIndex++) { + if (DeviceBusPcd[NextIndex] != I2cMasterContext->Bus) + continue; + NextDeviceAddress = DevicesPcd[NextIndex]; + if (NextIndex < DevCount) + I2cAllocDevice(NextDeviceAddress, I2cMasterContext->Bus, Device); + + return EFI_SUCCESS; + } + } + } + *Device = NULL; + return EFI_SUCCESS; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +I2cEnableConf ( + IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, + IN UINTN I2cBusConfiguration, + IN EFI_EVENT Event OPTIONAL, + IN EFI_STATUS *I2cStatus OPTIONAL + ) +{ + /* do nothing */ + if (I2cStatus != NULL) + I2cStatus = EFI_SUCCESS; + if (Event != NULL) + gBS->SignalEvent(Event); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.h new file mode 100644 index 0000000..c0f7f12 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.h @@ -0,0 +1,327 @@ +/** @file + * + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK_I2C_DXE_H__ +#define __RK_I2C_DXE_H__ + +#include + +#define I2C_PERIPHERAL_SIZE 0x1000 + +#define I2C_SLAVE_ADDR 0x00 +#define I2C_EXT_SLAVE_ADDR 0x10 +#define I2C_DATA 0x04 + +#define I2C_CONTROL 0x08 +#define I2C_CONTROL_ACK (1 << 2) +#define I2C_CONTROL_IFLG (1 << 3) +#define I2C_CONTROL_STOP (1 << 4) +#define I2C_CONTROL_START (1 << 5) +#define I2C_CONTROL_I2CEN (1 << 6) +#define I2C_CONTROL_INTEN (1 << 7) + +#define I2C_STATUS 0x0c +#define I2C_STATUS_START 0x08 +#define I2C_STATUS_RPTD_START 0x10 +#define I2C_STATUS_ADDR_W_ACK 0x18 +#define I2C_STATUS_DATA_WR_ACK 0x28 +#define I2C_STATUS_ADDR_R_ACK 0x40 +#define I2C_STATUS_DATA_RD_ACK 0x50 +#define I2C_STATUS_DATA_RD_NOACK 0x58 + +#define I2C_BAUD_RATE_REG 0x0c +#define I2C_BAUD_RATE_PARAM(M,N) ((((M) << 3) | ((N) & 0x7)) & 0x7f) +#define I2C_BAUD_RATE_RAW(C,M,N) ((C)/((10*(M+1))<<(N+1))) +#define I2C_M_FROM_BAUD(baud) (((baud) >> 3) & 0xf) +#define I2C_N_FROM_BAUD(baud) ((baud) & 0x7) + +#define I2C_SOFT_RESET 0x1c +#define I2C_TRANSFER_TIMEOUT 10000 +#define I2C_READY_TIMEOUT 100 + +#define I2C_UNKNOWN 0x0 +#define I2C_SLOW 0x1 +#define I2C_FAST 0x2 +#define I2C_FASTEST 0x3 + +/* rk i2c fifo max transfer bytes */ +#define RK_I2C_FIFO_SIZE 32 + +/* rk i2c device register size */ +#define RK_I2C_REGISTER_SIZE 3 + +/* i2c timerout */ +#define I2C_TIMEOUT_US 100000 // 100000us = 100ms +#define I2C_RETRY_COUNT 3 + +#define I2C_ADAP_SEL_BIT(nr) ((nr) + 11) +#define I2C_ADAP_SEL_MASK(nr) ((nr) + 27) + +#define RK_CEIL(x, y) \ + ({ unsigned long __x = (x), __y = (y); (__x + __y - 1) / __y; }) + +/* Control register */ +#define I2C_CON 0x000 +#define I2C_CON_EN (1 << 0) +#define I2C_CON_MOD(mod) ((mod) << 1) +#define I2C_MODE_TX 0x00 +#define I2C_MODE_TRX 0x01 +#define I2C_MODE_RX 0x02 +#define I2C_MODE_RRX 0x03 +#define I2C_CON_MASK (3 << 1) + +#define I2C_CON_START (1 << 3) +#define I2C_CON_STOP (1 << 4) +#define I2C_CON_LASTACK (1 << 5) +#define I2C_CON_ACTACK (1 << 6) + +#define I2C_CON_SDA_CFG(cfg) ((cfg) << 8) +#define I2C_CON_STA_CFG(cfg) ((cfg) << 12) +#define I2C_CON_STO_CFG(cfg) ((cfg) << 14 + +#define I2C_CON_VERSION (0xff << 16) +#define I2C_CON_VERSION_SHIFT 16 + +/* Clock dividor register */ +#define I2C_CLKDIV 0x004 +#define I2C_CLK_DIV_HIGH_SHIFT 16 +#define I2C_CLKDIV_VAL(divl, divh) (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) + +/* the slave address accessed for master rx mode */ +#define I2C_MRXADDR 0x008 +#define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) + +/* the slave register address accessed for master rx mode */ +#define I2C_MRXRADDR 0x00c +#define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) + +/* master tx count */ +#define I2C_MTXCNT 0x010 + +/* master rx count */ +#define I2C_MRXCNT 0x014 + +/* interrupt enable register */ +#define I2C_IEN 0x018 +#define I2C_BTFIEN (1 << 0) +#define I2C_BRFIEN (1 << 1) +#define I2C_MBTFIEN (1 << 2) +#define I2C_MBRFIEN (1 << 3) +#define I2C_STARTIEN (1 << 4) +#define I2C_STOPIEN (1 << 5) +#define I2C_NAKRCVIEN (1 << 6) + +/* interrupt pending register */ +#define I2C_IPD 0x01c +#define I2C_BTFIPD (1 << 0) +#define I2C_BRFIPD (1 << 1) +#define I2C_MBTFIPD (1 << 2) +#define I2C_MBRFIPD (1 << 3) +#define I2C_STARTIPD (1 << 4) +#define I2C_STOPIPD (1 << 5) +#define I2C_NAKRCVIPD (1 << 6) +#define I2C_IPD_ALL_CLEAN 0x7f + +/* finished count */ +#define I2C_FCNT 0x020 + +/* I2C tx data register */ +#define I2C_TXDATA_BASE 0X100 + +/* I2C rx data register */ +#define I2C_RXDATA_BASE 0x200 + + +#define I2C_GUID \ + { \ + 0xadc1901b, 0xb83c, 0x4831, { 0x8f, 0x59, 0x70, 0x89, 0x8f, 0x26, 0x57, 0x1e } \ + } + +#define I2C_MASTER_SIGNATURE SIGNATURE_32 ('I', '2', 'C', 'M') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Controller; + UINTN TclkFrequency; + UINTN BaseAddress; + INTN Bus; + UINTN Config; + BOOLEAN RuntimeSupport; + EFI_I2C_MASTER_PROTOCOL I2cMaster; + EFI_I2C_ENUMERATE_PROTOCOL I2cEnumerate; + EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL I2cBusConf; + ROCKCHIP_I2C_MASTER_PROTOCOL RockchipI2cMaster; +} I2C_MASTER_CONTEXT; + +#define I2C_SC_FROM_MASTER(a) CR (a, I2C_MASTER_CONTEXT, I2cMaster, I2C_MASTER_SIGNATURE) +#define I2C_SC_FROM_ENUMERATE(a) CR (a, I2C_MASTER_CONTEXT, I2cEnumerate, I2C_MASTER_SIGNATURE) +#define I2C_SC_FROM_BUSCONF(a) CR (a, I2C_MASTER_CONTEXT, I2cBusConf, I2C_MASTER_SIGNATURE) + +typedef struct { + VENDOR_DEVICE_PATH Guid; + UINTN Instance; + EFI_DEVICE_PATH_PROTOCOL End; +} I2C_DEVICE_PATH; + +typedef struct { + UINT32 MinLowNs; + UINT32 MinHighNs; + UINT32 MaxRiseNs; + UINT32 MaxFallNs; +} I2C_SPEC_VALUES; + +typedef enum { + RkI2cVersion0 = 0, + RkI2cVersion1, + RkI2cVersion5 = 5, +} I2C_VERSION; + +STATIC +UINT32 +I2cRead( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINTN Off + ); + +STATIC +EFI_STATUS +I2cWrite ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINTN Off, + IN UINT32 Val + ); + +STATIC +CONST I2C_SPEC_VALUES * +I2cGetSpec ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINT32 Speed); + +EFI_STATUS +EFIAPI +I2cInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +STATIC +VOID +I2cCalBaudRate ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINT32 Target, + IN UINT32 ClkRate + ); + +STATIC +EFI_STATUS +I2cAdapterBaudRate ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN CONST UINT32 Target, + IN CONST UINT32 ClkRate + ); + +STATIC +EFI_STATUS +EFIAPI +I2cSetBusFrequency ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN OUT UINTN *BusClockHertz + ); + +EFI_STATUS +EFIAPI +I2cReset ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This + ); + +STATIC +VOID +I2cDisable ( + IN I2C_MASTER_CONTEXT *I2cMasterContext + ); + +STATIC +EFI_STATUS +I2cStartEnable ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINT32 Con, + IN UINTN Timeout + ); + +STATIC +EFI_STATUS +I2cStop ( + IN I2C_MASTER_CONTEXT *I2cMasterContext + ); + +STATIC +EFI_STATUS +I2cReadOperation ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINTN SlaveAddress, + IN OUT UINT8 *buf, + IN UINTN len, + IN OUT UINTN *read, + IN UINTN last, + IN UINTN delay + ); + +STATIC +EFI_STATUS +I2cWriteOperation ( + IN I2C_MASTER_CONTEXT *I2cMasterContext, + IN UINTN SlaveAddress, + IN OUT CONST UINT8 *buf, + IN UINTN len, + IN OUT UINTN *sent, + IN UINTN timeout + ); + +STATIC +EFI_STATUS +EFIAPI +I2cStartRequest ( + IN CONST EFI_I2C_MASTER_PROTOCOL *This, + IN UINTN SlaveAddress, + IN EFI_I2C_REQUEST_PACKET *RequestPacket, + IN EFI_EVENT Event OPTIONAL, + OUT EFI_STATUS *I2cStatus OPTIONAL + ); + +STATIC +EFI_STATUS +EFIAPI +I2cEnumerate ( + IN CONST EFI_I2C_ENUMERATE_PROTOCOL *This, + IN OUT CONST EFI_I2C_DEVICE **Device + ); + +STATIC +EFI_STATUS +EFIAPI +I2cEnableConf ( + IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, + IN UINTN I2cBusConfiguration, + IN EFI_EVENT Event OPTIONAL, + IN EFI_STATUS *I2cStatus OPTIONAL + ); + +STATIC +I2C_VERSION +I2cGetVersion( + IN I2C_MASTER_CONTEXT *I2cMasterContext + ); + +STATIC +VOID +I2cShowRegs ( + IN I2C_MASTER_CONTEXT *I2cMasterContex + ); + +#endif // __RK_I2C_DXE_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf new file mode 100644 index 0000000..1630ee9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf @@ -0,0 +1,61 @@ +#/** @file +# +# Copyright (c) 2021 Rockchip Electronics Co., Ltd. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = I2cDxe + FILE_GUID = 9335a854-4b88-11ec-a8ee-f42a7dcb925d + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = I2cInitialise + +[Sources.common] + I2cDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + IoLib + PcdLib + BaseLib + DebugLib + DxeServicesTableLib + UefiLib + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeLib + RockchipPlatformLib + TimerLib + +[Protocols] + gEfiI2cMasterProtocolGuid + gEfiDevicePathProtocolGuid + gEfiI2cEnumerateProtocolGuid + gEfiI2cBusConfigurationManagementProtocolGuid + gRockchipI2cMasterProtocolGuid + +[Pcd] + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport + gRockchipTokenSpaceGuid.PcdI2cClockFrequency + gRockchipTokenSpaceGuid.PcdI2cBaudRate + +[Guids] + gEfiEndOfDxeEventGroupGuid + gEfiEventVirtualAddressChangeGuid + +[Depex] + gEfiCpuArchProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.c new file mode 100644 index 0000000..025cf6b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.c @@ -0,0 +1,546 @@ +/** @file +* +* Copyright (C) 2016 Marvell International Ltd. +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "Rk860xRegulatorDxe.h" + +STATIC CONST EFI_GUID I2cGuid = I2C_GUID; + +EFI_DRIVER_BINDING_PROTOCOL gDriverBindingProtocol = { + Rk860xRegulatorSupported, + Rk860xRegulatorStart, + Rk860xRegulatorStop +}; + +EFI_STATUS +EFIAPI +Rk860xRegulatorSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + EFI_I2C_IO_PROTOCOL *TmpI2cIo; + UINT8 *Rk860xRegulatorAddresses; + UINT8 *Rk860xRegulatorBuses; + UINTN i; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &TmpI2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + + /* get RK860X_REGULATOR devices' addresses from PCD */ + Rk860xRegulatorAddresses = PcdGetPtr (PcdRk860xRegulatorAddresses); + Rk860xRegulatorBuses = PcdGetPtr (PcdRk860xRegulatorBuses); + if (Rk860xRegulatorAddresses == 0) { + Status = EFI_UNSUPPORTED; + DEBUG((DEBUG_INFO, "Rk860xRegulatorSupported: I2C device found, but it's not RK860X_REGULATOR\n")); + goto out; + } + + Status = EFI_UNSUPPORTED; + for (i = 0; Rk860xRegulatorAddresses[i] != '\0'; i++) { + /* I2C guid must fit and valid DeviceIndex must be provided */ + if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) && + TmpI2cIo->DeviceIndex == I2C_DEVICE_INDEX(Rk860xRegulatorBuses[i], + Rk860xRegulatorAddresses[i])) { + DEBUG ((DEBUG_INFO, "Rk860xRegulatorSupported: attached to RK860X_REGULATOR device\n")); + Status = EFI_SUCCESS; + break; + } + } + +out: + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +STATIC +EFI_STATUS +EFIAPI +Rk860xRegulatorRead ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length + ) +{ + EFI_I2C_REQUEST_PACKET *RequestPacket; + UINTN RequestPacketSize; + EFI_STATUS Status = EFI_SUCCESS; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext = RK860X_REGULATOR_SC_FROM_PROTOCOL(This); + + ASSERT(Rk860xRegulatorContext != NULL); + ASSERT(Rk860xRegulatorContext->I2cIo != NULL); + + RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION) * 2; + RequestPacket = AllocateZeroPool (RequestPacketSize); + if (RequestPacket == NULL) + return EFI_OUT_OF_RESOURCES; + + RequestPacket->OperationCount = 2; + + RequestPacket->Operation[0].Flags = 0; + RequestPacket->Operation[0].LengthInBytes = RegAddressLength; + RequestPacket->Operation[0].Buffer = RegAddress; + + RequestPacket->Operation[1].Flags = I2C_FLAG_READ; + RequestPacket->Operation[1].LengthInBytes = Length; + RequestPacket->Operation[1].Buffer = Buffer; + + Status = Rk860xRegulatorContext->I2cIo->QueueRequest(Rk860xRegulatorContext->I2cIo, 0, NULL, RequestPacket, NULL); + if (EFI_ERROR(Status)) + DEBUG((DEBUG_INFO, "Rk860xRegulatorRead: error %d during transmission\n", Status)); + + FreePool(RequestPacket); + + return Status; +} + +STATIC +EFI_STATUS +EFIAPI +Rk860xRegulatorWrite ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length + ) +{ + EFI_I2C_REQUEST_PACKET *RequestPacket; + UINTN RequestPacketSize; + EFI_STATUS Status = EFI_SUCCESS; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext = RK860X_REGULATOR_SC_FROM_PROTOCOL(This); + UINT8 *Data; + UINT16 i; + + ASSERT(Rk860xRegulatorContext != NULL); + ASSERT(Rk860xRegulatorContext->I2cIo != NULL); + + RequestPacketSize = sizeof(UINTN) + sizeof (EFI_I2C_OPERATION); + RequestPacket = AllocateZeroPool (RequestPacketSize); + if (RequestPacket == NULL) + return EFI_OUT_OF_RESOURCES; + + Data = AllocateZeroPool ( RegAddressLength + Length ); + if (Data == NULL) + return EFI_OUT_OF_RESOURCES; + + for (i = 0; i < RegAddressLength; i++) + Data[i] = RegAddress[i] & 0xff; + + for (i = RegAddressLength; i < RegAddressLength + Length; i++) + Data[i] = Buffer[i - RegAddressLength] & 0xff; + + RequestPacket->OperationCount = 1; + + RequestPacket->Operation[0].Flags = 0; + RequestPacket->Operation[0].LengthInBytes = RegAddressLength + Length; + RequestPacket->Operation[0].Buffer = Data; + + Status = Rk860xRegulatorContext->I2cIo->QueueRequest(Rk860xRegulatorContext->I2cIo, 0, NULL, RequestPacket, NULL); + if (EFI_ERROR(Status)) + DEBUG((DEBUG_INFO, "Rk860xRegulatorWrite: error %d during transmission\n", Status)); + + FreePool(Data); + FreePool(RequestPacket); + + return Status; +} + +STATIC +EFI_STATUS +EFIAPI +Rk860xRegulatorReadRegister ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN UINT8 Address, + OUT UINT8 *Value + ) +{ + return Rk860xRegulatorRead(This, &Address, sizeof(UINT8), + Value, sizeof(UINT8)); +} + +STATIC +EFI_STATUS +EFIAPI +Rk860xRegulatorWriteRegister ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN UINT8 Address, + IN UINT8 Value + ) +{ + return Rk860xRegulatorWrite(This, &Address, sizeof(UINT8), + &Value, sizeof(UINT8)); +} + +STATIC +EFI_STATUS +EFIAPI +Rk860xRegulatorClearAndSetRegister ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN UINT8 Address, + IN UINT8 Clear, + IN UINT8 Set + ) +{ + UINT8 Value; + EFI_STATUS Status = EFI_SUCCESS; + + Status = Rk860xRegulatorReadRegister(This, Address, &Value); + if (EFI_ERROR(Status)) { + return Status; + } + + Value = (Value & ~Clear) | Set; + + return Rk860xRegulatorWriteRegister(This, Address, Value); +} + +EFI_STATUS +EFIAPI +Rk860xRegulatorGetVoltage ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + OUT UINT32 *Voltage, + IN BOOLEAN Suspend + ) +{ + UINT8 Value; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext = RK860X_REGULATOR_SC_FROM_PROTOCOL (This); + EFI_STATUS Status = EFI_SUCCESS; + + Status = Rk860xRegulatorReadRegister (This, + Suspend ? Rk860xRegulatorContext->Config.SleepReg : Rk860xRegulatorContext->Config.VolReg, + &Value); + if (EFI_ERROR(Status)) { + return Status; + } + + Value &= Rk860xRegulatorContext->Config.VolMask; + *Voltage = (Value * Rk860xRegulatorContext->Config.VselStep) + Rk860xRegulatorContext->Config.VselMin; + + return Status; +} + +EFI_STATUS +EFIAPI +Rk860xRegulatorSetVoltage ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN UINT32 Voltage, + IN BOOLEAN Suspend + ) +{ + UINT8 Value; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext = RK860X_REGULATOR_SC_FROM_PROTOCOL (This); + + Value = (Voltage - Rk860xRegulatorContext->Config.VselMin) / Rk860xRegulatorContext->Config.VselStep; + + return Rk860xRegulatorClearAndSetRegister (This, + Suspend ? Rk860xRegulatorContext->Config.SleepReg : Rk860xRegulatorContext->Config.VolReg, + Rk860xRegulatorContext->Config.VolMask, Value); +} + +EFI_STATUS +EFIAPI +Rk860xRegulatorGetEnable ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + OUT BOOLEAN *Enable, + IN BOOLEAN Suspend + ) +{ + UINT8 Value; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext = RK860X_REGULATOR_SC_FROM_PROTOCOL (This); + EFI_STATUS Status = EFI_SUCCESS; + + Status = Rk860xRegulatorReadRegister (This, + Suspend ? Rk860xRegulatorContext->Config.SleepEnReg : Rk860xRegulatorContext->Config.EnReg, + &Value); + if (EFI_ERROR(Status)) { + return Status; + } + + *Enable = Value & RK860X_VSEL_BUCK_EN; + + return Status; +} + +EFI_STATUS +EFIAPI +Rk860xRegulatorSetEnable ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN BOOLEAN Enable, + IN BOOLEAN Suspend + ) +{ + UINT8 Value; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext = RK860X_REGULATOR_SC_FROM_PROTOCOL (This); + + Value = Enable ? RK860X_VSEL_BUCK_EN : 0; + + return Rk860xRegulatorClearAndSetRegister (This, + Suspend ? Rk860xRegulatorContext->Config.SleepEnReg : Rk860xRegulatorContext->Config.EnReg, + RK860X_VSEL_BUCK_EN, Value); +} + +STATIC +EFI_STATUS +EFIAPI +Rk860xRegulatorInitConfig ( + IN CONST RK860X_REGULATOR_PROTOCOL *This + ) +{ + UINT8 ChipId; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext = RK860X_REGULATOR_SC_FROM_PROTOCOL (This); + EFI_STATUS Status = EFI_SUCCESS; + + Status = Rk860xRegulatorReadRegister (This, RK860X_ID1, &ChipId); + if (EFI_ERROR(Status)) { + return Status; + } + ChipId &= RK860X_DIE_ID_MASK; + + switch (ChipId) { + case RK860X_CHIP_ID_00_01: + Rk860xRegulatorContext->Config.VselMin = 712500; + Rk860xRegulatorContext->Config.VselStep = 12500; + Rk860xRegulatorContext->Config.NumVoltages = RK860X_NVOLTAGES_64; + Rk860xRegulatorContext->Config.VolMask = RK860X_VSEL_A_NSEL_MASK; + Rk860xRegulatorContext->Config.SleepReg = RK860X_VSEL1_A; + Rk860xRegulatorContext->Config.VolReg = RK860X_VSEL0_A; + Rk860xRegulatorContext->Config.EnReg = RK860X_VSEL0_A; + Rk860xRegulatorContext->Config.SleepEnReg = RK860X_VSEL1_A; + break; + case RK860X_CHIP_ID_02_03: + Rk860xRegulatorContext->Config.VselMin = 500000; + Rk860xRegulatorContext->Config.VselStep = 6250; + Rk860xRegulatorContext->Config.NumVoltages = RK860X_NVOLTAGES_160; + Rk860xRegulatorContext->Config.VolMask = RK860X_VSEL_B_NSEL_MASK; + Rk860xRegulatorContext->Config.SleepReg = RK860X_VSEL1_B; + Rk860xRegulatorContext->Config.VolReg = RK860X_VSEL0_B; + Rk860xRegulatorContext->Config.EnReg = RK860X_VSEL0_A; + Rk860xRegulatorContext->Config.SleepEnReg = RK860X_VSEL1_A; + break; + default: + DEBUG((DEBUG_ERROR, "Rk860xRegulatorInitConfig: unsupported chip id %u\n", ChipId)); + return EFI_UNSUPPORTED; + } + + return Status; +} + +EFI_STATUS +EFIAPI +Rk860xRegulatorStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext; + RK860X_REGULATOR_PROTOCOL *Rk860xRegulatorProtocol; + UINT8 *Rk860xRegulatorAddresses; + UINTN Rk860xRegulatorAddressesSize; + UINT8 *Rk860xRegulatorBuses; + UINT8 *Rk860xRegulatorTags; + UINT8 *Rk860xRegulatorMinVoltagesPtr; + UINTN Rk860xRegulatorMinVoltagesSize; + UINT8 *Rk860xRegulatorMaxVoltagesPtr; + UINTN Rk860xRegulatorMaxVoltagesSize; + UINT32 Index; + + Rk860xRegulatorContext = AllocateZeroPool (sizeof(RK860X_REGULATOR_CONTEXT)); + if (Rk860xRegulatorContext == NULL) { + DEBUG((DEBUG_ERROR, "Rk860xRegulator: allocation fail\n")); + return EFI_OUT_OF_RESOURCES; + } + + Rk860xRegulatorProtocol = &Rk860xRegulatorContext->Rk860xRegulatorProtocol; + + Rk860xRegulatorContext->ControllerHandle = ControllerHandle; + Rk860xRegulatorContext->Signature = RK860X_REGULATOR_SIGNATURE; + + Rk860xRegulatorProtocol->GetVoltage = Rk860xRegulatorGetVoltage; + Rk860xRegulatorProtocol->SetVoltage = Rk860xRegulatorSetVoltage; + Rk860xRegulatorProtocol->GetEnable = Rk860xRegulatorGetEnable; + Rk860xRegulatorProtocol->SetEnable = Rk860xRegulatorSetEnable; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &Rk860xRegulatorContext->I2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Rk860xRegulator: failed to open I2cIo\n")); + FreePool(Rk860xRegulatorContext); + return EFI_UNSUPPORTED; + } + + Rk860xRegulatorProtocol->Identifier = Rk860xRegulatorContext->I2cIo->DeviceIndex; + Status = gBS->InstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gRk860xRegulatorProtocolGuid, Rk860xRegulatorProtocol, + NULL + ); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Rk860xRegulator: failed to install RK860X_REGULATOR_PROTOCOL\n")); + goto fail; + } + + Status = Rk860xRegulatorInitConfig (Rk860xRegulatorProtocol); + if (EFI_ERROR(Status)) { + goto fail; + } + + Rk860xRegulatorProtocol->SupportedVoltageRange.Min = Rk860xRegulatorContext->Config.VselMin; + Rk860xRegulatorProtocol->SupportedVoltageRange.Max = RK860X_MAX_VOLTAGE; + + Rk860xRegulatorProtocol->PreferredVoltageRange = Rk860xRegulatorProtocol->SupportedVoltageRange; + + Rk860xRegulatorAddresses = PcdGetPtr (PcdRk860xRegulatorAddresses); + Rk860xRegulatorAddressesSize = PcdGetSize (PcdRk860xRegulatorAddresses); + Rk860xRegulatorBuses = PcdGetPtr (PcdRk860xRegulatorBuses); + Rk860xRegulatorTags = PcdGetPtr (PcdRk860xRegulatorTags); + Rk860xRegulatorMinVoltagesPtr = PcdGetPtr (PcdRk860xRegulatorMinVoltages); + Rk860xRegulatorMinVoltagesSize = PcdGetSize (PcdRk860xRegulatorMinVoltages); + Rk860xRegulatorMaxVoltagesPtr = PcdGetPtr (PcdRk860xRegulatorMaxVoltages); + Rk860xRegulatorMaxVoltagesSize = PcdGetSize (PcdRk860xRegulatorMaxVoltages); + + for (Index = 0; Rk860xRegulatorAddresses[Index] != '\0'; Index++) { + if (Rk860xRegulatorContext->I2cIo->DeviceIndex == I2C_DEVICE_INDEX(Rk860xRegulatorBuses[Index], + Rk860xRegulatorAddresses[Index])) { + + Rk860xRegulatorProtocol->Tag = Rk860xRegulatorTags[Index]; + + Index *= sizeof(UINT32); + + if (Rk860xRegulatorMinVoltagesSize / sizeof(UINT32) == Rk860xRegulatorAddressesSize) { + Rk860xRegulatorProtocol->PreferredVoltageRange.Min = Rk860xRegulatorMinVoltagesPtr[Index] | + Rk860xRegulatorMinVoltagesPtr[Index + 1] << 8 | + Rk860xRegulatorMinVoltagesPtr[Index + 2] << 16 | + Rk860xRegulatorMinVoltagesPtr[Index + 3] << 24; + } + if (Rk860xRegulatorMaxVoltagesSize / sizeof(UINT32) == Rk860xRegulatorAddressesSize) { + Rk860xRegulatorProtocol->PreferredVoltageRange.Max = Rk860xRegulatorMaxVoltagesPtr[Index] | + Rk860xRegulatorMaxVoltagesPtr[Index + 1] << 8 | + Rk860xRegulatorMaxVoltagesPtr[Index + 2] << 16 | + Rk860xRegulatorMaxVoltagesPtr[Index + 3] << 24; + } + break; + } + } + return Status; + +fail: + FreePool(Rk860xRegulatorContext); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +Rk860xRegulatorStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ) +{ + RK860X_REGULATOR_PROTOCOL *Rk860xRegulatorProtocol; + EFI_STATUS Status; + RK860X_REGULATOR_CONTEXT *Rk860xRegulatorContext; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gRk860xRegulatorProtocolGuid, + (VOID **) &Rk860xRegulatorProtocol, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + Rk860xRegulatorContext = RK860X_REGULATOR_SC_FROM_PROTOCOL(Rk860xRegulatorProtocol); + + gBS->UninstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gRk860xRegulatorProtocolGuid, &Rk860xRegulatorContext->Rk860xRegulatorProtocol, + &gEfiDriverBindingProtocolGuid, &gDriverBindingProtocol, + NULL + ); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + FreePool(Rk860xRegulatorContext); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +Rk860xRegulatorInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiDriverBindingProtocolGuid, &gDriverBindingProtocol, + NULL + ); + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.h new file mode 100644 index 0000000..f4b610c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.h @@ -0,0 +1,120 @@ +/** @file +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __RK860X_REGULATOR_DXE_H__ +#define __RK860X_REGULATOR_DXE_H__ + +#include + +#define RK860X_REGULATOR_SIGNATURE SIGNATURE_32 ('R', 'K', '8', '6') + +#define I2C_GUID \ + { \ + 0xadc1901b, 0xb83c, 0x4831, { 0x8f, 0x59, 0x70, 0x89, 0x8f, 0x26, 0x57, 0x1e } \ + } + +typedef struct { + UINT8 VolReg; + UINT8 SleepReg; + UINT8 EnReg; + UINT8 SleepEnReg; + UINT8 VolMask; + UINT16 NumVoltages; + UINT32 VselMin; + UINT32 VselStep; +} RK860X_REGULATOR_CONFIG; + +typedef struct { + UINT32 Signature; + EFI_HANDLE ControllerHandle; + EFI_I2C_IO_PROTOCOL *I2cIo; + RK860X_REGULATOR_PROTOCOL Rk860xRegulatorProtocol; + RK860X_REGULATOR_CONFIG Config; +} RK860X_REGULATOR_CONTEXT; + +#define RK860X_REGULATOR_SC_FROM_IO(a) CR (a, RK860X_REGULATOR_CONTEXT, I2cIo, RK860X_REGULATOR_SIGNATURE) +#define RK860X_REGULATOR_SC_FROM_PROTOCOL(a) CR (a, RK860X_REGULATOR_CONTEXT, Rk860xRegulatorProtocol, RK860X_REGULATOR_SIGNATURE) + +/* Registers & fields */ +#define RK860X_VSEL0_A 0x00 +#define RK860X_VSEL1_A 0x01 +#define RK860X_VSEL0_B 0x06 +#define RK860X_VSEL1_B 0x07 + +#define RK860X_VSEL_BUCK_EN BIT7 +#define RK860X_VSEL_A_NSEL_MASK 0x3F +#define RK860X_VSEL_B_NSEL_MASK 0xff + +#define RK860X_ID1 0x03 +#define RK860X_DIE_ID_MASK 0x0F +#define RK860X_CHIP_ID_00_01 8 +#define RK860X_CHIP_ID_02_03 10 + +#define RK860X_NVOLTAGES_64 64 +#define RK860X_NVOLTAGES_160 160 + +#define RK860X_MAX_VOLTAGE 1500000 + +EFI_STATUS +EFIAPI +Rk860xRegulatorSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +Rk860xRegulatorStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +Rk860xRegulatorStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ); + +EFI_STATUS +EFIAPI +Rk860xRegulatorGetVoltage ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + OUT UINT32 *Voltage, + IN BOOLEAN Suspend + ); + +EFI_STATUS +EFIAPI +Rk860xRegulatorSetVoltage ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN UINT32 Voltage, + IN BOOLEAN Suspend + ); + +EFI_STATUS +EFIAPI +Rk860xRegulatorGetEnable ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + OUT BOOLEAN *Enable, + IN BOOLEAN Suspend + ); + +EFI_STATUS +EFIAPI +Rk860xRegulatorSetEnable ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN BOOLEAN Enable, + IN BOOLEAN Suspend + ); + +#endif // __RK860X_REGULATOR_DXE_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf new file mode 100644 index 0000000..b1a9492 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf @@ -0,0 +1,52 @@ +#/** @file +# +# RK860X voltage regulator driver +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Rk860xRegulatorDxe + FILE_GUID = cd5a650e-20e1-47b4-b33a-5e77bf9be42a + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = Rk860xRegulatorInitialise + +[Sources.common] + Rk860xRegulatorDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEfiI2cIoProtocolGuid ## CONSUMES + gEfiDriverBindingProtocolGuid ## PRODUCES + gRk860xRegulatorProtocolGuid ## PRODUCES + +[Pcd] + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags + gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages + gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c new file mode 100644 index 0000000..a92f5f8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c @@ -0,0 +1,938 @@ +/** @file + + Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + **/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "LcdGraphicsOutputDxe.h" + +extern BOOLEAN mDisplayInitialized; + +// +// Function Definitions +// + +STATIC +EFI_STATUS +VideoCopyNoHorizontalOverlap ( + IN UINTN BitsPerPixel, + IN volatile VOID *FrameBufferBase, + IN UINT32 HorizontalResolution, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height +) +{ + EFI_STATUS Status; + UINTN SourceLine; + UINTN DestinationLine; + UINTN WidthInBytes; + UINTN LineCount; + INTN Step; + VOID *SourceAddr; + VOID *DestinationAddr; + + Status = EFI_SUCCESS; + + if( DestinationY <= SourceY ) { + // scrolling up (or horizontally but without overlap) + SourceLine = SourceY; + DestinationLine = DestinationY; + Step = 1; + } else { + // scrolling down + SourceLine = SourceY + Height; + DestinationLine = DestinationY + Height; + Step = -1; + } + + switch (BitsPerPixel) { + + case LcdBitsPerPixel_24: + + WidthInBytes = Width * 4; + + for( LineCount = 0; LineCount < Height; LineCount++ ) { + // Update the start addresses of source & destination using 32bit pointer arithmetic + SourceAddr = (VOID *)((UINT32 *)FrameBufferBase + SourceLine * HorizontalResolution + SourceX ); + DestinationAddr = (VOID *)((UINT32 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationX); + + // Copy the entire line Y from video ram to the temp buffer + CopyMem( DestinationAddr, SourceAddr, WidthInBytes); + + // Update the line numbers + SourceLine += Step; + DestinationLine += Step; + } + break; + + case LcdBitsPerPixel_16_555: + case LcdBitsPerPixel_16_565: + case LcdBitsPerPixel_12_444: + + WidthInBytes = Width * 2; + + for( LineCount = 0; LineCount < Height; LineCount++ ) { + // Update the start addresses of source & destination using 16bit pointer arithmetic + SourceAddr = (VOID *)((UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourceX ); + DestinationAddr = (VOID *)((UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationX); + + // Copy the entire line Y from video ram to the temp buffer + CopyMem( DestinationAddr, SourceAddr, WidthInBytes); + + // Update the line numbers + SourceLine += Step; + DestinationLine += Step; + } + break; + + case LcdBitsPerPixel_8: + case LcdBitsPerPixel_4: + case LcdBitsPerPixel_2: + case LcdBitsPerPixel_1: + default: + // Can't handle this case + DEBUG((DEBUG_ERROR, "ArmVeGraphics_Blt: EfiBltVideoToVideo: INVALID Number of Bits Per Pixel: %d\n", BitsPerPixel)); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + // break; + + } + + EXIT: + return Status; +} + +STATIC +EFI_STATUS +VideoCopyHorizontalOverlap ( + IN UINTN BitsPerPixel, + IN volatile VOID *FrameBufferBase, + UINT32 HorizontalResolution, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height +) +{ + EFI_STATUS Status; + + UINT32 *PixelBuffer32bit; + UINT32 *SourcePixel32bit; + UINT32 *DestinationPixel32bit; + + UINT16 *PixelBuffer16bit; + UINT16 *SourcePixel16bit; + UINT16 *DestinationPixel16bit; + + UINT32 SourcePixelY; + UINT32 DestinationPixelY; + UINTN SizeIn32Bits; + UINTN SizeIn16Bits; + + Status = EFI_SUCCESS; + + switch (BitsPerPixel) { + + case LcdBitsPerPixel_24: + // Allocate a temporary buffer + + PixelBuffer32bit = (UINT32 *) AllocatePool((Height * Width) * sizeof(UINT32)); + + if (PixelBuffer32bit == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto EXIT; + } + + SizeIn32Bits = Width * 4; + + // Copy from the video ram (source region) to a temp buffer + for (SourcePixelY = SourceY, DestinationPixel32bit = PixelBuffer32bit; + SourcePixelY < SourceY + Height; + SourcePixelY++, DestinationPixel32bit += Width) + { + // Update the start address of line Y (source) + SourcePixel32bit = (UINT32 *)FrameBufferBase + SourcePixelY * HorizontalResolution + SourceX; + + // Copy the entire line Y from video ram to the temp buffer + CopyMem( (VOID *)DestinationPixel32bit, (CONST VOID *)SourcePixel32bit, SizeIn32Bits); + } + + // Copy from the temp buffer to the video ram (destination region) + for (DestinationPixelY = DestinationY, SourcePixel32bit = PixelBuffer32bit; + DestinationPixelY < DestinationY + Height; + DestinationPixelY++, SourcePixel32bit += Width) + { + // Update the start address of line Y (target) + DestinationPixel32bit = (UINT32 *)FrameBufferBase + DestinationPixelY * HorizontalResolution + DestinationX; + + // Copy the entire line Y from the temp buffer to video ram + CopyMem( (VOID *)DestinationPixel32bit, (CONST VOID *)SourcePixel32bit, SizeIn32Bits); + } + + // Free up the allocated memory + FreePool((VOID *) PixelBuffer32bit); + + break; + + + case LcdBitsPerPixel_16_555: + case LcdBitsPerPixel_16_565: + case LcdBitsPerPixel_12_444: + // Allocate a temporary buffer + PixelBuffer16bit = (UINT16 *) AllocatePool((Height * Width) * sizeof(UINT16)); + + if (PixelBuffer16bit == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto EXIT; + } + + // Access each pixel inside the source area of the Video Memory and copy it to the temp buffer + + SizeIn16Bits = Width * 2; + + for (SourcePixelY = SourceY, DestinationPixel16bit = PixelBuffer16bit; + SourcePixelY < SourceY + Height; + SourcePixelY++, DestinationPixel16bit += Width) + { + // Calculate the source address: + SourcePixel16bit = (UINT16 *)FrameBufferBase + SourcePixelY * HorizontalResolution + SourceX; + + // Copy the entire line Y from Video to the temp buffer + CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits); + } + + // Copy from the temp buffer into the destination area of the Video Memory + + for (DestinationPixelY = DestinationY, SourcePixel16bit = PixelBuffer16bit; + DestinationPixelY < DestinationY + Height; + DestinationPixelY++, SourcePixel16bit += Width) + { + // Calculate the target address: + DestinationPixel16bit = (UINT16 *)FrameBufferBase + (DestinationPixelY * HorizontalResolution + DestinationX); + + // Copy the entire line Y from the temp buffer to Video + CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits); + } + + // Free the allocated memory + FreePool((VOID *) PixelBuffer16bit); + + break; + + + case LcdBitsPerPixel_8: + case LcdBitsPerPixel_4: + case LcdBitsPerPixel_2: + case LcdBitsPerPixel_1: + default: + // Can't handle this case + DEBUG((DEBUG_ERROR, "ArmVeGraphics_Blt: EfiBltVideoToVideo: INVALID Number of Bits Per Pixel: %d\n", BitsPerPixel)); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + // break; + + } + +EXIT: + return Status; +} + +STATIC +EFI_STATUS +BltVideoFill ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_PIXEL_BITMASK* PixelInformation; + EFI_STATUS Status; + UINT32 HorizontalResolution; + LCD_BPP BitsPerPixel; + VOID *FrameBufferBase; + VOID *DestinationAddr; + UINT16 *DestinationPixel16bit; + UINT16 Pixel16bit; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + UINTN WidthInBytes; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + HorizontalResolution = This->Mode->Info->HorizontalResolution; + + LcdGraphicsGetBpp (This->Mode->Mode, &BitsPerPixel); + + switch (BitsPerPixel) { + case LcdBitsPerPixel_24: + WidthInBytes = Width * 4; + + // Copy the SourcePixel into every pixel inside the target rectangle + for (DestinationLine = DestinationY; + DestinationLine < DestinationY + Height; + DestinationLine++) + { + // Calculate the target address using 32bit pointer arithmetic: + DestinationAddr = (VOID *)((UINT32 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationX); + + // Fill the entire line + SetMem32 (DestinationAddr, WidthInBytes, *((UINT32 *)EfiSourcePixel)); + } + break; + + case LcdBitsPerPixel_16_555: + // Convert the EFI pixel at the start of the BltBuffer(0,0) into a video display pixel + Pixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 7) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green << 2) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask ) +// | ( 0 & PixelInformation->ReservedMask ) + ); + + // Copy the SourcePixel into every pixel inside the target rectangle + for (DestinationLine = DestinationY; + DestinationLine < DestinationY + Height; + DestinationLine++) + { + for (DestinationPixelX = DestinationX; + DestinationPixelX < DestinationX + Width; + DestinationPixelX++) + { + // Calculate the target address: + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + *DestinationPixel16bit = Pixel16bit; + } + } + break; + + case LcdBitsPerPixel_16_565: + // Convert the EFI pixel at the start of the BltBuffer(0,0) into a video display pixel + Pixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 8) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green << 3) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask ) + ); + + // Copy the SourcePixel into every pixel inside the target rectangle + for (DestinationLine = DestinationY; + DestinationLine < DestinationY + Height; + DestinationLine++) + { + for (DestinationPixelX = DestinationX; + DestinationPixelX < DestinationX + Width; + DestinationPixelX++) + { + // Calculate the target address: + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + *DestinationPixel16bit = Pixel16bit; + } + } + break; + + case LcdBitsPerPixel_12_444: + // Convert the EFI pixel at the start of the BltBuffer(0,0) into a video display pixel + Pixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red >> 4) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green ) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue << 4) & PixelInformation->BlueMask ) + ); + + // Copy the SourcePixel into every pixel inside the target rectangle + for (DestinationLine = DestinationY; + DestinationLine < DestinationY + Height; + DestinationLine++) + { + for (DestinationPixelX = DestinationX; + DestinationPixelX < DestinationX + Width; + DestinationPixelX++) + { + // Calculate the target address: + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + *DestinationPixel16bit = Pixel16bit; + } + } + break; + + case LcdBitsPerPixel_8: + case LcdBitsPerPixel_4: + case LcdBitsPerPixel_2: + case LcdBitsPerPixel_1: + default: + // Can't handle this case + DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: EfiBltVideoFill: INVALID Number of Bits Per Pixel: %d\n", BitsPerPixel)); + Status = EFI_INVALID_PARAMETER; + break; + } + + return Status; +} + +STATIC +EFI_STATUS +BltVideoToBltBuffer ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + LCD_BPP BitsPerPixel; + EFI_PIXEL_BITMASK *PixelInformation; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiDestinationPixel; + VOID *FrameBufferBase; + VOID *SourceAddr; + VOID *DestinationAddr; + UINT16 *SourcePixel16bit; + UINT16 Pixel16bit; + UINT32 SourcePixelX; + UINT32 SourceLine; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + UINT32 BltBufferHorizontalResolution; + UINTN WidthInBytes; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) { + // Delta is not zero and it is different from the width. + // Divide it by the size of a pixel to find out the buffer's horizontal resolution. + BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL)); + } else { + BltBufferHorizontalResolution = Width; + } + + LcdGraphicsGetBpp (This->Mode->Mode, &BitsPerPixel); + + switch (BitsPerPixel) { + case LcdBitsPerPixel_24: + WidthInBytes = Width * 4; + + // Access each line inside the Video Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) + { + // Calculate the source and target addresses using 32bit pointer arithmetic: + SourceAddr = (VOID *)((UINT32 *)FrameBufferBase + SourceLine * HorizontalResolution + SourceX ); + DestinationAddr = (VOID *)((UINT32 *)BltBuffer + DestinationLine * BltBufferHorizontalResolution + DestinationX); + + // Copy the entire line + CopyMem( DestinationAddr, SourceAddr, WidthInBytes); + } + break; + + case LcdBitsPerPixel_16_555: + // Access each pixel inside the Video Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) + { + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + SourcePixel16bit = (UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourcePixelX; + EfiDestinationPixel = BltBuffer + DestinationLine * BltBufferHorizontalResolution + DestinationPixelX; + + // Snapshot the pixel from the video buffer once, to speed up the operation. + // If we were dereferencing the pointer, as it is volatile, we would perform 3 memory read operations. + Pixel16bit = *SourcePixel16bit; + + // Copy the pixel into the new target + EfiDestinationPixel->Red = (UINT8) ( (Pixel16bit & PixelInformation->RedMask ) >> 7 ); + EfiDestinationPixel->Green = (UINT8) ( (Pixel16bit & PixelInformation->GreenMask ) >> 2); + EfiDestinationPixel->Blue = (UINT8) ( (Pixel16bit & PixelInformation->BlueMask ) << 3 ); + // EfiDestinationPixel->Reserved = (UINT8) 0; + } + } + break; + + case LcdBitsPerPixel_16_565: + // Access each pixel inside the Video Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) + { + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + SourcePixel16bit = (UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourcePixelX; + EfiDestinationPixel = BltBuffer + DestinationLine * BltBufferHorizontalResolution + DestinationPixelX; + + // Snapshot the pixel from the video buffer once, to speed up the operation. + // If we were dereferencing the pointer, as it is volatile, we would perform 3 memory read operations. + Pixel16bit = *SourcePixel16bit; + + // Copy the pixel into the new target + // There is no info for the Reserved byte, so we set it to zero + EfiDestinationPixel->Red = (UINT8) ( (Pixel16bit & PixelInformation->RedMask ) >> 8 ); + EfiDestinationPixel->Green = (UINT8) ( (Pixel16bit & PixelInformation->GreenMask ) >> 3); + EfiDestinationPixel->Blue = (UINT8) ( (Pixel16bit & PixelInformation->BlueMask ) << 3 ); + // EfiDestinationPixel->Reserved = (UINT8) 0; + } + } + break; + + case LcdBitsPerPixel_12_444: + // Access each pixel inside the Video Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) + { + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + SourcePixel16bit = (UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourcePixelX; + EfiDestinationPixel = BltBuffer + DestinationLine * BltBufferHorizontalResolution + DestinationPixelX; + + // Snapshot the pixel from the video buffer once, to speed up the operation. + // If we were dereferencing the pointer, as it is volatile, we would perform 3 memory read operations. + Pixel16bit = *SourcePixel16bit; + + // Copy the pixel into the new target + EfiDestinationPixel->Red = (UINT8) ( (Pixel16bit & PixelInformation->RedMask ) >> 4 ); + EfiDestinationPixel->Green = (UINT8) ( (Pixel16bit & PixelInformation->GreenMask ) ); + EfiDestinationPixel->Blue = (UINT8) ( (Pixel16bit & PixelInformation->BlueMask ) << 4 ); + // EfiDestinationPixel->Reserved = (UINT8) 0; + } + } + break; + + case LcdBitsPerPixel_8: + case LcdBitsPerPixel_4: + case LcdBitsPerPixel_2: + case LcdBitsPerPixel_1: + default: + // Can't handle this case + DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: EfiBltVideoToBltBuffer: INVALID Number of Bits Per Pixel: %d\n", BitsPerPixel)); + Status = EFI_INVALID_PARAMETER; + break; + } + return Status; +} + +#if 0 +STATIC +VOID +DebugBitmap ( + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BitMapIn +) +{ + UINT32 Index = 0; + + for (Index = 0; Index < 0x3000; Index++) { + DEBUG ((DEBUG_WARN, "{%02x,%02x,%02x,%02x} ", (*(BitMapIn + Index)).Red, (*(BitMapIn + Index)).Green, (*(BitMapIn + Index)).Blue, (*(BitMapIn + Index)).Reserved)); + } +} + +STATIC +VOID +DebugMemory ( + UINT32 Reg +) +{ + UINT32 i; + + for (i = 0; i < 0x2000; i += 4) { + if (i % 0x20 == 0) { + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "%x:", Reg + i)); + } + DEBUG ((DEBUG_WARN, " %08x", MmioRead32(Reg + i))); + } +} +#endif + +STATIC +EFI_STATUS +BltBufferToVideo ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + LCD_BPP BitsPerPixel; + EFI_PIXEL_BITMASK *PixelInformation; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel; + VOID *FrameBufferBase; + VOID *SourceAddr; + VOID *DestinationAddr; + UINT16 *DestinationPixel16bit; + UINT32 SourcePixelX; + UINT32 SourceLine; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + UINT32 BltBufferHorizontalResolution; + UINTN WidthInBytes; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) { + // Delta is not zero and it is different from the width. + // Divide it by the size of a pixel to find out the buffer's horizontal resolution. + BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL)); + } else { + BltBufferHorizontalResolution = Width; + } + + LcdGraphicsGetBpp (This->Mode->Mode, &BitsPerPixel); + + switch (BitsPerPixel) { + case LcdBitsPerPixel_24: + WidthInBytes = Width * 4; + +#if 1 + // Access each pixel inside the BltBuffer Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) + { + // Calculate the source and target addresses using 32bit pointer arithmetic: + SourceAddr = (VOID *)((UINT32 *)BltBuffer + SourceLine * BltBufferHorizontalResolution + SourceX ); + DestinationAddr = (VOID *)((UINT32 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationX); + + // Copy the entire row Y + CopyMem( DestinationAddr, SourceAddr, WidthInBytes); + } +#endif +#if 0 + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) { + + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + EfiSourcePixel = BltBuffer + SourceLine * BltBufferHorizontalResolution + SourcePixelX; + DestinationPixel32bit = (UINT32 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + //DEBUG ((DEBUG_WARN, "(0x%08x) ", DestinationPixel32bit)); + // Copy the pixel into the new target + // Only the most significant bits will be copied across: + // To convert from 8 bits to 5 bits per pixel we throw away the 3 least significant bits + *DestinationPixel32bit = (UINT32) ( + ( (EfiSourcePixel->Red << 16)) + | ( (EfiSourcePixel->Green << 8)) + | ( (EfiSourcePixel->Blue << 0)) + | ( (EfiSourcePixel->Reserved << 24)) + ); + } + } +#endif + break; + + case LcdBitsPerPixel_16_555: + // Access each pixel inside the BltBuffer Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) { + + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + EfiSourcePixel = BltBuffer + SourceLine * BltBufferHorizontalResolution + SourcePixelX; + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + // Only the most significant bits will be copied across: + // To convert from 8 bits to 5 bits per pixel we throw away the 3 least significant bits + *DestinationPixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 7) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green << 2) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask ) + // | ( 0 & PixelInformation->ReservedMask ) + ); + } + } + break; + + case LcdBitsPerPixel_16_565: + // Access each pixel inside the BltBuffer Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) { + + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + EfiSourcePixel = BltBuffer + SourceLine * BltBufferHorizontalResolution + SourcePixelX; + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + // Only the most significant bits will be copied across: + // To convert from 8 bits to 5 or 6 bits per pixel we throw away the 3 or 2 least significant bits + // There is no room for the Reserved byte so we ignore that completely + *DestinationPixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 8) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green << 3) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask ) + ); + } + } + break; + + case LcdBitsPerPixel_12_444: + // Access each pixel inside the BltBuffer Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) { + + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + EfiSourcePixel = BltBuffer + SourceLine * BltBufferHorizontalResolution + SourcePixelX; + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + // Only the most significant bits will be copied across: + // To convert from 8 bits to 5 bits per pixel we throw away the 3 least significant bits + *DestinationPixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 4) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green ) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 4) & PixelInformation->BlueMask ) + // | ( 0 & PixelInformation->ReservedMask ) + ); + } + } + break; + + case LcdBitsPerPixel_8: + case LcdBitsPerPixel_4: + case LcdBitsPerPixel_2: + case LcdBitsPerPixel_1: + default: + // Can't handle this case + DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: EfiBltBufferToVideo: INVALID Number of Bits Per Pixel: %d\n", BitsPerPixel)); + Status = EFI_INVALID_PARAMETER; + break; + } + return Status; +} + +STATIC +EFI_STATUS +BltVideoToVideo ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + LCD_BPP BitsPerPixel; + VOID *FrameBufferBase; + + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + // + // BltVideo to BltVideo: + // + // Source is the Video Memory, + // Destination is the Video Memory + + LcdGraphicsGetBpp (This->Mode->Mode, &BitsPerPixel); + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + // The UEFI spec currently states: + // "There is no limitation on the overlapping of the source and destination rectangles" + // Therefore, we must be careful to avoid overwriting the source data + if( SourceY == DestinationY ) { + // Copying within the same height, e.g. horizontal shift + if( SourceX == DestinationX ) { + // Nothing to do + Status = EFI_SUCCESS; + } else if( ((SourceX>DestinationX)?(SourceX - DestinationX):(DestinationX - SourceX)) < Width ) { + // There is overlap + Status = VideoCopyHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } else { + // No overlap + Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } + } else { + // Copying from different heights + Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } + + return Status; +} + +/*************************************** + * GraphicsOutput Protocol function, mapping to + * EFI_GRAPHICS_OUTPUT_PROTOCOL.Blt + * + * PRESUMES: 1 pixel = 4 bytes (32bits) + * ***************************************/ +EFI_STATUS +EFIAPI +LcdGraphicsBlt ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + UINT32 VerticalResolution; + LCD_INSTANCE* Instance; + + Instance = LCD_INSTANCE_FROM_GOP_THIS(This); + + HorizontalResolution = This->Mode->Info->HorizontalResolution; + VerticalResolution = This->Mode->Info->VerticalResolution; + + DEBUG((DEBUG_VERBOSE, "[BLT]LcdGraphicsBlt (BltOperation:%d,DestX:%d,DestY:%d,Width:%d,Height:%d) res(%d,%d)\n", + BltOperation,DestinationX,DestinationY,Width,Height,HorizontalResolution,VerticalResolution)); + + // Check we have reasonable parameters + if (Width == 0 || Height == 0) { + DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: ERROR - Invalid dimension: Zero size area.\n" )); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + } + + if ((BltOperation == EfiBltVideoFill) || (BltOperation == EfiBltBufferToVideo) || (BltOperation == EfiBltVideoToBltBuffer)) { + ASSERT( BltBuffer != NULL); + } + + /*if ((DestinationX >= HorizontalResolution) || (DestinationY >= VerticalResolution)) { + DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: ERROR - Invalid destination.\n" )); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + }*/ + + // If we are reading data out of the video buffer, check that the source area is within the display limits + if ((BltOperation == EfiBltVideoToBltBuffer) || (BltOperation == EfiBltVideoToVideo)) { + if ((SourceY + Height > VerticalResolution) || (SourceX + Width > HorizontalResolution)) { + DEBUG((DEBUG_INFO, "LcdGraphicsBlt: ERROR - Invalid source resolution.\n" )); + DEBUG((DEBUG_INFO, " - SourceY=%d + Height=%d > VerticalResolution=%d.\n", SourceY, Height, VerticalResolution )); + DEBUG((DEBUG_INFO, " - SourceX=%d + Width=%d > HorizontalResolution=%d.\n", SourceX, Width, HorizontalResolution )); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + } + } + + // If we are writing data into the video buffer, that the destination area is within the display limits + if ((BltOperation == EfiBltVideoFill) || (BltOperation == EfiBltBufferToVideo) || (BltOperation == EfiBltVideoToVideo)) { + if ((DestinationY + Height > VerticalResolution) || (DestinationX + Width > HorizontalResolution)) { + DEBUG((DEBUG_INFO, "LcdGraphicsBlt: ERROR - Invalid destination resolution.\n" )); + DEBUG((DEBUG_INFO, " - DestinationY=%d + Height=%d > VerticalResolution=%d.\n", DestinationY, Height, VerticalResolution )); + DEBUG((DEBUG_INFO, " - DestinationX=%d + Width=%d > HorizontalResolution=%d.\n", DestinationX, Width, HorizontalResolution )); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + } + } + + // + // Perform the Block Transfer Operation + // + + switch (BltOperation) { + case EfiBltVideoFill: + Status = BltVideoFill (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltVideoToBltBuffer: + Status = BltVideoToBltBuffer (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltBufferToVideo: + Status = BltBufferToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltVideoToVideo: + Status = BltVideoToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiGraphicsOutputBltOperationMax: + default: + DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: Invalid Operation\n")); + Status = EFI_INVALID_PARAMETER; + break; + } + + WriteBackDataCacheRange ((void*)(Instance->Mode.FrameBufferBase), Instance->Mode.FrameBufferSize); + +EXIT: + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c new file mode 100644 index 0000000..8882240 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -0,0 +1,738 @@ +/** @file + This file implements the Graphics Output protocol for Arm platforms + + Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + Copyright (c) 2023, Mario Bălănică + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "LcdGraphicsOutputDxe.h" + + +// +// Global variables +// +STATIC LIST_ENTRY mDisplayStateList; + +//STATIC DISPLAY_PROTOCOL mDisplayProtocol; + +STATIC EFI_CPU_ARCH_PROTOCOL *mCpu; + +typedef enum { + ROCKCHIP_VOP2_CLUSTER0 = 0, + ROCKCHIP_VOP2_CLUSTER1, + ROCKCHIP_VOP2_ESMART0, + ROCKCHIP_VOP2_ESMART1, + ROCKCHIP_VOP2_SMART0, + ROCKCHIP_VOP2_SMART1, + ROCKCHIP_VOP2_CLUSTER2, + ROCKCHIP_VOP2_CLUSTER3, + ROCKCHIP_VOP2_ESMART2, + ROCKCHIP_VOP2_ESMART3, + ROCKCHIP_VOP2_LAYER_MAX, +} VOP2_LAYER_PHY_ID; + +STATIC OVER_SCAN mDefaultOverScanParas = { + .LeftMargin = 100, + .RightMargin = 100, + .TopMargin = 100, + .BottomMargin = 100 +}; + +STATIC DISPLAY_MODE mDisplayModes[] = { + { + 2, + 148500000, + {1920, 32, 200, 48}, + {1080, 5, 37, 3}, + 0, + 0, + 0, + 0, + 1 + }, +}; + +STATIC CONST UINT32 mMaxMode = ARRAY_SIZE (mDisplayModes); + +LCD_INSTANCE mLcdTemplate = { + LCD_INSTANCE_SIGNATURE, + NULL, // Handle + { // ModeInfo + 0, // Version + 0, // HorizontalResolution + 0, // VerticalResolution + PixelBltOnly, // PixelFormat + { 0 }, // PixelInformation + 0, // PixelsPerScanLine + }, + { + 0, // MaxMode; + 0, // Mode; + NULL, // Info; + 0, // SizeOfInfo; + 0, // FrameBufferBase; + 0 // FrameBufferSize; + }, + { // Gop + LcdGraphicsQueryMode, // QueryMode + LcdGraphicsSetMode, // SetMode + LcdGraphicsBlt, // Blt + NULL // *Mode + }, + { // DevicePath + { + { + HARDWARE_DEVICE_PATH, HW_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + }, + }, + // Hardware Device Path for Lcd + EFI_CALLER_ID_GUID // Use the driver's GUID + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } + }, + (EFI_EVENT)NULL, // ExitBootServicesEvent +}; + +EFI_STATUS +LcdInstanceContructor ( + OUT LCD_INSTANCE** NewInstance + ) +{ + LCD_INSTANCE* Instance; + + Instance = AllocateCopyPool (sizeof (LCD_INSTANCE), &mLcdTemplate); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Instance->Gop.Mode = &Instance->Mode; + Instance->Gop.Mode->MaxMode = mMaxMode; + Instance->Mode.Info = &Instance->ModeInfo; + + *NewInstance = Instance; + return EFI_SUCCESS; +} + +// +// Function Definitions +// + +EFIAPI +EFI_STATUS +DisplayGetTiming ( + OUT DISPLAY_STATE *DisplayState + ) +{ + DRM_DISPLAY_MODE *Mode = &DisplayState->ConnectorState.DisplayMode; + UINT32 ModeNumber = DisplayState->ModeNumber; + UINT32 HActive, VActive, PixelClock; + UINT32 HFrontPorch, HBackPorch, HSyncLen; + UINT32 VFrontPorch, VBackPorch, VSyncLen; + UINT32 Flags = 0; + UINT32 Val = 0; + + HActive = mDisplayModes[ModeNumber].Horizontal.Resolution; + VActive = mDisplayModes[ModeNumber].Vertical.Resolution; + PixelClock = mDisplayModes[ModeNumber].OscFreq; + HSyncLen = mDisplayModes[ModeNumber].Horizontal.Sync; + HFrontPorch = mDisplayModes[ModeNumber].Horizontal.FrontPorch; + HBackPorch = mDisplayModes[ModeNumber].Horizontal.BackPorch; + VSyncLen = mDisplayModes[ModeNumber].Vertical.Sync; + VFrontPorch = mDisplayModes[ModeNumber].Vertical.FrontPorch; + VBackPorch = mDisplayModes[ModeNumber].Vertical.BackPorch; + + Val = mDisplayModes[ModeNumber].HsyncActive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; + Flags |= Val; + Val = mDisplayModes[ModeNumber].VsyncActive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; + Flags |= Val; + Val = mDisplayModes[ModeNumber].ClkActive ? DRM_MODE_FLAG_PPIXDATA : 0; + Flags |= Val; + + Mode->HDisplay = HActive; + Mode->HSyncStart = Mode->HDisplay + HFrontPorch; + Mode->HSyncEnd = Mode->HSyncStart + HSyncLen; + Mode->HTotal = Mode->HSyncEnd + HBackPorch; + + Mode->VDisplay = VActive; + Mode->VSyncStart = Mode->VDisplay + VFrontPorch; + Mode->VSyncEnd = Mode->VSyncStart + VSyncLen; + Mode->VTotal = Mode->VSyncEnd + VBackPorch; + + Mode->Clock = PixelClock / 1000; + Mode->Flags = Flags; + + /* not to set fix --- todo */ + Mode->VScan = 0; + + return EFI_SUCCESS; +} + +STATIC +UINT32 +DisplayBppConvert ( + IN LCD_BPP LcdBpp + ) +{ + UINT32 DisplayBpp; + + switch (LcdBpp) { + case LcdBitsPerPixel_24: + DisplayBpp = 32; + break; + default: + DisplayBpp = 32; + break; + } + + return DisplayBpp; +} + +STATIC +EFI_STATUS +DisplayPreInit ( + IN LCD_INSTANCE* Instance + ) +{ + EFI_STATUS Status; + DISPLAY_STATE *StateInterate; + ROCKCHIP_CRTC_PROTOCOL *Crtc; + ROCKCHIP_CONNECTOR_PROTOCOL *Connector; + + LIST_FOR_EACH_ENTRY(StateInterate, &mDisplayStateList, ListHead) { + if (StateInterate->IsEnable) { + CRTC_STATE *CrtcState = &StateInterate->CrtcState; + CONNECTOR_STATE *ConnectorState = &StateInterate->ConnectorState; + Crtc = (ROCKCHIP_CRTC_PROTOCOL*)StateInterate->CrtcState.Crtc; + Connector = (ROCKCHIP_CONNECTOR_PROTOCOL *)StateInterate->ConnectorState.Connector; + + if (Connector && Connector->Preinit) + Status = Connector->Preinit(Connector, StateInterate); + + Crtc->Vps[CrtcState->CrtcID].OutputType = ConnectorState->Type; + + if (Crtc && Crtc->Preinit) { + Status = Crtc->Preinit(Crtc, StateInterate); + if (EFI_ERROR (Status)) { + goto EXIT; + } + } + } + } + +EXIT: + return Status; +} + +STATIC +EFI_STATUS +EFIAPI +LcdGraphicsOutputInit ( + VOID + ) +{ + EFI_STATUS Status; + LCD_INSTANCE *Instance; + DISPLAY_STATE *DisplayState; + DISPLAY_MODE *Mode; + UINTN ModeIndex; + ROCKCHIP_CRTC_PROTOCOL *Crtc; + UINTN ConnectorCount; + EFI_HANDLE *ConnectorHandles; + UINTN Index; + UINT32 HorizontalResolution; + UINT32 VerticalResolution; + + Status = LcdInstanceContructor (&Instance); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, + (VOID**)&mCpu); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = gBS->LocateProtocol (&gRockchipCrtcProtocolGuid, NULL, + (VOID **) &Crtc); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Can not locate the RockchipCrtcProtocol. Status=%r\n", + __func__, Status)); + return Status; + } + + Status = gBS->LocateHandleBuffer (ByProtocol, + &gRockchipConnectorProtocolGuid, + NULL, + &ConnectorCount, + &ConnectorHandles); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Can not locate gRockchipConnectorProtocolGuid. Status=%r\n", + __func__, Status)); + return Status; + } + + // + // TO-DO: When EDID is implemented. + // If native resolution is preferred (rather than custom, via PCDs), + // we should pick the maximum mode supported by all connected displays. + // + // Why? Because we provide a single GOP and framebuffer shared between + // all outputs. + // + // It is possible to install a GOP for each display, but then OSes would + // only draw on the primary (usually first) one. This needs additional + // logic to let users choose the primary display through a setup option. + // + + // + // Assume mode #0 is the highest supported mode for now. + // + ModeIndex = 0; + Mode = &mDisplayModes[ModeIndex]; + + InitializeListHead (&mDisplayStateList); + + for (Index = 0; Index < ConnectorCount; Index++) { + DisplayState = AllocateZeroPool (sizeof(DISPLAY_STATE)); + InitializeListHead (&DisplayState->ListHead); + + Status = gBS->HandleProtocol (ConnectorHandles[Index], + &gRockchipConnectorProtocolGuid, + (VOID **) &DisplayState->ConnectorState.Connector); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: HandleProtocol gRockchipConnectorProtocolGuid [%d] failed. Status=%r\n", + __func__, Index, Status)); + return Status; + } + + // + // DSI panel has a hardcoded mode. Overwrite the current one. + // This is all pretty ugly and prevents using multiple displays, + // but whatever... + // + ROCKCHIP_DSI_PANEL_PROTOCOL *DsiPanel; + + Status = gBS->HandleProtocol (ConnectorHandles[Index], + &gRockchipDsiPanelProtocolGuid, + (VOID **) &DsiPanel); + if (!EFI_ERROR (Status)) { + CopyMem (Mode, &DsiPanel->NativeMode, sizeof (*Mode)); + } + + /* adapt to UEFI architecture */ + DisplayState->ModeNumber = ModeIndex; + DisplayState->VpsConfigModeID = Mode->VpsConfigModeID; + + DisplayState->CrtcState.Crtc = (VOID *) Crtc; + DisplayState->CrtcState.CrtcID = Mode->CrtcId; + + DisplayState->ConnectorState.OverScan.LeftMargin = mDefaultOverScanParas.LeftMargin; + DisplayState->ConnectorState.OverScan.RightMargin = mDefaultOverScanParas.RightMargin; + DisplayState->ConnectorState.OverScan.TopMargin = mDefaultOverScanParas.TopMargin; + DisplayState->ConnectorState.OverScan.BottomMargin = mDefaultOverScanParas.BottomMargin; + + /* set MEDIA_BUS_FMT_RBG888_1X24 by default when using panel */ + /* move to panel driver later -- todo*/ + DisplayState->ConnectorState.BusFormat = MEDIA_BUS_FMT_RBG888_1X24; + + /* add BCSH data if needed --- todo */ + DisplayState->ConnectorState.DispInfo = NULL; + + Crtc->Vps[Mode->CrtcId].Enable = TRUE; + DisplayState->IsEnable = TRUE; + + InsertTailList (&mDisplayStateList, &DisplayState->ListHead); + } + + Status = DisplayPreInit (Instance); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: DisplayPreInit fail. Exit Status=%r\n", + __func__, Status)); + return Status; + } + + // Register for an ExitBootServicesEvent + // When ExitBootServices starts, this function will make sure that the + // graphics driver shuts down properly, i.e. it will free up all + // allocated memory and perform any necessary hardware re-configuration. + Status = gBS->CreateEvent ( + EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + LcdGraphicsExitBootServicesEvent, + NULL, + &Instance->ExitBootServicesEvent + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Can not install the ExitBootServicesEvent handler. Exit Status=%r\n", + __func__, Status)); + return Status; + } + + // Install the Graphics Output Protocol and the Device Path + Status = gBS->InstallMultipleProtocolInterfaces ( + &Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, + &Instance->Gop, + &gEfiDevicePathProtocolGuid, + &Instance->DevicePath, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Can not install the protocol. Status=%r\n", + __func__, Status)); + return Status; + } + + return EFI_SUCCESS; +} + +VOID +EFIAPI +LcdGraphicsOutputEndOfDxeEventHandler ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gBS->CloseEvent (Event); + + LcdGraphicsOutputInit (); +} + +EFI_STATUS +EFIAPI +LcdGraphicsOutputDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + LcdGraphicsOutputEndOfDxeEventHandler, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + return Status; +} + +/** This function should be called + on Event: ExitBootServices + to free up memory, stop the driver + and uninstall the protocols +**/ +VOID +LcdGraphicsExitBootServicesEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // By default, this PCD is FALSE. But if a platform starts a predefined OS + // that does not use a framebuffer then we might want to disable the display + // controller to avoid to display corrupted information on the screen. + if (FeaturePcdGet (PcdGopDisableOnExitBootServices)) { + // Turn-off the Display controller + } +} + +/** GraphicsOutput Protocol function, mapping to + EFI_GRAPHICS_OUTPUT_PROTOCOL.QueryMode +**/ +EFI_STATUS +EFIAPI +LcdGraphicsQueryMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber, + OUT UINTN *SizeOfInfo, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info + ) +{ + EFI_STATUS Status; + LCD_INSTANCE *Instance; + + Instance = LCD_INSTANCE_FROM_GOP_THIS (This); + + // Error checking + if ((This == NULL) || + (Info == NULL) || + (SizeOfInfo == NULL) || + (ModeNumber >= This->Mode->MaxMode)) { + DEBUG ((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d : Invalid Parameter.\n", ModeNumber)); + Status = EFI_INVALID_PARAMETER; + goto EXIT; + } + + *Info = AllocatePool (sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION)); + if (*Info == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto EXIT; + } + + *SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); + + (*Info)->Version = 0; + (*Info)->HorizontalResolution = mDisplayModes[ModeNumber].Horizontal.Resolution; + (*Info)->VerticalResolution = mDisplayModes[ModeNumber].Vertical.Resolution; + (*Info)->PixelsPerScanLine = mDisplayModes[ModeNumber].Horizontal.Resolution; + (*Info)->PixelFormat = FixedPcdGet32 (PcdLcdPixelFormat); + + return EFI_SUCCESS; + +EXIT: + return Status; +} + +/** GraphicsOutput Protocol function, mapping to + EFI_GRAPHICS_OUTPUT_PROTOCOL.SetMode +**/ +EFI_STATUS +EFIAPI +LcdGraphicsSetMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL FillColour; + LCD_INSTANCE* Instance; + LCD_BPP Bpp; + EFI_PHYSICAL_ADDRESS VramBaseAddress; + UINTN VramSize; + UINTN NumVramPages; + UINTN NumPreviousVramPages; + DISPLAY_MODE *Mode; + DRM_DISPLAY_MODE *DrmMode; + DISPLAY_STATE *StateInterate; + ROCKCHIP_CRTC_PROTOCOL *Crtc; + CRTC_STATE *CrtcState; + ROCKCHIP_CONNECTOR_PROTOCOL *Connector; + CONNECTOR_STATE *ConnectorState; + + Instance = LCD_INSTANCE_FROM_GOP_THIS (This); + + // Check if this mode is supported + if (ModeNumber >= This->Mode->MaxMode) { + DEBUG ((DEBUG_ERROR, "%a: ERROR - Unsupported mode number %d .\n", + __func__, ModeNumber)); + Status = EFI_UNSUPPORTED; + goto EXIT; + } + + Mode = &mDisplayModes[ModeNumber]; + + Status = LcdGraphicsGetBpp (ModeNumber, &Bpp); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: ERROR - Couldn't get bytes per pixel, status: %r\n", + __func__, Status)); + goto EXIT; + } + + VramBaseAddress = This->Mode->FrameBufferBase; + + VramSize = Mode->Horizontal.Resolution + * Mode->Vertical.Resolution + * GetBytesPerPixel (Bpp); + + NumVramPages = EFI_SIZE_TO_PAGES (VramSize); + NumPreviousVramPages = EFI_SIZE_TO_PAGES (This->Mode->FrameBufferSize); + + if (NumPreviousVramPages < NumVramPages) { + if (NumPreviousVramPages != 0) { + gBS->FreePages (VramBaseAddress, NumPreviousVramPages); + This->Mode->FrameBufferSize = 0; + } + + VramBaseAddress = SIZE_4GB - 1; // VOP2 only supports 32-bit addresses + Status = gBS->AllocatePages (AllocateMaxAddress, EfiRuntimeServicesData, + NumVramPages, &VramBaseAddress); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Could not allocate %u pages for mode %u: %r\n", + __func__, NumVramPages, ModeNumber, Status)); + return Status; + } + + Status = mCpu->SetMemoryAttributes (mCpu, VramBaseAddress, + ALIGN_VALUE (VramSize, EFI_PAGE_SIZE), + EFI_MEMORY_WC); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Couldn't set framebuffer attributes: %r\n", + __func__, Status)); + goto EXIT; + } + } + + // Update the UEFI mode information + This->Mode->Mode = ModeNumber; + + Instance->ModeInfo.Version = 0; + Instance->ModeInfo.HorizontalResolution = mDisplayModes[ModeNumber].Horizontal.Resolution; + Instance->ModeInfo.VerticalResolution = mDisplayModes[ModeNumber].Vertical.Resolution; + Instance->ModeInfo.PixelsPerScanLine = mDisplayModes[ModeNumber].Horizontal.Resolution; + Instance->ModeInfo.PixelFormat = FixedPcdGet32 (PcdLcdPixelFormat); + Instance->Mode.SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); + + This->Mode->FrameBufferBase = VramBaseAddress; + This->Mode->FrameBufferSize = VramSize; + + // The UEFI spec requires that we now clear the visible portions of the + // output display to black. + + // Set the fill colour to black + SetMem (&FillColour, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0); + + // Fill the entire visible area with the same colour. + Status = This->Blt ( + This, + &FillColour, + EfiBltVideoFill, + 0, + 0, + 0, + 0, + This->Mode->Info->HorizontalResolution, + This->Mode->Info->VerticalResolution, + 0 + ); + + LIST_FOR_EACH_ENTRY(StateInterate, &mDisplayStateList, ListHead) { + if (StateInterate->ModeNumber == ModeNumber && StateInterate->IsEnable) { + Crtc = (ROCKCHIP_CRTC_PROTOCOL*)StateInterate->CrtcState.Crtc; + Connector = (ROCKCHIP_CONNECTOR_PROTOCOL *)StateInterate->ConnectorState.Connector; + CrtcState = &StateInterate->CrtcState; + ConnectorState = &StateInterate->ConnectorState; + DrmMode = &StateInterate->ConnectorState.DisplayMode; + + StateInterate->ModeNumber = ModeNumber; + + if (Connector && Connector->Init) + Status = Connector->Init(Connector, StateInterate); + + /* move to panel protocol --- todo */ + DisplayGetTiming (StateInterate); + + DEBUG ((DEBUG_INIT, "[INIT]detailed mode clock %u kHz, flags[%x]\n" + " H: %04d %04d %04d %04d\n" + " V: %04d %04d %04d %04d\n" + " bus_format: %x\n", + DrmMode->Clock, DrmMode->Flags, + DrmMode->HDisplay, DrmMode->HSyncStart, + DrmMode->HSyncEnd, DrmMode->HTotal, + DrmMode->VDisplay, DrmMode->VSyncStart, + DrmMode->VSyncEnd, DrmMode->VTotal, + ConnectorState->BusFormat)); + + Status = DisplaySetCrtcInfo(DrmMode, CRTC_INTERLACE_HALVE_V); + if (EFI_ERROR (Status)) { + goto EXIT; + } + + if (Crtc && Crtc->Init) { + Status = Crtc->Init (Crtc, StateInterate); + if (EFI_ERROR (Status)) { + goto EXIT; + } + } + + /* adapt to uefi display architecture */ + CrtcState->Format = ROCKCHIP_FMT_ARGB8888; + CrtcState->SrcW = ConnectorState->DisplayMode.HDisplay; + CrtcState->SrcH = ConnectorState->DisplayMode.VDisplay; + CrtcState->SrcX = 0; + CrtcState->SrcY = 0; + CrtcState->CrtcW = ConnectorState->DisplayMode.HDisplay; + CrtcState->CrtcH = ConnectorState->DisplayMode.VDisplay; + CrtcState->CrtcX = 0; + CrtcState->CrtcY = 0; + CrtcState->YMirror = 0; + CrtcState->RBSwap = 0; + + CrtcState->XVirtual = ALIGN(CrtcState->SrcW * DisplayBppConvert (Bpp), 32) >> 5; + CrtcState->DMAAddress = (UINT32)VramBaseAddress; + + if (Crtc && Crtc->SetPlane) + Crtc->SetPlane (Crtc, StateInterate); + + if (Crtc && Crtc->Enable) + Crtc->Enable (Crtc, StateInterate); + + if (Connector && Connector->Enable) + Connector->Enable (Connector, StateInterate); + } + } + +EXIT: + return Status; +} + +EFI_STATUS +EFIAPI +LcdGraphicsGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP* Bpp + ) +{ + if (ModeNumber >= mMaxMode) { + return EFI_INVALID_PARAMETER; + } + + *Bpp = LcdBitsPerPixel_24; + + return EFI_SUCCESS; +} + +UINTN +GetBytesPerPixel ( + IN LCD_BPP Bpp + ) +{ + switch (Bpp) { + case LcdBitsPerPixel_24: + return 4; + + case LcdBitsPerPixel_16_565: + case LcdBitsPerPixel_16_555: + case LcdBitsPerPixel_12_444: + return 2; + + case LcdBitsPerPixel_8: + case LcdBitsPerPixel_4: + case LcdBitsPerPixel_2: + case LcdBitsPerPixel_1: + return 1; + + default: + return 0; + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h new file mode 100644 index 0000000..66b7256 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h @@ -0,0 +1,122 @@ +/** @file + + Copyright (c) 2011-2018, ARM Ltd. All rights reserved.
    + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef LCD_GRAPHICS_OUTPUT_DXE_H_ +#define LCD_GRAPHICS_OUTPUT_DXE_H_ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +/** The enumeration maps the PL111 LcdBpp values used in the LCD Control + Register +**/ +typedef enum { + LcdBitsPerPixel_1 = 0, + LcdBitsPerPixel_2, + LcdBitsPerPixel_4, + LcdBitsPerPixel_8, + LcdBitsPerPixel_16_555, + LcdBitsPerPixel_24, + LcdBitsPerPixel_16_565, + LcdBitsPerPixel_12_444, + LcdBitsPerPixel_Max +} LCD_BPP; + +// +// Device structures +// +typedef struct { + VENDOR_DEVICE_PATH Guid; + EFI_DEVICE_PATH_PROTOCOL End; +} LCD_GRAPHICS_DEVICE_PATH; + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; + EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE Mode; + EFI_GRAPHICS_OUTPUT_PROTOCOL Gop; + LCD_GRAPHICS_DEVICE_PATH DevicePath; + EFI_EVENT ExitBootServicesEvent; +} LCD_INSTANCE; + +#define LCD_INSTANCE_SIGNATURE SIGNATURE_32('l', 'c', 'd', '0') + +#define LCD_INSTANCE_FROM_GOP_THIS(a) CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE) + +// +// Function Prototypes +// + +VOID +LcdGraphicsExitBootServicesEvent ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS +EFIAPI +LcdGraphicsQueryMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber, + OUT UINTN *SizeOfInfo, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info +); + +EFI_STATUS +EFIAPI +LcdGraphicsSetMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber +); + +EFI_STATUS +EFIAPI +LcdGraphicsBlt ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL +); + +EFI_STATUS +EFIAPI +LcdGraphicsGetBpp ( + IN UINT32 ModeNumber, + OUT LCD_BPP* Bpp + ); + +UINTN +GetBytesPerPixel ( + IN LCD_BPP Bpp + ); + +EFI_STATUS +EFIAPI +GraphicsOutputDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +#endif /* LCD_GRAPHICS_OUTPUT_DXE_H_ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf new file mode 100644 index 0000000..bd2eb1f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf @@ -0,0 +1,62 @@ +#/** @file +# +# Component description file for LcdGraphicsOutputDxe module +# +# Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
    +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = LcdGraphicsOutputDxe + FILE_GUID = eaf89ad8-92e1-11ec-b51d-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = LcdGraphicsOutputDxeInitialize + +[Sources.common] + LcdGraphicsOutputBlt.c + LcdGraphicsOutputDxe.c + LcdGraphicsOutputDxe.h + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + ArmLib + BaseLib + BaseMemoryLib + CacheMaintenanceLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + RockchipDisplayLib + +[Protocols] + gEfiCpuArchProtocolGuid + gEfiDevicePathProtocolGuid + gEfiGraphicsOutputProtocolGuid + gRockchipCrtcProtocolGuid + gRockchipConnectorProtocolGuid + gRockchipDsiPanelProtocolGuid + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Pcd] + gRockchipTokenSpaceGuid.PcdLcdPixelFormat + +[FeaturePcd] + gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices + +[Depex] + gEfiCpuArchProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.c new file mode 100644 index 0000000..6ba68fe --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.c @@ -0,0 +1,1214 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2022 Rockchip Electronics Co., Ltd. + */ +#include +#include "Soc.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define HAL_SNOR_DEBUG +#ifdef HAL_SNOR_DEBUG +#define DEBUG_SNOR DEBUG_WARN +#else +#define DEBUG_SNOR DEBUG_INFO +#endif + +struct FLASH_INFO { + UINT32 id; + + UINT8 blockSize; + UINT8 sectorSize; + UINT8 readCmd; + UINT8 progCmd; + + UINT8 readCmd_4; + UINT8 progCmd_4; + UINT8 sectorEraseCmd; + UINT8 blockEraseCmd; + + UINT8 feature; + UINT8 density; /* (1 << density) sectors */ + UINT8 QEBits; + UINT8 reserved2; +}; + +/* FLASH_INFO feature */ +#define FEA_STATUE_MASK (0x3 << 0) +#define FEA_STATUE_MODE0 0 /* Readstatus0 05h-SR1, 35h-SR2, Writestatus0 01h-SR1, 31h-SR2 */ +#define FEA_STATUE_MODE1 1 /* Readstatus0 05h-SR1, 35h-SR2, Writestatus1 01h-SR1-SR2 */ +#define FEA_STATUE_MODE2 2 /* Readstatus1 05h-SR1, 15h-CR1, Writestatus1 01h-SR1-CR1 */ +#define FEA_4BIT_READ BIT(2) +#define FEA_4BIT_PROG BIT(3) +#define FEA_4BYTE_ADDR BIT(4) +#define FEA_4BYTE_ADDR_MODE BIT(5) + +/*Manufactory ID*/ +#define MID_WINBOND 0xEF +#define MID_GIGADEV 0xC8 +#define MID_MICRON 0x2C +#define MID_MACRONIX 0xC2 +#define MID_SPANSION 0x01 +#define MID_EON 0x1C +#define MID_ST 0x20 +#define MID_XTX 0x0B +#define MID_PUYA 0x85 +#define MID_XMC 0x20 + +/* Used for Macronix and Winbond flashes. */ +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */ +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */ + +/* Used for SST flashes only. */ +#define SPINOR_OP_WRDI 0x04 /* Write disable */ + +#define SPINOR_OP_MAX_SIZE 0x40 +#define UINT_MAX (~0U) + +#define READ_MAX_IOSIZE (1024 * 8) /* 8KB */ + +/********************* Private Structure Definition **************************/ + +/********************* Private Variable Definition ***************************/ +static const struct FLASH_INFO s_spiFlashbl[] = { + /* GD25Q32B */ + { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, + /* GD25Q64B */ + { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* GD25Q127C and GD25Q128C*/ + { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + /* GD25Q256B/C/D */ + { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, + /* GD25LQ64C */ + { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* GD25LQ32E */ + { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, + /* GD25Q256E */ + { 0xc86019, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 16, 9, 0 }, + + /* W25Q32JV */ + { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, + /* W25Q64JVSSIQ */ + { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + /* W25Q128FV and W25Q128JV*/ + { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + /* W25Q256F/J */ + { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, + /* 25Q32JW */ + { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, + /* W25Q256JWEQ*/ + { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, + /* W25Q64FWSSIG */ + { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + /* W25Q64JVSIQ */ + { 0xef7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + /* W25Q128JVSIM */ + { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + + /* MX25L3233FM2I-08G */ + { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, + /* MX25L6433F */ + { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, + /* MX25L12835E/F MX25L12833FMI-10G */ + { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, + /* MX25U12832F */ + { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 }, + /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */ + { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, + + /* XM25QH32C */ + { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, + /* XM25QH64B */ + { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, + /* XM25QH128B */ + { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, + /* XM25QH(QU)256B */ + { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, + /* XM25QH64A */ + { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, + /* XM25QU128C */ + { 0x204118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + /* XM25QU64C */ + { 0x204117, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + + /* XT25F64BSSIGU-5 */ + { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* XT25F128BSSIGU */ + { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, + /* XT25F32BS */ + { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, + /* XT25F16BS */ + { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, + + /* EN25QH64A */ + { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, + /* EN25QH128A */ + { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, + /* EN25QH32B */ + { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, + /* EN25S16A */ + { 0x1c3815, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 12, 0, 0 }, + /* EN25S32A */ + { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, + /* EN25S64A */ + { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, + /* EN25QH256A */ + { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, + + /* P25Q64H */ + { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + /* P25Q128H */ + { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + /* P25Q16H-SUH-IT */ + { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, + /* FM25Q64A */ + { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* FM25M64C */ + { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* P25Q32SL */ + { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, + + /* ZB25VQ64 */ + { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + /* ZB25VQ128 */ + { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + /* ZB25LQ128 */ + { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + + /* BH25Q128AS */ + { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, + /* BH25Q64BS */ + { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + + /* P25Q64H */ + { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + + /* FM25Q64-SOB-T-G */ + { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, + + /* FM25Q64A */ + { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, + /* FM25M4AA */ + { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, +}; +STATIC struct HAL_FSPI_HOST *g_spi; +STATIC struct SPI_NOR *g_nor; +STATIC EFI_EVENT mNorVirtualAddrChangeEvent; +/* Support single line case + * - id: get from SPI Nor device information + * - capacity: initial by SPI Nor id byte + * - QE bits: no need + * */ +static struct FLASH_INFO s_commonSpiFlash = { 0, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 0, 0, 0 }; + +/********************* Private Function Definition ***************************/ +static RETURN_STATUS SNOR_ReadWriteReg(struct SPI_NOR *nor, struct HAL_SPI_MEM_OP *op, void *buf) +{ + if (op->data.dir == HAL_SPI_MEM_DATA_IN) { + op->data.buf.in = buf; + } else { + op->data.buf.out = buf; + } + + return HAL_FSPI_SpiXfer(nor->spi, op); +} + +static RETURN_STATUS SNOR_ReadReg(struct SPI_NOR *nor, UINT8 code, UINT8 *val, UINT32 len) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(code, 1), + HAL_SPI_MEM_OP_NO_ADDR, + HAL_SPI_MEM_OP_NO_DUMMY, + HAL_SPI_MEM_OP_DATA_IN(len, NULL, 1)); + RETURN_STATUS ret; + + ret = SNOR_ReadWriteReg(nor, &op, val); + if (ret) { + DEBUG ((DEBUG_SNOR, "error %d reading %x\n", ret, code)); + } + + return ret; +} + +static RETURN_STATUS SNOR_WriteReg(struct SPI_NOR *nor, UINT8 opcode, UINT8 *buf, UINT32 len) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(opcode, 1), + HAL_SPI_MEM_OP_NO_ADDR, + HAL_SPI_MEM_OP_NO_DUMMY, + HAL_SPI_MEM_OP_DATA_OUT(len, NULL, 1)); + + /* DEBUG ((DEBUG_SNOR, "%s %x %ld\n", __func__, opcode, len)); */ + + return SNOR_ReadWriteReg(nor, &op, buf); +} + +static INT32 SNOR_ReadData(struct SPI_NOR *nor, UINT32 from, UINT32 len, UINT8 *buf) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(nor->readOpcode, 1), + HAL_SPI_MEM_OP_ADDR(nor->addrWidth, from, 1), + HAL_SPI_MEM_OP_DUMMY(nor->readDummy, 1), + HAL_SPI_MEM_OP_DATA_IN(len, buf, 1)); + INT32 ret; + + /* get transfer protocols. */ + op.cmd.buswidth = 1; + op.addr.buswidth = SNOR_GET_PROTOCOL_ADDR_BITS(nor->readProto); + op.dummy.buswidth = op.addr.buswidth; + op.data.buswidth = SNOR_GET_PROTOCOL_DATA_BITS(nor->readProto); + + /* DEBUG ((DEBUG_SNOR, "%s %x %lx %lx %lx\n", __func__, nor->readDummy, op.data.nbytes, from, op.addr.val)); */ + /* convert the dummy cycles to the number of bytes */ + op.dummy.nbytes = (nor->readDummy * op.dummy.buswidth) >> 3; + + ret = HAL_FSPI_SpiXfer(nor->spi, &op); + if (ret) { + return 0; + } + + return len; +} + +static INT32 SNOR_WriteData(struct SPI_NOR *nor, UINT32 to, UINT32 len, const UINT8 *buf) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(nor->programOpcode, 1), + HAL_SPI_MEM_OP_ADDR(nor->addrWidth, to, 1), + HAL_SPI_MEM_OP_NO_DUMMY, + HAL_SPI_MEM_OP_DATA_OUT(len, buf, 1)); + INT32 ret; + + /* get transfer protocols. */ + op.cmd.buswidth = 1; + op.addr.buswidth = SNOR_GET_PROTOCOL_ADDR_BITS(nor->writeProto); + op.data.buswidth = SNOR_GET_PROTOCOL_DATA_BITS(nor->writeProto); + + op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes; + + ret = HAL_FSPI_SpiXfer(nor->spi, &op); + if (ret) { + return 0; + } + + return op.data.nbytes; +} + +/* + * Initiate the erasure of a single sector + */ +static RETURN_STATUS SNOR_EraseSec(struct SPI_NOR *nor, UINT32 addr) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(nor->eraseOpcodeSec, 1), + HAL_SPI_MEM_OP_ADDR(nor->addrWidth, addr, 1), + HAL_SPI_MEM_OP_NO_DUMMY, + HAL_SPI_MEM_OP_NO_DATA); + + /* + * Default implementation, if driver doesn't have a specialized HW + * control + */ + return HAL_FSPI_SpiXfer(nor->spi, &op); +} + +/* + * Initiate the erasure of a single sector + */ +static RETURN_STATUS SNOR_EraseBlk(struct SPI_NOR *nor, UINT32 addr) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(nor->eraseOpcodeBlk, 1), + HAL_SPI_MEM_OP_ADDR(nor->addrWidth, addr, 1), + HAL_SPI_MEM_OP_NO_DUMMY, + HAL_SPI_MEM_OP_NO_DATA); + + /* + * Default implementation, if driver doesn't have a specialized HW + * control + */ + return HAL_FSPI_SpiXfer(nor->spi, &op); +} + +static RETURN_STATUS SNOR_EraseChip(struct SPI_NOR *nor, UINT32 addr) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 1), + HAL_SPI_MEM_OP_NO_ADDR, + HAL_SPI_MEM_OP_NO_DUMMY, + HAL_SPI_MEM_OP_NO_DATA); + /* + * Default implementation, if driver doesn't have a specialized HW + * control + */ + return HAL_FSPI_SpiXfer(nor->spi, &op); +} + +static const struct FLASH_INFO *SNOR_GerFlashInfo(UINT8 *flashId) +{ + UINT32 i; + UINT32 id = (flashId[0] << 16) | (flashId[1] << 8) | (flashId[2] << 0); + + for (i = 0; i < ARRAY_SIZE(s_spiFlashbl); i++) { + if (s_spiFlashbl[i].id == id) { + return &s_spiFlashbl[i]; + } + } + + return NULL; +} + +static RETURN_STATUS SNOR_WriteEnable(struct SPI_NOR *nor) +{ + return SNOR_WriteReg(nor, SPINOR_OP_WREN, NULL, 0); +} + +/* + * Service routine to read status register until ready, or timeout occurs. + * Returns non-zero if error. + */ +static RETURN_STATUS SNOR_WaitBusy(struct SPI_NOR *nor, unsigned long timeout) +{ + RETURN_STATUS ret; + UINT32 i; + UINT8 status; + + /* DEBUG ((DEBUG_SNOR, "%s %lx\n", __func__, timeout)); */ + for (i = 0; i < timeout; i++) { + ret = SNOR_ReadReg(nor, SPINOR_OP_RDSR, &status, 1); + if (ret != RETURN_SUCCESS) { + return ret; + } + + if ((status & 0x01) == 0) { + return RETURN_SUCCESS; + } + + NanoSecondDelay(500); + } + DEBUG ((DEBUG_SNOR, "%s error %ld\n", __func__, timeout)); + + return RETURN_NOT_READY; +} + +static RETURN_STATUS SNOR_ReadStatus(struct SPI_NOR *nor, UINT32 regIndex, UINT8 *status) +{ + UINT8 readStatCmd[] = { SPINOR_OP_RDSR, SPINOR_OP_RDSR1, SPINOR_OP_RDSR2 }; + UINT8 i = nor->info->feature & FEA_STATUE_MASK; + + if (i == FEA_STATUE_MODE2) { /* Readstatus1 */ + readStatCmd[1] = SPINOR_OP_RDCR; + } + + return SNOR_ReadReg(nor, readStatCmd[regIndex], status, 1); +} + +static RETURN_STATUS SNOR_WriteStatus(struct SPI_NOR *nor, UINT32 regIndex, UINT8 *status) +{ + UINT8 WriteStatCmd[2] = { SPINOR_OP_WRSR, SPINOR_OP_WRSR1 }; + UINT8 i = nor->info->feature & FEA_STATUE_MASK; + RETURN_STATUS ret; + + if (i == FEA_STATUE_MODE0) { /* Writestatus0 */ + SNOR_WriteEnable(nor); + + ret = SNOR_WriteReg(nor, WriteStatCmd[regIndex], status, 1); + if (ret) { + DEBUG ((DEBUG_SNOR, "error while writing configuration register\n")); + + return RETURN_DEVICE_ERROR; + } + + ret = SNOR_WaitBusy(nor, 10000); + if (ret) { + DEBUG ((DEBUG_SNOR, "timeout while writing configuration register\n")); + + return ret; + } + } else { /* Writestatus1 */ + UINT8 readIndex; + UINT8 status2[2]; + + status2[regIndex] = *status; + readIndex = (regIndex == 0) ? 1 : 0; + ret = SNOR_ReadStatus(nor, readIndex, &status2[readIndex]); + if (ret != RETURN_SUCCESS) { + return ret; + } + + SNOR_WriteEnable(nor); + ret = SNOR_WriteReg(nor, SPINOR_OP_WRSR, &status2[0], 2); + if (ret != RETURN_SUCCESS) { + return ret; + } + + ret = SNOR_WaitBusy(nor, 10000); + } + + return RETURN_SUCCESS; +} + +static RETURN_STATUS SNOR_EnableQE(struct SPI_NOR *nor) +{ + RETURN_STATUS ret = RETURN_SUCCESS; + int regIndex; + int bitOffset; + UINT8 status; + + regIndex = nor->info->QEBits >> 3; + bitOffset = nor->info->QEBits & 0x7; + ret = SNOR_ReadStatus(nor, regIndex, &status); + if (ret != RETURN_SUCCESS) { + return ret; + } + + if (status & (1 << bitOffset)) { //is QE bit set + return RETURN_SUCCESS; + } + + status |= (1 << bitOffset); + ret = SNOR_WriteStatus(nor, regIndex, &status); + + return ret; +} + +/* Enable/disable 4-byte addressing mode. */ +static RETURN_STATUS SNOR_Enter4byte(struct SPI_NOR *nor) +{ + return SNOR_WriteReg(nor, SPINOR_OP_EN4B, NULL, 0); +} + +RETURN_STATUS SNOR_ReadSFDP(struct SPI_NOR *nor, UINT32 addr, UINT8 *data) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(SPINOR_OP_READ_SFDP, 1), + HAL_SPI_MEM_OP_ADDR(3, addr, 1), + HAL_SPI_MEM_OP_DUMMY(1, 1), + HAL_SPI_MEM_OP_DATA_IN(1, data, 1)); + + return HAL_FSPI_SpiXfer(nor->spi, &op); +} + +static void *SNOR_InfoAdjust(struct SPI_NOR *nor, struct FLASH_INFO *info) +{ + UINT32 addr; + UINT8 para; + + if (info->id == 0xc84019) { + addr = 0x09; + SNOR_ReadSFDP(nor, addr, ¶); + if (para == 0x06) { + info->QEBits = 9; + info->progCmd_4 = 0x34; + } + } + + return 0; +} + +/** + * @brief Flash continuous writing. + * @param nor: nor dev. + * @param from: byte address. + * @param buf: source address. + * @param len: number of bytes. + * @return If the transfer is successful, return the transfer length, or error code. + */ +RETURN_STATUS HAL_SNOR_ReadData(struct SPI_NOR *nor, UINT32 from, void *buf, UINT32 len) +{ + RETURN_STATUS ret; + UINT8 *pBuf = (UINT8 *)buf; + UINT32 size, remain = len; + + /* DEBUG ((DEBUG_SNOR, "%s from 0x%08lx, len %lx\n", __func__, from, len)); */ + if (from >= nor->size || len > nor->size || (from + len) > nor->size) { + return RETURN_DEVICE_ERROR; + } + + while (remain) { + size = MIN(READ_MAX_IOSIZE, remain); + ret = SNOR_ReadData(nor, from, size, pBuf); + if (ret != (RETURN_STATUS)size) { + DEBUG ((DEBUG_SNOR, "%s %lu ret= %ld\n", __func__, from >> 9, ret)); + + return ret; + } + remain -= size; + from += size; + pBuf += size; + } + + return len; +} + +/** + * @brief Flash continuous reading. + * @param nor: nor dev. + * @param to: byte address. + * @param buf: source address. + * @param len: number of bytes. + * @return If the transfer is successful, return the transfer length, or error code. + */ +RETURN_STATUS HAL_SNOR_ProgData(struct SPI_NOR *nor, UINT32 to, void *buf, UINT32 len) +{ + RETURN_STATUS ret; + UINT8 *pBuf = (UINT8 *)buf; + UINT32 size, remain = len, pageOffset; + + /* DEBUG ((DEBUG_SNOR, "%s to 0x%08lx, len %lx\n", __func__, to, len)); */ + if (to >= nor->size || len > nor->size || (to + len) > nor->size) { + return RETURN_DEVICE_ERROR; + } + + while (remain) { + pageOffset = to & (nor->pageSize - 1); + size = MIN(nor->pageSize - pageOffset, remain); + SNOR_WriteEnable(nor); + ret = SNOR_WriteData(nor, to, size, pBuf); + if (ret != (RETURN_STATUS)size) { + DEBUG ((DEBUG_SNOR, "%s %lu ret= %ld\n", __func__, to >> 9, ret)); + + return ret; + } + SNOR_WaitBusy(nor, 10000); + remain -= size; + to += size; + pBuf += size; + } + + return len; +} + +/** + * @brief Flash erase with erase type. + * @param nor: nor dev. + * @param addr: byte address. + * @param eraseType: erase type. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_SNOR_Erase(struct SPI_NOR *nor, UINT32 addr, NOR_ERASE_TYPE eraseType) +{ + RETURN_STATUS ret; + INT32 timeout[] = { 400, 2000, 40000 }; + + /* DEBUG ((DEBUG_SNOR, "%s addr %lx\n", __func__, addr)); */ + if (addr >= nor->size) { + return RETURN_DEVICE_ERROR; + } + + SNOR_WriteEnable(nor); + if (eraseType == ERASE_SECTOR) { + ret = SNOR_EraseSec(nor, addr); + } else if (eraseType == ERASE_BLOCK64K) { + ret = SNOR_EraseBlk(nor, addr); + } else { + ret = SNOR_EraseChip(nor, addr); + } + if (ret != RETURN_SUCCESS) { + return ret; + } + + return SNOR_WaitBusy(nor, timeout[eraseType] * 1000); +} + +/** + * @brief Flash continuous reading according to sectors. + * @param nor: nor dev. + * @param sec: sector address. + * @param nSec: number of sectors. + * @param pData: destination address. + * @return If the transfer is successful, return the transfer length, or error code. + */ +RETURN_STATUS HAL_SNOR_Read(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData) +{ + RETURN_STATUS ret = RETURN_SUCCESS; + + /* DEBUG ((DEBUG_SNOR, "%s sec 0x%08lx, nSec %lx\n", __func__, sec, nSec)); */ + ret = HAL_SNOR_ReadData(nor, sec * nor->sectorSize, pData, nSec * nor->sectorSize); + if (ret != (RETURN_STATUS)(nSec * nor->sectorSize)) { + return ret; + } + + return (RETURN_STATUS)nSec; +} + +/** + * @brief Flash continuous writing according to sectors. + * @param nor: nor dev. + * @param sec: sector address. + * @param nSec: number of sectors. + * @param pData: source address. + * @return If the transfer is successful, return the transfer length, or error code. + */ +RETURN_STATUS HAL_SNOR_Write(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData) +{ + RETURN_STATUS ret = RETURN_SUCCESS; + + /* DEBUG ((DEBUG_SNOR, "%s sec 0x%08lx, nSec %lx\n", __func__, sec, nSec)); */ + ret = HAL_SNOR_ProgData(nor, sec * nor->sectorSize, pData, nSec * nor->sectorSize); + if (ret != (RETURN_STATUS)(nSec * nor->sectorSize)) { + return ret; + } + + return (RETURN_STATUS)nSec; +} + +/** + * @brief Flash continuous writing according to sectors. + * @param nor: nor dev. + * @param sec: sector address. + * @param nSec: number of sectors. + * @param pData: source address. + * @return If the transfer is successful, return the transfer length, or error code. + */ +RETURN_STATUS HAL_SNOR_OverWrite(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData) +{ + RETURN_STATUS ret = RETURN_SUCCESS; + UINT8 *pBuf = (UINT8 *)pData; + UINT32 remaining = nSec; + + /* DEBUG ((DEBUG_SNOR, "%s sec 0x%08lx, nSec %lx\n", __func__, sec, nSec)); */ + while (remaining) { + ret = HAL_SNOR_Erase(nor, sec * nor->sectorSize, ERASE_SECTOR); + if (ret != RETURN_SUCCESS) { + return ret; + } + + ret = HAL_SNOR_ProgData(nor, sec * nor->sectorSize, (void *)pBuf, nor->sectorSize); + if (ret != (RETURN_STATUS)(nor->sectorSize)) { + return ret; + } + + pBuf += nor->sectorSize; + remaining--; + sec++; + } + + return (RETURN_STATUS)nSec; +} + +/** @} */ + +/** @defgroup SNOR_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + ...to do or delete this row + + * @{ + */ + +/** + * @brief SFC NOR flash module init. + * @param nor: nor dev. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_SNOR_Init(struct SPI_NOR *nor) +{ + UINT8 idByte[5]; + const struct FLASH_INFO *info; + INT32 ret = RETURN_SUCCESS; + + if (!nor->spi) { + DEBUG ((DEBUG_SNOR, "%a no host\n", __func__)); + + return RETURN_DEVICE_ERROR; + } + //nor->read = SNOR_ReadData; + //nor->write = SNOR_WriteData; + //nor->readReg = SNOR_ReadReg; + //nor->writeReg = SNOR_WriteReg; + + HAL_SNOR_ReadID(nor, idByte); + DEBUG ((DEBUG_SNOR, "SPI Nor ID: %x %x %x\n", idByte[0], idByte[1], idByte[2])); + + if ((idByte[0] == 0xFF) || (idByte[0] == 0x00)) { + return RETURN_DEVICE_ERROR; + } + + info = SNOR_GerFlashInfo(idByte); + if (!info) { + if (nor->spi->mode & HAL_SPI_RX_QUAD || + nor->spi->mode & HAL_SPI_TX_QUAD) { + return RETURN_NO_MEDIA; + } + s_commonSpiFlash.id = (idByte[0] << 16) | (idByte[1] << 8) | idByte[2]; + s_commonSpiFlash.density = idByte[2] - 9; + info = &s_commonSpiFlash; + } else { + SNOR_InfoAdjust(nor, (struct FLASH_INFO *)info); + } + + nor->info = info; + nor->pageSize = 256; + nor->addrWidth = 3; + nor->eraseOpcodeSec = info->sectorEraseCmd; + nor->eraseOpcodeBlk = info->blockEraseCmd; + nor->readOpcode = info->readCmd; + nor->readProto = SNOR_PROTO_1_1_1; + nor->readDummy = 0; + nor->programOpcode = info->progCmd; + nor->writeProto = SNOR_PROTO_1_1_1; + //nor->name = "spi-nor"; + nor->sectorSize = info->sectorSize * 512; + nor->size = 1 << (info->density + 9); + nor->eraseSize = nor->sectorSize; + if (nor->spi->mode & HAL_SPI_RX_QUAD) { + ret = RETURN_SUCCESS; + if (info->QEBits) { + ret = SNOR_EnableQE(nor); + } + if (ret == RETURN_SUCCESS) { + nor->readOpcode = info->readCmd_4; + switch (nor->readOpcode) { + case SPINOR_OP_READ_1_4_4: + nor->readDummy = 6; + nor->readProto = SNOR_PROTO_1_4_4; + break; + default: + nor->readDummy = 8; + nor->readProto = SNOR_PROTO_1_1_4; + break; + } + } + } else if (nor->spi->mode & HAL_SPI_RX_DUAL) { + nor->readOpcode = SPINOR_OP_READ_1_1_2; + nor->readDummy = 8; + nor->readProto = SNOR_PROTO_1_1_2; + } + if (nor->spi->mode & HAL_SPI_TX_QUAD && + info->QEBits) { + if (SNOR_EnableQE(nor) == RETURN_SUCCESS) { + nor->programOpcode = info->progCmd_4; + switch (nor->programOpcode) { + case SPINOR_OP_PP_1_4_4: + nor->writeProto = SNOR_PROTO_1_4_4; + break; + default: + nor->writeProto = SNOR_PROTO_1_1_4; + break; + } + } + } + if (info->feature & FEA_4BYTE_ADDR) { + nor->addrWidth = 4; + } + + if (info->feature & FEA_4BYTE_ADDR_MODE) { + SNOR_Enter4byte(nor); + } + + DEBUG ((DEBUG_SNOR, "nor->addrWidth: %x\n", nor->addrWidth)); + DEBUG ((DEBUG_SNOR, "nor->readProto: %x\n", nor->readProto)); + DEBUG ((DEBUG_SNOR, "nor->writeProto: %x\n", nor->writeProto)); + DEBUG ((DEBUG_SNOR, "nor->readCmd: %x\n", nor->readOpcode)); + DEBUG ((DEBUG_SNOR, "nor->programCmd: %x\n", nor->programOpcode)); + DEBUG ((DEBUG_SNOR, "nor->eraseOpcodeBlk: %x\n", nor->eraseOpcodeBlk)); + DEBUG ((DEBUG_SNOR, "nor->eraseOpcodeSec: %x\n", nor->eraseOpcodeSec)); + DEBUG ((DEBUG_SNOR, "nor->size: %ldMB\n", nor->size >> 20)); + DEBUG ((DEBUG_SNOR, "nor->size: %ldMB\n", nor->size >> 20)); + + return RETURN_SUCCESS; +} + +/** + * @brief SFC NOR flash module deinit. + * @param nor: nor dev. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_SNOR_DeInit(struct SPI_NOR *nor) +{ + return RETURN_SUCCESS; +} + +/** @} */ + +/** @defgroup SNOR_Exported_Functions_Group5 Other Functions + * @{ + */ + +/** + * @brief Read flash ID. + * @param nor: nor dev. + * @param data: address to storage flash ID value. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_SNOR_ReadID(struct SPI_NOR *nor, UINT8 *data) +{ + INT32 ret; + UINT8 *id = data; + + ret = SNOR_ReadReg(nor, SPINOR_OP_RDID, id, 3); + if (ret) { + DEBUG ((DEBUG_SNOR, "error reading JEDEC ID%x %x %x\n", id[0], id[1], id[2])); + + return RETURN_DEVICE_ERROR; + } + + return RETURN_SUCCESS; +} + +/** + * @brief Get flash capacity. + * @param nor: nor dev. + * @return UINT32: flash capacity, n bytes. + */ +UINT32 HAL_SNOR_GetCapacity(struct SPI_NOR *nor) +{ + return nor->size; +} + +/** + * @brief Check if the flash support. + * @param flashId: flash id. + * @return HAL_Check. + */ +BOOLEAN HAL_SNOR_IsFlashSupported(UINT8 *flashId) +{ + UINT32 i; + UINT32 id = (flashId[0] << 16) | (flashId[1] << 8) | (flashId[2] << 0); + + for (i = 0; i < ARRAY_SIZE(s_spiFlashbl); i++) { + if (s_spiFlashbl[i].id == id) { + return TRUE; + } + } + + return FALSE; +} + +RETURN_STATUS HAL_SNOR_ReadUUID(struct SPI_NOR *nor, void *buf) +{ + struct HAL_SPI_MEM_OP op = HAL_SPI_MEM_OP_FORMAT(HAL_SPI_MEM_OP_CMD(SPINOR_OP_READ_UUID, 1), + HAL_SPI_MEM_OP_ADDR(4, 0, 1), + HAL_SPI_MEM_OP_DUMMY(0, 1), + HAL_SPI_MEM_OP_DATA_IN(8, buf, 1)); + + return HAL_FSPI_SpiXfer(nor->spi, &op); +} + +EFI_STATUS Erase( + IN UNI_NOR_FLASH_PROTOCOL *This, + IN UINT32 Offset, + IN UINT32 ulLen + ) +{ + EFI_STATUS Status; + UINTN EraseSize; + + if (EfiAtRuntime ()) + NorFspiEnableClock(g_nor->spi->CruBase); + + EraseSize = g_nor->sectorSize; + + // Check input parameters + if (Offset % EraseSize || ulLen % EraseSize) { + DEBUG((DEBUG_ERROR, "SpiFlash: Either erase offset or length is not multiple of erase size\n")); + return EFI_DEVICE_ERROR; + } + + while (ulLen) { + Status = HAL_SNOR_Erase(g_nor, Offset, ERASE_SECTOR); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while erase target address\n")); + return Status; + } + Offset += EraseSize; + ulLen -= EraseSize; + } + return EFI_SUCCESS; +} + +UINT32 GetSize( + IN UNI_NOR_FLASH_PROTOCOL *This + ) +{ + return HAL_SNOR_GetCapacity(g_nor); +} + +EFI_STATUS Write( + IN UNI_NOR_FLASH_PROTOCOL *This, + IN UINT32 Offset, + IN UINT8 *Buffer, + UINT32 ulLen + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + if (EfiAtRuntime ()) + NorFspiEnableClock(g_nor->spi->CruBase); + + //DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: %x!......................\n", __FUNCTION__,__LINE__,Offset)); + Status = HAL_SNOR_ProgData(g_nor, Offset, Buffer, ulLen); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while programming target address\n")); + } + return Status; +} + +EFI_STATUS Read( + IN UNI_NOR_FLASH_PROTOCOL *This, + IN UINT32 Offset, + IN OUT UINT8 *Buffer, + IN UINT32 ulLen + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + if (EfiAtRuntime ()) + NorFspiEnableClock(g_nor->spi->CruBase); + + //DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: %x!......................\n", __FUNCTION__,__LINE__,Offset)); + Status = HAL_SNOR_ReadData(g_nor, Offset, Buffer, ulLen); + return Status; +} + +STATIC +EFI_STATUS +SpiFlashUpdateBlock ( + IN UINT32 Offset, + IN UINT32 Align, + IN UINTN ToUpdate, + IN UINT8 *Buf, + IN UINT8 *TmpBuf, + IN UINTN EraseSize + ) +{ + + EFI_STATUS Status; + + if (EfiAtRuntime ()) + NorFspiEnableClock(g_nor->spi->CruBase); + + // Read backup + if (ToUpdate != EraseSize) { + Status = HAL_SNOR_ReadData (g_nor, Offset - Align, TmpBuf, EraseSize); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while reading old data\n")); + return Status; + } + } + // Erase entire sector + Status = HAL_SNOR_Erase (g_nor, Offset, ERASE_SECTOR); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while erasing block\n")); + return Status; + } + + if (Align) { + CopyMem (&TmpBuf[Align], Buf, ToUpdate); + Status = HAL_SNOR_ProgData (g_nor, Offset - Align, TmpBuf, EraseSize); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while writing new data\n")); + return Status; + } + return EFI_SUCCESS; + } + + // Write new data + Status = HAL_SNOR_ProgData (g_nor, Offset, Buf, ToUpdate); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while writing new data\n")); + return Status; + } + + // Write backup + if (ToUpdate != EraseSize) { + Status = HAL_SNOR_ProgData (g_nor, Offset + ToUpdate, &TmpBuf[ToUpdate], EraseSize - ToUpdate); + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Update: Error while writing backup\n")); + return Status; + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS Update( + IN UNI_NOR_FLASH_PROTOCOL *This, + IN UINT32 Offset, + IN UINT8 *Buffer, + UINT32 ulLength + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT64 SectorSize, ToUpdate, Align, Scale = 1; + UINT8 *TmpBuf, *End; + //DEBUG ((DEBUG_ERROR, "[%a]:%x %x!......................\n", __FUNCTION__, Offset, ulLength)); + + SectorSize = g_nor->sectorSize; + Align = Offset & (SectorSize -1); + End = Buffer + ulLength; + + TmpBuf = (UINT8 *)AllocateZeroPool (SectorSize); + if (TmpBuf == NULL) { + DEBUG((DEBUG_ERROR, "SpiFlash: Cannot allocate memory\n")); + return EFI_OUT_OF_RESOURCES; + } + + if (End - Buffer >= 200) + Scale = (End - Buffer) / 100; + + for (; Buffer < End; Buffer += ToUpdate, Offset += ToUpdate) { + ToUpdate = MIN((UINT64)(End - Buffer), SectorSize); + Print (L" \rUpdating, %d%%", 100 - (End - Buffer) / Scale); + Status = SpiFlashUpdateBlock (Offset, Align, ToUpdate, Buffer, TmpBuf, SectorSize); + + if (EFI_ERROR (Status)) { + DEBUG((DEBUG_ERROR, "SpiFlash: Error while updating\n")); + break; + } + } + + Print(L"\n"); + FreePool (TmpBuf); + + return Status; +} + +UNI_NOR_FLASH_PROTOCOL gUniNorFlash = { + GetSize, + Erase, + Write, + Read, + Update +}; + +#if 0 +#define maxest_sector 4 +static UINT32 pread32[maxest_sector * 4096 + 64]; +static UINT32 pwrite32[maxest_sector * 4096 + 64]; +#define FLASH_SKIP_LBA 0x100 /* About 1M space skip */ + +static RETURN_STATUS SNOR_STRESS_RANDOM_TEST(UINT32 testEndLBA) +{ + UINT32 ret, j; + UINT32 testCount, testLBA = 0; + UINT32 testSecCount = 1; + + DEBUG ((DEBUG_ERROR, "---------%a %lx---------\n", __func__, testEndLBA)); + DEBUG ((DEBUG_ERROR, "---------%a---------\n", __func__)); + for (j = 0; j < testSecCount * (UINT32)g_nor->sectorSize / 4; j++) + pwrite32[j] = j + (0xFFFF0000 - j); + + for (testCount = 0; testCount < testEndLBA;) { + testLBA = testCount; + pwrite32[0] = testLBA; + ret = HAL_SNOR_OverWrite(g_nor, testLBA, testSecCount, pwrite32); + if (ret != testSecCount) { + return RETURN_DEVICE_ERROR; + } + pread32[0] = -1; + ret = HAL_SNOR_Read(g_nor, testLBA, testSecCount, pread32); + if (ret != testSecCount) { + return RETURN_DEVICE_ERROR; + } + for (j = 0; j < testSecCount * (UINT32)g_nor->sectorSize / 4; j++) { + if (pwrite32[j] != pread32[j]) { + DEBUG ((DEBUG_ERROR, + "check not match:row=%lx, num=%lx, write=%lx, read=%lx %lx %lx %lx\n", + testLBA, j, pwrite32[j], pread32[j], pread32[j + 1], pread32[j + 2], pread32[j - 1])); + while (1) { + ; + } + } + } + DEBUG ((DEBUG_ERROR, "testCount= %lx testLBA= %lx\n", testCount, testLBA)); + testCount += testSecCount; + } + DEBUG ((DEBUG_ERROR, "---------%a SUCCESS---------\n", __func__)); + + return RETURN_SUCCESS; +} +#endif + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +STATIC +VOID +EFIAPI +NorVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // Convert SPI device description + EfiConvertPointer (0, (VOID**)&g_nor->spi->instance); + EfiConvertPointer (0, (VOID**)&g_nor->spi->CruBase); + EfiConvertPointer (0, (VOID**)&g_nor->spi); + EfiConvertPointer (0, (VOID**)&g_nor->info); + EfiConvertPointer (0, (VOID**)&g_nor); + + return; +} + + +EFI_STATUS +EFIAPI InitializeFlash ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable) +{ + EFI_STATUS Status = RETURN_SUCCESS; + + g_spi = AllocateRuntimeZeroPool (sizeof (struct HAL_FSPI_HOST)); + g_nor = AllocateRuntimeZeroPool (sizeof (struct SPI_NOR)); + if (g_spi == NULL || g_nor == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + g_spi->instance = (struct FSPI_REG *)FixedPcdGet32(FspiBaseAddr); + g_spi->CruBase = (UINT32 *)FixedPcdGet32(CruBaseAddr); + + NorFspiIomux(); + HAL_FSPI_Init(g_spi); + g_nor->spi = g_spi; + g_nor->spi->mode = HAL_SPI_MODE_3; + g_nor->spi->mode |= (HAL_SPI_TX_QUAD | HAL_SPI_RX_QUAD); + Status = HAL_SNOR_Init(g_nor); + + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gUniNorFlashProtocolGuid, + EFI_NATIVE_INTERFACE, + &gUniNorFlash); + if(EFI_SUCCESS != Status) + { + DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:Install Protocol Interface %r!\n", __FUNCTION__,__LINE__,Status)); + } + + Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + NorVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mNorVirtualAddrChangeEvent); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to register VA change event\n", __FUNCTION__)); + goto ErrorSetMemAttr; + } + + return Status; +ErrorSetMemAttr: + gBS->UninstallProtocolInterface (gImageHandle, + &gUniNorFlashProtocolGuid, + NULL); + + FreePool (g_nor); + FreePool (g_spi); + + return Status; + +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf new file mode 100644 index 0000000..0e37f34 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf @@ -0,0 +1,61 @@ +#/** @file +# +# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-3-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = NorFlashDxe + FILE_GUID = ce7de226-ae7c-11ec-a154-f42a7dcb925d + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeFlash + +[Sources.common] + NorFlashDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiDriverEntryPoint + DebugLib + BaseLib + DebugLib + IoLib + SerialPortLib + ArmLib + CacheMaintenanceLib + UefiLib + PrintLib + PcdLib + TimerLib + DxeServicesTableLib + FspiLib + RockchipPlatformLib + + HobLib + UefiRuntimeLib + BaseMemoryLib + DevicePathLib + MemoryAllocationLib + UefiRuntimeServicesTableLib + +[Guids] + gEfiEventVirtualAddressChangeGuid +[Protocols] + gUniNorFlashProtocolGuid + +[Pcd] + gRockchipTokenSpaceGuid.FspiBaseAddr + gRockchipTokenSpaceGuid.CruBaseAddr + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/ComponentName.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/ComponentName.c new file mode 100644 index 0000000..7e690a7 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/ComponentName.c @@ -0,0 +1,219 @@ +/** @file +UEFI Component Name and Name2 protocol for OHCI driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "Ohci.h" + + +// +// EFI Component Name Protocol +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gOhciComponentName = { + OhciComponentNameGetDriverName, + OhciComponentNameGetControllerName, + "eng" +}; + +// +// EFI Component Name 2 Protocol +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gOhciComponentName2 = { + (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) OhciComponentNameGetDriverName, + (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) OhciComponentNameGetControllerName, + "en" +}; + + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mOhciDriverNameTable[] = { + { "eng;en", L"Usb Ohci Driver" }, + { NULL, NULL } +}; + + +/** + Retrieves a Unicode string that is the user readable name of the driver. + + This function retrieves the user readable name of a driver in the form of a + Unicode string. If the driver specified by This has a user readable name in + the language specified by Language, then a pointer to the driver name is + returned in DriverName, and EFI_SUCCESS is returned. If the driver specified + by This does not support the language specified by Language, + then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified + in RFC 4646 or ISO 639-2 language code format. + + @param DriverName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + driver specified by This in the language + specified by Language. + + @retval EFI_SUCCESS The Unicode string for the Driver specified by + This and the language specified by Language was + returned in DriverName. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER DriverName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +OhciComponentNameGetDriverName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ) +{ + return LookupUnicodeString2 ( + Language, + This->SupportedLanguages, + mOhciDriverNameTable, + DriverName, + (BOOLEAN)(This == &gOhciComponentName) + ); +} + +/** + Retrieves a Unicode string that is the user readable name of the controller + that is being managed by a driver. + + This function retrieves the user readable name of the controller specified by + ControllerHandle and ChildHandle in the form of a Unicode string. If the + driver specified by This has a user readable name in the language specified by + Language, then a pointer to the controller name is returned in ControllerName, + and EFI_SUCCESS is returned. If the driver specified by This is not currently + managing the controller specified by ControllerHandle and ChildHandle, + then EFI_UNSUPPORTED is returned. If the driver specified by This does not + support the language specified by Language, then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param ControllerHandle[in] The handle of a controller that the driver + specified by This is managing. This handle + specifies the controller whose name is to be + returned. + + @param ChildHandle[in] The handle of the child controller to retrieve + the name of. This is an optional parameter that + may be NULL. It will be NULL for device + drivers. It will also be NULL for a bus drivers + that wish to retrieve the name of the bus + controller. It will not be NULL for a bus + driver that wishes to retrieve the name of a + child controller. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified in + RFC 4646 or ISO 639-2 language code format. + + @param ControllerName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + controller specified by ControllerHandle and + ChildHandle in the language specified by + Language from the point of view of the driver + specified by This. + + @retval EFI_SUCCESS The Unicode string for the user readable name in + the language specified by Language for the + driver specified by This was returned in + DriverName. + + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid + EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER ControllerName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This is not currently + managing the controller specified by + ControllerHandle and ChildHandle. + + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +OhciComponentNameGetControllerName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ) +{ + EFI_STATUS Status; + USB_OHCI_HC_DEV *OhciDev; + EFI_USB_HC_PROTOCOL *UsbHc; + + // + // This is a device driver, so ChildHandle must be NULL. + // + if (ChildHandle != NULL) { + return EFI_UNSUPPORTED; + } + // + // Make sure this driver is currently managing ControllerHandle + // + Status = EfiTestManagedDevice ( + ControllerHandle, + gOhciDriverBinding.DriverBindingHandle, + &gOhciDeviceProtocolGuid + ); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Get the device context + // + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiUsbHcProtocolGuid, + (VOID **) &UsbHc, + gOhciDriverBinding.DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + return Status; + } + + OhciDev = USB_OHCI_HC_DEV_FROM_THIS (UsbHc); + + return LookupUnicodeString2 ( + Language, + This->SupportedLanguages, + OhciDev->ControllerNameTable, + ControllerName, + (BOOLEAN)(This == &gOhciComponentName) + ); + +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/ComponentName.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/ComponentName.h new file mode 100644 index 0000000..c54cd63 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/ComponentName.h @@ -0,0 +1,141 @@ +/** @file +This file contains the delarations for componet name routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _COMPONENT_NAME_H_ +#define _COMPONENT_NAME_H_ + + +/** + Retrieves a Unicode string that is the user readable name of the driver. + + This function retrieves the user readable name of a driver in the form of a + Unicode string. If the driver specified by This has a user readable name in + the language specified by Language, then a pointer to the driver name is + returned in DriverName, and EFI_SUCCESS is returned. If the driver specified + by This does not support the language specified by Language, + then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified + in RFC 4646 or ISO 639-2 language code format. + + @param DriverName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + driver specified by This in the language + specified by Language. + + @retval EFI_SUCCESS The Unicode string for the Driver specified by + This and the language specified by Language was + returned in DriverName. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER DriverName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +OhciComponentNameGetDriverName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + + +/** + Retrieves a Unicode string that is the user readable name of the controller + that is being managed by a driver. + + This function retrieves the user readable name of the controller specified by + ControllerHandle and ChildHandle in the form of a Unicode string. If the + driver specified by This has a user readable name in the language specified by + Language, then a pointer to the controller name is returned in ControllerName, + and EFI_SUCCESS is returned. If the driver specified by This is not currently + managing the controller specified by ControllerHandle and ChildHandle, + then EFI_UNSUPPORTED is returned. If the driver specified by This does not + support the language specified by Language, then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param ControllerHandle[in] The handle of a controller that the driver + specified by This is managing. This handle + specifies the controller whose name is to be + returned. + + @param ChildHandle[in] The handle of the child controller to retrieve + the name of. This is an optional parameter that + may be NULL. It will be NULL for device + drivers. It will also be NULL for a bus drivers + that wish to retrieve the name of the bus + controller. It will not be NULL for a bus + driver that wishes to retrieve the name of a + child controller. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified in + RFC 4646 or ISO 639-2 language code format. + + @param ControllerName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + controller specified by ControllerHandle and + ChildHandle in the language specified by + Language from the point of view of the driver + specified by This. + + @retval EFI_SUCCESS The Unicode string for the user readable name in + the language specified by Language for the + driver specified by This was returned in + DriverName. + + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid + EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER ControllerName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This is not currently + managing the controller specified by + ControllerHandle and ChildHandle. + + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +OhciComponentNameGetControllerName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +#endif + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Descriptor.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Descriptor.h new file mode 100644 index 0000000..14a619b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Descriptor.h @@ -0,0 +1,132 @@ +/** @file +This file contains the descriptor definination of OHCI spec + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + +#ifndef _DESCRIPTOR_H +#define _DESCRIPTOR_H + +#define ED_FUNC_ADD 0x0001 +#define ED_ENDPT_NUM 0x0002 +#define ED_DIR 0x0004 +#define ED_SPEED 0x0008 +#define ED_SKIP 0x0010 +#define ED_FORMAT 0x0020 +#define ED_MAX_PACKET 0x0040 +#define ED_TDTAIL_PTR 0x0080 +#define ED_HALTED 0x0100 +#define ED_DTTOGGLE 0x0200 +#define ED_TDHEAD_PTR 0x0400 +#define ED_NEXT_EDPTR 0x0800 +#define ED_PDATA 0x1000 +#define ED_ZERO 0x2000 + +#define TD_BUFFER_ROUND 0x0001 +#define TD_DIR_PID 0x0002 +#define TD_DELAY_INT 0x0004 +#define TD_DT_TOGGLE 0x0008 +#define TD_ERROR_CNT 0x0010 +#define TD_COND_CODE 0x0020 +#define TD_CURR_BUFFER_PTR 0x0040 +#define TD_NEXT_PTR 0x0080 +#define TD_BUFFER_END_PTR 0x0100 +#define TD_PDATA 0x0200 + +#define ED_FROM_TD_DIR 0x0 +#define ED_OUT_DIR 0x1 +#define ED_IN_DIR 0x2 +#define ED_FROM_TD_ALSO_DIR 0x3 + +#define TD_SETUP_PID 0x00 +#define TD_OUT_PID 0x01 +#define TD_IN_PID 0x02 +#define TD_NODATA_PID 0x03 + +#define HI_SPEED 0 +#define LO_SPEED 1 + +#define TD_NO_ERROR 0x00 +#define TD_CRC_ERROR 0x01 +#define TD_BITSTUFFING_ERROR 0x02 +#define TD_TOGGLE_ERROR 0x03 +#define TD_DEVICE_STALL 0x04 +#define TD_NO_RESPONSE 0x05 +#define TD_PIDCHK_FAIL 0x06 +#define TD_PID_UNEXPECTED 0x07 +#define TD_DATA_OVERRUN 0x08 +#define TD_DATA_UNDERRUN 0x09 +#define TD_BUFFER_OVERRUN 0x0C +#define TD_BUFFER_UNDERRUN 0x0D +#define TD_TOBE_PROCESSED 0x0E +#define TD_TOBE_PROCESSED_2 0x0F + +#define TD_NO_DELAY 0x7 + +#define TD_INT 0x1 +#define TD_CTL 0x2 +#define TD_BLK 0x3 + +typedef struct { + UINT32 Reserved:18; + UINT32 BufferRounding:1; + UINT32 DirPID:2; + UINT32 DelayInterrupt:3; + UINT32 DataToggle:2; + UINT32 ErrorCount:2; + UINT32 ConditionCode:4; +} TD_DESCRIPTOR_WORD0; + +typedef struct _TD_DESCRIPTOR { + TD_DESCRIPTOR_WORD0 Word0; + UINT32 CurrBufferPointer; // 32-bit Physical Address of buffer + UINT32 NextTD; // 32-bit Physical Address of TD_DESCRIPTOR + UINT32 BufferEndPointer; // 32-bit Physical Address of buffer + UINT32 NextTDPointer; // 32-bit Physical Address of TD_DESCRIPTOR + UINT32 DataBuffer; // 32-bit Physical Address of buffer + UINT32 ActualSendLength; + UINT32 Reserved; +} TD_DESCRIPTOR; + +typedef struct { + UINT32 FunctionAddress:7; + UINT32 EndPointNum:4; + UINT32 Direction:2; + UINT32 Speed:1; + UINT32 Skip:1; + UINT32 Format:1; + UINT32 MaxPacketSize:11; + UINT32 FreeSpace:5; +} ED_DESCRIPTOR_WORD0; + +typedef struct { + UINT32 Halted:1; + UINT32 ToggleCarry:1; + UINT32 Zero:2; + UINT32 TdHeadPointer:28; +} ED_DESCRIPTOR_WORD2; + +typedef struct _ED_DESCRIPTOR { + ED_DESCRIPTOR_WORD0 Word0; + UINT32 TdTailPointer; // 32-bit Physical Address of TD_DESCRIPTOR + ED_DESCRIPTOR_WORD2 Word2; + UINT32 NextED; // 32-bit Physical Address of ED_DESCRIPTOR +} ED_DESCRIPTOR; + +#define TD_PTR(p) ((TD_DESCRIPTOR *)(UINTN)((p) << 4)) +#define ED_PTR(p) ((ED_DESCRIPTOR *)(UINTN)((p) << 4)) +#define RIGHT_SHIFT_4(p) ((UINT32)(p) >> 4) + +typedef enum { + CONTROL_LIST, + BULK_LIST, + INTERRUPT_LIST, + ISOCHRONOUS_LIST +} DESCRIPTOR_LIST_TYPE; + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Ohci.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Ohci.c new file mode 100644 index 0000000..46956bb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Ohci.c @@ -0,0 +1,2416 @@ +/** @file +This file contains the implementation of Usb Hc Protocol. + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "Ohci.h" + +STATIC OHCI_DEVICE_PATH OhciDevicePathProtocol = { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(OFFSET_OF (OHCI_DEVICE_PATH, End)), + (UINT8)(OFFSET_OF (OHCI_DEVICE_PATH, End) >> 8), + }, + }, + EFI_CALLER_ID_GUID + }, + 0, // Instance + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof(EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } +}; + +/** + Provides software reset for the USB host controller. + + @param This This EFI_USB_HC_PROTOCOL instance. + @param Attributes A bit mask of the reset operation to perform. + + @retval EFI_SUCCESS The reset operation succeeded. + @retval EFI_INVALID_PARAMETER Attributes is not valid. + @retval EFI_UNSUPPOURTED The type of reset specified by Attributes is + not currently supported by the host controller. + @retval EFI_DEVICE_ERROR Host controller isn't halted to reset. + +**/ +EFI_STATUS +EFIAPI +OhciReset ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT16 Attributes + ) +{ + EFI_STATUS Status; + USB_OHCI_HC_DEV *Ohc; + UINT8 Index; + UINT8 NumOfPorts; + UINT32 PowerOnGoodTime; + UINT32 Data32; + BOOLEAN Flag = FALSE; + + if ((Attributes & ~(EFI_USB_HC_RESET_GLOBAL | EFI_USB_HC_RESET_HOST_CONTROLLER)) != 0) { + return EFI_INVALID_PARAMETER; + } + + Status = EFI_SUCCESS; + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + if ((Attributes & EFI_USB_HC_RESET_HOST_CONTROLLER) != 0) { + gBS->Stall (50 * 1000); + Status = OhciSetHcCommandStatus (Ohc, HC_RESET, HC_RESET); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + gBS->Stall (50 * 1000); + // + // Wait for host controller reset. + // + PowerOnGoodTime = 50; + do { + gBS->Stall (1 * 1000); + Data32 = OhciGetOperationalReg (Ohc, HC_COMMAND_STATUS ); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + if ((Data32 & HC_RESET) == 0) { + Flag = TRUE; + break; + } + }while(PowerOnGoodTime--); + if (!Flag){ + return EFI_DEVICE_ERROR; + } + } + OhciFreeIntTransferMemory (Ohc); + Status = OhciInitializeInterruptList (Ohc); + OhciSetFrameInterval (Ohc, FRAME_INTERVAL, 0x2edf); + if ((Attributes & EFI_USB_HC_RESET_GLOBAL) != 0) { + Status = OhciSetHcControl (Ohc, HC_FUNCTIONAL_STATE, HC_STATE_RESET); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + gBS->Stall (50 * 1000); + } + // + // Initialize host controller operational registers + // + OhciSetFrameInterval (Ohc, FS_LARGEST_DATA_PACKET, 0x2778); + OhciSetFrameInterval (Ohc, FRAME_INTERVAL, 0x2edf); + OhciSetPeriodicStart (Ohc, 0x2a2f); + OhciSetHcControl (Ohc, CONTROL_BULK_RATIO, 0x3); + OhciSetHcCommandStatus (Ohc, CONTROL_LIST_FILLED | BULK_LIST_FILLED, 0); + OhciSetRootHubDescriptor (Ohc, RH_PSWITCH_MODE, 0); + OhciSetRootHubDescriptor (Ohc, RH_NO_PSWITCH | RH_NOC_PROT, 1); + //OhciSetRootHubDescriptor (Hc, RH_PSWITCH_MODE | RH_NO_PSWITCH, 0); + //OhciSetRootHubDescriptor (Hc, RH_PSWITCH_MODE | RH_NOC_PROT, 1); + + OhciSetRootHubDescriptor (Ohc, RH_DEV_REMOVABLE, 0); + OhciSetRootHubDescriptor (Ohc, RH_PORT_PWR_CTRL_MASK, 0xffff); + OhciSetRootHubStatus (Ohc, RH_LOCAL_PSTAT_CHANGE); + OhciSetRootHubPortStatus (Ohc, 0, RH_SET_PORT_POWER); + OhciGetRootHubNumOfPorts (This, &NumOfPorts); + for (Index = 0; Index < NumOfPorts; Index++) { + if (!EFI_ERROR (OhciSetRootHubPortFeature (This, Index, EfiUsbPortReset))) { + gBS->Stall (200 * 1000); + OhciClearRootHubPortFeature (This, Index, EfiUsbPortReset); + gBS->Stall (1000); + OhciSetRootHubPortFeature (This, Index, EfiUsbPortEnable); + gBS->Stall (1000); + } + } + OhciSetMemoryPointer (Ohc, HC_HCCA, Ohc->HccaMemoryBlock); + OhciSetMemoryPointer (Ohc, HC_CONTROL_HEAD, NULL); + OhciSetMemoryPointer (Ohc, HC_BULK_HEAD, NULL); + OhciSetHcControl (Ohc, PERIODIC_ENABLE | CONTROL_ENABLE | BULK_ENABLE, 1); /*ISOCHRONOUS_ENABLE*/ + OhciSetHcControl (Ohc, HC_FUNCTIONAL_STATE, HC_STATE_OPERATIONAL); + gBS->Stall (50*1000); + // + // Wait till first SOF occurs, and then clear it + // + while (OhciGetHcInterruptStatus (Ohc, START_OF_FRAME) == 0); + OhciClearInterruptStatus (Ohc, START_OF_FRAME); + gBS->Stall (1000); + + return Status; +} + +/** + Retrieve the current state of the USB host controller. + + @param This This EFI_USB_HC_PROTOCOL instance. + @param State Variable to return the current host controller + state. + + @retval EFI_SUCCESS Host controller state was returned in State. + @retval EFI_INVALID_PARAMETER State is NULL. + @retval EFI_DEVICE_ERROR An error was encountered while attempting to + retrieve the host controller's current state. + +**/ + +EFI_STATUS +EFIAPI +OhciGetState ( + IN EFI_USB_HC_PROTOCOL *This, + OUT EFI_USB_HC_STATE *State + ) +{ + USB_OHCI_HC_DEV *Ohc; + UINT32 FuncState; + + if (State == NULL) { + return EFI_INVALID_PARAMETER; + } + + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + FuncState = OhciGetHcControl (Ohc, HC_FUNCTIONAL_STATE); + + switch (FuncState) { + case HC_STATE_RESET: + case HC_STATE_RESUME: + *State = EfiUsbHcStateHalt; + break; + + case HC_STATE_OPERATIONAL: + *State = EfiUsbHcStateOperational; + break; + + case HC_STATE_SUSPEND: + *State = EfiUsbHcStateSuspend; + break; + + default: + ASSERT (FALSE); + } + return EFI_SUCCESS; +} + +/** + Sets the USB host controller to a specific state. + + @param This This EFI_USB_HC_PROTOCOL instance. + @param State The state of the host controller that will be set. + + @retval EFI_SUCCESS The USB host controller was successfully placed + in the state specified by State. + @retval EFI_INVALID_PARAMETER State is invalid. + @retval EFI_DEVICE_ERROR Failed to set the state due to device error. + +**/ + +EFI_STATUS +EFIAPI +OhciSetState( + IN EFI_USB_HC_PROTOCOL *This, + IN EFI_USB_HC_STATE State + ) +{ + EFI_STATUS Status; + USB_OHCI_HC_DEV *Ohc; + + Ohc = USB_OHCI_HC_DEV_FROM_THIS(This); + + switch (State) { + case EfiUsbHcStateHalt: + Status = OhciSetHcControl (Ohc, HC_FUNCTIONAL_STATE, HC_STATE_RESET); + break; + + case EfiUsbHcStateOperational: + Status = OhciSetHcControl (Ohc, HC_FUNCTIONAL_STATE, HC_STATE_OPERATIONAL); + break; + + case EfiUsbHcStateSuspend: + Status = OhciSetHcControl (Ohc, HC_FUNCTIONAL_STATE, HC_STATE_SUSPEND); + break; + + default: + Status = EFI_INVALID_PARAMETER; + } + + gBS->Stall (1000); + + return Status; +} + +/** + + Submits control transfer to a target USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param IsSlowDevice Indicates whether the target device is slow device + or full-speed device. + @param MaxPaketLength Indicates the maximum packet size that the + default control transfer endpoint is capable of + sending or receiving. + @param Request A pointer to the USB device request that will be sent + to the USB device. + @param TransferDirection Specifies the data direction for the transfer. + There are three values available, DataIn, DataOut + and NoData. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param DataLength Indicates the size, in bytes, of the data buffer + specified by Data. + @param TimeOut Indicates the maximum time, in microseconds, + which the transfer is allowed to complete. + @param TransferResult A pointer to the detailed result information generated + by this control transfer. + + @retval EFI_SUCCESS The control transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The control transfer could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The control transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The control transfer failed due to host controller or device error. + Caller should check TranferResult for detailed error information. + +--*/ + + +EFI_STATUS +EFIAPI +OhciControlTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxPacketLength, + IN EFI_USB_DEVICE_REQUEST *Request, + IN EFI_USB_DATA_DIRECTION TransferDirection, + IN OUT VOID *Data OPTIONAL, + IN OUT UINTN *DataLength OPTIONAL, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ) +{ + USB_OHCI_HC_DEV *Ohc; + ED_DESCRIPTOR *HeadEd; + ED_DESCRIPTOR *Ed; + TD_DESCRIPTOR *HeadTd; + TD_DESCRIPTOR *SetupTd; + TD_DESCRIPTOR *DataTd; + TD_DESCRIPTOR *StatusTd; + TD_DESCRIPTOR *EmptyTd; + EFI_STATUS Status; + UINT32 DataPidDir; + UINT32 StatusPidDir; + UINTN TimeCount; + OHCI_ED_RESULT EdResult; + + DMA_MAP_OPERATION MapOp; + + UINTN ActualSendLength; + UINTN LeftLength; + UINT8 DataToggle; + + VOID *ReqMapping = NULL; + UINTN ReqMapLength = 0; + EFI_PHYSICAL_ADDRESS ReqMapPhyAddr = 0; + + VOID *DataMapping = NULL; + UINTN DataMapLength = 0; + EFI_PHYSICAL_ADDRESS DataMapPhyAddr = 0; + + HeadTd = NULL; + DataTd = NULL; + + if ((TransferDirection != EfiUsbDataOut && TransferDirection != EfiUsbDataIn && + TransferDirection != EfiUsbNoData) || + Request == NULL || DataLength == NULL || TransferResult == NULL || + (TransferDirection == EfiUsbNoData && (*DataLength != 0 || Data != NULL)) || + (TransferDirection != EfiUsbNoData && (*DataLength == 0 || Data == NULL)) || + (IsSlowDevice && MaxPacketLength != 8) || + (MaxPacketLength != 8 && MaxPacketLength != 16 && + MaxPacketLength != 32 && MaxPacketLength != 64)) { + return EFI_INVALID_PARAMETER; + } + + if (*DataLength > MAX_BYTES_PER_TD) { + DEBUG ((DEBUG_ERROR, "OhciControlTransfer: Request data size is too large\r\n")); + return EFI_INVALID_PARAMETER; + } + + Ohc = USB_OHCI_HC_DEV_FROM_THIS(This); + + if (TransferDirection == EfiUsbDataIn) { + DataPidDir = TD_IN_PID; + StatusPidDir = TD_OUT_PID; + } else { + DataPidDir = TD_OUT_PID; + StatusPidDir = TD_IN_PID; + } + + Status = OhciSetHcControl (Ohc, CONTROL_ENABLE, 0); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: fail to disable CONTROL_ENABLE\r\n")); + *TransferResult = EFI_USB_ERR_SYSTEM; + return EFI_DEVICE_ERROR; + } + Status = OhciSetHcCommandStatus (Ohc, CONTROL_LIST_FILLED, 0); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: fail to disable CONTROL_LIST_FILLED\r\n")); + *TransferResult = EFI_USB_ERR_SYSTEM; + return EFI_DEVICE_ERROR; + } + gBS->Stall(20 * 1000); + + OhciSetMemoryPointer (Ohc, HC_CONTROL_HEAD, NULL); + Ed = OhciCreateED (Ohc); + if (Ed == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_INFO, "OhciControlTransfer: Fail to allocate ED buffer\r\n")); + goto CTRL_EXIT; + } + OhciSetEDField (Ed, ED_SKIP, 1); + OhciSetEDField (Ed, ED_FUNC_ADD, DeviceAddress); + OhciSetEDField (Ed, ED_ENDPT_NUM, 0); + OhciSetEDField (Ed, ED_DIR, ED_FROM_TD_DIR); + OhciSetEDField (Ed, ED_SPEED, IsSlowDevice); + OhciSetEDField (Ed, ED_FORMAT | ED_HALTED | ED_DTTOGGLE, 0); + OhciSetEDField (Ed, ED_MAX_PACKET, MaxPacketLength); + OhciSetEDField (Ed, ED_PDATA, 0); + OhciSetEDField (Ed, ED_ZERO, 0); + OhciSetEDField (Ed, ED_TDHEAD_PTR, 0); + OhciSetEDField (Ed, ED_TDTAIL_PTR, 0); + OhciSetEDField (Ed, ED_NEXT_EDPTR, 0); + HeadEd = OhciAttachEDToList (Ohc, CONTROL_LIST, Ed, NULL); + // + // Setup Stage + // + if(Request != NULL) { + ReqMapLength = sizeof(EFI_USB_DEVICE_REQUEST); + MapOp = MapOperationBusMasterRead; + Status = DmaMap (MapOp, (UINT8 *)Request, &ReqMapLength, &ReqMapPhyAddr, &ReqMapping); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: Fail to Map Request Buffer\r\n")); + goto FREE_ED_BUFF; + } + } + SetupTd = OhciCreateTD (Ohc); + if (SetupTd == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_INFO, "OhciControlTransfer: Fail to allocate Setup TD buffer\r\n")); + goto UNMAP_SETUP_BUFF; + } + HeadTd = SetupTd; + OhciSetTDField (SetupTd, TD_PDATA, 0); + OhciSetTDField (SetupTd, TD_BUFFER_ROUND, 1); + OhciSetTDField (SetupTd, TD_DIR_PID, TD_SETUP_PID); + OhciSetTDField (SetupTd, TD_DELAY_INT, TD_NO_DELAY); + OhciSetTDField (SetupTd, TD_DT_TOGGLE, 2); + OhciSetTDField (SetupTd, TD_ERROR_CNT, 0); + OhciSetTDField (SetupTd, TD_COND_CODE, TD_TOBE_PROCESSED); + OhciSetTDField (SetupTd, TD_CURR_BUFFER_PTR, (UINT32)ReqMapPhyAddr); + OhciSetTDField (SetupTd, TD_NEXT_PTR, 0); + OhciSetTDField (SetupTd, TD_BUFFER_END_PTR, (UINT32)(ReqMapPhyAddr + sizeof (EFI_USB_DEVICE_REQUEST) - 1)); + SetupTd->ActualSendLength = sizeof (EFI_USB_DEVICE_REQUEST); + SetupTd->DataBuffer = (UINT32)ReqMapPhyAddr; + SetupTd->NextTDPointer = 0; + + if (TransferDirection == EfiUsbDataIn) { + MapOp = MapOperationBusMasterWrite; + } else { + MapOp = MapOperationBusMasterRead; + } + DataMapLength = *DataLength; + if ((Data != NULL) && (DataMapLength != 0)) { + Status = DmaMap (MapOp, Data, &DataMapLength, &DataMapPhyAddr, &DataMapping); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: Fail To Map Data Buffer\r\n")); + goto FREE_TD_BUFF; + } + } + // + //Data Stage + // + LeftLength = DataMapLength; + ActualSendLength = DataMapLength; + DataToggle = 1; + while (LeftLength > 0) { + ActualSendLength = LeftLength; + if (LeftLength > MaxPacketLength) { + ActualSendLength = MaxPacketLength; + } + DataTd = OhciCreateTD (Ohc); + if (DataTd == NULL) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: Fail to allocate buffer for Data Stage TD\r\n")); + Status = EFI_OUT_OF_RESOURCES; + goto UNMAP_DATA_BUFF; + } + OhciSetTDField (DataTd, TD_PDATA, 0); + OhciSetTDField (DataTd, TD_BUFFER_ROUND, 1); + OhciSetTDField (DataTd, TD_DIR_PID, DataPidDir); + OhciSetTDField (DataTd, TD_DELAY_INT, TD_NO_DELAY); + OhciSetTDField (DataTd, TD_DT_TOGGLE, DataToggle); + OhciSetTDField (DataTd, TD_ERROR_CNT, 0); + OhciSetTDField (DataTd, TD_COND_CODE, TD_TOBE_PROCESSED); + OhciSetTDField (DataTd, TD_CURR_BUFFER_PTR, (UINT32) DataMapPhyAddr); + OhciSetTDField (DataTd, TD_BUFFER_END_PTR, (UINT32)(DataMapPhyAddr + ActualSendLength - 1)); + OhciSetTDField (DataTd, TD_NEXT_PTR, 0); + DataTd->ActualSendLength = (UINT32)ActualSendLength; + DataTd->DataBuffer = (UINT32)DataMapPhyAddr; + DataTd->NextTDPointer = 0; + OhciLinkTD (HeadTd, DataTd); + DataToggle ^= 1; + DataMapPhyAddr += ActualSendLength; + LeftLength -= ActualSendLength; + } + // + // Status Stage + // + StatusTd = OhciCreateTD (Ohc); + if (StatusTd == NULL) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: Fail to allocate buffer for Status Stage TD\r\n")); + Status = EFI_OUT_OF_RESOURCES; + goto UNMAP_DATA_BUFF; + } + OhciSetTDField (StatusTd, TD_PDATA, 0); + OhciSetTDField (StatusTd, TD_BUFFER_ROUND, 1); + OhciSetTDField (StatusTd, TD_DIR_PID, StatusPidDir); + OhciSetTDField (StatusTd, TD_DELAY_INT, 7); + OhciSetTDField (StatusTd, TD_DT_TOGGLE, 3); + OhciSetTDField (StatusTd, TD_ERROR_CNT, 0); + OhciSetTDField (StatusTd, TD_COND_CODE, TD_TOBE_PROCESSED); + OhciSetTDField (StatusTd, TD_CURR_BUFFER_PTR, 0); + OhciSetTDField (StatusTd, TD_NEXT_PTR, 0); + OhciSetTDField (StatusTd, TD_BUFFER_END_PTR, 0); + StatusTd->ActualSendLength = 0; + StatusTd->DataBuffer = 0; + StatusTd->NextTDPointer = 0; + OhciLinkTD (HeadTd, StatusTd); + // + // Empty Stage + // + EmptyTd = OhciCreateTD (Ohc); + if (EmptyTd == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto UNMAP_DATA_BUFF; + } + OhciSetTDField (EmptyTd, TD_PDATA, 0); + OhciSetTDField (EmptyTd, TD_BUFFER_ROUND, 0); + OhciSetTDField (EmptyTd, TD_DIR_PID, 0); + OhciSetTDField (EmptyTd, TD_DELAY_INT, 0); + //OhciSetTDField (EmptyTd, TD_DT_TOGGLE, CurrentToggle); + EmptyTd->Word0.DataToggle = 0; + OhciSetTDField (EmptyTd, TD_ERROR_CNT, 0); + OhciSetTDField (EmptyTd, TD_COND_CODE, 0); + OhciSetTDField (EmptyTd, TD_CURR_BUFFER_PTR, 0); + OhciSetTDField (EmptyTd, TD_BUFFER_END_PTR, 0); + OhciSetTDField (EmptyTd, TD_NEXT_PTR, 0); + EmptyTd->ActualSendLength = 0; + EmptyTd->DataBuffer = 0; + EmptyTd->NextTDPointer = 0; + OhciLinkTD (HeadTd, EmptyTd); + Ed->TdTailPointer = (UINT32)(UINTN)EmptyTd; + OhciAttachTDListToED (Ed, HeadTd); + // + // For debugging, dump ED & TD buffer befor transferring + // + // + //OhciDumpEdTdInfo (Ohc, Ed, HeadTd, TRUE); + // + OhciSetEDField (Ed, ED_SKIP, 0); + Status = OhciSetHcControl (Ohc, CONTROL_ENABLE, 1); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: fail to enable CONTROL_ENABLE\r\n")); + *TransferResult = EFI_USB_ERR_SYSTEM; + Status = EFI_DEVICE_ERROR; + goto UNMAP_DATA_BUFF; + } + Status = OhciSetHcCommandStatus (Ohc, CONTROL_LIST_FILLED, 1); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: fail to enable CONTROL_LIST_FILLED\r\n")); + *TransferResult = EFI_USB_ERR_SYSTEM; + Status = EFI_DEVICE_ERROR; + goto UNMAP_DATA_BUFF; + } + gBS->Stall(20 * 1000); + + + TimeCount = 0; + Status = CheckIfDone (Ohc, CONTROL_LIST, Ed, HeadTd, &EdResult); + + while (Status == EFI_NOT_READY && TimeCount <= TimeOut) { + gBS->Stall (1000); + TimeCount++; + Status = CheckIfDone (Ohc, CONTROL_LIST, Ed, HeadTd, &EdResult); + } + // + // For debugging, dump ED & TD buffer after transferring + // + //OhciDumpEdTdInfo (Ohc, Ed, HeadTd, FALSE); + // + *TransferResult = ConvertErrorCode (EdResult.ErrorCode); + + if (EdResult.ErrorCode != TD_NO_ERROR) { + if (EdResult.ErrorCode == TD_TOBE_PROCESSED) { + DEBUG ((DEBUG_ERROR, "Control pipe timeout, > %d mS\r\n", TimeOut)); + } else { + DEBUG ((DEBUG_ERROR, "Control pipe broken\r\n")); + } + *DataLength = 0; + } else { + DEBUG ((DEBUG_INFO, "Control transfer successed\r\n")); + } + +UNMAP_DATA_BUFF: + OhciSetEDField (Ed, ED_SKIP, 1); + if (HeadEd == Ed) { + OhciSetMemoryPointer (Ohc, HC_CONTROL_HEAD, NULL); + } else { + HeadEd->NextED = Ed->NextED; + } + if(DataMapping != NULL) { + DmaUnmap(DataMapping); + } + +FREE_TD_BUFF: + while (HeadTd) { + DataTd = HeadTd; + HeadTd = (TD_DESCRIPTOR *)(UINTN)(HeadTd->NextTDPointer); + UsbHcFreeMem(Ohc->MemPool, DataTd, sizeof(TD_DESCRIPTOR)); + } + +UNMAP_SETUP_BUFF: + if(ReqMapping != NULL) { + DmaUnmap(ReqMapping); + } + +FREE_ED_BUFF: + UsbHcFreeMem(Ohc->MemPool, Ed, sizeof(ED_DESCRIPTOR)); + +CTRL_EXIT: + return Status; +} + +/** + + Submits bulk transfer to a bulk endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an + endpoint direction of the target USB device. + Each endpoint address supports data transfer in + one direction except the control endpoint + (whose default endpoint address is 0). + It is the caller's responsibility to make sure that + the EndPointAddress represents a bulk endpoint. + @param MaximumPacketLength Indicates the maximum packet size the target endpoint + is capable of sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param DataLength When input, indicates the size, in bytes, of the data buffer + specified by Data. When output, indicates the actually + transferred data size. + @param DataToggle A pointer to the data toggle value. On input, it indicates + the initial data toggle value the bulk transfer should adopt; + on output, it is updated to indicate the data toggle value + of the subsequent bulk transfer. + @param TimeOut Indicates the maximum time, in microseconds, which the + transfer is allowed to complete. + TransferResult A pointer to the detailed result information of the + bulk transfer. + + @retval EFI_SUCCESS The bulk transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The bulk transfer could not be submitted due to lack of resource. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The bulk transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The bulk transfer failed due to host controller or device error. + Caller should check TranferResult for detailed error information. + +**/ + + +EFI_STATUS +EFIAPI +OhciBulkTransfer( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaxPacketLength, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN OUT UINT8 *DataToggle, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ) +{ + USB_OHCI_HC_DEV *Ohc; + ED_DESCRIPTOR *HeadEd; + ED_DESCRIPTOR *Ed; + UINT32 DataPidDir; + TD_DESCRIPTOR *HeadTd; + TD_DESCRIPTOR *DataTd; + TD_DESCRIPTOR *EmptyTd; + EFI_STATUS Status; + UINT8 EndPointNum; + UINTN TimeCount; + OHCI_ED_RESULT EdResult; + + DMA_MAP_OPERATION MapOp; + VOID *Mapping; + UINTN MapLength; + EFI_PHYSICAL_ADDRESS MapPyhAddr; + UINTN LeftLength; + UINTN ActualSendLength; + BOOLEAN FirstTD; + + Mapping = NULL; + MapLength = 0; + MapPyhAddr = 0; + LeftLength = 0; + Status = EFI_SUCCESS; + + if (Data == NULL || DataLength == NULL || DataToggle == NULL || TransferResult == NULL || + *DataLength == 0 || (*DataToggle != 0 && *DataToggle != 1) || + (MaxPacketLength != 8 && MaxPacketLength != 16 && + MaxPacketLength != 32 && MaxPacketLength != 64)) { + return EFI_INVALID_PARAMETER; + } + + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + if ((EndPointAddress & 0x80) != 0) { + DataPidDir = TD_IN_PID; + MapOp = MapOperationBusMasterWrite; + } else { + DataPidDir = TD_OUT_PID; + MapOp = MapOperationBusMasterRead; + } + + EndPointNum = (EndPointAddress & 0xF); + EdResult.NextToggle = *DataToggle; + + Status = OhciSetHcControl (Ohc, BULK_ENABLE, 0); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: fail to disable BULK_ENABLE\r\n")); + *TransferResult = EFI_USB_ERR_SYSTEM; + return EFI_DEVICE_ERROR; + } + Status = OhciSetHcCommandStatus (Ohc, BULK_LIST_FILLED, 0); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciControlTransfer: fail to disable BULK_LIST_FILLED\r\n")); + *TransferResult = EFI_USB_ERR_SYSTEM; + return EFI_DEVICE_ERROR; + } + gBS->Stall(20 * 1000); + + OhciSetMemoryPointer (Ohc, HC_BULK_HEAD, NULL); + + Ed = OhciCreateED (Ohc); + if (Ed == NULL) { + return EFI_OUT_OF_RESOURCES; + } + OhciSetEDField (Ed, ED_SKIP, 1); + OhciSetEDField (Ed, ED_FUNC_ADD, DeviceAddress); + OhciSetEDField (Ed, ED_ENDPT_NUM, EndPointNum); + OhciSetEDField (Ed, ED_DIR, ED_FROM_TD_DIR); + OhciSetEDField (Ed, ED_SPEED, HI_SPEED); + OhciSetEDField (Ed, ED_FORMAT | ED_HALTED | ED_DTTOGGLE, 0); + OhciSetEDField (Ed, ED_MAX_PACKET, MaxPacketLength); + OhciSetEDField (Ed, ED_PDATA, 0); + OhciSetEDField (Ed, ED_ZERO, 0); + OhciSetEDField (Ed, ED_TDHEAD_PTR, 0); + OhciSetEDField (Ed, ED_TDTAIL_PTR, 0); + OhciSetEDField (Ed, ED_NEXT_EDPTR, 0); + HeadEd = OhciAttachEDToList (Ohc, BULK_LIST, Ed, NULL); + + if(Data != NULL) { + MapLength = *DataLength; + Status = DmaMap (MapOp, (UINT8 *)Data, &MapLength, &MapPyhAddr, &Mapping); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "OhciBulkTransfer: Fail to Map Data Buffer for Bulk\r\n")); + goto FREE_ED_BUFF; + } + } + // + //Data Stage + // + LeftLength = MapLength; + ActualSendLength = MapLength; + HeadTd = NULL; + FirstTD = TRUE; + while (LeftLength > 0) { + ActualSendLength = LeftLength; + if (LeftLength > MaxPacketLength) { + ActualSendLength = MaxPacketLength; + } + DataTd = OhciCreateTD (Ohc); + if (DataTd == NULL) { + DEBUG ((DEBUG_INFO, "OhciBulkTransfer: Fail to allocate buffer for Data Stage TD\r\n")); + Status = EFI_OUT_OF_RESOURCES; + goto FREE_OHCI_TDBUFF; + } + OhciSetTDField (DataTd, TD_PDATA, 0); + OhciSetTDField (DataTd, TD_BUFFER_ROUND, 1); + OhciSetTDField (DataTd, TD_DIR_PID, DataPidDir); + OhciSetTDField (DataTd, TD_DELAY_INT, TD_NO_DELAY); + OhciSetTDField (DataTd, TD_DT_TOGGLE, *DataToggle); + OhciSetTDField (DataTd, TD_ERROR_CNT, 0); + OhciSetTDField (DataTd, TD_COND_CODE, TD_TOBE_PROCESSED); + OhciSetTDField (DataTd, TD_CURR_BUFFER_PTR, (UINT32) MapPyhAddr); + OhciSetTDField (DataTd, TD_BUFFER_END_PTR, (UINT32)(MapPyhAddr + ActualSendLength - 1)); + OhciSetTDField (DataTd, TD_NEXT_PTR, 0); + DataTd->ActualSendLength = (UINT32)ActualSendLength; + DataTd->DataBuffer = (UINT32)MapPyhAddr; + DataTd->NextTDPointer = 0; + if (FirstTD) { + HeadTd = DataTd; + FirstTD = FALSE; + } else { + OhciLinkTD (HeadTd, DataTd); + } + *DataToggle ^= 1; + MapPyhAddr += ActualSendLength; + LeftLength -= ActualSendLength; + } + // + // Empty Stage + // + EmptyTd = OhciCreateTD (Ohc); + if (EmptyTd == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_INFO, "OhciBulkTransfer: Fail to allocate buffer for Empty TD\r\n")); + goto FREE_OHCI_TDBUFF; + } + OhciSetTDField (EmptyTd, TD_PDATA, 0); + OhciSetTDField (EmptyTd, TD_BUFFER_ROUND, 0); + OhciSetTDField (EmptyTd, TD_DIR_PID, 0); + OhciSetTDField (EmptyTd, TD_DELAY_INT, 0); + //OhciSetTDField (EmptyTd, TD_DT_TOGGLE, CurrentToggle); + EmptyTd->Word0.DataToggle = 0; + OhciSetTDField (EmptyTd, TD_ERROR_CNT, 0); + OhciSetTDField (EmptyTd, TD_COND_CODE, 0); + OhciSetTDField (EmptyTd, TD_CURR_BUFFER_PTR, 0); + OhciSetTDField (EmptyTd, TD_BUFFER_END_PTR, 0); + OhciSetTDField (EmptyTd, TD_NEXT_PTR, 0); + EmptyTd->ActualSendLength = 0; + EmptyTd->DataBuffer = 0; + EmptyTd->NextTDPointer = 0; + OhciLinkTD (HeadTd, EmptyTd); + Ed->TdTailPointer = (UINT32)(UINTN)EmptyTd; + OhciAttachTDListToED (Ed, HeadTd); + + OhciSetEDField (Ed, ED_SKIP, 0); + Status = OhciSetHcCommandStatus (Ohc, BULK_LIST_FILLED, 1); + if (EFI_ERROR(Status)) { + *TransferResult = EFI_USB_ERR_SYSTEM; + Status = EFI_DEVICE_ERROR; + DEBUG ((DEBUG_INFO, "OhciControlTransfer: Fail to enable BULK_LIST_FILLED\r\n")); + goto FREE_OHCI_TDBUFF; + } + Status = OhciSetHcControl (Ohc, BULK_ENABLE, 1); + if (EFI_ERROR(Status)) { + *TransferResult = EFI_USB_ERR_SYSTEM; + Status = EFI_DEVICE_ERROR; + DEBUG ((DEBUG_INFO, "OhciControlTransfer: Fail to enable BULK_ENABLE\r\n")); + goto FREE_OHCI_TDBUFF; + } + gBS->Stall(20 * 1000); + + TimeCount = 0; + Status = CheckIfDone (Ohc, BULK_LIST, Ed, HeadTd, &EdResult); + while (Status == EFI_NOT_READY && TimeCount <= TimeOut) { + gBS->Stall (1000); + TimeCount++; + Status = CheckIfDone (Ohc, BULK_LIST, Ed, HeadTd, &EdResult); + } + + *TransferResult = ConvertErrorCode (EdResult.ErrorCode); + + if (EdResult.ErrorCode != TD_NO_ERROR) { + if (EdResult.ErrorCode == TD_TOBE_PROCESSED) { + DEBUG ((DEBUG_ERROR, "Bulk pipe timeout, > %d mS\r\n", TimeOut)); + } else { + DEBUG ((DEBUG_ERROR, "Bulk pipe broken\r\n")); + *DataToggle = EdResult.NextToggle; + } + *DataLength = 0; + } else { + DEBUG ((DEBUG_INFO, "Bulk transfer successed\r\n")); + } + //*DataToggle = (UINT8) OhciGetEDField (Ed, ED_DTTOGGLE); + +FREE_OHCI_TDBUFF: + OhciSetEDField (Ed, ED_SKIP, 1); + if (HeadEd == Ed) { + OhciSetMemoryPointer (Ohc, HC_BULK_HEAD, NULL); + }else { + HeadEd->NextED = Ed->NextED; + } + while (HeadTd) { + DataTd = HeadTd; + HeadTd = (TD_DESCRIPTOR *)(UINTN)(HeadTd->NextTDPointer); + UsbHcFreeMem(Ohc->MemPool, DataTd, sizeof(TD_DESCRIPTOR)); + } + + if(Mapping != NULL) { + DmaUnmap(Mapping); + } + +FREE_ED_BUFF: + UsbHcFreeMem(Ohc->MemPool, Ed, sizeof(ED_DESCRIPTOR)); + + return Status; +} +/** + + Submits an interrupt transfer to an interrupt endpoint of a USB device. + + @param Ohc Device private data + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the + control endpoint (whose default endpoint address is 0). + It is the caller's responsibility to make sure that + the EndPointAddress represents an interrupt endpoint. + @param IsSlowDevice Indicates whether the target device is slow device + or full-speed device. + @param MaxPacketLength Indicates the maximum packet size the target endpoint + is capable of sending or receiving. + @param IsNewTransfer If TRUE, an asynchronous interrupt pipe is built between + the host and the target interrupt endpoint. + If FALSE, the specified asynchronous interrupt pipe + is canceled. + @param DataToggle A pointer to the data toggle value. On input, it is valid + when IsNewTransfer is TRUE, and it indicates the initial + data toggle value the asynchronous interrupt transfer + should adopt. + On output, it is valid when IsNewTransfer is FALSE, + and it is updated to indicate the data toggle value of + the subsequent asynchronous interrupt transfer. + @param PollingInterval Indicates the interval, in milliseconds, that the + asynchronous interrupt transfer is polled. + This parameter is required when IsNewTransfer is TRUE. + @param UCBuffer Uncacheable buffer + @param DataLength Indicates the length of data to be received at the + rate specified by PollingInterval from the target + asynchronous interrupt endpoint. This parameter + is only required when IsNewTransfer is TRUE. + @param CallBackFunction The Callback function.This function is called at the + rate specified by PollingInterval.This parameter is + only required when IsNewTransfer is TRUE. + @param Context The context that is passed to the CallBackFunction. + This is an optional parameter and may be NULL. + @param IsPeriodic Periodic interrupt or not + @param OutputED The correspoding ED carried out + @param OutputTD The correspoding TD carried out + + + @retval EFI_SUCCESS The asynchronous interrupt transfer request has been successfully + submitted or canceled. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ + +EFI_STATUS +OhciInterruptTransfer ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxPacketLength, + IN BOOLEAN IsNewTransfer, + IN OUT UINT8 *DataToggle OPTIONAL, + IN UINTN PollingInterval OPTIONAL, + IN VOID *UCBuffer OPTIONAL, + IN UINTN DataLength OPTIONAL, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction OPTIONAL, + IN VOID *Context OPTIONAL, + IN BOOLEAN IsPeriodic OPTIONAL, + OUT ED_DESCRIPTOR **OutputED OPTIONAL, + OUT TD_DESCRIPTOR **OutputTD OPTIONAL + ) +{ + ED_DESCRIPTOR *Ed; + UINT8 EdDir; + ED_DESCRIPTOR *HeadEd; + TD_DESCRIPTOR *HeadTd; + TD_DESCRIPTOR *DataTd; + TD_DESCRIPTOR *EmptTd; + UINTN Depth; + UINTN Index; + EFI_STATUS Status; + UINT8 EndPointNum; + UINT32 DataPidDir; + INTERRUPT_CONTEXT_ENTRY *Entry; + EFI_TPL OldTpl; + BOOLEAN FirstTD; + + VOID *Mapping; + UINTN MapLength; + EFI_PHYSICAL_ADDRESS MapPyhAddr; + UINTN LeftLength; + UINTN ActualSendLength; + + if (DataLength > MAX_BYTES_PER_TD) { + DEBUG ((DEBUG_ERROR, "OhciInterruptTransfer: Error param\r\n")); + return EFI_INVALID_PARAMETER; + } + + if ((EndPointAddress & 0x80) != 0) { + EdDir = ED_IN_DIR; + DataPidDir = TD_IN_PID; + } else { + EdDir = ED_OUT_DIR; + DataPidDir = TD_OUT_PID; + } + + EndPointNum = (EndPointAddress & 0xF); + if (!IsNewTransfer) { + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + OhciSetHcControl (Ohc, PERIODIC_ENABLE, 0); + OhciFreeInterruptContext (Ohc, DeviceAddress, EndPointAddress, DataToggle); + Status = OhciFreeInterruptEdByAddr (Ohc, DeviceAddress, EndPointNum); + OhciSetHcControl (Ohc, PERIODIC_ENABLE, 1); + gBS->RestoreTPL (OldTpl); + return Status; + } + MapLength = DataLength; + Status = DmaMap( + MapOperationBusMasterWrite, + UCBuffer, + &MapLength, + &MapPyhAddr, + &Mapping + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "OhciInterruptTransfer: Fail to Map buffer \r\n")); + goto EXIT; + } + Depth = 5; + Index = 1; + while (PollingInterval >= Index * 2 && Depth > 0) { + Index *= 2; + Depth--; + } + // + //ED Stage + // + HeadEd = OhciFindMinInterruptEDList (Ohc, (UINT32)Depth); + if ((Ed = OhciFindWorkingEd (HeadEd, DeviceAddress, EndPointNum, EdDir)) != NULL) { + OhciSetEDField (Ed, ED_SKIP, 1); + } else { + Ed = OhciCreateED (Ohc); + if (Ed == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "OhciInterruptTransfer: Fail to allocate buffer for ED\r\n")); + goto UNMAP_OHCI_XBUFF; + } + OhciSetEDField (Ed, ED_SKIP, 1); + OhciSetEDField (Ed, ED_FUNC_ADD, DeviceAddress); + OhciSetEDField (Ed, ED_ENDPT_NUM, EndPointNum); + OhciSetEDField (Ed, ED_DIR, ED_FROM_TD_DIR); + OhciSetEDField (Ed, ED_SPEED, IsSlowDevice); + OhciSetEDField (Ed, ED_FORMAT, 0); + OhciSetEDField (Ed, ED_MAX_PACKET, MaxPacketLength); + OhciSetEDField (Ed, ED_PDATA | ED_ZERO | ED_HALTED | ED_DTTOGGLE, 0); + OhciSetEDField (Ed, ED_TDHEAD_PTR, 0); + OhciSetEDField (Ed, ED_TDTAIL_PTR, 0); + OhciSetEDField (Ed, ED_NEXT_EDPTR, 0); + OhciAttachEDToList (Ohc, INTERRUPT_LIST, Ed, HeadEd); + } + // + //Data Stage + // + LeftLength = MapLength; + ActualSendLength = MapLength; + HeadTd = NULL; + FirstTD = TRUE; + while (LeftLength > 0) { + ActualSendLength = LeftLength; + if (LeftLength > MaxPacketLength) { + ActualSendLength = MaxPacketLength; + } + DataTd = OhciCreateTD (Ohc); + if (DataTd == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "OhciInterruptTransfer: Fail to allocate buffer for Data Stage TD\r\n")); + goto FREE_OHCI_TDBUFF; + } + OhciSetTDField (DataTd, TD_PDATA, 0); + OhciSetTDField (DataTd, TD_BUFFER_ROUND, 1); + OhciSetTDField (DataTd, TD_DIR_PID, DataPidDir); + OhciSetTDField (DataTd, TD_DELAY_INT, TD_NO_DELAY); + OhciSetTDField (DataTd, TD_DT_TOGGLE, *DataToggle); + OhciSetTDField (DataTd, TD_ERROR_CNT, 0); + OhciSetTDField (DataTd, TD_COND_CODE, TD_TOBE_PROCESSED); + OhciSetTDField (DataTd, TD_CURR_BUFFER_PTR, (UINT32) MapPyhAddr); + OhciSetTDField (DataTd, TD_BUFFER_END_PTR, (UINT32)(MapPyhAddr + ActualSendLength - 1)); + OhciSetTDField (DataTd, TD_NEXT_PTR, 0); + DataTd->ActualSendLength = (UINT32)ActualSendLength; + DataTd->DataBuffer = (UINT32)(UINTN)MapPyhAddr; + DataTd->NextTDPointer = 0; + if (FirstTD) { + HeadTd = DataTd; + FirstTD = FALSE; + } else { + OhciLinkTD (HeadTd, DataTd); + } + *DataToggle ^= 1; + MapPyhAddr += ActualSendLength; + LeftLength -= ActualSendLength; + } + + EmptTd = OhciCreateTD (Ohc); + if (EmptTd == NULL) { + Status = EFI_OUT_OF_RESOURCES; + DEBUG ((DEBUG_ERROR, "OhciInterruptTransfer: Fail to allocate buffer for Empty Stage TD\r\n")); + goto FREE_OHCI_TDBUFF; + } + OhciSetTDField (EmptTd, TD_PDATA, 0); + OhciSetTDField (EmptTd, TD_BUFFER_ROUND, 0); + OhciSetTDField (EmptTd, TD_DIR_PID, 0); + OhciSetTDField (EmptTd, TD_DELAY_INT, 0); + //OhciSetTDField (EmptTd, TD_DT_TOGGLE, CurrentToggle); + EmptTd->Word0.DataToggle = 0; + OhciSetTDField (EmptTd, TD_ERROR_CNT, 0); + OhciSetTDField (EmptTd, TD_COND_CODE, 0); + OhciSetTDField (EmptTd, TD_CURR_BUFFER_PTR, 0); + OhciSetTDField (EmptTd, TD_BUFFER_END_PTR, 0); + OhciSetTDField (EmptTd, TD_NEXT_PTR, 0); + EmptTd->ActualSendLength = 0; + EmptTd->DataBuffer = 0; + EmptTd->NextTDPointer = 0; + OhciLinkTD (HeadTd, EmptTd); + Ed->TdTailPointer = (UINT32)(UINTN)EmptTd; + OhciAttachTDListToED (Ed, HeadTd); + + if (OutputED != NULL) { + *OutputED = Ed; + } + if (OutputTD != NULL) { + *OutputTD = HeadTd; + } + + if (CallBackFunction != NULL) { + Entry = AllocatePool (sizeof (INTERRUPT_CONTEXT_ENTRY)); + if (Entry == NULL) { + goto FREE_OHCI_TDBUFF; + } + + Entry->DeviceAddress = DeviceAddress; + Entry->EndPointAddress = EndPointAddress; + Entry->Ed = Ed; + Entry->DataTd = HeadTd; + Entry->IsSlowDevice = IsSlowDevice; + Entry->MaxPacketLength = MaxPacketLength; + Entry->PollingInterval = PollingInterval; + Entry->CallBackFunction = CallBackFunction; + Entry->Context = Context; + Entry->IsPeriodic = IsPeriodic; + Entry->UCBuffer = UCBuffer; + Entry->UCBufferMapping = Mapping; + Entry->DataLength = DataLength; + Entry->Toggle = DataToggle; + Entry->NextEntry = NULL; + OhciAddInterruptContextEntry (Ohc, Entry); + } + OhciSetEDField (Ed, ED_SKIP, 0); + + if (OhciGetHcControl (Ohc, PERIODIC_ENABLE) == 0) { + Status = OhciSetHcControl (Ohc, PERIODIC_ENABLE, 1); + gBS->Stall (1000); + } + + return EFI_SUCCESS; + +FREE_OHCI_TDBUFF: + while (HeadTd) { + DataTd = HeadTd; + HeadTd = (TD_DESCRIPTOR *)(UINTN)(HeadTd->NextTDPointer); + UsbHcFreeMem(Ohc->MemPool, DataTd, sizeof(TD_DESCRIPTOR)); + } + +//FREE_OHCI_EDBUFF: + if ((HeadEd != Ed) && HeadEd && Ed) { + while(HeadEd->NextED != (UINT32)(UINTN)Ed) { + HeadEd = (ED_DESCRIPTOR *)(UINTN)(HeadEd->NextED); + } + HeadEd->NextED = Ed->NextED; + UsbHcFreeMem(Ohc->MemPool, Ed, sizeof(ED_DESCRIPTOR)); + } + +UNMAP_OHCI_XBUFF: + DmaUnmap(Mapping); + +EXIT: + return Status; +} + + +/** + + Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the + control endpoint (whose default endpoint address is 0). + It is the caller's responsibility to make sure that + the EndPointAddress represents an interrupt endpoint. + @param IsSlowDevice Indicates whether the target device is slow device + or full-speed device. + @param MaxiumPacketLength Indicates the maximum packet size the target endpoint + is capable of sending or receiving. + @param IsNewTransfer If TRUE, an asynchronous interrupt pipe is built between + the host and the target interrupt endpoint. + If FALSE, the specified asynchronous interrupt pipe + is canceled. + @param DataToggle A pointer to the data toggle value. On input, it is valid + when IsNewTransfer is TRUE, and it indicates the initial + data toggle value the asynchronous interrupt transfer + should adopt. + On output, it is valid when IsNewTransfer is FALSE, + and it is updated to indicate the data toggle value of + the subsequent asynchronous interrupt transfer. + @param PollingInterval Indicates the interval, in milliseconds, that the + asynchronous interrupt transfer is polled. + This parameter is required when IsNewTransfer is TRUE. + @param DataLength Indicates the length of data to be received at the + rate specified by PollingInterval from the target + asynchronous interrupt endpoint. This parameter + is only required when IsNewTransfer is TRUE. + @param CallBackFunction The Callback function.This function is called at the + rate specified by PollingInterval.This parameter is + only required when IsNewTransfer is TRUE. + @param Context The context that is passed to the CallBackFunction. + This is an optional parameter and may be NULL. + + @retval EFI_SUCCESS The asynchronous interrupt transfer request has been successfully + submitted or canceled. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ + + +EFI_STATUS +EFIAPI +OhciAsyncInterruptTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxPacketLength, + IN BOOLEAN IsNewTransfer, + IN OUT UINT8 *DataToggle OPTIONAL, + IN UINTN PollingInterval OPTIONAL, + IN UINTN DataLength OPTIONAL, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction OPTIONAL, + IN VOID *Context OPTIONAL + ) +{ + EFI_STATUS Status; + USB_OHCI_HC_DEV *Ohc; + VOID *UCBuffer; + UINTN Pages; + if (DataToggle == NULL || (EndPointAddress & 0x80) == 0 || + (IsNewTransfer && (DataLength == 0 || + (*DataToggle != 0 && *DataToggle != 1) || (PollingInterval < 1 || PollingInterval > 255)))) { + return EFI_INVALID_PARAMETER; + } + + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + if ( IsNewTransfer ) { + Pages = EFI_SIZE_TO_PAGES (DataLength); + Status = DmaAllocateBuffer ( + EfiBootServicesData, + Pages, + &UCBuffer + ); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + } else { + UCBuffer = NULL; + } + + Status = OhciInterruptTransfer ( + Ohc, + DeviceAddress, + EndPointAddress, + IsSlowDevice, + MaxPacketLength, + IsNewTransfer, + DataToggle, + PollingInterval, + UCBuffer, + DataLength, + CallBackFunction, + Context, + TRUE, + NULL, + NULL + ); + + if ( UCBuffer ) { + if (EFI_ERROR(Status)) { + DmaFreeBuffer (Pages, UCBuffer); + } + } + return Status; +} + + +/** + + Submits synchronous interrupt transfer to an interrupt endpoint + of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint + address supports data transfer in one direction + except the control endpoint (whose default + endpoint address is 0). It is the caller's responsibility + to make sure that the EndPointAddress represents + an interrupt endpoint. + @param IsSlowDevice Indicates whether the target device is slow device + or full-speed device. + @param MaxPacketLength Indicates the maximum packet size the target endpoint + is capable of sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param DataLength On input, the size, in bytes, of the data buffer specified + by Data. On output, the number of bytes transferred. + @param DataToggle A pointer to the data toggle value. On input, it indicates + the initial data toggle value the synchronous interrupt + transfer should adopt; + on output, it is updated to indicate the data toggle value + of the subsequent synchronous interrupt transfer. + @param TimeOut Indicates the maximum time, in microseconds, which the + transfer is allowed to complete. + @param TransferResult A pointer to the detailed result information from + the synchronous interrupt transfer. + + @retval EFI_UNSUPPORTED This interface not available. + @retval EFI_INVALID_PARAMETER Parameters not follow spec + +**/ + + +EFI_STATUS +EFIAPI +OhciSyncInterruptTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxPacketLength, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN OUT UINT8 *DataToggle, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ) +{ + USB_OHCI_HC_DEV *Ohc; + EFI_STATUS Status; + ED_DESCRIPTOR *Ed; + TD_DESCRIPTOR *HeadTd; + OHCI_ED_RESULT EdResult; + VOID *UCBuffer; + + if ((EndPointAddress & 0x80) == 0 || Data == NULL || DataLength == NULL || *DataLength == 0 || + (IsSlowDevice && MaxPacketLength > 8) || (!IsSlowDevice && MaxPacketLength > 64) || + DataToggle == NULL || (*DataToggle != 0 && *DataToggle != 1) || TransferResult == NULL) { + return EFI_INVALID_PARAMETER; + } + + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + UCBuffer = AllocatePool (*DataLength); + if (UCBuffer == NULL) { + return EFI_OUT_OF_RESOURCES; + } + Status = OhciInterruptTransfer ( + Ohc, + DeviceAddress, + EndPointAddress, + IsSlowDevice, + MaxPacketLength, + TRUE, + DataToggle, + 1, + UCBuffer, + *DataLength, + NULL, + NULL, + FALSE, + &Ed, + &HeadTd + ); + + if (!EFI_ERROR (Status)) { + Status = CheckIfDone (Ohc, INTERRUPT_LIST, Ed, HeadTd, &EdResult); + while (Status == EFI_NOT_READY && TimeOut > 0) { + gBS->Stall (1000); + TimeOut--; + Status = CheckIfDone (Ohc, INTERRUPT_LIST, Ed, HeadTd, &EdResult); + } + + *TransferResult = ConvertErrorCode (EdResult.ErrorCode); + } + CopyMem(Data, UCBuffer, *DataLength); + Status = OhciInterruptTransfer ( + Ohc, + DeviceAddress, + EndPointAddress, + IsSlowDevice, + MaxPacketLength, + FALSE, + DataToggle, + 0, + NULL, + 0, + NULL, + NULL, + FALSE, + NULL, + NULL + ); + + return Status; +} +/** + + Submits isochronous transfer to a target USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress End point address + @param MaximumPacketLength Indicates the maximum packet size that the + default control transfer endpoint is capable of + sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param DataLength Indicates the size, in bytes, of the data buffer + specified by Data. + @param TransferResult A pointer to the detailed result information generated + by this control transfer. + + @retval EFI_UNSUPPORTED This interface not available + @retval EFI_INVALID_PARAMETER Data is NULL or DataLength is 0 or TransferResult is NULL + +**/ + + +EFI_STATUS +EFIAPI +OhciIsochronousTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaximumPacketLength, + IN OUT VOID *Data, + IN OUT UINTN DataLength, + OUT UINT32 *TransferResult + ) +{ + if (Data == NULL || DataLength == 0 || TransferResult == NULL) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +/** + + Submits Async isochronous transfer to a target USB device. + + @param his A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress End point address + @param MaximumPacketLength Indicates the maximum packet size that the + default control transfer endpoint is capable of + sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param IsochronousCallBack When the transfer complete, the call back function will be called + @param Context Pass to the call back function as parameter + + @retval EFI_UNSUPPORTED This interface not available + @retval EFI_INVALID_PARAMETER Data is NULL or Datalength is 0 + +**/ + +EFI_STATUS +EFIAPI +OhciAsyncIsochronousTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaximumPacketLength, + IN OUT VOID *Data, + IN OUT UINTN DataLength, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack, + IN VOID *Context OPTIONAL + ) +{ + + if (Data == NULL || DataLength == 0) { + return EFI_INVALID_PARAMETER; + } + + return EFI_UNSUPPORTED; +} + +/** + + Retrieves the number of root hub ports. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param NumOfPorts A pointer to the number of the root hub ports. + + @retval EFI_SUCCESS The port number was retrieved successfully. +**/ +EFI_STATUS +EFIAPI +OhciGetRootHubNumOfPorts ( + IN EFI_USB_HC_PROTOCOL *This, + OUT UINT8 *NumOfPorts + ) +{ + USB_OHCI_HC_DEV *Ohc; + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + if (NumOfPorts == NULL) { + return EFI_INVALID_PARAMETER; + } + + *NumOfPorts = (UINT8)OhciGetRootHubDescriptor(Ohc, RH_NUM_DS_PORTS); + + return EFI_SUCCESS; +} +/** + + Retrieves the current status of a USB root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL. + @param PortNumber Specifies the root hub port from which the status + is to be retrieved. This value is zero-based. For example, + if a root hub has two ports, then the first port is numbered 0, + and the second port is numbered 1. + @param PortStatus A pointer to the current port status bits and + port status change bits. + + @retval EFI_SUCCESS The status of the USB root hub port specified by PortNumber + was returned in PortStatus. + @retval EFI_INVALID_PARAMETER Port number not valid +**/ + + +EFI_STATUS +EFIAPI +OhciGetRootHubPortStatus ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + OUT EFI_USB_PORT_STATUS *PortStatus + ) +{ + USB_OHCI_HC_DEV *Ohc; + UINT8 NumOfPorts; + + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + OhciGetRootHubNumOfPorts (This, &NumOfPorts); + if (PortNumber >= NumOfPorts) { + return EFI_INVALID_PARAMETER; + } + PortStatus->PortStatus = 0; + PortStatus->PortChangeStatus = 0; + + if (OhciReadRootHubPortStatus (Ohc,PortNumber, RH_CURR_CONNECT_STAT)) { + PortStatus->PortStatus |= USB_PORT_STAT_CONNECTION; + } + if (OhciReadRootHubPortStatus (Ohc,PortNumber, RH_PORT_ENABLE_STAT)) { + PortStatus->PortStatus |= USB_PORT_STAT_ENABLE; + } + if (OhciReadRootHubPortStatus (Ohc,PortNumber, RH_PORT_SUSPEND_STAT)) { + PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND; + } + if (OhciReadRootHubPortStatus (Ohc,PortNumber, RH_PORT_OC_INDICATOR)) { + PortStatus->PortStatus |= USB_PORT_STAT_OVERCURRENT; + } + if (OhciReadRootHubPortStatus (Ohc,PortNumber, RH_PORT_RESET_STAT)) { + PortStatus->PortStatus |= USB_PORT_STAT_RESET; + } + if (OhciReadRootHubPortStatus (Ohc,PortNumber, RH_PORT_POWER_STAT)) { + PortStatus->PortStatus |= USB_PORT_STAT_POWER; + } + if (OhciReadRootHubPortStatus (Ohc,PortNumber, RH_LSDEVICE_ATTACHED)) { + PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED; + } + if (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_ENABLE_STAT_CHANGE)) { + PortStatus->PortChangeStatus |= USB_PORT_STAT_C_ENABLE; + } + if (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_CONNECT_STATUS_CHANGE)) { + PortStatus->PortChangeStatus |= USB_PORT_STAT_C_CONNECTION; + } + if (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_SUSPEND_STAT_CHANGE)) { + PortStatus->PortChangeStatus |= USB_PORT_STAT_C_SUSPEND; + } + if (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_OC_INDICATOR_CHANGE)) { + PortStatus->PortChangeStatus |= USB_PORT_STAT_C_OVERCURRENT; + } + if (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_RESET_STAT_CHANGE)) { + PortStatus->PortChangeStatus |= USB_PORT_STAT_C_RESET; + } + + return EFI_SUCCESS; +} +/** + + Sets a feature for the specified root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL. + @param PortNumber Specifies the root hub port whose feature + is requested to be set. + @param PortFeature Indicates the feature selector associated + with the feature set request. + + @retval EFI_SUCCESS The feature specified by PortFeature was set for the + USB root hub port specified by PortNumber. + @retval EFI_DEVICE_ERROR Set feature failed because of hardware issue + @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid. +**/ +EFI_STATUS +EFIAPI +OhciSetRootHubPortFeature ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + IN EFI_USB_PORT_FEATURE PortFeature + ) +{ + USB_OHCI_HC_DEV *Ohc; + EFI_STATUS Status; + UINT8 NumOfPorts; + UINTN RetryTimes; + + OhciGetRootHubNumOfPorts (This, &NumOfPorts); + if (PortNumber >= NumOfPorts) { + return EFI_INVALID_PARAMETER; + } + + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + Status = EFI_SUCCESS; + + + switch (PortFeature) { + case EfiUsbPortPower: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_SET_PORT_POWER); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_POWER_STAT) == 0 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + case EfiUsbPortReset: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_SET_PORT_RESET); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while ((OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_RESET_STAT_CHANGE) == 0 || + OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_RESET_STAT) == 1) && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + + OhciSetRootHubPortStatus (Ohc, PortNumber, RH_PORT_RESET_STAT_CHANGE); + break; + + case EfiUsbPortEnable: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_SET_PORT_ENABLE); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_ENABLE_STAT) == 0 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + + case EfiUsbPortSuspend: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_SET_PORT_SUSPEND); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_SUSPEND_STAT) == 0 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + default: + return EFI_INVALID_PARAMETER; + } + + return Status; +} + +/** + + Clears a feature for the specified root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param PortNumber Specifies the root hub port whose feature + is requested to be cleared. + @param PortFeature Indicates the feature selector associated with the + feature clear request. + + @retval EFI_SUCCESS The feature specified by PortFeature was cleared for the + USB root hub port specified by PortNumber. + @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid. + @retval EFI_DEVICE_ERROR Some error happened when clearing feature +**/ +EFI_STATUS +EFIAPI +OhciClearRootHubPortFeature ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + IN EFI_USB_PORT_FEATURE PortFeature + ) +{ + USB_OHCI_HC_DEV *Ohc; + EFI_STATUS Status; + UINT8 NumOfPorts; + UINTN RetryTimes; + + + OhciGetRootHubNumOfPorts (This, &NumOfPorts); + if (PortNumber >= NumOfPorts) { + return EFI_INVALID_PARAMETER; + } + + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + Status = EFI_SUCCESS; + + switch (PortFeature) { + case EfiUsbPortEnable: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_CLEAR_PORT_ENABLE); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_ENABLE_STAT) == 1 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + case EfiUsbPortSuspend: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_CLEAR_SUSPEND_STATUS); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_SUSPEND_STAT) == 1 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + case EfiUsbPortReset: + break; + + case EfiUsbPortPower: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_CLEAR_PORT_POWER); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_POWER_STAT) == 1 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + case EfiUsbPortConnectChange: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_CONNECT_STATUS_CHANGE); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_CONNECT_STATUS_CHANGE) == 1 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + case EfiUsbPortResetChange: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_PORT_RESET_STAT_CHANGE); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_RESET_STAT_CHANGE) == 1 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + + case EfiUsbPortEnableChange: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_PORT_ENABLE_STAT_CHANGE); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_ENABLE_STAT_CHANGE) == 1 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + case EfiUsbPortSuspendChange: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_PORT_SUSPEND_STAT_CHANGE); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_PORT_SUSPEND_STAT_CHANGE) == 1 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + case EfiUsbPortOverCurrentChange: + Status = OhciSetRootHubPortStatus (Ohc, PortNumber, RH_OC_INDICATOR_CHANGE); + + // + // Verify the state + // + RetryTimes = 0; + do { + gBS->Stall (1000); + RetryTimes++; + } while (OhciReadRootHubPortStatus (Ohc, PortNumber, RH_OC_INDICATOR_CHANGE) == 1 && + RetryTimes < MAX_RETRY_TIMES); + + if (RetryTimes >= MAX_RETRY_TIMES) { + return EFI_DEVICE_ERROR; + } + break; + + default: + return EFI_INVALID_PARAMETER; + } + + return Status; +} + + +EFI_STATUS +OhcInitHC ( +IN USB_OHCI_HC_DEV *Ohc +) +{ +EFI_STATUS Status; +UINT8 Index; +UINT8 NumOfPorts; +UINT32 PowerOnGoodTime; +UINT32 Data32; +BOOLEAN Flag = FALSE; + + Status = OhciSetHcCommandStatus (Ohc, HC_RESET, HC_RESET); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + + gBS->Stall (50 * 1000); + // + // Wait for host controller reset. + // + PowerOnGoodTime = 50; + do { + gBS->Stall(1000); + Data32 = OhciGetOperationalReg (Ohc, HC_COMMAND_STATUS ); + if ((Data32 & HC_RESET) == 0) { + Flag = TRUE; + break; + } + }while(PowerOnGoodTime--); + if (!Flag){ + return EFI_DEVICE_ERROR; + } + OhciInitializeInterruptList(Ohc); + + OhciSetFrameInterval (Ohc, FRAME_INTERVAL, 0x2edf); + Status = OhciSetHcControl (Ohc, HC_FUNCTIONAL_STATE, HC_STATE_RESET); + if (EFI_ERROR (Status)) { + return EFI_DEVICE_ERROR; + } + gBS->Stall (50 * 1000); + // + // Initialize host controller operational registers + // + OhciSetFrameInterval (Ohc, FS_LARGEST_DATA_PACKET, 0x2778); + OhciSetFrameInterval (Ohc, FRAME_INTERVAL, 0x2edf); + OhciSetPeriodicStart (Ohc, 0x2a2f); + OhciSetHcControl (Ohc, CONTROL_BULK_RATIO, 0x3); + OhciSetHcCommandStatus (Ohc, CONTROL_LIST_FILLED | BULK_LIST_FILLED, 0); + OhciSetRootHubDescriptor (Ohc, RH_PSWITCH_MODE, 0); + OhciSetRootHubDescriptor (Ohc, RH_NO_PSWITCH | RH_NOC_PROT, 1); + + OhciSetRootHubDescriptor (Ohc, RH_DEV_REMOVABLE, 0); + OhciSetRootHubDescriptor (Ohc, RH_PORT_PWR_CTRL_MASK, 0xffff); + OhciSetRootHubStatus (Ohc, RH_LOCAL_PSTAT_CHANGE); + OhciSetRootHubPortStatus (Ohc, 0, RH_SET_PORT_POWER); + NumOfPorts = OhciGetRootHubDescriptor(Ohc, RH_NUM_DS_PORTS); + + for (Index = 0; Index < NumOfPorts; Index++) { + if (!EFI_ERROR (OhciSetRootHubPortFeature (&Ohc->UsbHc, Index, EfiUsbPortReset))) { + gBS->Stall (200 * 1000); + OhciClearRootHubPortFeature (&Ohc->UsbHc, Index, EfiUsbPortReset); + gBS->Stall (1000); + OhciSetRootHubPortFeature (&Ohc->UsbHc, Index, EfiUsbPortEnable); + gBS->Stall (1000); + } + } + + OhciSetMemoryPointer (Ohc, HC_HCCA, Ohc->HccaMemoryBlock); + OhciSetMemoryPointer (Ohc, HC_CONTROL_HEAD, NULL); + OhciSetMemoryPointer (Ohc, HC_BULK_HEAD, NULL); + OhciSetHcControl (Ohc, PERIODIC_ENABLE | CONTROL_ENABLE | BULK_ENABLE, 1); + OhciSetHcControl (Ohc, HC_FUNCTIONAL_STATE, HC_STATE_OPERATIONAL); + + // + // Wait till first SOF occurs, and then clear it + // + while (OhciGetHcInterruptStatus (Ohc, START_OF_FRAME) == 0); + OhciClearInterruptStatus (Ohc, START_OF_FRAME); + gBS->Stall (1000); + + return EFI_SUCCESS; +} + + +/** + + Free the OHCI device and release its associated resources. + + @param Ohc The OHCI device to release. + +**/ +VOID +OhciFreeDev ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + OhciFreeFixedIntMemory (Ohc); + + if (Ohc->HouseKeeperTimer != NULL) { + gBS->CloseEvent (Ohc->HouseKeeperTimer); + } + + if (Ohc->ExitBootServiceEvent != NULL) { + gBS->CloseEvent (Ohc->ExitBootServiceEvent); + } + + if (Ohc->MemPool != NULL) { + UsbHcFreeMemPool (Ohc->MemPool); + } + + if (Ohc->HccaMemoryMapping != NULL ) { + + DmaFreeBuffer (Ohc->HccaMemoryPages, Ohc->HccaMemoryBuf); + } + + if (Ohc->ControllerNameTable != NULL) { + FreeUnicodeStringTable (Ohc->ControllerNameTable); + } + + FreePool (Ohc); +} +/** + + Uninstall all Ohci Interface. + + @param Controller Controller handle. + @param This Protocol instance pointer. + +**/ +VOID +OhciCleanDevUp ( + IN EFI_HANDLE Controller, + IN EFI_USB_HC_PROTOCOL *This + ) +{ + USB_OHCI_HC_DEV *Ohc; + + // + // Retrieve private context structure + // + Ohc = USB_OHCI_HC_DEV_FROM_THIS (This); + + // + // Uninstall the USB_HC and USB_HC2 protocol + // + gBS->UninstallProtocolInterface ( + Controller, + &gEfiUsbHcProtocolGuid, + &Ohc->UsbHc + ); + + // + // Cancel the timer event + // + gBS->SetTimer (Ohc->HouseKeeperTimer, TimerCancel, 0); + + // + // Stop the host controller + // + OhciSetHcControl (Ohc, PERIODIC_ENABLE | CONTROL_ENABLE | ISOCHRONOUS_ENABLE | BULK_ENABLE, 0); + This->Reset (This, EFI_USB_HC_RESET_GLOBAL); + This->SetState (This, EfiUsbHcStateHalt); + + // + // Free resources + // + OhciFreeDynamicIntMemory (Ohc); + + // + // Free the private context structure + // + OhciFreeDev (Ohc); +} + +/** + + One notified function to stop the Host Controller when gBS->ExitBootServices() called. + + @param Event Pointer to this event + @param Context Event handler private data +**/ +VOID +EFIAPI +OhcExitBootService ( + EFI_EVENT Event, + VOID *Context + ) +{ + USB_OHCI_HC_DEV *Ohc; + EFI_USB_HC_PROTOCOL *UsbHc; + Ohc = (USB_OHCI_HC_DEV *) Context; + + UsbHc = &Ohc->UsbHc; + // + // Stop the Host Controller + // + //OhciStopHc (Ohc, OHC_GENERIC_TIMEOUT); + OhciSetHcControl (Ohc, PERIODIC_ENABLE | CONTROL_ENABLE | ISOCHRONOUS_ENABLE | BULK_ENABLE, 0); + UsbHc->Reset (UsbHc, EFI_USB_HC_RESET_GLOBAL); + UsbHc->SetState (UsbHc, EfiUsbHcStateHalt); + + return; +} + +/** + Test to see if this driver supports ControllerHandle. Any + ControllerHandle that has UsbHcProtocol installed will be supported. + + @param This Protocol instance pointer. + @param Controller Handle of device to test. + @param RemainingDevicePath Not used. + + @return EFI_SUCCESS This driver supports this device. + @return EFI_UNSUPPORTED This driver does not support this device. + +**/ +EFI_STATUS +EFIAPI +OHCIDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + OHCI_DEVICE_PROTOCOL *Dev; + EFI_STATUS Status; + + // + // Connect to the non-discoverable device + // + Status = gBS->OpenProtocol (ControllerHandle, + &gOhciDeviceProtocolGuid, + (VOID **)&Dev, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Clean up. + // + gBS->CloseProtocol (ControllerHandle, + &gOhciDeviceProtocolGuid, + This->DriverBindingHandle, + ControllerHandle); + + return EFI_SUCCESS; +} + +/** + + Allocate and initialize the empty OHCI device. + + @param OriginalPciAttributes The original PCI attributes. + + @return Allocated OHCI device If err, return NULL. + +**/ + +EFI_STATUS +EFIAPI +OHCIDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + USB_OHCI_HC_DEV *Ohc; + EFI_STATUS Status; + VOID *Buf; + EFI_PHYSICAL_ADDRESS PhyAddr; + VOID *Map; + UINTN Pages; + UINTN Bytes; + + Ohc = AllocateZeroPool (sizeof (USB_OHCI_HC_DEV)); + if (Ohc == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status = gBS->OpenProtocol (ControllerHandle, + &gOhciDeviceProtocolGuid, + (VOID **)&Ohc->Protocol, + This->DriverBindingHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Couldn't open protocol: %r\n", __FUNCTION__, Status)); + goto FREE_OHC; + } + + Ohc->Signature = USB_OHCI_HC_DEV_SIGNATURE; + + Ohc->UsbHc.Reset = OhciReset; + Ohc->UsbHc.GetState = OhciGetState; + Ohc->UsbHc.SetState = OhciSetState; + Ohc->UsbHc.ControlTransfer = OhciControlTransfer; + Ohc->UsbHc.BulkTransfer = OhciBulkTransfer; + Ohc->UsbHc.AsyncInterruptTransfer = OhciAsyncInterruptTransfer; + Ohc->UsbHc.SyncInterruptTransfer = OhciSyncInterruptTransfer; + Ohc->UsbHc.IsochronousTransfer = OhciIsochronousTransfer; + Ohc->UsbHc.AsyncIsochronousTransfer = OhciAsyncIsochronousTransfer; + Ohc->UsbHc.GetRootHubPortNumber = OhciGetRootHubNumOfPorts; + Ohc->UsbHc.GetRootHubPortStatus = OhciGetRootHubPortStatus; + Ohc->UsbHc.SetRootHubPortFeature = OhciSetRootHubPortFeature; + Ohc->UsbHc.ClearRootHubPortFeature = OhciClearRootHubPortFeature; + Ohc->UsbHc.MajorRevision = 0x1; + Ohc->UsbHc.MinorRevision = 0x1; + Ohc->UsbHcBaseAddress = Ohc->Protocol->BaseAddress; + Ohc->HccaMemoryBlock = NULL; + Ohc->HccaMemoryMapping = NULL; + Ohc->HccaMemoryBuf = NULL; + Ohc->HccaMemoryPages = 0; + Ohc->InterruptContextList = NULL; + Ohc->ControllerNameTable = NULL; + Ohc->HouseKeeperTimer = NULL; + + Ohc->MemPool = UsbHcInitMemPool(TRUE, 0); + if(Ohc->MemPool == NULL) { + goto FREE_DEV_BUFFER; + } + + Bytes = 4096; + Pages = EFI_SIZE_TO_PAGES (Bytes); + + Status = DmaAllocateBuffer ( + EfiBootServicesData, + Pages, + &Buf + ); + + if (EFI_ERROR (Status)) { + goto FREE_MEM_POOL; + } + + Status = DmaMap ( + MapOperationBusMasterCommonBuffer, + Buf, + &Bytes, + &PhyAddr, + &Map + ); + + if (EFI_ERROR (Status) || (Bytes != 4096)) { + goto FREE_MEM_PAGE; + } + + Ohc->HccaMemoryBlock = (HCCA_MEMORY_BLOCK *)(UINTN)PhyAddr; + Ohc->HccaMemoryMapping = Map; + Ohc->HccaMemoryBuf = (VOID *)(UINTN)Buf; + Ohc->HccaMemoryPages = Pages; + + // + //Install Host Controller Protocol + // + Status = gBS->InstallProtocolInterface ( + &ControllerHandle, + &gEfiUsbHcProtocolGuid, + EFI_NATIVE_INTERFACE, + &Ohc->UsbHc + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Install protocol error")); + goto FREE_OHC; + } + + // + // Create event to stop the HC on exit boot services. + // + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + OhcExitBootService, + Ohc, + &gEfiEventExitBootServicesGuid, + &Ohc->ExitBootServiceEvent + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "Create exit boot event error")); + goto UNINSTALL_USBHC; + } + + // + // Set 0.01 s timer + // + Status = gBS->CreateEvent ( + EVT_TIMER | EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + OhciHouseKeeper, + Ohc, + &Ohc->HouseKeeperTimer + ); + if (EFI_ERROR (Status)) { + goto FREE_OHC; + } + + Status = OhcInitHC (Ohc); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "failed to init ohci host controller\n")); + goto UNINSTALL_USBHC; + } + + Status = gBS->SetTimer (Ohc->HouseKeeperTimer, TimerPeriodic, 10 * 1000 * 10); + if (EFI_ERROR (Status)) { + goto FREE_OHC; + } + DEBUG ((DEBUG_INFO, "OHCI started for controller @ %p, base address: 0x%p\n", + ControllerHandle, Ohc->UsbHcBaseAddress)); + return EFI_SUCCESS; + +FREE_OHC: + OhciFreeDev (Ohc); +UNINSTALL_USBHC: + gBS->UninstallMultipleProtocolInterfaces ( + ControllerHandle, + &gEfiUsbHcProtocolGuid, + &Ohc->UsbHc, + NULL + ); + gBS->CloseProtocol (ControllerHandle, + &gOhciDeviceProtocolGuid, + This->DriverBindingHandle, + ControllerHandle); +FREE_MEM_PAGE: + DmaFreeBuffer (Pages, Buf); +FREE_MEM_POOL: + UsbHcFreeMemPool (Ohc->MemPool); +FREE_DEV_BUFFER: + FreePool(Ohc); + + return Status; +} + +/** + Stop this driver on ControllerHandle. Support stopping any child handles + created by this driver. + + @param This Protocol instance pointer. + @param Controller Handle of device to stop driver on. + @param NumberOfChildren Number of Children in the ChildHandleBuffer. + @param ChildHandleBuffer List of handles for the children we need to stop. + + @return EFI_SUCCESS + @return others + +**/ +EFI_STATUS +EFIAPI +OHCIDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ) +{ + EFI_STATUS Status; + EFI_USB_HC_PROTOCOL *UsbHc; + + Status = gBS->OpenProtocol ( + Controller, + &gEfiUsbHcProtocolGuid, + (VOID **)&UsbHc, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + return Status; + } + + OhciCleanDevUp(Controller, UsbHc); + + gBS->CloseProtocol ( + Controller, + &gOhciDeviceProtocolGuid, + This->DriverBindingHandle, + Controller + ); + return EFI_SUCCESS; +} + +EFI_DRIVER_BINDING_PROTOCOL gOhciDriverBinding = { + OHCIDriverBindingSupported, + OHCIDriverBindingStart, + OHCIDriverBindingStop, + 0x10, + NULL, + NULL +}; + +EFI_STATUS +EFIAPI +OhciInitialise ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, + SystemTable, + &gOhciDriverBinding, + ImageHandle, + &gOhciComponentName, + &gOhciComponentName2 + ); +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Ohci.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Ohci.h new file mode 100644 index 0000000..06a2b33 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/Ohci.h @@ -0,0 +1,668 @@ +/** @file +Provides the definition of Usb Hc Protocol and OHCI controller +private data structure. + +Copyright (c) 2013-2016 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + +#ifndef _OHCI_H +#define _OHCI_H + + +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +typedef struct _USB_OHCI_HC_DEV USB_OHCI_HC_DEV; + +#include "UsbHcMem.h" +#include "OhciReg.h" +#include "OhciSched.h" +#include "OhciUrb.h" +#include "Descriptor.h" +#include "OhciDebug.h" +#include "ComponentName.h" + +extern EFI_DRIVER_BINDING_PROTOCOL gOhciDriverBinding; +extern EFI_COMPONENT_NAME_PROTOCOL gOhciComponentName; +extern EFI_COMPONENT_NAME2_PROTOCOL gOhciComponentName2; + +#define USB_OHCI_HC_DEV_SIGNATURE SIGNATURE_32('o','h','c','i') + +typedef struct _HCCA_MEMORY_BLOCK{ + UINT32 HccaInterruptTable[32]; // 32-bit Physical Address to ED_DESCRIPTOR + UINT16 HccaFrameNumber; + UINT16 HccaPad; + UINT32 HccaDoneHead; // 32-bit Physical Address to TD_DESCRIPTOR + UINT8 Reserved[116]; +} HCCA_MEMORY_BLOCK; + +typedef struct { + VENDOR_DEVICE_PATH Guid; + UINTN Instance; + EFI_DEVICE_PATH_PROTOCOL End; +} OHCI_DEVICE_PATH; + +struct _USB_OHCI_HC_DEV { + UINTN Signature; + EFI_USB_HC_PROTOCOL UsbHc; + EFI_USB2_HC_PROTOCOL Usb2Hc; + UINT32 UsbHcBaseAddress; + HCCA_MEMORY_BLOCK *HccaMemoryBlock; + VOID *HccaMemoryBuf; + VOID *HccaMemoryMapping; + UINTN HccaMemoryPages; + ED_DESCRIPTOR *IntervalList[6][32]; + INTERRUPT_CONTEXT_ENTRY *InterruptContextList; + VOID *MemPool; + + UINT32 ToggleFlag; + + EFI_EVENT HouseKeeperTimer; + // + // ExitBootServicesEvent is used to stop the OHC DMA operation + // after exit boot service. + // + EFI_EVENT ExitBootServiceEvent; + + EFI_UNICODE_STRING_TABLE *ControllerNameTable; + + OHCI_DEVICE_PROTOCOL *Protocol; +}; + +#define USB_OHCI_HC_DEV_FROM_THIS(a) CR(a, USB_OHCI_HC_DEV, UsbHc, USB_OHCI_HC_DEV_SIGNATURE) + +// +// Func List +// + +/** + Provides software reset for the USB host controller. + + @param This This EFI_USB_HC_PROTOCOL instance. + @param Attributes A bit mask of the reset operation to perform. + + @retval EFI_SUCCESS The reset operation succeeded. + @retval EFI_INVALID_PARAMETER Attributes is not valid. + @retval EFI_UNSUPPOURTED The type of reset specified by Attributes is + not currently supported by the host controller. + @retval EFI_DEVICE_ERROR Host controller isn't halted to reset. + +**/ +EFI_STATUS +EFIAPI +OhciReset ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT16 Attributes + ); +/** + Retrieve the current state of the USB host controller. + + @param This This EFI_USB_HC_PROTOCOL instance. + @param State Variable to return the current host controller + state. + + @retval EFI_SUCCESS Host controller state was returned in State. + @retval EFI_INVALID_PARAMETER State is NULL. + @retval EFI_DEVICE_ERROR An error was encountered while attempting to + retrieve the host controller's current state. + +**/ + +EFI_STATUS +EFIAPI +OhciGetState ( + IN EFI_USB_HC_PROTOCOL *This, + OUT EFI_USB_HC_STATE *State + ); +/** + Sets the USB host controller to a specific state. + + @param This This EFI_USB_HC_PROTOCOL instance. + @param State The state of the host controller that will be set. + + @retval EFI_SUCCESS The USB host controller was successfully placed + in the state specified by State. + @retval EFI_INVALID_PARAMETER State is invalid. + @retval EFI_DEVICE_ERROR Failed to set the state due to device error. + +**/ + +EFI_STATUS +EFIAPI +OhciSetState( + IN EFI_USB_HC_PROTOCOL *This, + IN EFI_USB_HC_STATE State + ); +/** + + Submits control transfer to a target USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param IsSlowDevice Indicates whether the target device is slow device + or full-speed device. + @param MaxPaketLength Indicates the maximum packet size that the + default control transfer endpoint is capable of + sending or receiving. + @param Request A pointer to the USB device request that will be sent + to the USB device. + @param TransferDirection Specifies the data direction for the transfer. + There are three values available, DataIn, DataOut + and NoData. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param DataLength Indicates the size, in bytes, of the data buffer + specified by Data. + @param TimeOut Indicates the maximum time, in microseconds, + which the transfer is allowed to complete. + @param TransferResult A pointer to the detailed result information generated + by this control transfer. + + @retval EFI_SUCCESS The control transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The control transfer could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The control transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The control transfer failed due to host controller or device error. + Caller should check TranferResult for detailed error information. + +--*/ + + +EFI_STATUS +EFIAPI +OhciControlTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxPacketLength, + IN EFI_USB_DEVICE_REQUEST *Request, + IN EFI_USB_DATA_DIRECTION TransferDirection, + IN OUT VOID *Data OPTIONAL, + IN OUT UINTN *DataLength OPTIONAL, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ); +/** + + Submits bulk transfer to a bulk endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an + endpoint direction of the target USB device. + Each endpoint address supports data transfer in + one direction except the control endpoint + (whose default endpoint address is 0). + It is the caller's responsibility to make sure that + the EndPointAddress represents a bulk endpoint. + @param MaximumPacketLength Indicates the maximum packet size the target endpoint + is capable of sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param DataLength When input, indicates the size, in bytes, of the data buffer + specified by Data. When output, indicates the actually + transferred data size. + @param DataToggle A pointer to the data toggle value. On input, it indicates + the initial data toggle value the bulk transfer should adopt; + on output, it is updated to indicate the data toggle value + of the subsequent bulk transfer. + @param TimeOut Indicates the maximum time, in microseconds, which the + transfer is allowed to complete. + TransferResult A pointer to the detailed result information of the + bulk transfer. + + @retval EFI_SUCCESS The bulk transfer was completed successfully. + @retval EFI_OUT_OF_RESOURCES The bulk transfer could not be submitted due to lack of resource. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_TIMEOUT The bulk transfer failed due to timeout. + @retval EFI_DEVICE_ERROR The bulk transfer failed due to host controller or device error. + Caller should check TranferResult for detailed error information. + +**/ + + +EFI_STATUS +EFIAPI +OhciBulkTransfer( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaxPacketLength, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN OUT UINT8 *DataToggle, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ); +/** + + Submits an interrupt transfer to an interrupt endpoint of a USB device. + + @param Ohc Device private data + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the + control endpoint (whose default endpoint address is 0). + It is the caller's responsibility to make sure that + the EndPointAddress represents an interrupt endpoint. + @param IsSlowDevice Indicates whether the target device is slow device + or full-speed device. + @param MaxPacketLength Indicates the maximum packet size the target endpoint + is capable of sending or receiving. + @param IsNewTransfer If TRUE, an asynchronous interrupt pipe is built between + the host and the target interrupt endpoint. + If FALSE, the specified asynchronous interrupt pipe + is canceled. + @param DataToggle A pointer to the data toggle value. On input, it is valid + when IsNewTransfer is TRUE, and it indicates the initial + data toggle value the asynchronous interrupt transfer + should adopt. + On output, it is valid when IsNewTransfer is FALSE, + and it is updated to indicate the data toggle value of + the subsequent asynchronous interrupt transfer. + @param PollingInterval Indicates the interval, in milliseconds, that the + asynchronous interrupt transfer is polled. + This parameter is required when IsNewTransfer is TRUE. + @param UCBuffer Uncacheable buffer + @param DataLength Indicates the length of data to be received at the + rate specified by PollingInterval from the target + asynchronous interrupt endpoint. This parameter + is only required when IsNewTransfer is TRUE. + @param CallBackFunction The Callback function.This function is called at the + rate specified by PollingInterval.This parameter is + only required when IsNewTransfer is TRUE. + @param Context The context that is passed to the CallBackFunction. + This is an optional parameter and may be NULL. + @param IsPeriodic Periodic interrupt or not + @param OutputED The correspoding ED carried out + @param OutputTD The correspoding TD carried out + + + @retval EFI_SUCCESS The asynchronous interrupt transfer request has been successfully + submitted or canceled. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ + +EFI_STATUS +OhciInterruptTransfer ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxPacketLength, + IN BOOLEAN IsNewTransfer, + IN OUT UINT8 *DataToggle OPTIONAL, + IN UINTN PollingInterval OPTIONAL, + IN VOID *UCBuffer OPTIONAL, + IN UINTN DataLength OPTIONAL, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction OPTIONAL, + IN VOID *Context OPTIONAL, + IN BOOLEAN IsPeriodic OPTIONAL, + OUT ED_DESCRIPTOR **OutputED OPTIONAL, + OUT TD_DESCRIPTOR **OutputTD OPTIONAL + ); +/** + + Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint address + supports data transfer in one direction except the + control endpoint (whose default endpoint address is 0). + It is the caller's responsibility to make sure that + the EndPointAddress represents an interrupt endpoint. + @param IsSlowDevice Indicates whether the target device is slow device + or full-speed device. + @param MaxiumPacketLength Indicates the maximum packet size the target endpoint + is capable of sending or receiving. + @param IsNewTransfer If TRUE, an asynchronous interrupt pipe is built between + the host and the target interrupt endpoint. + If FALSE, the specified asynchronous interrupt pipe + is canceled. + @param DataToggle A pointer to the data toggle value. On input, it is valid + when IsNewTransfer is TRUE, and it indicates the initial + data toggle value the asynchronous interrupt transfer + should adopt. + On output, it is valid when IsNewTransfer is FALSE, + and it is updated to indicate the data toggle value of + the subsequent asynchronous interrupt transfer. + @param PollingInterval Indicates the interval, in milliseconds, that the + asynchronous interrupt transfer is polled. + This parameter is required when IsNewTransfer is TRUE. + @param DataLength Indicates the length of data to be received at the + rate specified by PollingInterval from the target + asynchronous interrupt endpoint. This parameter + is only required when IsNewTransfer is TRUE. + @param CallBackFunction The Callback function.This function is called at the + rate specified by PollingInterval.This parameter is + only required when IsNewTransfer is TRUE. + @param Context The context that is passed to the CallBackFunction. + This is an optional parameter and may be NULL. + + @retval EFI_SUCCESS The asynchronous interrupt transfer request has been successfully + submitted or canceled. + @retval EFI_INVALID_PARAMETER Some parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + +**/ + + +EFI_STATUS +EFIAPI +OhciAsyncInterruptTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxPacketLength, + IN BOOLEAN IsNewTransfer, + IN OUT UINT8 *DataToggle OPTIONAL, + IN UINTN PollingInterval OPTIONAL, + IN UINTN DataLength OPTIONAL, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction OPTIONAL, + IN VOID *Context OPTIONAL + ); +/** + + Submits synchronous interrupt transfer to an interrupt endpoint + of a USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress The combination of an endpoint number and an endpoint + direction of the target USB device. Each endpoint + address supports data transfer in one direction + except the control endpoint (whose default + endpoint address is 0). It is the caller's responsibility + to make sure that the EndPointAddress represents + an interrupt endpoint. + @param IsSlowDevice Indicates whether the target device is slow device + or full-speed device. + @param MaxPacketLength Indicates the maximum packet size the target endpoint + is capable of sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param DataLength On input, the size, in bytes, of the data buffer specified + by Data. On output, the number of bytes transferred. + @param DataToggle A pointer to the data toggle value. On input, it indicates + the initial data toggle value the synchronous interrupt + transfer should adopt; + on output, it is updated to indicate the data toggle value + of the subsequent synchronous interrupt transfer. + @param TimeOut Indicates the maximum time, in microseconds, which the + transfer is allowed to complete. + @param TransferResult A pointer to the detailed result information from + the synchronous interrupt transfer. + + @retval EFI_UNSUPPORTED This interface not available. + @retval EFI_INVALID_PARAMETER Parameters not follow spec + +**/ + + +EFI_STATUS +EFIAPI +OhciSyncInterruptTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN BOOLEAN IsSlowDevice, + IN UINT8 MaxPacketLength, + IN OUT VOID *Data, + IN OUT UINTN *DataLength, + IN OUT UINT8 *DataToggle, + IN UINTN TimeOut, + OUT UINT32 *TransferResult + ); +/** + + Submits isochronous transfer to a target USB device. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress End point address + @param MaximumPacketLength Indicates the maximum packet size that the + default control transfer endpoint is capable of + sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param DataLength Indicates the size, in bytes, of the data buffer + specified by Data. + @param TransferResult A pointer to the detailed result information generated + by this control transfer. + + @retval EFI_UNSUPPORTED This interface not available + @retval EFI_INVALID_PARAMETER Data is NULL or DataLength is 0 or TransferResult is NULL + +**/ + + +EFI_STATUS +EFIAPI +OhciIsochronousTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaximumPacketLength, + IN OUT VOID *Data, + IN OUT UINTN DataLength, + OUT UINT32 *TransferResult + ); +/** + + Submits Async isochronous transfer to a target USB device. + + @param his A pointer to the EFI_USB_HC_PROTOCOL instance. + @param DeviceAddress Represents the address of the target device on the USB, + which is assigned during USB enumeration. + @param EndPointAddress End point address + @param MaximumPacketLength Indicates the maximum packet size that the + default control transfer endpoint is capable of + sending or receiving. + @param Data A pointer to the buffer of data that will be transmitted + to USB device or received from USB device. + @param IsochronousCallBack When the transfer complete, the call back function will be called + @param Context Pass to the call back function as parameter + + @retval EFI_UNSUPPORTED This interface not available + @retval EFI_INVALID_PARAMETER Data is NULL or Datalength is 0 + +**/ + +EFI_STATUS +EFIAPI +OhciAsyncIsochronousTransfer ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + IN UINT8 MaximumPacketLength, + IN OUT VOID *Data, + IN OUT UINTN DataLength, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK IsochronousCallBack, + IN VOID *Context OPTIONAL + ); + +/** + + Retrieves the number of root hub ports. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param NumOfPorts A pointer to the number of the root hub ports. + + @retval EFI_SUCCESS The port number was retrieved successfully. +**/ +EFI_STATUS +EFIAPI +OhciGetRootHubNumOfPorts ( + IN EFI_USB_HC_PROTOCOL *This, + OUT UINT8 *NumOfPorts + ); +/** + + Retrieves the current status of a USB root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL. + @param PortNumber Specifies the root hub port from which the status + is to be retrieved. This value is zero-based. For example, + if a root hub has two ports, then the first port is numbered 0, + and the second port is numbered 1. + @param PortStatus A pointer to the current port status bits and + port status change bits. + + @retval EFI_SUCCESS The status of the USB root hub port specified by PortNumber + was returned in PortStatus. + @retval EFI_INVALID_PARAMETER Port number not valid +**/ + + +EFI_STATUS +EFIAPI +OhciGetRootHubPortStatus ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + OUT EFI_USB_PORT_STATUS *PortStatus + ); + +/** + + Sets a feature for the specified root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL. + @param PortNumber Specifies the root hub port whose feature + is requested to be set. + @param PortFeature Indicates the feature selector associated + with the feature set request. + + @retval EFI_SUCCESS The feature specified by PortFeature was set for the + USB root hub port specified by PortNumber. + @retval EFI_DEVICE_ERROR Set feature failed because of hardware issue + @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid. +**/ +EFI_STATUS +EFIAPI +OhciSetRootHubPortFeature ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + IN EFI_USB_PORT_FEATURE PortFeature + ); +/** + + Clears a feature for the specified root hub port. + + @param This A pointer to the EFI_USB_HC_PROTOCOL instance. + @param PortNumber Specifies the root hub port whose feature + is requested to be cleared. + @param PortFeature Indicates the feature selector associated with the + feature clear request. + + @retval EFI_SUCCESS The feature specified by PortFeature was cleared for the + USB root hub port specified by PortNumber. + @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid. + @retval EFI_DEVICE_ERROR Some error happened when clearing feature +**/ +EFI_STATUS +EFIAPI +OhciClearRootHubPortFeature ( + IN EFI_USB_HC_PROTOCOL *This, + IN UINT8 PortNumber, + IN EFI_USB_PORT_FEATURE PortFeature + ); + + +/** + Test to see if this driver supports ControllerHandle. Any + ControllerHandle that has UsbHcProtocol installed will be supported. + + @param This Protocol instance pointer. + @param Controller Handle of device to test. + @param RemainingDevicePath Not used. + + @return EFI_SUCCESS This driver supports this device. + @return EFI_UNSUPPORTED This driver does not support this device. + +**/ +EFI_STATUS +EFIAPI + +OHCIDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ); + +/** + Starting the Usb OHCI Driver. + + @param This Protocol instance pointer. + @param Controller Handle of device to test. + @param RemainingDevicePath Not used. + + @retval EFI_SUCCESS This driver supports this device. + @retval EFI_UNSUPPORTED This driver does not support this device. + @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error. + EFI_OUT_OF_RESOURCES- Failed due to resource shortage. + +**/ +EFI_STATUS +EFIAPI +OHCIDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ); + +/** + Stop this driver on ControllerHandle. Support stopping any child handles + created by this driver. + + @param This Protocol instance pointer. + @param Controller Handle of device to stop driver on. + @param NumberOfChildren Number of Children in the ChildHandleBuffer. + @param ChildHandleBuffer List of handles for the children we need to stop. + + @return EFI_SUCCESS + @return others + +**/ +EFI_STATUS +EFIAPI +OHCIDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDebug.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDebug.c new file mode 100644 index 0000000..e467499 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDebug.c @@ -0,0 +1,85 @@ +/** @file +This file provides the information dump support for OHCI when in debug mode. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "Ohci.h" + + +/*++ + + Print the data of ED and the TDs attached to the ED + + @param Uhc Pointer to OHCI private data + @param Ed Pointer to a ED to free + @param Td Pointer to the Td head + + @retval EFI_SUCCESS ED + +**/ +EFI_STATUS +OhciDumpEdTdInfo ( + IN USB_OHCI_HC_DEV *Uhc, + IN ED_DESCRIPTOR *Ed, + IN TD_DESCRIPTOR *Td, + BOOLEAN Stage + ) +{ + UINT32 Index; + + if (Stage) { + DEBUG ((DEBUG_INFO, "\n Before executing command\n")); + }else{ + DEBUG ((DEBUG_INFO, "\n after executing command\n")); + } + if (Ed != NULL) { + DEBUG ((DEBUG_INFO, "\nED Address:%p, ED buffer:\n", Ed)); + DEBUG ((DEBUG_INFO, "DWord0 :TD Tail :TD Head :Next ED\n")); + for (Index = 0; Index < sizeof (ED_DESCRIPTOR)/4; Index ++) { + DEBUG ((DEBUG_INFO, "%8x ", *((UINT32*)(Ed) + Index) )); + } + DEBUG ((DEBUG_INFO, "\nNext TD buffer:%p\n", Td)); + } + while (Td != NULL) { + if (Td->Word0.DirPID == TD_SETUP_PID) { + DEBUG ((DEBUG_INFO, "\nSetup PID ")); + }else if (Td->Word0.DirPID == TD_OUT_PID) { + DEBUG ((DEBUG_INFO, "\nOut PID ")); + }else if (Td->Word0.DirPID == TD_IN_PID) { + DEBUG ((DEBUG_INFO, "\nIn PID ")); + }else if (Td->Word0.DirPID == TD_NODATA_PID) { + DEBUG ((DEBUG_INFO, "\nNo data PID ")); + } + DEBUG ((DEBUG_INFO, "TD Address:%p, TD buffer:\n", Td)); + DEBUG ((DEBUG_INFO, "DWord0 :CuBuffer:Next TD :Buff End:Next TD :DataBuff:ActLength\n")); + for (Index = 0; Index < sizeof (TD_DESCRIPTOR)/4; Index ++) { + DEBUG ((DEBUG_INFO, "%8x ", *((UINT32*)(Td) + Index) )); + } + DEBUG ((DEBUG_INFO, "\nCurrent TD Data buffer(size%d)\n", (UINT32)Td->ActualSendLength)); + for (Index = 0; Index < Td->ActualSendLength; Index ++) { + DEBUG ((DEBUG_INFO, "%2x ", *(UINT8 *)(UINTN)(Td->DataBuffer + Index) )); + } + Td = (TD_DESCRIPTOR *)(UINTN)(Td->NextTDPointer); + } + DEBUG ((DEBUG_INFO, "\n TD buffer End\n")); + + return EFI_SUCCESS; +} + +VOID +OhciDumpReg ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + UINT32 Data; + for(int i=0;i < 22; i++){ + Data = MmioRead32 (Ohc->UsbHcBaseAddress + 0x04*i); + DEBUG ((DEBUG_INFO, "OhcDumpReg 0x%x = 0x%x\n",Ohc->UsbHcBaseAddress +0x04*i, Data)); + } +} + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDebug.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDebug.h new file mode 100644 index 0000000..97c89d1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDebug.h @@ -0,0 +1,46 @@ +/** @file +This file contains the definination for host controller +debug support routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + +/*++ + +Routine Description: + + Print the data of ED and the TDs attached to the ED + + @param Uhc Pointer to OHCI private data + @param Ed Pointer to a ED to free + @param Td Pointer to the Td head + + @retval EFI_SUCCESS ED + +**/ +EFI_STATUS +OhciDumpEdTdInfo ( + IN USB_OHCI_HC_DEV *Ohc, + IN ED_DESCRIPTOR *Ed, + IN TD_DESCRIPTOR *Td, + BOOLEAN Stage + ); + +/*++ + + Print the register data of ohci host controller + + @param Ohc Pointer to OHCI private data + +**/ + +VOID +OhciDumpReg ( + IN USB_OHCI_HC_DEV *Ohc + ); + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf new file mode 100644 index 0000000..a586a88 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf @@ -0,0 +1,77 @@ +## @file +# OHCI USB Host Controller UEFI Driver +# +# Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
    +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OhciDxe + FILE_GUID = 3914AE34-B946-11EC-9D33-F42A7DCB925D + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = OhciInitialise + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# +# +[Sources] + Descriptor.h + Ohci.c + Ohci.h + OhciSched.c + OhciSched.h + OhciReg.c + OhciReg.h + OhciUrb.c + OhciUrb.h + OhciDebug.c + OhciDebug.h + UsbHcMem.c + UsbHcMem.h + ComponentName.c + ComponentName.h + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + MemoryAllocationLib + BaseLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + BaseMemoryLib + DebugLib + PcdLib + ReportStatusCodeLib + RockchipPlatformLib + DmaLib + +[Guids] + gEfiEventExitBootServicesGuid ## SOMETIMES_CONSUMES ## Event + gEfiEndOfDxeEventGroupGuid + +[Protocols] + gOhciDeviceProtocolGuid ## TO_START + gEfiUsbHcProtocolGuid ## BY_START + +[Depex] + TRUE + +# +# [Event] +# ## +# # Periodic timer event for checking the result of interrupt transfer execution. +# # +# EVENT_TYPE_PERIODIC_TIMER ## CONSUMES +# diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciReg.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciReg.c new file mode 100644 index 0000000..8c4038f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciReg.c @@ -0,0 +1,1383 @@ +/** @file +The OHCI register operation routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "Ohci.h" + +/** + + Get OHCI operational reg value + + @param Offset Offset of the operational reg + + @retval Value of the register + +**/ +UINT32 +OhciGetOperationalReg ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Offset + ) +{ + UINT32 Value; + + Value = MmioRead32(Ohc->UsbHcBaseAddress + Offset); + + return Value; +} +/** + + Set OHCI operational reg value + + @param Offset Offset of the operational reg + @param Value Value to set + + @retval EFI_SUCCESS Value set to the reg + +**/ + + +EFI_STATUS +OhciSetOperationalReg ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Offset, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Status = MmioWrite32(Ohc->UsbHcBaseAddress + Offset, Value); + + return Status; +} +/** + + Get HcRevision reg value + + @retval Value of the register + +**/ + + +UINT32 +OhciGetHcRevision ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + return OhciGetOperationalReg (Ohc, HC_REVISION); +} +/** + + Set HcReset reg value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetHcReset ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Field, + IN UINT32 Value + ) +{ + HcRESET Reset; + + *(UINT32 *) &Reset = OhciGetOperationalReg (Ohc, USBHOST_OFFSET_UHCHR); + + if (Field & RESET_SYSTEM_BUS) { + Reset.FSBIR = Value; + } + + if (Field & RESET_HOST_CONTROLLER) { + Reset.FHR = Value; + } + + if (Field & RESET_CLOCK_GENERATION) { + Reset.CGR = Value; + } + + if (Field & RESET_SSE_GLOBAL) { + Reset.SSE = Value; + } + + if (Field & RESET_PSPL) { + Reset.PSPL = Value; + } + + if (Field & RESET_PCPL) { + Reset.PCPL = Value; + } + + if (Field & RESET_SSEP1) { + Reset.SSEP1 = Value; + } + + if (Field & RESET_SSEP2) { + Reset.SSEP2 = Value; + } + + if (Field & RESET_SSEP3) { + Reset.SSEP3 = Value; + } + + OhciSetOperationalReg (Ohc, USBHOST_OFFSET_UHCHR, *(UINT32 *) &Reset); + + return EFI_SUCCESS; +} + +/** + + Get specific field of HcReset reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetHcReset ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Field + ) +{ + HcRESET Reset; + UINT32 Value; + + + *(UINT32 *) &Reset = OhciGetOperationalReg (Ohc, USBHOST_OFFSET_UHCHR); + Value = 0; + + switch (Field) { + case RESET_SYSTEM_BUS: + Value = Reset.FSBIR; + break; + + case RESET_HOST_CONTROLLER: + Value = Reset.FHR; + break; + + case RESET_CLOCK_GENERATION: + Value = Reset.CGR; + break; + + case RESET_SSE_GLOBAL: + Value = Reset.SSE; + break; + + case RESET_PSPL: + Value = Reset.PSPL; + break; + + case RESET_PCPL: + Value = Reset.PCPL; + break; + + case RESET_SSEP1: + Value = Reset.SSEP1; + break; + + case RESET_SSEP2: + Value = Reset.SSEP2; + break; + + case RESET_SSEP3: + Value = Reset.SSEP3; + break; + + default: + ASSERT (FALSE); + } + + + return Value; +} + +/** + + Set HcControl reg value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetHcControl ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + HcCONTROL Control; + + + + *(UINT32 *) &Control = OhciGetOperationalReg (Ohc, HC_CONTROL); + + if (Field & CONTROL_BULK_RATIO) { + Control.ControlBulkRatio = Value; + } + + if (Field & HC_FUNCTIONAL_STATE) { + Control.FunctionalState = Value; + } + + if (Field & PERIODIC_ENABLE) { + Control.PeriodicEnable = Value; + } + + if (Field & CONTROL_ENABLE) { + Control.ControlEnable = Value; + } + + if (Field & ISOCHRONOUS_ENABLE) { + Control.IsochronousEnable = Value; + } + + if (Field & BULK_ENABLE) { + Control.BulkEnable = Value; + } + + if (Field & INTERRUPT_ROUTING) { + Control.InterruptRouting = Value; + } + + Status = OhciSetOperationalReg (Ohc, HC_CONTROL, *(UINT32 *) &Control); + + return Status; +} + + +/** + + Get specific field of HcControl reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + + +UINT32 +OhciGetHcControl ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + HcCONTROL Control; + + *(UINT32 *) &Control = OhciGetOperationalReg (Ohc, HC_CONTROL); + + switch (Field) { + case CONTROL_BULK_RATIO: + return Control.ControlBulkRatio; + break; + case PERIODIC_ENABLE: + return Control.PeriodicEnable; + break; + case CONTROL_ENABLE: + return Control.ControlEnable; + break; + case BULK_ENABLE: + return Control.BulkEnable; + break; + case ISOCHRONOUS_ENABLE: + return Control.IsochronousEnable; + break; + case HC_FUNCTIONAL_STATE: + return Control.FunctionalState; + break; + case INTERRUPT_ROUTING: + return Control.InterruptRouting; + break; + default: + ASSERT (FALSE); + } + + return 0; +} + +/** + + Set HcCommand reg value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetHcCommandStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + HcCOMMAND_STATUS CommandStatus; + + ZeroMem (&CommandStatus, sizeof (HcCOMMAND_STATUS)); + + if(Field & HC_RESET){ + CommandStatus.HcReset = Value; + } + + if(Field & CONTROL_LIST_FILLED){ + CommandStatus.ControlListFilled = Value; + } + + if(Field & BULK_LIST_FILLED){ + CommandStatus.BulkListFilled = Value; + } + + if(Field & CHANGE_OWNER_REQUEST){ + CommandStatus.ChangeOwnerRequest = Value; + } + + if(Field & SCHEDULE_OVERRUN_COUNT){ + CommandStatus.ScheduleOverrunCount = Value; + } + + Status = OhciSetOperationalReg (Ohc, HC_COMMAND_STATUS, *(UINT32 *) &CommandStatus); + + return Status; +} + +/** + + Get specific field of HcCommand reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetHcCommandStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + HcCOMMAND_STATUS CommandStatus; + + *(UINT32 *) &CommandStatus = OhciGetOperationalReg (Ohc, HC_COMMAND_STATUS); + + switch (Field){ + case HC_RESET: + return CommandStatus.HcReset; + break; + case CONTROL_LIST_FILLED: + return CommandStatus.ControlListFilled; + break; + case BULK_LIST_FILLED: + return CommandStatus.BulkListFilled; + break; + case CHANGE_OWNER_REQUEST: + return CommandStatus.ChangeOwnerRequest; + break; + case SCHEDULE_OVERRUN_COUNT: + return CommandStatus.ScheduleOverrunCount; + break; + default: + ASSERT (FALSE); + } + + return 0; +} + +/** + + Clear specific fields of Interrupt Status + + @param Ohc UHC private data + @param Field Field to clear + + @retval EFI_SUCCESS Fields cleared + +**/ + +EFI_STATUS +OhciClearInterruptStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + EFI_STATUS Status; + HcINTERRUPT_STATUS InterruptStatus; + + ZeroMem (&InterruptStatus, sizeof (HcINTERRUPT_STATUS)); + + if(Field & SCHEDULE_OVERRUN){ + InterruptStatus.SchedulingOverrun = 1; + } + + if(Field & WRITEBACK_DONE_HEAD){ + InterruptStatus.WriteBackDone = 1; + } + if(Field & START_OF_FRAME){ + InterruptStatus.Sof = 1; + } + + if(Field & RESUME_DETECT){ + InterruptStatus.ResumeDetected = 1; + } + + if(Field & UNRECOVERABLE_ERROR){ + InterruptStatus.UnrecoverableError = 1; + } + + if(Field & FRAME_NUMBER_OVERFLOW){ + InterruptStatus.FrameNumOverflow = 1; + } + + if(Field & ROOTHUB_STATUS_CHANGE){ + InterruptStatus.RHStatusChange = 1; + } + + if(Field & OWNERSHIP_CHANGE){ + InterruptStatus.OwnerChange = 1; + } + + Status = OhciSetOperationalReg (Ohc, HC_INTERRUPT_STATUS, *(UINT32 *) &InterruptStatus); + + return Status; +} + +/** + + Get fields of HcInterrupt reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetHcInterruptStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + HcINTERRUPT_STATUS InterruptStatus; + + *(UINT32 *) &InterruptStatus = OhciGetOperationalReg (Ohc, HC_INTERRUPT_STATUS); + + switch (Field){ + case SCHEDULE_OVERRUN: + return InterruptStatus.SchedulingOverrun; + break; + + case WRITEBACK_DONE_HEAD: + return InterruptStatus.WriteBackDone; + break; + + case START_OF_FRAME: + return InterruptStatus.Sof; + break; + + case RESUME_DETECT: + return InterruptStatus.ResumeDetected; + break; + + case UNRECOVERABLE_ERROR: + return InterruptStatus.UnrecoverableError; + break; + + case FRAME_NUMBER_OVERFLOW: + return InterruptStatus.FrameNumOverflow; + break; + + case ROOTHUB_STATUS_CHANGE: + return InterruptStatus.RHStatusChange; + break; + + case OWNERSHIP_CHANGE: + return InterruptStatus.OwnerChange; + break; + + default: + ASSERT (FALSE); + } + + return 0; +} + +/** + + Set Interrupt Control reg value + + @param Ohc UHC private data + @param StatEnable Enable or Disable + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetInterruptControl ( + IN USB_OHCI_HC_DEV *Ohc, + IN BOOLEAN StatEnable, + IN UINTN Field, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + HcINTERRUPT_CONTROL InterruptState; + + + ZeroMem (&InterruptState, sizeof (HcINTERRUPT_CONTROL)); + + if(Field & SCHEDULE_OVERRUN) { + InterruptState.SchedulingOverrunInt = Value; + } + + if(Field & WRITEBACK_DONE_HEAD) { + InterruptState.WriteBackDoneInt = Value; + } + if(Field & START_OF_FRAME) { + InterruptState.SofInt = Value; + } + + if(Field & RESUME_DETECT) { + InterruptState.ResumeDetectedInt = Value; + } + + if(Field & UNRECOVERABLE_ERROR) { + InterruptState.UnrecoverableErrorInt = Value; + } + + if(Field & FRAME_NUMBER_OVERFLOW) { + InterruptState.FrameNumOverflowInt = Value; + } + + if(Field & ROOTHUB_STATUS_CHANGE) { + InterruptState.RHStatusChangeInt = Value; + } + + if(Field & OWNERSHIP_CHANGE) { + InterruptState.OwnerChangedInt = Value; + } + + if(Field & MASTER_INTERRUPT) { + InterruptState.MasterInterruptEnable = Value; + } + + if (StatEnable) { + Status = OhciSetOperationalReg (Ohc, HC_INTERRUPT_ENABLE, *(UINT32 *) &InterruptState); + } else { + Status = OhciSetOperationalReg (Ohc, HC_INTERRUPT_DISABLE, *(UINT32 *) &InterruptState); + } + + return Status; +} + +/** + + Get field of HcInterruptControl reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetHcInterruptControl ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + HcINTERRUPT_CONTROL InterruptState; + + *(UINT32 *) &InterruptState = OhciGetOperationalReg (Ohc, HC_INTERRUPT_ENABLE); + + switch (Field){ + case SCHEDULE_OVERRUN: + return InterruptState.SchedulingOverrunInt; + break; + + case WRITEBACK_DONE_HEAD: + return InterruptState.WriteBackDoneInt; + break; + + case START_OF_FRAME: + return InterruptState.SofInt; + break; + + case RESUME_DETECT: + return InterruptState.ResumeDetectedInt; + break; + + case UNRECOVERABLE_ERROR: + return InterruptState.UnrecoverableErrorInt; + break; + + case FRAME_NUMBER_OVERFLOW: + return InterruptState.FrameNumOverflowInt; + break; + + case ROOTHUB_STATUS_CHANGE: + return InterruptState.RHStatusChangeInt; + break; + + case OWNERSHIP_CHANGE: + return InterruptState.OwnerChangedInt; + break; + + case MASTER_INTERRUPT: + return InterruptState.MasterInterruptEnable; + break; + + default: + ASSERT (FALSE); + } + + return 0; +} + +/** + + Set memory pointer of specific type + + @param Ohc UHC private data + @param PointerType Type of the pointer to set + @param Value Value to set + + @retval EFI_SUCCESS Memory pointer set + +**/ + +EFI_STATUS +OhciSetMemoryPointer( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 PointerType, + IN VOID *Value + ) +{ + EFI_STATUS Status; + UINT32 Verify; + + Status = OhciSetOperationalReg (Ohc, PointerType, (UINT32)(UINTN)Value); + + if (EFI_ERROR (Status)) { + return Status; + } + + Verify = OhciGetOperationalReg (Ohc, PointerType); + while (Verify != (UINT32)(UINTN) Value) { + gBS->Stall(1000); + Verify = OhciGetOperationalReg (Ohc, PointerType); + }; + + return Status; +} + +/** + + Get memory pointer of specific type + + @param Ohc UHC private data + @param PointerType Type of pointer + + @retval Memory pointer of the specific type + +**/ + +VOID * +OhciGetMemoryPointer ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 PointerType + ) +{ + + return (VOID *)(UINTN) OhciGetOperationalReg (Ohc, PointerType); +} + + +/** + + Set Frame Interval value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetFrameInterval ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + HcFRM_INTERVAL FrameInterval; + + + *(UINT32 *) &FrameInterval = OhciGetOperationalReg(Ohc, HC_FRM_INTERVAL); + + if (Field & FRAME_INTERVAL) { + FrameInterval.FrmIntervalToggle = !FrameInterval.FrmIntervalToggle; + FrameInterval.FrameInterval = Value; + } + + if (Field & FS_LARGEST_DATA_PACKET) { + FrameInterval.FSMaxDataPacket = Value; + } + + if (Field & FRMINT_TOGGLE) { + FrameInterval.FrmIntervalToggle = Value; + } + + Status = OhciSetOperationalReg ( + Ohc, + HC_FRM_INTERVAL, + *(UINT32 *) &FrameInterval + ); + + return Status; +} + + +/** + + Get field of frame interval reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetFrameInterval ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + HcFRM_INTERVAL FrameInterval; + + *(UINT32 *) &FrameInterval = OhciGetOperationalReg (Ohc, HC_FRM_INTERVAL); + + switch (Field){ + case FRAME_INTERVAL: + return FrameInterval.FrameInterval; + break; + + case FS_LARGEST_DATA_PACKET: + return FrameInterval.FSMaxDataPacket; + break; + + case FRMINT_TOGGLE: + return FrameInterval.FrmIntervalToggle; + break; + + default: + ASSERT (FALSE); + } + + return 0; +} + +/** + + Set Frame Remaining reg value + + @param Ohc UHC private data + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetFrameRemaining ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + HcFRAME_REMAINING FrameRemaining; + + + *(UINT32 *) &FrameRemaining = OhciGetOperationalReg (Ohc, HC_FRM_REMAINING); + + FrameRemaining.FrameRemaining = Value; + FrameRemaining.FrameRemainingToggle = !FrameRemaining.FrameRemainingToggle; + + Status = OhciSetOperationalReg (Ohc, HC_FRM_REMAINING, *(UINT32 *) &FrameRemaining); + + return Status; +} +/** + + Get value of frame remaining reg + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of frame remaining reg + +**/ +UINT32 +OhciGetFrameRemaining ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) + +{ + HcFRAME_REMAINING FrameRemaining; + + + *(UINT32 *) &FrameRemaining = OhciGetOperationalReg (Ohc, HC_FRM_REMAINING); + + switch (Field){ + case FRAME_REMAINING: + return FrameRemaining.FrameRemaining; + break; + + case FRAME_REMAIN_TOGGLE: + return FrameRemaining.FrameRemainingToggle; + break; + + default: + ASSERT (FALSE); + } + + return 0; +} + +/** + + Set frame number reg value + + @param Ohc UHC private data + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetFrameNumber( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + Status = OhciSetOperationalReg (Ohc, HC_FRM_NUMBER, Value); + + return Status; +} + +/** + + Get frame number reg value + + @param Ohc UHC private data + + @retval Value of frame number reg + +**/ + +UINT32 +OhciGetFrameNumber ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + return OhciGetOperationalReg(Ohc, HC_FRM_NUMBER); +} + +/** + + Set period start reg value + + @param Ohc UHC private data + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetPeriodicStart ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + + Status = OhciSetOperationalReg (Ohc, HC_PERIODIC_START, Value); + + return Status; +} + + +/** + + Get periodic start reg value + + @param Ohc UHC private data + + @param Value of periodic start reg + +**/ + +UINT32 +OhciGetPeriodicStart ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + return OhciGetOperationalReg(Ohc, HC_PERIODIC_START); +} + + +/** + + Set Ls Threshold reg value + + @param Ohc UHC private data + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetLsThreshold ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + + + Status = OhciSetOperationalReg (Ohc, HC_LS_THREASHOLD, Value); + + return Status; +} + + +/** + + Get Ls Threshold reg value + + @param Ohc UHC private data + + @retval Value of Ls Threshold reg + +**/ + +UINT32 +OhciGetLsThreshold ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + return OhciGetOperationalReg(Ohc, HC_LS_THREASHOLD); +} + +/** + + Set Root Hub Descriptor reg value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ +EFI_STATUS +OhciSetRootHubDescriptor ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field, + IN UINT32 Value + ) +{ + EFI_STATUS Status; + HcRH_DESC_A DescriptorA; + HcRH_DESC_B DescriptorB; + + + if (Field & (RH_DEV_REMOVABLE | RH_PORT_PWR_CTRL_MASK)) { + *(UINT32 *) &DescriptorB = OhciGetOperationalReg (Ohc, HC_RH_DESC_B); + + if(Field & RH_DEV_REMOVABLE) { + DescriptorB.DeviceRemovable = Value; + } + if(Field & RH_PORT_PWR_CTRL_MASK) { + DescriptorB.PortPowerControlMask = Value; + } + + Status = OhciSetOperationalReg (Ohc, HC_RH_DESC_B, *(UINT32 *) &DescriptorB); + + return Status; + } + + *(UINT32 *)&DescriptorA = OhciGetOperationalReg (Ohc, HC_RH_DESC_A); + + if(Field & RH_NUM_DS_PORTS) { + DescriptorA.NumDownStrmPorts = Value; + } + if(Field & RH_NO_PSWITCH) { + DescriptorA.NoPowerSwitch = Value; + } + if(Field & RH_PSWITCH_MODE) { + DescriptorA.PowerSwitchMode = Value; + } + if(Field & RH_DEVICE_TYPE) { + DescriptorA.DeviceType = Value; + } + if(Field & RH_OC_PROT_MODE) { + DescriptorA.OverCurrentProtMode = Value; + } + if(Field & RH_NOC_PROT) { + DescriptorA.NoOverCurrentProtMode = Value; + } + if(Field & RH_NO_POTPGT) { + DescriptorA.PowerOnToPowerGoodTime = Value; + } + + Status = OhciSetOperationalReg (Ohc, HC_RH_DESC_A, *(UINT32 *) &DescriptorA); + + return Status; +} + + +/** + + Get Root Hub Descriptor reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetRootHubDescriptor ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + HcRH_DESC_A DescriptorA; + HcRH_DESC_B DescriptorB; + + *(UINT32 *) &DescriptorA = OhciGetOperationalReg (Ohc, HC_RH_DESC_A); + *(UINT32 *) &DescriptorB = OhciGetOperationalReg (Ohc, HC_RH_DESC_B); + + switch (Field){ + case RH_DEV_REMOVABLE: + return DescriptorB.DeviceRemovable; + break; + + case RH_PORT_PWR_CTRL_MASK: + return DescriptorB.PortPowerControlMask; + break; + + case RH_NUM_DS_PORTS: + return DescriptorA.NumDownStrmPorts; + break; + + case RH_NO_PSWITCH: + return DescriptorA.NoPowerSwitch; + break; + + case RH_PSWITCH_MODE: + return DescriptorA.PowerSwitchMode; + break; + + case RH_DEVICE_TYPE: + return DescriptorA.DeviceType; + break; + + case RH_OC_PROT_MODE: + return DescriptorA.OverCurrentProtMode; + break; + + case RH_NOC_PROT: + return DescriptorA.NoOverCurrentProtMode; + break; + + case RH_NO_POTPGT: + return DescriptorA.PowerOnToPowerGoodTime; + break; + + default: + ASSERT (FALSE); + } + + return 0; +} + + +/** + + Set Root Hub Status reg value + + @param Ohc UHC private data + @param Field Field to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetRootHubStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + EFI_STATUS Status; + HcRH_STATUS RootHubStatus; + + + ZeroMem (&RootHubStatus, sizeof(HcRH_STATUS)); + + if(Field & RH_LOCAL_PSTAT){ + RootHubStatus.LocalPowerStat = 1; + } + if(Field & RH_OC_ID){ + RootHubStatus.OverCurrentIndicator = 1; + } + if(Field & RH_REMOTE_WK_ENABLE){ + RootHubStatus.DevRemoteWakeupEnable = 1; + } + if(Field & RH_LOCAL_PSTAT_CHANGE){ + RootHubStatus.LocalPowerStatChange = 1; + } + if(Field & RH_OC_ID_CHANGE){ + RootHubStatus.OverCurrentIndicatorChange = 1; + } + if(Field & RH_CLR_RMT_WK_ENABLE){ + RootHubStatus.ClearRemoteWakeupEnable = 1; + } + + Status = OhciSetOperationalReg (Ohc, HC_RH_STATUS, *(UINT32 *) &RootHubStatus); + + return Status; +} + + +/** + + Get Root Hub Status reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetRootHubStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ) +{ + HcRH_STATUS RootHubStatus; + + + *(UINT32 *) &RootHubStatus = OhciGetOperationalReg (Ohc, HC_RH_STATUS); + + switch (Field) { + case RH_LOCAL_PSTAT: + return RootHubStatus.LocalPowerStat; + break; + case RH_OC_ID: + return RootHubStatus.OverCurrentIndicator; + break; + case RH_REMOTE_WK_ENABLE: + return RootHubStatus.DevRemoteWakeupEnable; + break; + case RH_LOCAL_PSTAT_CHANGE: + return RootHubStatus.LocalPowerStatChange; + break; + case RH_OC_ID_CHANGE: + return RootHubStatus.OverCurrentIndicatorChange; + break; + case RH_CLR_RMT_WK_ENABLE: + return RootHubStatus.ClearRemoteWakeupEnable; + break; + default: + ASSERT (FALSE); + } + + return 0; +} + + +/** + + Set Root Hub Port Status reg value + + @param Ohc UHC private data + @param Index Index of the port + @param Field Field to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetRootHubPortStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Index, + IN UINTN Field + ) +{ + EFI_STATUS Status; + HcRHPORT_STATUS PortStatus; + + + ZeroMem (&PortStatus, sizeof(HcRHPORT_STATUS)); + + if (Field & RH_CLEAR_PORT_ENABLE) { + PortStatus.CurrentConnectStat = 1; + } + if (Field & RH_SET_PORT_ENABLE) { + PortStatus.EnableStat = 1; + } + if (Field & RH_SET_PORT_SUSPEND) { + PortStatus.SuspendStat = 1; + } + if (Field & RH_CLEAR_SUSPEND_STATUS) { + PortStatus.OCIndicator = 1; + } + if (Field & RH_SET_PORT_RESET) { + PortStatus.ResetStat = 1; + } + if (Field & RH_SET_PORT_POWER) { + PortStatus.PowerStat = 1; + } + if (Field & RH_CLEAR_PORT_POWER) { + PortStatus.LsDeviceAttached = 1; + } + if (Field & RH_CONNECT_STATUS_CHANGE) { + PortStatus.ConnectStatChange = 1; + } + if (Field & RH_PORT_ENABLE_STAT_CHANGE) { + PortStatus.EnableStatChange = 1; + } + if (Field & RH_PORT_SUSPEND_STAT_CHANGE) { + PortStatus.SuspendStatChange = 1; + } + if (Field & RH_OC_INDICATOR_CHANGE) { + PortStatus.OCIndicatorChange = 1; + } + if (Field & RH_PORT_RESET_STAT_CHANGE ) { + PortStatus.ResetStatChange = 1; + } + + Status = OhciSetOperationalReg (Ohc, HC_RH_PORT_STATUS + (Index * 4), *(UINT32 *) &PortStatus); + + return Status; +} + + +/** + + Get Root Hub Port Status reg value + + @param Ohc UHC private data + @param Index Index of the port + @param Field Field to get + + @retval Value of the field and index + +**/ + +UINT32 +OhciReadRootHubPortStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Index, + IN UINTN Field + ) +{ + HcRHPORT_STATUS PortStatus; + + *(UINT32 *) &PortStatus = OhciGetOperationalReg ( + Ohc, + HC_RH_PORT_STATUS + (Index * 4) + ); + + switch (Field){ + case RH_CURR_CONNECT_STAT: + return PortStatus.CurrentConnectStat; + break; + case RH_PORT_ENABLE_STAT: + return PortStatus.EnableStat; + break; + case RH_PORT_SUSPEND_STAT: + return PortStatus.SuspendStat; + break; + case RH_PORT_OC_INDICATOR: + return PortStatus.OCIndicator; + break; + case RH_PORT_RESET_STAT: + return PortStatus.ResetStat; + break; + case RH_PORT_POWER_STAT: + return PortStatus.PowerStat; + break; + case RH_LSDEVICE_ATTACHED: + return PortStatus.LsDeviceAttached; + break; + case RH_CONNECT_STATUS_CHANGE: + return PortStatus.ConnectStatChange; + break; + case RH_PORT_ENABLE_STAT_CHANGE: + return PortStatus.EnableStatChange; + break; + case RH_PORT_SUSPEND_STAT_CHANGE: + return PortStatus.SuspendStatChange; + break; + case RH_OC_INDICATOR_CHANGE: + return PortStatus.OCIndicatorChange; + break; + case RH_PORT_RESET_STAT_CHANGE: + return PortStatus.ResetStatChange; + break; + default: + ASSERT (FALSE); + } + + return 0; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciReg.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciReg.h new file mode 100644 index 0000000..6214e31 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciReg.h @@ -0,0 +1,920 @@ +/** @file +This file contains the definination for host controller +register operation routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + +#ifndef _OHCI_REG_H +#define _OHCI_REG_H + +#define HC_STATE_RESET 0x0 +#define HC_STATE_RESUME 0x1 +#define HC_STATE_OPERATIONAL 0x2 +#define HC_STATE_SUSPEND 0x3 + +#define PERIODIC_ENABLE 0x01 +#define ISOCHRONOUS_ENABLE 0x02 +#define CONTROL_ENABLE 0x04 +#define BULK_ENABLE 0x08 +#define CONTROL_BULK_RATIO 0x10 + +#define HC_FUNCTIONAL_STATE 0x20 +#define INTERRUPT_ROUTING 0x40 + +#define HC_RESET 0x01 +#define CONTROL_LIST_FILLED 0x02 +#define BULK_LIST_FILLED 0x04 +#define CHANGE_OWNER_REQUEST 0x08 + +#define SCHEDULE_OVERRUN_COUNT 0x10 + +#define SCHEDULE_OVERRUN 0x00001 +#define WRITEBACK_DONE_HEAD 0x00002 +#define START_OF_FRAME 0x00004 +#define RESUME_DETECT 0x00008 +#define UNRECOVERABLE_ERROR 0x00010 +#define FRAME_NUMBER_OVERFLOW 0x00020 +#define ROOTHUB_STATUS_CHANGE 0x00040 +#define OWNERSHIP_CHANGE 0x00080 + +#define MASTER_INTERRUPT 0x00400 + +#define CONTROL_HEAD 0x001 +#define BULK_HEAD 0x002 +#define DONE_HEAD 0x004 + +#define Hc_HCCA 0x001 +#define Hc_PERIODIC_CURRENT 0x002 +#define Hc_CONTOL_HEAD 0x004 +#define Hc_CONTROL_CURRENT_PTR 0x008 +#define Hc_BULK_HEAD 0x010 +#define Hc_BULK_CURRENT_PTR 0x020 +#define Hc_DONE_HEAD 0x040 + +#define FRAME_INTERVAL 0x008 +#define FS_LARGEST_DATA_PACKET 0x010 +#define FRMINT_TOGGLE 0x020 +#define FRAME_REMAINING 0x040 +#define FRAME_REMAIN_TOGGLE 0x080 + +#define RH_DESC_A 0x00001 +#define RH_DESC_B 0x00002 +#define RH_NUM_DS_PORTS 0x00004 +#define RH_NO_PSWITCH 0x00008 +#define RH_PSWITCH_MODE 0x00010 +#define RH_DEVICE_TYPE 0x00020 +#define RH_OC_PROT_MODE 0x00040 +#define RH_NOC_PROT 0x00080 +#define RH_POTPGT 0x00100 +#define RH_NO_POTPGT 0x00200 +#define RH_DEV_REMOVABLE 0x00400 +#define RH_PORT_PWR_CTRL_MASK 0x00800 + +#define RH_LOCAL_PSTAT 0x00001 +#define RH_OC_ID 0x00002 +#define RH_REMOTE_WK_ENABLE 0x00004 +#define RH_LOCAL_PSTAT_CHANGE 0x00008 +#define RH_OC_ID_CHANGE 0x00010 +#define RH_CLR_RMT_WK_ENABLE 0x00020 + +#define RH_CLEAR_PORT_ENABLE 0x0001 +#define RH_SET_PORT_ENABLE 0x0002 +#define RH_SET_PORT_SUSPEND 0x0004 +#define RH_CLEAR_SUSPEND_STATUS 0x0008 +#define RH_SET_PORT_RESET 0x0010 +#define RH_SET_PORT_POWER 0x0020 +#define RH_CLEAR_PORT_POWER 0x0040 +#define RH_CONNECT_STATUS_CHANGE 0x10000 +#define RH_PORT_ENABLE_STAT_CHANGE 0x20000 +#define RH_PORT_SUSPEND_STAT_CHANGE 0x40000 +#define RH_OC_INDICATOR_CHANGE 0x80000 +#define RH_PORT_RESET_STAT_CHANGE 0x100000 + +#define RH_CURR_CONNECT_STAT 0x0001 +#define RH_PORT_ENABLE_STAT 0x0002 +#define RH_PORT_SUSPEND_STAT 0x0004 +#define RH_PORT_OC_INDICATOR 0x0008 +#define RH_PORT_RESET_STAT 0x0010 +#define RH_PORT_POWER_STAT 0x0020 +#define RH_LSDEVICE_ATTACHED 0x0040 + +#define RESET_SYSTEM_BUS (1 << 0) +#define RESET_HOST_CONTROLLER (1 << 1) +#define RESET_CLOCK_GENERATION (1 << 2) +#define RESET_SSE_GLOBAL (1 << 5) +#define RESET_PSPL (1 << 6) +#define RESET_PCPL (1 << 7) +#define RESET_SSEP1 (1 << 9) +#define RESET_SSEP2 (1 << 10) +#define RESET_SSEP3 (1 << 11) + +#define ONE_SECOND 1000000 +#define ONE_MILLI_SEC 1000 +#define MAX_BYTES_PER_TD 0x1000 +#define MAX_RETRY_TIMES 100 +#define PORT_NUMBER_ON_MAINSTONE2 1 + + +// +// Operational Register Offsets +// + +// +// Command & Status Registers Offsets +// +#define HC_REVISION 0x00 +#define HC_CONTROL 0x04 +#define HC_COMMAND_STATUS 0x08 +#define HC_INTERRUPT_STATUS 0x0C +#define HC_INTERRUPT_ENABLE 0x10 +#define HC_INTERRUPT_DISABLE 0x14 + +// +// Memory Pointer Offsets +// +#define HC_HCCA 0x18 +#define HC_PERIODIC_CURRENT 0x1C +#define HC_CONTROL_HEAD 0x20 +#define HC_CONTROL_CURRENT_PTR 0x24 +#define HC_BULK_HEAD 0x28 +#define HC_BULK_CURRENT_PTR 0x2C +#define HC_DONE_HEAD 0x30 + +// +// Frame Register Offsets +// +#define HC_FRM_INTERVAL 0x34 +#define HC_FRM_REMAINING 0x38 +#define HC_FRM_NUMBER 0x3C +#define HC_PERIODIC_START 0x40 +#define HC_LS_THREASHOLD 0x44 + +// +// Root Hub Register Offsets +// +#define HC_RH_DESC_A 0x48 +#define HC_RH_DESC_B 0x4C +#define HC_RH_STATUS 0x50 +#define HC_RH_PORT_STATUS 0x54 + +#define USBHOST_OFFSET_UHCHR 0x64 // Usb Host reset register + +#define OHC_BAR_INDEX 0 + +// +// Usb Host controller register offset +// +#define USBHOST_OFFSET_UHCREV 0x0 // Usb Host revision register +#define USBHOST_OFFSET_UHCHCON 0x4 // Usb Host control register +#define USBHOST_OFFSET_UHCCOMS 0x8 // Usb Host Command Status register +#define USBHOST_OFFSET_UHCINTS 0xC // Usb Host Interrupt Status register +#define USBHOST_OFFSET_UHCINTE 0x10 // Usb Host Interrupt Enable register +#define USBHOST_OFFSET_UHCINTD 0x14 // Usb Host Interrupt Disable register +#define USBHOST_OFFSET_UHCHCCA 0x18 // Usb Host Controller Communication Area +#define USBHOST_OFFSET_UHCPCED 0x1C // Usb Host Period Current Endpoint Descriptor +#define USBHOST_OFFSET_UHCCHED 0x20 // Usb Host Control Head Endpoint Descriptor +#define USBHOST_OFFSET_UHCCCED 0x24 // Usb Host Control Current Endpoint Descriptor +#define USBHOST_OFFSET_UHCBHED 0x28 // Usb Host Bulk Head Endpoint Descriptor +#define USBHOST_OFFSET_UHCBCED 0x2C // Usb Host Bulk Current Endpoint Descriptor +#define USBHOST_OFFSET_UHCDHEAD 0x30 // Usb Host Done Head register +#define USBHOST_OFFSET_UHCFMI 0x34 // Usb Host Frame Interval register +#define USBHOST_OFFSET_UHCFMR 0x38 // Usb Host Frame Remaining register +#define USBHOST_OFFSET_UHCFMN 0x3C // Usb Host Frame Number register +#define USBHOST_OFFSET_UHCPERS 0x40 // Usb Host Periodic Start register +#define USBHOST_OFFSET_UHCLST 0x44 // Usb Host Low-Speed Threshold register +#define USBHOST_OFFSET_UHCRHDA 0x48 // Usb Host Root Hub Descriptor A register +#define USBHOST_OFFSET_UHCRHDB 0x4C // Usb Host Root Hub Descriptor B register +#define USBHOST_OFFSET_UHCRHS 0x50 // Usb Host Root Hub Status register +#define USBHOST_OFFSET_UHCRHPS1 0x54 // Usb Host Root Hub Port Status 1 register + +// +// Usb Host controller register bit fields +// +#pragma pack(1) + +typedef struct { + UINT8 ProgInterface; + UINT8 SubClassCode; + UINT8 BaseCode; +} USB_CLASSC; + +typedef struct { + UINT32 Revision:8; + UINT32 Rsvd:24; +} HcREVISION; + +typedef struct { + UINT32 ControlBulkRatio:2; + UINT32 PeriodicEnable:1; + UINT32 IsochronousEnable:1; + UINT32 ControlEnable:1; + UINT32 BulkEnable:1; + UINT32 FunctionalState:2; + UINT32 InterruptRouting:1; + UINT32 RemoteWakeup:1; + UINT32 RemoteWakeupEnable:1; + UINT32 Reserved:21; +} HcCONTROL; + +typedef struct { + UINT32 HcReset:1; + UINT32 ControlListFilled:1; + UINT32 BulkListFilled:1; + UINT32 ChangeOwnerRequest:1; + UINT32 Reserved1:12; + UINT32 ScheduleOverrunCount:2; + UINT32 Reserved:14; +} HcCOMMAND_STATUS; + +typedef struct { + UINT32 SchedulingOverrun:1; + UINT32 WriteBackDone:1; + UINT32 Sof:1; + UINT32 ResumeDetected:1; + UINT32 UnrecoverableError:1; + UINT32 FrameNumOverflow:1; + UINT32 RHStatusChange:1; + UINT32 Reserved1:23; + UINT32 OwnerChange:1; + UINT32 Reserved2:1; +} HcINTERRUPT_STATUS; + +typedef struct { + UINT32 SchedulingOverrunInt:1; + UINT32 WriteBackDoneInt:1; + UINT32 SofInt:1; + UINT32 ResumeDetectedInt:1; + UINT32 UnrecoverableErrorInt:1; + UINT32 FrameNumOverflowInt:1; + UINT32 RHStatusChangeInt:1; + UINT32 Reserved:23; + UINT32 OwnerChangedInt:1; + UINT32 MasterInterruptEnable:1; +} HcINTERRUPT_CONTROL; + +typedef struct { + UINT32 Rerserved:8; + UINT32 Hcca:24; +} HcHCCA; + +typedef struct { + UINT32 Reserved:4; + UINT32 MemoryPtr:28; +} HcMEMORY_PTR; + +typedef struct { + UINT32 FrameInterval:14; + UINT32 Reserved:2; + UINT32 FSMaxDataPacket:15; + UINT32 FrmIntervalToggle:1; +} HcFRM_INTERVAL; + +typedef struct { + UINT32 FrameRemaining:14; + UINT32 Reserved:17; + UINT32 FrameRemainingToggle:1; +} HcFRAME_REMAINING; + +typedef struct { + UINT32 FrameNumber:16; + UINT32 Reserved:16; +} HcFRAME_NUMBER; + +typedef struct { + UINT32 PeriodicStart:14; + UINT32 Reserved:18; +} HcPERIODIC_START; + +typedef struct { + UINT32 LsThreshold:12; + UINT32 Reserved:20; +} HcLS_THRESHOLD; + +typedef struct { + UINT32 NumDownStrmPorts:8; + UINT32 PowerSwitchMode:1; + UINT32 NoPowerSwitch:1; + UINT32 DeviceType:1; + UINT32 OverCurrentProtMode:1; + UINT32 NoOverCurrentProtMode:1; + UINT32 Reserved:11; + UINT32 PowerOnToPowerGoodTime:8; +} HcRH_DESC_A; + +typedef struct { + UINT32 DeviceRemovable:16; + UINT32 PortPowerControlMask:16; +} HcRH_DESC_B; + +typedef struct { + UINT32 LocalPowerStat:1; + UINT32 OverCurrentIndicator:1; + UINT32 Reserved1:13; + UINT32 DevRemoteWakeupEnable:1; + UINT32 LocalPowerStatChange:1; + UINT32 OverCurrentIndicatorChange:1; + UINT32 Reserved2:13; + UINT32 ClearRemoteWakeupEnable:1; +} HcRH_STATUS; + +typedef struct { + UINT32 CurrentConnectStat:1; + UINT32 EnableStat:1; + UINT32 SuspendStat:1; + UINT32 OCIndicator:1; + UINT32 ResetStat:1; + UINT32 Reserved1:3; + UINT32 PowerStat:1; + UINT32 LsDeviceAttached:1; + UINT32 Reserved2:6; + UINT32 ConnectStatChange:1; + UINT32 EnableStatChange:1; + UINT32 SuspendStatChange:1; + UINT32 OCIndicatorChange:1; + UINT32 ResetStatChange:1; + UINT32 Reserved3:11; +} HcRHPORT_STATUS; + +typedef struct { + UINT32 FSBIR:1; + UINT32 FHR:1; + UINT32 CGR:1; + UINT32 SSDC:1; + UINT32 UIT:1; + UINT32 SSE:1; + UINT32 PSPL:1; + UINT32 PCPL:1; + UINT32 Reserved0:1; + UINT32 SSEP1:1; + UINT32 SSEP2:1; + UINT32 SSEP3:1; + UINT32 Reserved1:20; +} HcRESET; + + +#pragma pack() + +// +// Func List +// + + +/** + + Get OHCI operational reg value + + @param PciIo PciIo protocol instance + @param Offset Offset of the operational reg + + @retval Value of the register + +**/ +UINT32 +OhciGetOperationalReg ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Offset + ); + +/** + + Set OHCI operational reg value + + @param PciIo PCI Bus Io protocol instance + @param Offset Offset of the operational reg + @param Value Value to set + + @retval EFI_SUCCESS Value set to the reg + +**/ + + +EFI_STATUS +OhciSetOperationalReg ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Offset, + IN UINT32 Value + ); + + +/** + + Get HcRevision reg value + + @param PciIo PCI Bus Io protocol instance + + @retval Value of the register + +**/ + + +UINT32 +OhciGetHcRevision ( + IN USB_OHCI_HC_DEV *Ohc + ); + +/** + + Set HcReset reg value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetHcReset ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Field, + IN UINT32 Value + ); +/** + + Get specific field of HcReset reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetHcReset ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Field + ); +/** + + Set HcControl reg value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetHcControl ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field, + IN UINT32 Value + ); + + +/** + + Get specific field of HcControl reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + + +UINT32 +OhciGetHcControl ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + + +/** + + Set HcCommand reg value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetHcCommandStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field, + IN UINT32 Value + ); + +/** + + Get specific field of HcCommand reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetHcCommandStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + +/** + + Clear specific fields of Interrupt Status + + @param Ohc UHC private data + @param Field Field to clear + + @retval EFI_SUCCESS Fields cleared + +**/ + +EFI_STATUS +OhciClearInterruptStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + +/** + + Get fields of HcInterrupt reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetHcInterruptStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + +/** + + Set Interrupt Control reg value + + @param Ohc UHC private data + @param StatEnable Enable or Disable + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetInterruptControl ( + IN USB_OHCI_HC_DEV *Ohc, + IN BOOLEAN StatEnable, + IN UINTN Field, + IN UINT32 Value + ); + +/** + + Get field of HcInterruptControl reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetHcInterruptControl ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + + +/** + + Set memory pointer of specific type + + @param Ohc UHC private data + @param PointerType Type of the pointer to set + @param Value Value to set + + @retval EFI_SUCCESS Memory pointer set + +**/ + +EFI_STATUS +OhciSetMemoryPointer( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 PointerType, + IN VOID *Value + ); + +/** + + Get memory pointer of specific type + + @param Ohc UHC private data + @param PointerType Type of pointer + + @retval Memory pointer of the specific type + +**/ + +VOID * +OhciGetMemoryPointer ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 PointerType + ); + +/** + + Set Frame Interval value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetFrameInterval ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field, + IN UINT32 Value + ); + + +/** + + Get field of frame interval reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetFrameInterval ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + + +/** + + Set Frame Remaining reg value + + @param Ohc UHC private data + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetFrameRemaining ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Value + ); + +/** + + Get value of frame remaining reg + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of frame remaining reg + +**/ +UINT32 +OhciGetFrameRemaining ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + +/** + + Set frame number reg value + + @param Ohc UHC private data + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetFrameNumber( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Value + ); + +/** + + Get frame number reg value + + @param Ohc UHC private data + + @retval Value of frame number reg + +**/ + +UINT32 +OhciGetFrameNumber ( + IN USB_OHCI_HC_DEV *Ohc + ); + + +/** + + Set period start reg value + + @param Ohc UHC private data + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetPeriodicStart ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Value + ); + + +/** + + Get periodic start reg value + + @param Ohc UHC private data + + @param Value of periodic start reg + +**/ + +UINT32 +OhciGetPeriodicStart ( + IN USB_OHCI_HC_DEV *Ohc + ); + + +/** + + Set Ls Threshold reg value + + @param Ohc UHC private data + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetLsThreshold ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Value + ); + +/** + + Get Ls Threshold reg value + + @param Ohc UHC private data + + @retval Value of Ls Threshold reg + +**/ + +UINT32 +OhciGetLsThreshold ( + IN USB_OHCI_HC_DEV *Ohc + ); + +/** + + Set Root Hub Descriptor reg value + + @param Ohc UHC private data + @param Field Field to set + @param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ +EFI_STATUS +OhciSetRootHubDescriptor ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field, + IN UINT32 Value + ); + + +/** + + Get Root Hub Descriptor reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetRootHubDescriptor ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + +/** + + Set Root Hub Status reg value + + @param Ohc UHC private data + @param Field Field to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetRootHubStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + + +/** + + Get Root Hub Status reg value + + @param Ohc UHC private data + @param Field Field to get + + @retval Value of the field + +**/ + +UINT32 +OhciGetRootHubStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINTN Field + ); + + +/** + + Set Root Hub Port Status reg value + + @param Ohc UHC private data + @param Index Index of the port + @param Field Field to set + + @retval EFI_SUCCESS Value set + +**/ + +EFI_STATUS +OhciSetRootHubPortStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Index, + IN UINTN Field + ); + + +/** + + Get Root Hub Port Status reg value + + @param Ohc UHC private data + @param Index Index of the port + @param Field Field to get + + @retval Value of the field and index + +**/ + +UINT32 +OhciReadRootHubPortStatus ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Index, + IN UINTN Field + ); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciSched.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciSched.c new file mode 100644 index 0000000..8aee833 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciSched.c @@ -0,0 +1,531 @@ +/** @file +OHCI transfer scheduling routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "Ohci.h" + +/** + + Add an item of interrupt context + + @param Ohc UHC private data + @param NewEntry New entry to add + + @retval EFI_SUCCESS Item successfully added + +**/ +EFI_STATUS +OhciAddInterruptContextEntry ( + IN USB_OHCI_HC_DEV *Ohc, + IN INTERRUPT_CONTEXT_ENTRY *NewEntry + ) +{ + INTERRUPT_CONTEXT_ENTRY *Entry; + EFI_TPL OriginalTPL; + + OriginalTPL = gBS->RaiseTPL (TPL_NOTIFY); + + if (Ohc->InterruptContextList == NULL) { + Ohc->InterruptContextList = NewEntry; + } else { + Entry = Ohc->InterruptContextList; + while (Entry->NextEntry != NULL) { + Entry = Entry->NextEntry; + } + Entry->NextEntry = NewEntry; + } + + gBS->RestoreTPL (OriginalTPL); + + return EFI_SUCCESS; +} + + +/** + + Free a interrupt context entry + + @param Ohc UHC private data + @param Entry Pointer to an interrupt context entry + + @retval EFI_SUCCESS Entry freed + @retval EFI_INVALID_PARAMETER Entry is NULL + +**/ +EFI_STATUS +OhciFreeInterruptContextEntry ( + IN USB_OHCI_HC_DEV *Ohc, + IN INTERRUPT_CONTEXT_ENTRY *Entry + ) +{ + TD_DESCRIPTOR *Td; + if (Entry == NULL) { + return EFI_INVALID_PARAMETER; + } + if (Entry->UCBufferMapping != NULL) { + DmaUnmap(Entry->UCBufferMapping); + } + if (Entry->UCBuffer != NULL) { + UINTN Pages = EFI_SIZE_TO_PAGES (Entry->DataLength); + DmaFreeBuffer (Pages, Entry->UCBuffer); + } + while (Entry->DataTd) { + Td = Entry->DataTd; + Entry->DataTd = (TD_DESCRIPTOR *)(UINTN)(Entry->DataTd->NextTDPointer); + UsbHcFreeMem(Ohc->MemPool, Td, sizeof(TD_DESCRIPTOR)); + } + FreePool(Entry); + return EFI_SUCCESS; +} + + +/** + + Free entries match the device address and endpoint address + + @Param Ohc UHC private date + @Param DeviceAddress Item to free must match this device address + @Param EndPointAddress Item to free must match this end point address + @Param DataToggle DataToggle for output + + @retval EFI_SUCCESS Items match the requirement removed + +**/ +EFI_STATUS +OhciFreeInterruptContext( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + OUT UINT8 *DataToggle + ) +{ + INTERRUPT_CONTEXT_ENTRY *Entry; + INTERRUPT_CONTEXT_ENTRY *TempEntry; + EFI_TPL OriginalTPL; + + + OriginalTPL = gBS->RaiseTPL (TPL_NOTIFY); + + while (Ohc->InterruptContextList != NULL && + Ohc->InterruptContextList->DeviceAddress == DeviceAddress && + Ohc->InterruptContextList->EndPointAddress == EndPointAddress) { + TempEntry = Ohc->InterruptContextList; + Ohc->InterruptContextList = Ohc->InterruptContextList->NextEntry; + if (DataToggle != NULL) { + *DataToggle = (UINT8) (TempEntry->DataTd->Word0.DataToggle & 0x1); + } + OhciFreeInterruptContextEntry (Ohc, TempEntry); + } + + Entry = Ohc->InterruptContextList; + if (Entry == NULL) { + gBS->RestoreTPL (OriginalTPL); + return EFI_SUCCESS; + } + while (Entry->NextEntry != NULL) { + if (Entry->NextEntry->DeviceAddress == DeviceAddress && + Entry->NextEntry->EndPointAddress == EndPointAddress) { + TempEntry = Entry->NextEntry; + Entry->NextEntry = Entry->NextEntry->NextEntry; + if (DataToggle != NULL) { + *DataToggle = (UINT8) (TempEntry->DataTd->Word0.DataToggle & 0x1); + } + OhciFreeInterruptContextEntry (Ohc, TempEntry); + } else { + Entry = Entry->NextEntry; + } + } + + gBS->RestoreTPL (OriginalTPL); + + return EFI_SUCCESS; +} + + +/** + + Convert Error code from OHCI format to EFI format + + @Param ErrorCode ErrorCode in OHCI format + + @retval ErrorCode in EFI format + +**/ +UINT32 +ConvertErrorCode ( + IN UINT32 ErrorCode + ) +{ + UINT32 TransferResult; + + switch (ErrorCode) { + case TD_NO_ERROR: + TransferResult = EFI_USB_NOERROR; + break; + + case TD_TOBE_PROCESSED: + case TD_TOBE_PROCESSED_2: + TransferResult = EFI_USB_ERR_NOTEXECUTE; + break; + + case TD_DEVICE_STALL: + TransferResult = EFI_USB_ERR_STALL; + break; + + case TD_BUFFER_OVERRUN: + case TD_BUFFER_UNDERRUN: + TransferResult = EFI_USB_ERR_BUFFER; + break; + + case TD_CRC_ERROR: + TransferResult = EFI_USB_ERR_CRC; + break; + + case TD_NO_RESPONSE: + TransferResult = EFI_USB_ERR_TIMEOUT; + break; + + case TD_BITSTUFFING_ERROR: + TransferResult = EFI_USB_ERR_BITSTUFF; + break; + + default: + TransferResult = EFI_USB_ERR_SYSTEM; + } + + return TransferResult; +} + + +/** + + Check TDs Results + + @Param Ohc UHC private data + @Param Td TD_DESCRIPTOR + @Param Result Result to return + + @retval TRUE means OK + @retval FLASE means Error or Short packet + +**/ +BOOLEAN +OhciCheckTDsResults ( + IN USB_OHCI_HC_DEV *Ohc, + IN TD_DESCRIPTOR *Td, + OUT UINT32 *Result + ) +{ + UINT32 TdCompletionCode; + + *Result = EFI_USB_NOERROR; + + while (Td) { + TdCompletionCode = Td->Word0.ConditionCode; + + *Result |= ConvertErrorCode(TdCompletionCode); + // + // if any error encountered, stop processing the left TDs. + // + if (*Result) { + return FALSE; + } + + Td = (TD_DESCRIPTOR *)(UINTN)(Td->NextTDPointer); + } + return TRUE; + +} + + +/** + + Check the task status on an ED + + @Param Ed Pointer to the ED task that TD hooked on + @Param HeadTd TD header for current transaction + + @retval Task Status Code + +**/ + +UINT32 +CheckEDStatus ( + IN ED_DESCRIPTOR *Ed, + IN TD_DESCRIPTOR *HeadTd, + OUT OHCI_ED_RESULT *EdResult + ) +{ + while(HeadTd != NULL) { + if (HeadTd->NextTDPointer == 0) { + return TD_NO_ERROR; + } + if (HeadTd->Word0.ConditionCode != 0) { + return HeadTd->Word0.ConditionCode; + } + EdResult->NextToggle = ((UINT8)(HeadTd->Word0.DataToggle) & BIT0) ^ BIT0; + HeadTd = (TD_DESCRIPTOR *)(UINTN)(HeadTd->NextTDPointer); + } + if (OhciGetEDField (Ed, ED_TDHEAD_PTR) != OhciGetEDField (Ed, ED_TDTAIL_PTR)) { + return TD_TOBE_PROCESSED; + } + return TD_NO_ERROR; +} + +/** + + Check the task status + + @Param Ohc UHC private data + @Param ListType Pipe type + @Param Ed Pointer to the ED task hooked on + @Param HeadTd Head of TD corresponding to the task + @Param ErrorCode return the ErrorCode + + @retval EFI_SUCCESS Task done + @retval EFI_NOT_READY Task on processing + @retval EFI_DEVICE_ERROR Some error occured + +**/ +EFI_STATUS +CheckIfDone ( + IN USB_OHCI_HC_DEV *Ohc, + IN DESCRIPTOR_LIST_TYPE ListType, + IN ED_DESCRIPTOR *Ed, + IN TD_DESCRIPTOR *HeadTd, + OUT OHCI_ED_RESULT *EdResult + ) +{ + EdResult->ErrorCode = TD_TOBE_PROCESSED; + + switch (ListType) { + case CONTROL_LIST: + if (OhciGetHcCommandStatus (Ohc, CONTROL_LIST_FILLED) != 0) { + return EFI_NOT_READY; + } + break; + case BULK_LIST: + if (OhciGetHcCommandStatus (Ohc, BULK_LIST_FILLED) != 0) { + return EFI_NOT_READY; + } + break; + default: + break; + } + + EdResult->ErrorCode = CheckEDStatus (Ed, HeadTd, EdResult); + + if (EdResult->ErrorCode == TD_NO_ERROR) { + return EFI_SUCCESS; + } else if (EdResult->ErrorCode == TD_TOBE_PROCESSED) { + return EFI_NOT_READY; + } else { + return EFI_DEVICE_ERROR; + } +} + + +/** + + Convert TD condition code to Efi Status + + @Param ConditionCode Condition code to convert + + @retval EFI_SUCCESS No error occured + @retval EFI_NOT_READY TD still on processing + @retval EFI_DEVICE_ERROR Error occured in processing TD + +**/ + +EFI_STATUS +OhciTDConditionCodeToStatus ( + IN UINT32 ConditionCode + ) +{ + if (ConditionCode == TD_NO_ERROR) { + return EFI_SUCCESS; + } + + if (ConditionCode == TD_TOBE_PROCESSED) { + return EFI_NOT_READY; + } + + return EFI_DEVICE_ERROR; +} + +/** + + Invoke callbacks hooked on done TDs + + @Param Entry Interrupt transfer transaction information data structure + @Param Context Ohc private data + +**/ + +VOID +OhciInvokeInterruptCallBack( + IN INTERRUPT_CONTEXT_ENTRY *Entry, + IN UINT32 Result +) +{ + //Generally speaking, Keyboard driver should not + //check the Keyboard buffer if an error happens, it will be robust + //if we NULLed the buffer once error happens + if (Result) { + Entry->CallBackFunction ( + NULL, + 0, + Entry->Context, + Result + ); + }else{ + Entry->CallBackFunction ( + (VOID *)(UINTN)(Entry->DataTd->DataBuffer), + Entry->DataTd->ActualSendLength, + Entry->Context, + Result + ); + } +} + + +/** + + Timer to submit periodic interrupt transfer, and invoke callbacks hooked on done TDs + + @param Event Event handle + @param Context Device private data + +**/ + +VOID +EFIAPI +OhciHouseKeeper ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + + USB_OHCI_HC_DEV *Ohc; + INTERRUPT_CONTEXT_ENTRY *Entry; + INTERRUPT_CONTEXT_ENTRY *PreEntry; + ED_DESCRIPTOR *Ed; + TD_DESCRIPTOR *DataTd; + TD_DESCRIPTOR *HeadTd; + + UINT8 Toggle; + EFI_TPL OriginalTPL; + UINT32 Result; + + Ohc = (USB_OHCI_HC_DEV *) Context; + OriginalTPL = gBS->RaiseTPL(TPL_NOTIFY); + + Entry = Ohc->InterruptContextList; + PreEntry = NULL; + + while(Entry != NULL) { + + OhciCheckTDsResults(Ohc, Entry->DataTd, &Result ); + if (((Result & EFI_USB_ERR_STALL) == EFI_USB_ERR_STALL) || + ((Result & EFI_USB_ERR_NOTEXECUTE) == EFI_USB_ERR_NOTEXECUTE)) { + PreEntry = Entry; + Entry = Entry->NextEntry; + continue; + } + + if (Entry->CallBackFunction != NULL) { + OhciInvokeInterruptCallBack (Entry, Result); + if (Ohc->InterruptContextList == NULL) { + gBS->RestoreTPL (OriginalTPL); + return; + } + } + if (Entry->IsPeriodic) { + + Ed = Entry->Ed; + HeadTd = Entry->DataTd; + DataTd = HeadTd; + Toggle = 0; + if (Result == EFI_USB_NOERROR) { + // + // Update toggle if there is no error, and re-submit the interrupt Ed&Tds + // + if ((Ed != NULL) && (DataTd != NULL)) { + Ed->Word0.Skip = 1; + } + // + // From hcir1_0a.pdf 4.2.2 + // ToggleCarry:This bit is the data toggle carry bit, + // Whenever a TD is retired, this bit is written to + // contain the last data toggle value(LSb of data Toggel + // file) from the retired TD. + // This field is not used for Isochronous Endpoints + // + if (Ed == NULL) { + return; + } + Toggle = (UINT8) OhciGetEDField (Ed, ED_DTTOGGLE); + while(DataTd != NULL) { + if (DataTd->NextTDPointer == 0) { + DataTd->Word0.DataToggle = 0; + break; + } else { + OhciSetTDField (DataTd, TD_DT_TOGGLE, Toggle); + } + DataTd = (TD_DESCRIPTOR *)(UINTN)(DataTd->NextTDPointer); + Toggle ^= 1; + } + // + // HC will only update DataToggle, ErrorCount, ConditionCode + // CurrentBufferPointer & NextTD, so we only need to update + // them once we want to active them again + // + DataTd = HeadTd; + while (DataTd != NULL) { + if (DataTd->NextTDPointer == 0) { + OhciSetTDField (DataTd, TD_ERROR_CNT | TD_COND_CODE | TD_CURR_BUFFER_PTR | TD_NEXT_PTR, 0); + break; + } + OhciSetTDField (DataTd, TD_ERROR_CNT, 0); + OhciSetTDField (DataTd, TD_COND_CODE, TD_TOBE_PROCESSED); + DataTd->NextTD = DataTd->NextTDPointer; + DataTd->CurrBufferPointer = DataTd->DataBuffer; + DataTd = (TD_DESCRIPTOR *)(UINTN)(DataTd->NextTDPointer); + } + // + // Active current Ed,Td + // + // HC will only update Halted, ToggleCarry & TDQueueHeadPointer, + // So we only need to update them once we want to active them again. + // + if ((Ed != NULL) && (DataTd != NULL)) { + Ed->Word2.TdHeadPointer = (UINT32)((UINTN)HeadTd>>4); + OhciSetEDField (Ed, ED_HALTED | ED_DTTOGGLE, 0); + Ed->Word0.Skip = 0; + } + } else { + return; + } + } else { + if (PreEntry == NULL) { + Ohc->InterruptContextList = Entry->NextEntry; + } else { + PreEntry = Entry; + PreEntry->NextEntry = Entry->NextEntry; + } + OhciFreeInterruptContextEntry (Ohc, PreEntry); + gBS->RestoreTPL (OriginalTPL); + return; + } + PreEntry = Entry; + Entry = Entry->NextEntry; + } + gBS->RestoreTPL (OriginalTPL); +} + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciSched.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciSched.h new file mode 100644 index 0000000..1c4114c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciSched.h @@ -0,0 +1,225 @@ +/** @file +This file contains the definination for host controller schedule routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + +#ifndef _OHCI_SCHED_H +#define _OHCI_SCHED_H + +#include "Descriptor.h" + +#define HCCA_MEM_SIZE 256 +#define GRID_SIZE 16 +#define GRID_SHIFT 4 + +typedef struct _INTERRUPT_CONTEXT_ENTRY INTERRUPT_CONTEXT_ENTRY; + +struct _INTERRUPT_CONTEXT_ENTRY{ + UINT8 DeviceAddress; + UINT8 EndPointAddress; + ED_DESCRIPTOR *Ed; + TD_DESCRIPTOR *DataTd; + BOOLEAN IsSlowDevice; + UINT8 MaxPacketLength; + UINTN PollingInterval; + EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction; + VOID *Context; + BOOLEAN IsPeriodic; + VOID *Buffer; + UINTN DataLength; + VOID *UCBuffer; + VOID *UCBufferMapping; + UINT8 *Toggle; + INTERRUPT_CONTEXT_ENTRY *NextEntry; +}; + + +typedef struct { + UINT32 ErrorCode; + UINT8 NextToggle; +} OHCI_ED_RESULT; + +/** + + Add an item of interrupt context + + @param Ohc UHC private data + @param NewEntry New entry to add + + @retval EFI_SUCCESS Item successfully added + +**/ +EFI_STATUS +OhciAddInterruptContextEntry ( + IN USB_OHCI_HC_DEV *Ohc, + IN INTERRUPT_CONTEXT_ENTRY *NewEntry + ); + +/** + + Free a interrupt context entry + + @param Ohc UHC private data + @param Entry Pointer to an interrupt context entry + + @retval EFI_SUCCESS Entry freed + @retval EFI_INVALID_PARAMETER Entry is NULL + +**/ +EFI_STATUS +OhciFreeInterruptContextEntry ( + IN USB_OHCI_HC_DEV *Ohc, + IN INTERRUPT_CONTEXT_ENTRY *Entry + ); + +/** + + Free entries match the device address and endpoint address + + @Param Ohc UHC private date + @Param DeviceAddress Item to free must match this device address + @Param EndPointAddress Item to free must match this end point address + @Param DataToggle DataToggle for output + + @retval EFI_SUCCESS Items match the requirement removed + +**/ +EFI_STATUS +OhciFreeInterruptContext( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT8 DeviceAddress, + IN UINT8 EndPointAddress, + OUT UINT8 *DataToggle + ); + + +/** + + Convert Error code from OHCI format to EFI format + + @Param ErrorCode ErrorCode in OHCI format + + @retval ErrorCode in EFI format + +**/ +UINT32 +ConvertErrorCode ( + IN UINT32 ErrorCode + ); + + +/** + + Check TDs Results + + @Param Ohc UHC private data + @Param Td TD_DESCRIPTOR + @Param Result Result to return + + @retval TRUE means OK + @retval FLASE means Error or Short packet + +**/ +BOOLEAN +OhciCheckTDsResults ( + IN USB_OHCI_HC_DEV *Ohc, + IN TD_DESCRIPTOR *Td, + OUT UINT32 *Result + ); +/** + + Check the task status on an ED + + @Param Ed Pointer to the ED task that TD hooked on + @Param HeadTd TD header for current transaction + + @retval Task Status Code + +**/ + +UINT32 +CheckEDStatus ( + IN ED_DESCRIPTOR *Ed, + IN TD_DESCRIPTOR *HeadTd, + OUT OHCI_ED_RESULT *EdResult + ); +/** + + Check the task status + + @Param Ohc UHC private data + @Param ListType Pipe type + @Param Ed Pointer to the ED task hooked on + @Param HeadTd Head of TD corresponding to the task + @Param ErrorCode return the ErrorCode + + @retval EFI_SUCCESS Task done + @retval EFI_NOT_READY Task on processing + @retval EFI_DEVICE_ERROR Some error occured + +**/ +EFI_STATUS +CheckIfDone ( + IN USB_OHCI_HC_DEV *Ohc, + IN DESCRIPTOR_LIST_TYPE ListType, + IN ED_DESCRIPTOR *Ed, + IN TD_DESCRIPTOR *HeadTd, + OUT OHCI_ED_RESULT *EdResult + ); + +/** + + Convert TD condition code to Efi Status + + @Param ConditionCode Condition code to convert + + @retval EFI_SUCCESS No error occured + @retval EFI_NOT_READY TD still on processing + @retval EFI_DEVICE_ERROR Error occured in processing TD + +**/ + +EFI_STATUS +OhciTDConditionCodeToStatus ( + IN UINT32 ConditionCode + ); + +/** + + Invoke callbacks hooked on done TDs + + @Param Entry Interrupt transfer transaction information data structure + @Param Context Ohc private data + +**/ + +VOID +OhciInvokeInterruptCallBack( + IN INTERRUPT_CONTEXT_ENTRY *Entry, + IN UINT32 Result +); + + +/** + + Timer to submit periodic interrupt transfer, and invoke callbacks hooked on done TDs + + @param Event Event handle + @param Context Device private data + +**/ + +VOID +EFIAPI +OhciHouseKeeper ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciUrb.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciUrb.c new file mode 100644 index 0000000..fb0b56a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciUrb.c @@ -0,0 +1,889 @@ +/** @file +This file contains URB request, each request is warpped in a +URB (Usb Request Block). + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + + +#include "Ohci.h" + + +/** + + Create a TD + + @Param Ohc UHC private data + + @retval TD structure pointer + +**/ +TD_DESCRIPTOR * +OhciCreateTD ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + TD_DESCRIPTOR *Td; + + Td = UsbHcAllocateMem(Ohc->MemPool, sizeof(TD_DESCRIPTOR)); + if (Td == NULL) { + DEBUG ((DEBUG_INFO, "STV allocate TD fail !\r\n")); + return NULL; + } + Td->CurrBufferPointer = 0; + Td->NextTD = 0; + Td->BufferEndPointer = 0; + Td->NextTDPointer = 0; + + return Td; +} + + +/** + + Free a TD + + @Param Ohc UHC private data + @Param Td Pointer to a TD to free + + @retval EFI_SUCCESS TD freed + +**/ +EFI_STATUS +OhciFreeTD ( + IN USB_OHCI_HC_DEV *Ohc, + IN TD_DESCRIPTOR *Td + ) +{ + if (Td == NULL) { + return EFI_SUCCESS; + } + UsbHcFreeMem(Ohc->MemPool, Td, sizeof(TD_DESCRIPTOR)); + + return EFI_SUCCESS; +} + + +/** + + Create a ED + + @Param Ohc Device private data + + @retval ED descriptor pointer + +**/ +ED_DESCRIPTOR * +OhciCreateED ( + USB_OHCI_HC_DEV *Ohc + ) +{ + ED_DESCRIPTOR *Ed; + Ed = UsbHcAllocateMem(Ohc->MemPool, sizeof (ED_DESCRIPTOR)); + if (Ed == NULL) { + DEBUG ((DEBUG_INFO, "STV allocate ED fail !\r\n")); + return NULL; + } + Ed->Word0.Skip = 1; + Ed->TdTailPointer = 0; + Ed->Word2.TdHeadPointer = 0; + Ed->NextED = 0; + + return Ed; +} + +/** + + Free a ED + + @Param Ohc UHC private data + @Param Ed Pointer to a ED to free + + @retval EFI_SUCCESS ED freed + +**/ + +EFI_STATUS +OhciFreeED ( + IN USB_OHCI_HC_DEV *Ohc, + IN ED_DESCRIPTOR *Ed + ) +{ + if (Ed == NULL) { + return EFI_SUCCESS; + } + UsbHcFreeMem(Ohc->MemPool, Ed, sizeof(ED_DESCRIPTOR)); + + return EFI_SUCCESS; +} + +/** + + Free ED + + @Param Ohc Device private data + @Param Ed Pointer to a ED to free + + @retval EFI_SUCCESS ED freed + +**/ +EFI_STATUS +OhciFreeAllTDFromED ( + IN USB_OHCI_HC_DEV *Ohc, + IN ED_DESCRIPTOR *Ed + ) +{ + TD_DESCRIPTOR *HeadTd; + TD_DESCRIPTOR *TailTd; + TD_DESCRIPTOR *Td; + TD_DESCRIPTOR *TempTd; + + if (Ed == NULL) { + return EFI_SUCCESS; + } + + HeadTd = TD_PTR (Ed->Word2.TdHeadPointer); + TailTd = (TD_DESCRIPTOR *)(UINTN)(Ed->TdTailPointer); + + Td = HeadTd; + while (Td != TailTd) { + TempTd = Td; + Td = (TD_DESCRIPTOR *)(UINTN)(Td->NextTDPointer); + OhciFreeTD (Ohc, TempTd); + } + + return EFI_SUCCESS; +} + +/** + + Find a working ED match the requirement + + @Param EdHead Head of the ED list + @Param DeviceAddress Device address to search + @Param EndPointNum End point num to search + @Param EdDir ED Direction to search + + @retval ED descriptor searched + +**/ + +ED_DESCRIPTOR * +OhciFindWorkingEd ( + IN ED_DESCRIPTOR *EdHead, + IN UINT8 DeviceAddress, + IN UINT8 EndPointNum, + IN UINT8 EdDir + ) +{ + ED_DESCRIPTOR *Ed; + + for (Ed = EdHead; Ed != NULL; Ed = (ED_DESCRIPTOR *)(UINTN)(Ed->NextED)) { + if (Ed->Word2.Halted == 0 && Ed->Word0.Skip == 0 && + Ed->Word0.FunctionAddress == DeviceAddress && Ed->Word0.EndPointNum == EndPointNum && + Ed->Word0.Direction == EdDir) { + break; + } + } + + return Ed; +} + + +/** + + Initialize interrupt list. + + @Param Ohc Device private data + + @retval EFI_SUCCESS Initialization done + +**/ +EFI_STATUS +OhciInitializeInterruptList ( + USB_OHCI_HC_DEV *Ohc + ) +{ + static UINT32 Leaf[32] = {0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, + 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31}; + UINT32 *HccaInterruptTable; + UINTN Index; + UINTN Level; + UINTN Count; + ED_DESCRIPTOR *NewEd; + + HccaInterruptTable = Ohc->HccaMemoryBlock->HccaInterruptTable; + + for (Index = 0; Index < 32; Index++) { + NewEd = OhciCreateED (Ohc); + if (NewEd == NULL) { + return EFI_OUT_OF_RESOURCES; + } + HccaInterruptTable[Index] = (UINT32)(UINTN)NewEd; + } + + for (Index = 0; Index < 32; Index++) { + Ohc->IntervalList[0][Index] = (ED_DESCRIPTOR *)(UINTN)HccaInterruptTable[Leaf[Index]]; + } + + Count = 32; + for (Level = 1; Level <= 5; Level++) { + Count = Count >> 1; + + for (Index = 0; Index < Count; Index++) { + Ohc->IntervalList[Level][Index] = OhciCreateED (Ohc); + if (HccaInterruptTable[Index] == 0) { + return EFI_OUT_OF_RESOURCES; + } + Ohc->IntervalList[Level - 1][Index * 2 ]->NextED = (UINT32)(UINTN)Ohc->IntervalList[Level][Index]; + Ohc->IntervalList[Level - 1][Index * 2 + 1]->NextED = (UINT32)(UINTN)Ohc->IntervalList[Level][Index]; + } + } + + return EFI_SUCCESS; +} + +/** + + Attach an ED + + @Param Ed Ed to be attached + @Param NewEd Ed to attach + + @retval EFI_SUCCESS NewEd attached to Ed + @retval EFI_INVALID_PARAMETER Ed is NULL + +**/ +EFI_STATUS +OhciAttachED ( + IN ED_DESCRIPTOR *Ed, + IN ED_DESCRIPTOR *NewEd + ) +{ + ED_DESCRIPTOR *Temp; + + if (Ed == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Ed->NextED == 0){ + Ed->NextED = (UINT32)(UINTN)NewEd; + } else { + Temp = (ED_DESCRIPTOR *)(UINTN)(Ed->NextED); + Ed->NextED = (UINT32)(UINTN)NewEd; + NewEd->NextED = (UINT32)(UINTN)Temp; + } + + return EFI_SUCCESS; +} + + +/** + + Count ED number on a ED chain + + @Param Ed Head of the ED chain + + @retval ED number on the chain + +**/ + +UINTN +CountEdNum ( + IN ED_DESCRIPTOR *Ed + ) +{ + UINTN Count; + + Count = 0; + + while (Ed) { + Ed = (ED_DESCRIPTOR *)(UINTN)(Ed->NextED); + Count++; + } + + return Count; +} + +/** + + Find the minimal burn ED list on a specific depth level + + @Param Ohc Device private data + @Param Depth Depth level + + @retval ED list found + +**/ + +ED_DESCRIPTOR * +OhciFindMinInterruptEDList ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Depth + ) +{ + UINTN EdNum; + UINTN MinEdNum; + ED_DESCRIPTOR *TempEd; + ED_DESCRIPTOR *HeadEd; + UINTN Index; + + if (Depth > 5) { + return NULL; + } + + MinEdNum = 0xFFFFFFFF; + TempEd = NULL; + for (Index = 0; Index < (UINTN)(32 >> Depth); Index++) { + HeadEd = Ohc->IntervalList[Depth][Index]; + EdNum = CountEdNum (HeadEd); + if (EdNum < MinEdNum) { + MinEdNum = EdNum; + TempEd = HeadEd; + } + } + + ASSERT (TempEd != NULL); + + return TempEd; +} + + +/** + + Attach an ED to an ED list + + @Param OHC UHC private data + @Param ListType Type of the ED list + @Param Ed ED to attach + @Param EdList ED list to be attached + + @retval EFI_SUCCESS ED attached to ED list + +**/ +ED_DESCRIPTOR * +OhciAttachEDToList ( + IN USB_OHCI_HC_DEV *Ohc, + IN DESCRIPTOR_LIST_TYPE ListType, + IN ED_DESCRIPTOR *Ed, + IN ED_DESCRIPTOR *EdList + ) +{ + ED_DESCRIPTOR *HeadEd; + + HeadEd = NULL; + switch(ListType) { + case CONTROL_LIST: + HeadEd = (ED_DESCRIPTOR *) OhciGetMemoryPointer (Ohc, HC_CONTROL_HEAD); + if (HeadEd == NULL) { + OhciSetMemoryPointer (Ohc, HC_CONTROL_HEAD, Ed); + HeadEd = Ed; + } else { + OhciAttachED (HeadEd, Ed); + } + break; + + case BULK_LIST: + HeadEd = (ED_DESCRIPTOR *) OhciGetMemoryPointer (Ohc, HC_BULK_HEAD); + if (HeadEd == NULL) { + OhciSetMemoryPointer (Ohc, HC_BULK_HEAD, Ed); + HeadEd = Ed; + } else { + OhciAttachED (HeadEd, Ed); + } + break; + + case INTERRUPT_LIST: + OhciAttachED (EdList, Ed); + break; + + default: + ASSERT (FALSE); + } + + return HeadEd; +} + +/** + + Remove interrupt EDs that match requirement + + @Param Ohc UHC private data + @Param IntEd The address of Interrupt endpoint + + @retval EFI_SUCCESS EDs match requirement removed + +**/ + +EFI_STATUS +OhciFreeInterruptEdByEd ( + IN USB_OHCI_HC_DEV *Ohc, + IN ED_DESCRIPTOR *IntEd + ) +{ + ED_DESCRIPTOR *Ed; + ED_DESCRIPTOR *TempEd; + UINTN Index; + + if (IntEd == NULL) + return EFI_SUCCESS; + + for (Index = 0; Index < 32; Index++) { + Ed = (ED_DESCRIPTOR *)(UINTN)Ohc->HccaMemoryBlock->HccaInterruptTable[Index]; + if (Ed == NULL) { + continue; + } + while (Ed->NextED != 0) { + if (Ed->NextED == (UINT32)(UINTN)IntEd ) { + TempEd = (ED_DESCRIPTOR *)(UINTN)(Ed->NextED); + Ed->NextED = TempEd->NextED; + OhciFreeED (Ohc, TempEd); + } else { + Ed = (ED_DESCRIPTOR *)(UINTN)(Ed->NextED); + } + } + } + return EFI_SUCCESS; +} + +/** + + Remove interrupt EDs that match requirement + + @Param Ohc UHC private data + @Param FunctionAddress Requirement on function address + @Param EndPointNum Requirement on end point number + + @retval EFI_SUCCESS EDs match requirement removed + +**/ +EFI_STATUS +OhciFreeInterruptEdByAddr ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT8 FunctionAddress, + IN UINT8 EndPointNum + ) +{ + ED_DESCRIPTOR *Ed; + ED_DESCRIPTOR *TempEd; + UINTN Index; + + for (Index = 0; Index < 32; Index++) { + Ed = (ED_DESCRIPTOR *)(UINTN)Ohc->HccaMemoryBlock->HccaInterruptTable[Index]; + if (Ed == NULL) { + continue; + } + + while (Ed->NextED != 0) { + TempEd = (ED_DESCRIPTOR *)(UINTN)(Ed->NextED); + if (TempEd->Word0.FunctionAddress == FunctionAddress && + TempEd->Word0.EndPointNum == EndPointNum ) { + Ed->NextED = TempEd->NextED; + OhciFreeED (Ohc, TempEd); + } else { + Ed = (ED_DESCRIPTOR *)(UINTN)(Ed->NextED); + } + } + } + + return EFI_SUCCESS; +} + + +/** + + Link Td2 to the end of Td1 + + @Param Td1 TD to be linked + @Param Td2 TD to link + + @retval EFI_SUCCESS TD successfully linked + @retval EFI_INVALID_PARAMETER Td1 is NULL + +**/ +EFI_STATUS +OhciLinkTD ( + IN TD_DESCRIPTOR *Td1, + IN TD_DESCRIPTOR *Td2 + ) +{ + TD_DESCRIPTOR *TempTd; + + if (Td1 == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Td1 == Td2) { + return EFI_SUCCESS; + } + + TempTd = Td1; + while (TempTd->NextTD != 0) { + TempTd = (TD_DESCRIPTOR *)(UINTN)(TempTd->NextTD); + } + + TempTd->NextTD = (UINT32)(UINTN)Td2; + TempTd->NextTDPointer = (UINT32)(UINTN)Td2; + + return EFI_SUCCESS; +} + + +/** + + Attach TD list to ED + + @Param Ed ED which TD list attach on + @Param HeadTd Head of the TD list to attach + + @retval EFI_SUCCESS TD list attached on the ED + +**/ +EFI_STATUS +OhciAttachTDListToED ( + IN ED_DESCRIPTOR *Ed, + IN TD_DESCRIPTOR *HeadTd + ) +{ + TD_DESCRIPTOR *TempTd; + + TempTd = TD_PTR (Ed->Word2.TdHeadPointer); + + if (TempTd != NULL) { + while (TempTd->NextTD != 0) { + TempTd = (TD_DESCRIPTOR *)(UINTN)(TempTd->NextTD); + } + TempTd->NextTD = (UINT32)(UINTN)HeadTd; + TempTd->NextTDPointer = (UINT32)(UINTN)HeadTd; + } else { + Ed->Word2.TdHeadPointer = RIGHT_SHIFT_4 ((UINT32)(UINTN)HeadTd); + } + + return EFI_SUCCESS; +} + + +/** + + Set value to ED specific field + + @Param Ed ED to be set + @Param Field Field to be set + @Param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ +EFI_STATUS +OhciSetEDField ( + IN ED_DESCRIPTOR *Ed, + IN UINT32 Field, + IN UINT32 Value + ) +{ + if (Field & ED_FUNC_ADD) { + Ed->Word0.FunctionAddress = Value; + } + if (Field & ED_ENDPT_NUM) { + Ed->Word0.EndPointNum = Value; + } + if (Field & ED_DIR) { + Ed->Word0.Direction = Value; + } + if (Field & ED_SPEED) { + Ed->Word0.Speed = Value; + } + if (Field & ED_SKIP) { + Ed->Word0.Skip = Value; + } + if (Field & ED_FORMAT) { + Ed->Word0.Format = Value; + } + if (Field & ED_MAX_PACKET) { + Ed->Word0.MaxPacketSize = Value; + } + if (Field & ED_PDATA) { + Ed->Word0.FreeSpace = Value; + } + if (Field & ED_ZERO) { + Ed->Word2.Zero = Value; + } + if (Field & ED_TDTAIL_PTR) { + Ed->TdTailPointer = Value; + } + + if (Field & ED_HALTED) { + Ed->Word2.Halted = Value; + } + if (Field & ED_DTTOGGLE) { + Ed->Word2.ToggleCarry = Value; + } + if (Field & ED_TDHEAD_PTR) { + Ed->Word2.TdHeadPointer = RIGHT_SHIFT_4 (Value); + } + + if (Field & ED_NEXT_EDPTR) { + Ed->NextED = Value; + } + + return EFI_SUCCESS; +} + +/** + + Get value from an ED's specific field + + @Param Ed ED pointer + @Param Field Field to get value from + + @retval Value of the field + +**/ +UINT32 +OhciGetEDField ( + IN ED_DESCRIPTOR *Ed, + IN UINT32 Field + ) +{ + switch (Field) { + case ED_FUNC_ADD: + return Ed->Word0.FunctionAddress; + break; + case ED_ENDPT_NUM: + return Ed->Word0.EndPointNum; + break; + case ED_DIR: + return Ed->Word0.Direction; + break; + case ED_SPEED: + return Ed->Word0.Speed; + break; + case ED_SKIP: + return Ed->Word0.Skip; + break; + case ED_FORMAT: + return Ed->Word0.Format; + break; + case ED_MAX_PACKET: + return Ed->Word0.MaxPacketSize; + break; + + case ED_TDTAIL_PTR: + return Ed->TdTailPointer; + break; + + case ED_HALTED: + return Ed->Word2.Halted; + break; + + case ED_DTTOGGLE: + return Ed->Word2.ToggleCarry; + break; + + case ED_TDHEAD_PTR: + return Ed->Word2.TdHeadPointer << 4; + break; + + case ED_NEXT_EDPTR: + return Ed->NextED; + break; + + default: + ASSERT (FALSE); + } + + return 0; +} + + +/** + + Set value to TD specific field + + @Param Td TD to be set + @Param Field Field to be set + @Param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ +EFI_STATUS +OhciSetTDField ( + IN TD_DESCRIPTOR *Td, + IN UINT32 Field, + IN UINT32 Value + ) +{ + if (Field & TD_PDATA) { + Td->Word0.Reserved = Value; + } + if (Field & TD_BUFFER_ROUND) { + Td->Word0.BufferRounding = Value; + } + if (Field & TD_DIR_PID) { + Td->Word0.DirPID = Value; + } + if (Field & TD_DELAY_INT) { + Td->Word0.DelayInterrupt = Value; + } + if (Field & TD_DT_TOGGLE) { + Td->Word0.DataToggle = Value | 0x2; + } + if (Field & TD_ERROR_CNT) { + Td->Word0.ErrorCount = Value; + } + if (Field & TD_COND_CODE) { + Td->Word0.ConditionCode = Value; + } + + if (Field & TD_CURR_BUFFER_PTR) { + Td->CurrBufferPointer = Value; + } + + + if (Field & TD_NEXT_PTR) { + Td->NextTD = Value; + } + + if (Field & TD_BUFFER_END_PTR) { + Td->BufferEndPointer = Value; + } + + return EFI_SUCCESS; +} + + +/** + + Get value from ED specific field + + @Param Td TD pointer + @Param Field Field to get value from + + @retval Value of the field + +**/ + +UINT32 +OhciGetTDField ( + IN TD_DESCRIPTOR *Td, + IN UINT32 Field + ) +{ + switch (Field){ + case TD_BUFFER_ROUND: + return Td->Word0.BufferRounding; + break; + case TD_DIR_PID: + return Td->Word0.DirPID; + break; + case TD_DELAY_INT: + return Td->Word0.DelayInterrupt; + break; + case TD_DT_TOGGLE: + return Td->Word0.DataToggle; + break; + case TD_ERROR_CNT: + return Td->Word0.ErrorCount; + break; + case TD_COND_CODE: + return Td->Word0.ConditionCode; + break; + case TD_CURR_BUFFER_PTR: + return Td->CurrBufferPointer; + break; + + case TD_NEXT_PTR: + return Td->NextTD; + break; + + case TD_BUFFER_END_PTR: + return Td->BufferEndPointer; + break; + + default: + ASSERT (FALSE); + } + + return 0; +} + +/** + + Free the Ed,Td,buffer that were created during transferring + + @Param Ohc Device private data +**/ + +VOID +OhciFreeDynamicIntMemory( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + INTERRUPT_CONTEXT_ENTRY *Entry; + if (Ohc != NULL) { + while (Ohc->InterruptContextList != NULL) { + Entry = Ohc->InterruptContextList; + Ohc->InterruptContextList = Ohc->InterruptContextList->NextEntry; + OhciFreeInterruptEdByEd (Ohc, Entry->Ed); + OhciFreeInterruptContextEntry (Ohc, Entry); + } + } +} +/** + + Free the Ed that were initilized during driver was starting, + those memory were used as interrupt ED head + + @Param Ohc Device private data + + +**/ +VOID +OhciFreeFixedIntMemory ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + static UINT32 Leaf[] = {32,16,8,4,2,1}; + UINTN Index; + UINTN Level; + + for (Level = 0; Level < 6; Level++) { + for (Index = 0; Index < Leaf[Level]; Index++) { + if (Ohc->IntervalList[Level][Index] != NULL) { + UsbHcFreeMem(Ohc->MemPool, Ohc->IntervalList[Level][Index], sizeof(ED_DESCRIPTOR)); + } + } + } +} +/** + + Release all OHCI used memory when OHCI going to quit + + @Param Ohc Device private data + + @retval EFI_SUCCESS Memory released + +**/ + +EFI_STATUS +OhciFreeIntTransferMemory ( + IN USB_OHCI_HC_DEV *Ohc + ) +{ + // + // Free the Ed,Td,buffer that were created during transferring + // + OhciFreeDynamicIntMemory (Ohc); + // + // Free the Ed that were initilized during driver was starting + // + OhciFreeFixedIntMemory (Ohc); + return EFI_SUCCESS; +} + + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciUrb.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciUrb.h new file mode 100644 index 0000000..6bf2fe7 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/OhciUrb.h @@ -0,0 +1,387 @@ +/** @file +Provides some data struct used by OHCI controller driver. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _OHCI_URB_H +#define _OHCI_URB_H + +#include "Descriptor.h" + + +// +// Func List +// + + +/** + + Create a TD + + @Param Ohc UHC private data + + @retval TD structure pointer + +**/ +TD_DESCRIPTOR * +OhciCreateTD ( + IN USB_OHCI_HC_DEV *Ohc + ); + +/** + + Free a TD + + @Param Ohc UHC private data + @Param Td Pointer to a TD to free + + @retval EFI_SUCCESS TD freed + +**/ +EFI_STATUS +OhciFreeTD ( + IN USB_OHCI_HC_DEV *Ohc, + IN TD_DESCRIPTOR *Td + ); + +/** + + Create a ED + + @Param Ohc Device private data + + @retval ED descriptor pointer + +**/ +ED_DESCRIPTOR * +OhciCreateED ( + USB_OHCI_HC_DEV *Ohc + ); + + +/** + + Free a ED + + @Param Ohc UHC private data + @Param Ed Pointer to a ED to free + + @retval EFI_SUCCESS ED freed + +**/ + +EFI_STATUS +OhciFreeED ( + IN USB_OHCI_HC_DEV *Ohc, + IN ED_DESCRIPTOR *Ed + ); + +/** + + Free ED + + @Param Ohc Device private data + @Param Ed Pointer to a ED to free + + @retval EFI_SUCCESS ED freed + +**/ +EFI_STATUS +OhciFreeAllTDFromED ( + IN USB_OHCI_HC_DEV *Ohc, + IN ED_DESCRIPTOR *Ed + ); + +/** + + Find a working ED match the requirement + + @Param EdHead Head of the ED list + @Param DeviceAddress Device address to search + @Param EndPointNum End point num to search + @Param EdDir ED Direction to search + + @retval ED descriptor searched + +**/ + +ED_DESCRIPTOR * +OhciFindWorkingEd ( + IN ED_DESCRIPTOR *EdHead, + IN UINT8 DeviceAddress, + IN UINT8 EndPointNum, + IN UINT8 EdDir + ); + + +/** + + Initialize interrupt list. + + @Param Ohc Device private data + + @retval EFI_SUCCESS Initialization done + +**/ +EFI_STATUS +OhciInitializeInterruptList ( + USB_OHCI_HC_DEV *Ohc + ); + +/** + + Attach an ED + + @Param Ed Ed to be attached + @Param NewEd Ed to attach + + @retval EFI_SUCCESS NewEd attached to Ed + @retval EFI_INVALID_PARAMETER Ed is NULL + +**/ +EFI_STATUS +OhciAttachED ( + IN ED_DESCRIPTOR *Ed, + IN ED_DESCRIPTOR *NewEd + ); + +/** + + Count ED number on a ED chain + + @Param Ed Head of the ED chain + + @retval ED number on the chain + +**/ + +UINTN +CountEdNum ( + IN ED_DESCRIPTOR *Ed + ); + +/** + + Find the minimal burn ED list on a specific depth level + + @Param Ohc Device private data + @Param Depth Depth level + + @retval ED list found + +**/ + +ED_DESCRIPTOR * +OhciFindMinInterruptEDList ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT32 Depth + ); + +/** + + Attach an ED to an ED list + + @Param OHC UHC private data + @Param ListType Type of the ED list + @Param Ed ED to attach + @Param EdList ED list to be attached + + @retval EFI_SUCCESS ED attached to ED list + +**/ +ED_DESCRIPTOR * +OhciAttachEDToList ( + IN USB_OHCI_HC_DEV *Ohc, + IN DESCRIPTOR_LIST_TYPE ListType, + IN ED_DESCRIPTOR *Ed, + IN ED_DESCRIPTOR *EdList + ); + +/** + + Remove interrupt EDs that match requirement + + @Param Ohc UHC private data + @Param IntEd The address of Interrupt endpoint + + @retval EFI_SUCCESS EDs match requirement removed + +**/ + +EFI_STATUS +OhciFreeInterruptEdByEd ( + IN USB_OHCI_HC_DEV *Ohc, + IN ED_DESCRIPTOR *IntEd + ); + +/** + + Remove interrupt EDs that match requirement + + @Param Ohc UHC private data + @Param FunctionAddress Requirement on function address + @Param EndPointNum Requirement on end point number + + @retval EFI_SUCCESS EDs match requirement removed + +**/ +EFI_STATUS +OhciFreeInterruptEdByAddr ( + IN USB_OHCI_HC_DEV *Ohc, + IN UINT8 FunctionAddress, + IN UINT8 EndPointNum + ); + + +/** + + Link Td2 to the end of Td1 + + @Param Td1 TD to be linked + @Param Td2 TD to link + + @retval EFI_SUCCESS TD successfully linked + @retval EFI_INVALID_PARAMETER Td1 is NULL + +**/ +EFI_STATUS +OhciLinkTD ( + IN TD_DESCRIPTOR *Td1, + IN TD_DESCRIPTOR *Td2 + ); + + +/** + + Attach TD list to ED + + @Param Ed ED which TD list attach on + @Param HeadTd Head of the TD list to attach + + @retval EFI_SUCCESS TD list attached on the ED + +**/ +EFI_STATUS +OhciAttachTDListToED ( + IN ED_DESCRIPTOR *Ed, + IN TD_DESCRIPTOR *HeadTd + ); + + +/** + + Set value to ED specific field + + @Param Ed ED to be set + @Param Field Field to be set + @Param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ +EFI_STATUS +OhciSetEDField ( + IN ED_DESCRIPTOR *Ed, + IN UINT32 Field, + IN UINT32 Value + ); + + +/** + + Get value from an ED's specific field + + @Param Ed ED pointer + @Param Field Field to get value from + + @retval Value of the field + +**/ +UINT32 +OhciGetEDField ( + IN ED_DESCRIPTOR *Ed, + IN UINT32 Field + ); + + +/** + + Set value to TD specific field + + @Param Td TD to be set + @Param Field Field to be set + @Param Value Value to set + + @retval EFI_SUCCESS Value set + +**/ +EFI_STATUS +OhciSetTDField ( + IN TD_DESCRIPTOR *Td, + IN UINT32 Field, + IN UINT32 Value + ); + + +/** + + Get value from ED specific field + + @Param Td TD pointer + @Param Field Field to get value from + + @retval Value of the field + +**/ + +UINT32 +OhciGetTDField ( + IN TD_DESCRIPTOR *Td, + IN UINT32 Field + ); +/** + + Free the Ed,Td,buffer that were created during transferring + + @Param Ohc Device private data +**/ + +VOID +OhciFreeDynamicIntMemory( + IN USB_OHCI_HC_DEV *Ohc + ); + +/** + + Free the Ed that were initilized during driver was starting, + those memory were used as interrupt ED head + + @Param Ohc Device private data + + +**/ +VOID +OhciFreeFixedIntMemory ( + IN USB_OHCI_HC_DEV *Ohc + ); +/** + + Release all OHCI used memory when OHCI going to quit + + @Param Ohc Device private data + + @retval EFI_SUCCESS Memory released + +**/ + +EFI_STATUS +OhciFreeIntTransferMemory ( + IN USB_OHCI_HC_DEV *Ohc + ); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/UsbHcMem.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/UsbHcMem.c new file mode 100644 index 0000000..c70f7e6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/UsbHcMem.c @@ -0,0 +1,546 @@ +/** @file +Routine procedures for memory allocate/free. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include "Ohci.h" + + +/** + Allocate a block of memory to be used by the buffer pool. + + @param Pool The buffer pool to allocate memory for. + @param Pages How many pages to allocate. + + @return The allocated memory block or NULL if failed. + +**/ +USBHC_MEM_BLOCK * +UsbHcAllocMemBlock ( + IN USBHC_MEM_POOL *Pool, + IN UINTN Pages + ) +{ + USBHC_MEM_BLOCK *Block; + VOID *BufHost; + VOID *Mapping; + EFI_PHYSICAL_ADDRESS MappedAddr; + UINTN Bytes; + EFI_STATUS Status; + + Block = AllocateZeroPool (sizeof (USBHC_MEM_BLOCK)); + if (Block == NULL) { + return NULL; + } + + // + // each bit in the bit array represents USBHC_MEM_UNIT + // bytes of memory in the memory block. + // + ASSERT (USBHC_MEM_UNIT * 8 <= EFI_PAGE_SIZE); + + Block->BufLen = EFI_PAGES_TO_SIZE (Pages); + Block->BitsLen = Block->BufLen / (USBHC_MEM_UNIT * 8); + Block->Bits = AllocateZeroPool (Block->BitsLen); + + if (Block->Bits == NULL) { + gBS->FreePool (Block); + return NULL; + } + + // + // Allocate the number of Pages of memory, then map it for + // bus master read and write. + // + Status = DmaAllocateBuffer ( + EfiBootServicesData, + Pages, + &BufHost + ); + + if (EFI_ERROR (Status)) { + goto FREE_BITARRAY; + } + + Bytes = EFI_PAGES_TO_SIZE (Pages); + Status = DmaMap ( + MapOperationBusMasterCommonBuffer, + BufHost, + &Bytes, + &MappedAddr, + &Mapping + ); + + if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (Pages))) { + goto FREE_BUFFER; + } + + // + // Check whether the data structure used by the host controller + // should be restricted into the same 4G + // + if (Pool->Check4G && (Pool->Which4G != USB_HC_HIGH_32BIT (MappedAddr))) { + DmaUnmap (Mapping); + goto FREE_BUFFER; + } + + Block->BufHost = BufHost; + Block->Buf = (UINT8 *) ((UINTN) MappedAddr); + Block->Mapping = Mapping; + + return Block; + +FREE_BUFFER: + DmaFreeBuffer (Pages, BufHost); + +FREE_BITARRAY: + gBS->FreePool (Block->Bits); + gBS->FreePool (Block); + return NULL; +} + + +/** + Free the memory block from the memory pool. + + @param Pool The memory pool to free the block from. + @param Block The memory block to free. + +**/ +VOID +UsbHcFreeMemBlock ( + IN USBHC_MEM_POOL *Pool, + IN USBHC_MEM_BLOCK *Block + ) +{ + ASSERT ((Pool != NULL) && (Block != NULL)); + + // + // Unmap the common buffer then free the structures + // + DmaUnmap (Block->Mapping); + DmaFreeBuffer (EFI_SIZE_TO_PAGES (Block->BufLen), Block->BufHost); + + gBS->FreePool (Block->Bits); + gBS->FreePool (Block); +} + + +/** + Alloc some memory from the block. + + @param Block The memory block to allocate memory from. + @param Units Number of memory units to allocate. + + @return The pointer to the allocated memory. If couldn't allocate the needed memory, + the return value is NULL. + +**/ +VOID * +UsbHcAllocMemFromBlock ( + IN USBHC_MEM_BLOCK *Block, + IN UINTN Units + ) +{ + UINTN Byte; + UINT8 Bit; + UINTN StartByte; + UINT8 StartBit; + UINTN Available; + UINTN Count; + + ASSERT ((Block != 0) && (Units != 0)); + + StartByte = 0; + StartBit = 0; + Available = 0; + + for (Byte = 0, Bit = 0; Byte < Block->BitsLen;) { + // + // If current bit is zero, the corresponding memory unit is + // available, otherwise we need to restart our searching. + // Available counts the consective number of zero bit. + // + if (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit)) { + Available++; + + if (Available >= Units) { + break; + } + + NEXT_BIT (Byte, Bit); + + } else { + NEXT_BIT (Byte, Bit); + + Available = 0; + StartByte = Byte; + StartBit = Bit; + } + } + + if (Available < Units) { + return NULL; + } + + // + // Mark the memory as allocated + // + Byte = StartByte; + Bit = StartBit; + + for (Count = 0; Count < Units; Count++) { + ASSERT (!USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit)); + + Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] | USB_HC_BIT (Bit)); + NEXT_BIT (Byte, Bit); + } + + return Block->BufHost + (StartByte * 8 + StartBit) * USBHC_MEM_UNIT; +} + +/** + Calculate the corresponding address according to the Mem parameter. + + @param Pool The memory pool of the host controller. + @param Mem The pointer to host memory. + @param Size The size of the memory region. + + @return the pci memory address +**/ +EFI_PHYSICAL_ADDRESS +UsbHcGetAddressForHostMem ( + IN USBHC_MEM_POOL *Pool, + IN VOID *Mem, + IN UINTN Size + ) +{ + USBHC_MEM_BLOCK *Head; + USBHC_MEM_BLOCK *Block; + UINTN AllocSize; + EFI_PHYSICAL_ADDRESS PhyAddr; + UINTN Offset; + + Head = Pool->Head; + AllocSize = USBHC_MEM_ROUND (Size); + + if (Mem == NULL) { + return 0; + } + + for (Block = Head; Block != NULL; Block = Block->Next) { + // + // scan the memory block list for the memory block that + // completely contains the allocated memory. + // + if ((Block->BufHost <= (UINT8 *) Mem) && (((UINT8 *) Mem + AllocSize) <= (Block->BufHost + Block->BufLen))) { + break; + } + } + + ASSERT ((Block != NULL)); + // + // calculate the pci memory address for host memory address. + // + Offset = (UINT8 *)Mem - Block->BufHost; + PhyAddr = (EFI_PHYSICAL_ADDRESS)(UINTN) (Block->Buf + Offset); + return PhyAddr; +} + + +/** + Insert the memory block to the pool's list of the blocks. + + @param Head The head of the memory pool's block list. + @param Block The memory block to insert. + +**/ +VOID +UsbHcInsertMemBlockToPool ( + IN USBHC_MEM_BLOCK *Head, + IN USBHC_MEM_BLOCK *Block + ) +{ + ASSERT ((Head != NULL) && (Block != NULL)); + Block->Next = Head->Next; + Head->Next = Block; +} + + +/** + Is the memory block empty? + + @param Block The memory block to check. + + @retval TRUE The memory block is empty. + @retval FALSE The memory block isn't empty. + +**/ +BOOLEAN +UsbHcIsMemBlockEmpty ( + IN USBHC_MEM_BLOCK *Block + ) +{ + UINTN Index; + + for (Index = 0; Index < Block->BitsLen; Index++) { + if (Block->Bits[Index] != 0) { + return FALSE; + } + } + + return TRUE; +} + + +/** + Unlink the memory block from the pool's list. + + @param Head The block list head of the memory's pool. + @param BlockToUnlink The memory block to unlink. + +**/ +VOID +UsbHcUnlinkMemBlock ( + IN USBHC_MEM_BLOCK *Head, + IN USBHC_MEM_BLOCK *BlockToUnlink + ) +{ + USBHC_MEM_BLOCK *Block; + + ASSERT ((Head != NULL) && (BlockToUnlink != NULL)); + + for (Block = Head; Block != NULL; Block = Block->Next) { + if (Block->Next == BlockToUnlink) { + Block->Next = BlockToUnlink->Next; + BlockToUnlink->Next = NULL; + break; + } + } +} + + +/** + Initialize the memory management pool for the host controller. + + @param Check4G Whether the host controller requires allocated memory + from one 4G address space. + @param Which4G The 4G memory area each memory allocated should be from. + + @retval EFI_SUCCESS The memory pool is initialized. + @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool. + +**/ +USBHC_MEM_POOL * +UsbHcInitMemPool ( + IN BOOLEAN Check4G, + IN UINT32 Which4G + ) +{ + USBHC_MEM_POOL *Pool; + + Pool = AllocatePool (sizeof (USBHC_MEM_POOL)); + + if (Pool == NULL) { + return Pool; + } + + Pool->Check4G = Check4G; + Pool->Which4G = Which4G; + Pool->Head = UsbHcAllocMemBlock (Pool, USBHC_MEM_DEFAULT_PAGES); + + if (Pool->Head == NULL) { + gBS->FreePool (Pool); + Pool = NULL; + } + + return Pool; +} + + +/** + Release the memory management pool. + + @param Pool The USB memory pool to free. + + @retval EFI_SUCCESS The memory pool is freed. + @retval EFI_DEVICE_ERROR Failed to free the memory pool. + +**/ +EFI_STATUS +UsbHcFreeMemPool ( + IN USBHC_MEM_POOL *Pool + ) +{ + USBHC_MEM_BLOCK *Block; + + ASSERT (Pool->Head != NULL); + + // + // Unlink all the memory blocks from the pool, then free them. + // UsbHcUnlinkMemBlock can't be used to unlink and free the + // first block. + // + for (Block = Pool->Head->Next; Block != NULL; Block = Pool->Head->Next) { + UsbHcUnlinkMemBlock (Pool->Head, Block); + UsbHcFreeMemBlock (Pool, Block); + } + + UsbHcFreeMemBlock (Pool, Pool->Head); + gBS->FreePool (Pool); + return EFI_SUCCESS; +} + + +/** + Allocate some memory from the host controller's memory pool + which can be used to communicate with host controller. + + @param Pool The host controller's memory pool. + @param Size Size of the memory to allocate. + + @return The allocated memory or NULL. + +**/ +VOID * +UsbHcAllocateMem ( + IN USBHC_MEM_POOL *Pool, + IN UINTN Size + ) +{ + USBHC_MEM_BLOCK *Head; + USBHC_MEM_BLOCK *Block; + USBHC_MEM_BLOCK *NewBlock; + VOID *Mem; + UINTN AllocSize; + UINTN Pages; + + Mem = NULL; + AllocSize = USBHC_MEM_ROUND (Size); + Head = Pool->Head; + ASSERT (Head != NULL); + + // + // First check whether current memory blocks can satisfy the allocation. + // + for (Block = Head; Block != NULL; Block = Block->Next) { + Mem = UsbHcAllocMemFromBlock (Block, AllocSize / USBHC_MEM_UNIT); + + if (Mem != NULL) { + ZeroMem (Mem, Size); + break; + } + } + + if (Mem != NULL) { + return Mem; + } + + // + // Create a new memory block if there is not enough memory + // in the pool. If the allocation size is larger than the + // default page number, just allocate a large enough memory + // block. Otherwise allocate default pages. + // + if (AllocSize > EFI_PAGES_TO_SIZE (USBHC_MEM_DEFAULT_PAGES)) { + Pages = EFI_SIZE_TO_PAGES (AllocSize) + 1; + } else { + Pages = USBHC_MEM_DEFAULT_PAGES; + } + + NewBlock = UsbHcAllocMemBlock (Pool, Pages); + + if (NewBlock == NULL) { + DEBUG ((DEBUG_INFO, "UsbHcAllocateMem: failed to allocate block\n")); + return NULL; + } + + // + // Add the new memory block to the pool, then allocate memory from it + // + UsbHcInsertMemBlockToPool (Head, NewBlock); + Mem = UsbHcAllocMemFromBlock (NewBlock, AllocSize / USBHC_MEM_UNIT); + + if (Mem != NULL) { + ZeroMem (Mem, Size); + } + + return Mem; +} + + +/** + Free the allocated memory back to the memory pool. + + @param Pool The memory pool of the host controller. + @param Mem The memory to free. + @param Size The size of the memory to free. + +**/ +VOID +UsbHcFreeMem ( + IN USBHC_MEM_POOL *Pool, + IN VOID *Mem, + IN UINTN Size + ) +{ + USBHC_MEM_BLOCK *Head; + USBHC_MEM_BLOCK *Block; + UINT8 *ToFree; + UINTN AllocSize; + UINTN Byte; + UINTN Bit; + UINTN Count; + + Head = Pool->Head; + AllocSize = USBHC_MEM_ROUND (Size); + ToFree = (UINT8 *) Mem; + + for (Block = Head; Block != NULL; Block = Block->Next) { + // + // scan the memory block list for the memory block that + // completely contains the memory to free. + // + if ((Block->BufHost <= ToFree) && ((ToFree + AllocSize) <= (Block->BufHost + Block->BufLen))) { + // + // compute the start byte and bit in the bit array + // + Byte = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) / 8; + Bit = ((ToFree - Block->BufHost) / USBHC_MEM_UNIT) % 8; + + // + // reset associated bits in bit arry + // + for (Count = 0; Count < (AllocSize / USBHC_MEM_UNIT); Count++) { + ASSERT (USB_HC_BIT_IS_SET (Block->Bits[Byte], Bit)); + + Block->Bits[Byte] = (UINT8) (Block->Bits[Byte] ^ USB_HC_BIT (Bit)); + NEXT_BIT (Byte, Bit); + } + + break; + } + } + + // + // If Block == NULL, it means that the current memory isn't + // in the host controller's pool. This is critical because + // the caller has passed in a wrong memory point + // + ASSERT (Block != NULL); + + // + // Release the current memory block if it is empty and not the head + // + if ((Block != Head) && UsbHcIsMemBlockEmpty (Block)) { + UsbHcUnlinkMemBlock (Head, Block); + UsbHcFreeMemBlock (Pool, Block); + } + + return ; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/UsbHcMem.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/UsbHcMem.h new file mode 100644 index 0000000..3948ea5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/OhciDxe/UsbHcMem.h @@ -0,0 +1,150 @@ +/** @file +This file contains the definination for host controller memory +management routines. + +Copyright (c) 2013-2015 Intel Corporation. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _USB_HC_MEM_H_ +#define _USB_HC_MEM_H_ + +#define USB_HC_BIT(a) ((UINTN)(1 << (a))) + +#define USB_HC_BIT_IS_SET(Data, Bit) \ + ((BOOLEAN)(((Data) & USB_HC_BIT(Bit)) == USB_HC_BIT(Bit))) + +#define USB_HC_HIGH_32BIT(Addr64) \ + ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF)) + +typedef struct _USBHC_MEM_BLOCK USBHC_MEM_BLOCK; +struct _USBHC_MEM_BLOCK { + UINT8 *Bits; // Bit array to record which unit is allocated + UINTN BitsLen; + UINT8 *Buf; + UINT8 *BufHost; + UINTN BufLen; // Memory size in bytes + VOID *Mapping; + USBHC_MEM_BLOCK *Next; +}; + +// +// USBHC_MEM_POOL is used to manage the memory used by USB +// host controller. EHCI requires the control memory and transfer +// data to be on the same 4G memory. +// +typedef struct _USBHC_MEM_POOL { + BOOLEAN Check4G; + UINT32 Which4G; + USBHC_MEM_BLOCK *Head; +} USBHC_MEM_POOL; + +// +// Memory allocation unit, must be 2^n, n>4 +// +#define USBHC_MEM_UNIT 64 + +#define USBHC_MEM_UNIT_MASK (USBHC_MEM_UNIT - 1) +#define USBHC_MEM_DEFAULT_PAGES 16 + +#define USBHC_MEM_ROUND(Len) (((Len) + USBHC_MEM_UNIT_MASK) & (~USBHC_MEM_UNIT_MASK)) + +// +// Advance the byte and bit to the next bit, adjust byte accordingly. +// +#define NEXT_BIT(Byte, Bit) \ + do { \ + (Bit)++; \ + if ((Bit) > 7) { \ + (Byte)++; \ + (Bit) = 0; \ + } \ + } while (0) + + + +/** + Initialize the memory management pool for the host controller. + + @param PciIo The PciIo that can be used to access the host controller. + @param Check4G Whether the host controller requires allocated memory + from one 4G address space. + @param Which4G The 4G memory area each memory allocated should be from. + + @retval EFI_SUCCESS The memory pool is initialized. + @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool. + +**/ +USBHC_MEM_POOL * +UsbHcInitMemPool ( + IN BOOLEAN Check4G, + IN UINT32 Which4G + ); + + +/** + Release the memory management pool. + + @param Pool The USB memory pool to free. + + @retval EFI_SUCCESS The memory pool is freed. + @retval EFI_DEVICE_ERROR Failed to free the memory pool. + +**/ +EFI_STATUS +UsbHcFreeMemPool ( + IN USBHC_MEM_POOL *Pool + ); + + +/** + Allocate some memory from the host controller's memory pool + which can be used to communicate with host controller. + + @param Pool The host controller's memory pool. + @param Size Size of the memory to allocate. + + @return The allocated memory or NULL. + +**/ +VOID * +UsbHcAllocateMem ( + IN USBHC_MEM_POOL *Pool, + IN UINTN Size + ); + + +/** + Free the allocated memory back to the memory pool. + + @param Pool The memory pool of the host controller. + @param Mem The memory to free. + @param Size The size of the memory to free. + +**/ +VOID +UsbHcFreeMem ( + IN USBHC_MEM_POOL *Pool, + IN VOID *Mem, + IN UINTN Size + ); + +/** + Calculate the corresponding address according to the Mem parameter. + + @param Pool The memory pool of the host controller. + @param Mem The pointer to host memory. + @param Size The size of the memory region. + + @return the memory address +**/ +EFI_PHYSICAL_ADDRESS +UsbHcGetAddressForHostMem ( + IN USBHC_MEM_POOL *Pool, + IN VOID *Mem, + IN UINTN Size + ); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.c new file mode 100644 index 0000000..845aec4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.c @@ -0,0 +1,869 @@ +/** @file + * + * PCA9555 GPIO driver for Rockchip platforms. + * + * Contribs: + * + * Copyright (c) 2018, Marvell International Ltd. All rights reserved. + * Copyright (c) 2023, Mario Bălănică + * Copyright (c) 2023, Shimrra Shai + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "Pca9555Dxe.h" + +STATIC CONST EFI_GUID I2cGuid = I2C_GUID; + +/* Much of the driver below is ripped from the Marvell version, with + * some adaptation. + */ + +/* --- Low-level Methods --- */ + +EFI_STATUS +EFIAPI +Pca95xxI2cTransfer ( + IN EFI_I2C_IO_PROTOCOL *I2cIo, + IN UINT8 Address, + IN UINT8 *Buffer, + IN BOOLEAN Read + ) +{ + EFI_I2C_REQUEST_PACKET *RequestPacket; + UINTN RequestPacketSize; + UINT8 AddressBuffer; + UINT8 WritePacketBuffer[2]; + EFI_STATUS Status; + UINTN NumOps; + + if (Read) { + NumOps = 2; + } else { + NumOps = 1; + } + + RequestPacketSize = sizeof (UINTN) + + sizeof (EFI_I2C_OPERATION) * NumOps; + RequestPacket = AllocateZeroPool (RequestPacketSize); + if (RequestPacket == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + /* Operations contain address and payload, consecutively. */ + /* Note: in the Rockchip I2C driver, a special control byte is sent with + * each operation *implicitly*. PCA9555 expects this only ONCE. So + * unlike the Marvell driver, we should encode the whole operation + * on a single buffer. + */ + if (Read) { + RequestPacket->OperationCount = NumOps; + RequestPacket->Operation[0].LengthInBytes = 1; + RequestPacket->Operation[0].Buffer = &AddressBuffer; + RequestPacket->Operation[0].Buffer[0] = Address & MAX_UINT8; + RequestPacket->Operation[0].Flags = 0; + + RequestPacket->Operation[1].LengthInBytes = 1; + RequestPacket->Operation[1].Buffer = Buffer; + RequestPacket->Operation[1].Flags = I2C_FLAG_READ; + } else { + RequestPacket->OperationCount = NumOps; + RequestPacket->Operation[0].LengthInBytes = 2; + RequestPacket->Operation[0].Buffer = WritePacketBuffer; + RequestPacket->Operation[0].Buffer[0] = Address & MAX_UINT8; + RequestPacket->Operation[0].Buffer[1] = Buffer[0]; + RequestPacket->Operation[0].Flags = 0; + } + + Status = I2cIo->QueueRequest (I2cIo, 0, NULL, RequestPacket, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: transmission error: 0x%d\n", + __FUNCTION__, + Status)); + } + + gBS->FreePool(RequestPacket); + + return Status; +} + +STATIC +EFI_STATUS +Pca95xxReadRegs ( + IN EFI_I2C_IO_PROTOCOL *I2cIo, + IN UINT8 Reg, + OUT UINT8 *RegVal + ) +{ + return Pca95xxI2cTransfer (I2cIo, Reg, RegVal, TRUE); +} + +STATIC +EFI_STATUS +Pca95xxWriteRegs ( + IN EFI_I2C_IO_PROTOCOL *I2cIo, + IN UINTN Reg, + IN UINT8 RegVal + ) +{ + return Pca95xxI2cTransfer (I2cIo, Reg, &RegVal, FALSE); +} + +#if 0 +VOID +EFIAPI +DumpRegs ( + IN EFI_I2C_IO_PROTOCOL *I2cIo + ) +{ + UINT8 Regs[6]; + Pca95xxReadRegs(I2cIo, 0x0, &Regs[0]); + Pca95xxReadRegs(I2cIo, 0x1, &Regs[1]); + Pca95xxReadRegs(I2cIo, 0x2, &Regs[2]); + Pca95xxReadRegs(I2cIo, 0x3, &Regs[3]); + Pca95xxReadRegs(I2cIo, 0x4, &Regs[4]); + Pca95xxReadRegs(I2cIo, 0x5, &Regs[5]); + Pca95xxReadRegs(I2cIo, 0x6, &Regs[6]); + Pca95xxReadRegs(I2cIo, 0x7, &Regs[7]); + + DEBUG ((DEBUG_INFO, "PCA9555 state:\n")); + DEBUG ((DEBUG_INFO, "reg 0 = 0x%02X\n", Regs[0])); + DEBUG ((DEBUG_INFO, "reg 1 = 0x%02X\n", Regs[1])); + DEBUG ((DEBUG_INFO, "reg 2 = 0x%02X\n", Regs[2])); + DEBUG ((DEBUG_INFO, "reg 3 = 0x%02X\n", Regs[3])); + DEBUG ((DEBUG_INFO, "reg 4 = 0x%02X\n", Regs[4])); + DEBUG ((DEBUG_INFO, "reg 5 = 0x%02X\n", Regs[5])); + DEBUG ((DEBUG_INFO, "reg 6 = 0x%02X\n", Regs[6])); + DEBUG ((DEBUG_INFO, "reg 7 = 0x%02X\n", Regs[7])); + DEBUG ((DEBUG_INFO, "\n")); +} +#endif + +/* ------------------------- */ + +/* --- Driver Methods --- */ +STATIC PCA9555_CONTEXT *mPca9555Context = NULL; + +/* Probe the device, bringing it up. */ +EFI_STATUS +EFIAPI +Pca9555Probe ( + IN EFI_I2C_IO_PROTOCOL *I2c + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT8 Zero = 0x00; + UINTN Index; + + if (mPca9555Context != NULL) { + /* The device has already been brought online. Nothing to do. */ + return EFI_SUCCESS; + } + + mPca9555Context = AllocateZeroPool (sizeof(PCA9555_CONTEXT)); + if (mPca9555Context == NULL) { + DEBUG ((DEBUG_ERROR, "%a: context allocation failed\n", __func__)); + Status = EFI_OUT_OF_RESOURCES; + goto fail; + } + + mPca9555Context->Signature = PCA95XX_SIGNATURE; + + mPca9555Context->I2cAddress = PcdGet8 (PcdPca9555Address); + mPca9555Context->I2cBus = PcdGet8 (PcdPca9555Bus); + + /* Device setup: disable polarity inversion on all pins */ + for (Index = 0; Index < PCA9555_NUM_BANKS; ++Index) { + Status = Pca95xxWriteRegs(I2c, PCA9555_INVERSION_REG_BASE + Index, Zero); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: setup failed!\n", __FUNCTION__)); + goto fail; + } + } + + /* and preset all outputs to 0 */ + for (Index = 0; Index < PCA9555_NUM_BANKS; ++Index) { + Status = Pca95xxWriteRegs(I2c, PCA9555_OUTPUT_REG_BASE + Index, Zero); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "%a: setup failed!\n", __FUNCTION__)); + goto fail; + } + } + + DEBUG ((DEBUG_INFO, + "%a: PCA9555 bound at I2C addr 0x%02X, bus 0x%02X\n", + __FUNCTION__, + mPca9555Context->I2cAddress, + mPca9555Context->I2cBus + )); + + return EFI_SUCCESS; +fail: + if (mPca9555Context != NULL) { + FreePool (mPca9555Context); + mPca9555Context = NULL; + } + + return Status; +} + +/* Shut down the device */ +EFI_STATUS +EFIAPI +Pca9555Unprobe ( + IN EFI_I2C_IO_PROTOCOL *I2c +) +{ + if (mPca9555Context != NULL) { + FreePool (mPca9555Context); + mPca9555Context = NULL; + + DEBUG ((DEBUG_INFO, "%a: PCA9555 has been shut down.", __FUNCTION__)); + } + + return EFI_SUCCESS; +} + +/* Read a pin register */ +EFI_STATUS +EFIAPI +Pca9555ReadPinReg ( + IN EFI_I2C_IO_PROTOCOL *I2c, + IN UINT8 BaseReg, + IN UINTN GpioPin, + OUT UINTN *Value + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN Bank; + UINT8 RegVal = 0x00; + + if (mPca9555Context == NULL) { + DEBUG ((DEBUG_ERROR, "%a: device not probed", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + Bank = GpioPin / PCA95XX_BANK_SIZE; + Status = Pca95xxReadRegs (I2c, BaseReg + Bank, &RegVal); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: read failure", __FUNCTION__)); + return Status; + } + + if (RegVal & (1 << (GpioPin % PCA95XX_BANK_SIZE))) { + *Value = 1; + } else { + *Value = 0; + } + + return EFI_SUCCESS; +} + +/* Write the output pin register */ +EFI_STATUS +EFIAPI +Pca9555WritePinOutReg ( + IN EFI_I2C_IO_PROTOCOL *I2c, + IN UINTN GpioPin, + IN UINTN Value + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN Bank; + UINT8 RegVal = 0x00; + + if (mPca9555Context == NULL) { + DEBUG ((DEBUG_ERROR, "%a: device not probed", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + Bank = GpioPin / PCA95XX_BANK_SIZE; + + Status = Pca95xxReadRegs (I2c, + PCA9555_OUTPUT_REG_BASE + Bank, + &RegVal + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: read failure", __FUNCTION__)); + return Status; + } + + if (Value) { + RegVal |= (1 << (GpioPin % PCA95XX_BANK_SIZE)); + } else { + RegVal &= ~(1 << (GpioPin % PCA95XX_BANK_SIZE)); + } + + Status = Pca95xxWriteRegs (I2c, + PCA9555_OUTPUT_REG_BASE + Bank, + RegVal + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: write failure", __FUNCTION__)); + return Status; + } + + return EFI_SUCCESS; +} + +/* Write the pin control register */ +EFI_STATUS +EFIAPI +Pca9555WritePinCtrlReg ( + IN EFI_I2C_IO_PROTOCOL *I2c, + IN UINTN GpioPin, + IN UINTN Value + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN Bank; + UINT8 RegVal = 0x00; + + if (mPca9555Context == NULL) { + DEBUG ((DEBUG_ERROR, "%a: device not probed", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + Bank = GpioPin / PCA95XX_BANK_SIZE; + + Status = Pca95xxReadRegs (I2c, + PCA9555_CONTROL_REG_BASE + Bank, + &RegVal); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: read failure", __FUNCTION__)); + return Status; + } + + if (Value) { + RegVal |= (1 << (GpioPin % PCA95XX_BANK_SIZE)); + } else { + RegVal &= ~(1 << (GpioPin % PCA95XX_BANK_SIZE)); + } + + Status = Pca95xxWriteRegs (I2c, + PCA9555_CONTROL_REG_BASE + Bank, + RegVal); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: write failure", __FUNCTION__)); + return Status; + } + + return EFI_SUCCESS; +} + +/* ---------------------- */ + +/* --- Embedded GPIO Protocol --- */ + +/* Get the I2C */ +EFI_STATUS +EFIAPI +Pca9555GetI2c ( + IN OUT EFI_I2C_IO_PROTOCOL **I2cIo + ) +{ + UINTN I2cBus, I2cAddress; + UINTN HandleCount, Index; + EFI_HANDLE *HandleBuffer; + EFI_STATUS Status; + + if (mPca9555Context == NULL) { + DEBUG ((DEBUG_ERROR, "%a: device not probed\n", __FUNCTION__)); + return EFI_UNSUPPORTED; + } + + I2cBus = mPca9555Context->I2cBus; + I2cAddress = mPca9555Context->I2cAddress; + + /* Locate Handles of all EfiI2cIoProtocol producers */ + Status = gBS->LocateHandleBuffer (ByProtocol, + &gEfiI2cIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__)); + return Status; + } + + /* Iterate over all protocol producers and pick one upon DeviceIndex match */ + for (Index = 0; Index < HandleCount; Index++) { + Status = gBS->OpenProtocol (HandleBuffer[Index], + &gEfiI2cIoProtocolGuid, + (VOID **)I2cIo, + gImageHandle, + NULL, + EFI_OPEN_PROTOCOL_GET_PROTOCOL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to open protocol\n", __FUNCTION__)); + gBS->FreePool (HandleBuffer); + return Status; + } + if ((*I2cIo)->DeviceIndex == I2C_DEVICE_INDEX (I2cBus, I2cAddress)) { + gBS->FreePool (HandleBuffer); + return EFI_SUCCESS; + } + } + + gBS->FreePool (HandleBuffer); + + return EFI_NOT_FOUND; +} + +#if !defined(MDEPKG_NDEBUG) +/* A validator; unlike Marvell version we only assume 1 chip */ +STATIC +EFI_STATUS +Pca9555ValidatePin ( + IN UINTN GpioPin + ) +{ + UINTN ControllerId; + + if (GpioPin >= PCA9555_NUM_GPIO) { + DEBUG ((DEBUG_ERROR, + "%a: GPIO pin #%d not available\n", + __FUNCTION__, + GpioPin)); + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} +#endif + +/** + +Routine Description: + + Gets the state of a GPIO pin + +Arguments: + + This - pointer to protocol + Gpio - which pin to read + Value - state of the pin + +Returns: + + EFI_SUCCESS - GPIO state returned in Value + EFI_INVALID_PARAMETER - Value is NULL pointer or Gpio pin is out of range +**/ +STATIC +EFI_STATUS +Pca9555Get ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT UINTN *Value + ) +{ + EFI_I2C_IO_PROTOCOL *I2cIo; + EFI_STATUS Status; + UINTN GpioPin; + UINT8 RegVal; + UINTN Bank; + + GpioPin = GPIO_PIN (Gpio); + + ASSERT_EFI_ERROR (Pca9555ValidatePin (GpioPin)); + + Status = Pca9555GetI2c (&I2cIo); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: fail to get I2C protocol\n", __FUNCTION__)); + return Status; + } + + Status = Pca9555ReadPinReg(I2cIo, PCA9555_INPUT_REG_BASE, Gpio, Value); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: register read failure\n", __FUNCTION__)); + return Status; + } + + return EFI_SUCCESS; +} + +/** + +Routine Description: + + Sets the state of a GPIO pin + +Arguments: + + This - pointer to protocol + Gpio - which pin to modify + Mode - mode to set + +Returns: + + EFI_SUCCESS - GPIO set as requested + EFI_UNSUPPORTED - Mode is not supported + EFI_INVALID_PARAMETER - Gpio pin is out of range +**/ +STATIC +EFI_STATUS +Pca9555Set ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_MODE Mode + ) +{ + EFI_I2C_IO_PROTOCOL *I2cIo; + EFI_STATUS Status; + UINTN GpioPin; + UINTN Bit; + + GpioPin = GPIO_PIN (Gpio); + + ASSERT_EFI_ERROR (Pca9555ValidatePin (GpioPin)); + + Status = Pca9555GetI2c (&I2cIo); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: fail to get I2C protocol\n", __FUNCTION__)); + return Status; + } + +#if 0 + DEBUG ((DEBUG_INFO, "Status before set of pin %d to mode 0x%02X:\n", Gpio, Mode)); + DumpRegs(I2cIo); +#endif + + switch (Mode) { + case GPIO_MODE_OUTPUT_0: + case GPIO_MODE_OUTPUT_1: + if (Mode == GPIO_MODE_OUTPUT_0) { + Bit = 0; + } else { + Bit = 1; + } + + Status = Pca9555WritePinOutReg (I2cIo, GpioPin, Bit); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: fail to set ouput value\n", __FUNCTION__)); + return Status; + } + + Status = Pca9555WritePinCtrlReg (I2cIo, GpioPin, 0); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: fail to set direction\n", __FUNCTION__)); + return Status; + } + + break; + case GPIO_MODE_INPUT: + Status = Pca9555WritePinCtrlReg (I2cIo, GpioPin, 1); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: fail to set direction\n", __FUNCTION__)); + return Status; + } + break; + + default: + return EFI_UNSUPPORTED; + } + +#if 0 + DEBUG ((DEBUG_INFO, "Status after set:\n")); + DumpRegs(I2cIo); +#endif + + return EFI_SUCCESS; +} + +/** + +Routine Description: + + Gets the mode (function) of a GPIO pin + +Arguments: + + This - pointer to protocol + Gpio - which pin + Mode - pointer to output mode value + +Returns: + + EFI_SUCCESS - mode value retrieved + EFI_INVALID_PARAMETER - Mode is a null pointer or Gpio pin is out of range + +**/ +STATIC +EFI_STATUS +Pca9555GetMode ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT EMBEDDED_GPIO_MODE *Mode + ) +{ + EFI_I2C_IO_PROTOCOL *I2cIo; + EFI_STATUS Status; + UINTN GpioPin; + UINTN RegVal; + + GpioPin = GPIO_PIN (Gpio); + + ASSERT_EFI_ERROR (Pca9555ValidatePin (GpioPin)); + + Status = Pca9555GetI2c (&I2cIo); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: fail to get I2C protocol\n", __FUNCTION__)); + return Status; + } + + Status = Pca9555ReadPinReg(I2cIo, PCA9555_CONTROL_REG_BASE, Gpio, &RegVal); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: register read failure\n", __FUNCTION__)); + return Status; + } + + if (RegVal == 0) { + /* output modes */ + Status = Pca9555ReadPinReg(I2cIo, PCA9555_OUTPUT_REG_BASE, Gpio, &RegVal); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: register read failure\n", __FUNCTION__)); + return Status; + } + + if (RegVal) { + *Mode = GPIO_MODE_OUTPUT_1; + } else { + *Mode = GPIO_MODE_OUTPUT_0; + } + } else { + /* input mode */ + *Mode = GPIO_MODE_INPUT; + } + + return EFI_SUCCESS; +} + +/** + +Routine Description: + + Sets the pull-up / pull-down resistor of a GPIO pin + +Arguments: + + This - pointer to protocol + Gpio - which pin + Direction - pull-up, pull-down, or none + +Returns: + + EFI_UNSUPPORTED - Can not perform the requested operation + +**/ +EFI_STATUS +EFIAPI +Pca9555SetPull ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_PULL Direction + ) +{ + return EFI_UNSUPPORTED; +} + +PCA95XX_PROTOCOL mPca95xxProtocol = { + .GpioProtocol = { + .Get = Pca9555Get, + .Set = Pca9555Set, + .GetMode = Pca9555GetMode, + .SetPull = Pca9555SetPull, + }, +}; + +/* ------------------------------ */ + +/* --- Binding Protocol --- */ +EFI_DRIVER_BINDING_PROTOCOL mDriverBindingProtocol = { + Pca9555Supported, + Pca9555Start, + Pca9555Stop, +}; + +EFI_STATUS +EFIAPI +Pca9555Supported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + EFI_I2C_IO_PROTOCOL *TmpI2cIo; + UINT8 Pca9555Address = 0x00; + UINT8 Pca9555Bus = 0x00; + UINTN i; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &TmpI2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + + Pca9555Address = PcdGet8 (PcdPca9555Address); + Pca9555Bus = PcdGet8 (PcdPca9555Bus); + + DEBUG ((DEBUG_INFO, + "%a: addr = 0x%02X, bus = 0x%02X\n", + __FUNCTION__, + Pca9555Address, + Pca9555Bus)); + + if (CompareGuid(TmpI2cIo->DeviceGuid, &I2cGuid) && + TmpI2cIo->DeviceIndex == I2C_DEVICE_INDEX(Pca9555Bus, Pca9555Address)) { + DEBUG ((DEBUG_INFO, "%a: PCA9555 device is supported\n", __FUNCTION__)); + Status = EFI_SUCCESS; + } + +/*out:*/ + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +Pca9555Start ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_I2C_IO_PROTOCOL *TmpI2cIo; + + Status = gBS->OpenProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + (VOID **) &TmpI2cIo, + gImageHandle, + ControllerHandle, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + + Status = Pca9555Probe (TmpI2cIo); + if (EFI_ERROR (Status)) { + goto fail; + } + + Status = gBS->InstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gPca95xxProtocolGuid, + &mPca95xxProtocol, + NULL); + if (EFI_ERROR (Status)) { + goto fail; + } + + Status = EFI_SUCCESS; + +fail: + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + + return Status; +} + +EFI_STATUS +EFIAPI +Pca9555Stop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + gBS->UninstallMultipleProtocolInterfaces ( + &ControllerHandle, + &gPca95xxProtocolGuid, &mPca95xxProtocol, + &gEfiDriverBindingProtocolGuid, &mDriverBindingProtocol, + NULL + ); + + /* (SS) is this necessary? */ + + /* + Status = Pca9555Unprobe(); + gBS->CloseProtocol ( + ControllerHandle, + &gEfiI2cIoProtocolGuid, + gImageHandle, + ControllerHandle + ); + */ + + return EFI_SUCCESS; +} +/* ------------------------ */ + +EFI_STATUS +EFIAPI +Pca9555DxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiDriverBindingProtocolGuid, &mDriverBindingProtocol, + NULL + ); + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.h new file mode 100644 index 0000000..530978e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.h @@ -0,0 +1,76 @@ +/** @file +* +* Copyright (c) 2023, Mario Bălănică +* Copyright (c) 2023, Shimrra Shai +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __PCA9555_DXE_H__ +#define __PCA9555_DXE_H__ + +#include + +#define PCA95XX_SIGNATURE SIGNATURE_32 ('P', '9', '5', 'X') + +#define I2C_GUID \ + { \ + 0xadc1901b, 0xb83c, 0x4831, { 0x8f, 0x59, 0x70, 0x89, 0x8f, 0x26, 0x57, 0x1e } \ + } + +/* NB: Only PCA9555 is supported now. This driver can/should be generalized to + * whole PCA95XX family. + */ +#define PCA9555_INPUT_REG_BASE 0x00 +#define PCA9555_OUTPUT_REG_BASE 0x02 +#define PCA9555_INVERSION_REG_BASE 0x04 +#define PCA9555_CONTROL_REG_BASE 0x06 + +#define PCA9555_NUM_GPIO 16 +#define PCA9555_NUM_BANKS 2 + +#define PCA95XX_BANK_SIZE 8 /* bits */ +#define PCA95XX_MAX_BANK 5 + +typedef struct { + UINT32 Signature; + + UINT8 I2cAddress; + UINT8 I2cBus; +} PCA9555_CONTEXT; + +/* --- Method Prototypes --- */ +EFI_STATUS +EFIAPI +Pca9555Supported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +Pca9555Start ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath OPTIONAL + ); + +EFI_STATUS +EFIAPI +Pca9555Stop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer OPTIONAL + ); + +EFI_STATUS +EFIAPI +Pca9555DxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif // __PCA9555_DXE_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.inf new file mode 100644 index 0000000..cfb22aa --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.inf @@ -0,0 +1,48 @@ +#/** @file +# +# PCA9555 GPIO initializer for Rockchip platforms. +# +# Copyright (c) 2023, Mario Bălănică +# Copyright (c) 2023, Shimrra Shai +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = Pca9555Dxe + FILE_GUID = 2ee8d685-8066-4f37-ae0e-5235730b9cc7 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = Pca9555DxeInitialize + +[Sources.common] + Pca9555Dxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiLib + UefiBootServicesTableLib + MemoryAllocationLib + DebugLib + +[Protocols] + gEfiDriverBindingProtocolGuid + gEfiI2cIoProtocolGuid ## CONSUMES + gPca95xxProtocolGuid ## PRODUCES + gRockchipI2cMasterProtocolGuid + +[Pcd] + gRockchipTokenSpaceGuid.PcdPca9555Address + gRockchipTokenSpaceGuid.PcdPca9555Bus + +[Depex] + TRUE + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/Crc32Table.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/Crc32Table.h new file mode 100644 index 0000000..fbbaf93 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/Crc32Table.h @@ -0,0 +1,266 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 mCrcTable[256] = { + 0x00000000, + 0x77073096, + 0xEE0E612C, + 0x990951BA, + 0x076DC419, + 0x706AF48F, + 0xE963A535, + 0x9E6495A3, + 0x0EDB8832, + 0x79DCB8A4, + 0xE0D5E91E, + 0x97D2D988, + 0x09B64C2B, + 0x7EB17CBD, + 0xE7B82D07, + 0x90BF1D91, + 0x1DB71064, + 0x6AB020F2, + 0xF3B97148, + 0x84BE41DE, + 0x1ADAD47D, + 0x6DDDE4EB, + 0xF4D4B551, + 0x83D385C7, + 0x136C9856, + 0x646BA8C0, + 0xFD62F97A, + 0x8A65C9EC, + 0x14015C4F, + 0x63066CD9, + 0xFA0F3D63, + 0x8D080DF5, + 0x3B6E20C8, + 0x4C69105E, + 0xD56041E4, + 0xA2677172, + 0x3C03E4D1, + 0x4B04D447, + 0xD20D85FD, + 0xA50AB56B, + 0x35B5A8FA, + 0x42B2986C, + 0xDBBBC9D6, + 0xACBCF940, + 0x32D86CE3, + 0x45DF5C75, + 0xDCD60DCF, + 0xABD13D59, + 0x26D930AC, + 0x51DE003A, + 0xC8D75180, + 0xBFD06116, + 0x21B4F4B5, + 0x56B3C423, + 0xCFBA9599, + 0xB8BDA50F, + 0x2802B89E, + 0x5F058808, + 0xC60CD9B2, + 0xB10BE924, + 0x2F6F7C87, + 0x58684C11, + 0xC1611DAB, + 0xB6662D3D, + 0x76DC4190, + 0x01DB7106, + 0x98D220BC, + 0xEFD5102A, + 0x71B18589, + 0x06B6B51F, + 0x9FBFE4A5, + 0xE8B8D433, + 0x7807C9A2, + 0x0F00F934, + 0x9609A88E, + 0xE10E9818, + 0x7F6A0DBB, + 0x086D3D2D, + 0x91646C97, + 0xE6635C01, + 0x6B6B51F4, + 0x1C6C6162, + 0x856530D8, + 0xF262004E, + 0x6C0695ED, + 0x1B01A57B, + 0x8208F4C1, + 0xF50FC457, + 0x65B0D9C6, + 0x12B7E950, + 0x8BBEB8EA, + 0xFCB9887C, + 0x62DD1DDF, + 0x15DA2D49, + 0x8CD37CF3, + 0xFBD44C65, + 0x4DB26158, + 0x3AB551CE, + 0xA3BC0074, + 0xD4BB30E2, + 0x4ADFA541, + 0x3DD895D7, + 0xA4D1C46D, + 0xD3D6F4FB, + 0x4369E96A, + 0x346ED9FC, + 0xAD678846, + 0xDA60B8D0, + 0x44042D73, + 0x33031DE5, + 0xAA0A4C5F, + 0xDD0D7CC9, + 0x5005713C, + 0x270241AA, + 0xBE0B1010, + 0xC90C2086, + 0x5768B525, + 0x206F85B3, + 0xB966D409, + 0xCE61E49F, + 0x5EDEF90E, + 0x29D9C998, + 0xB0D09822, + 0xC7D7A8B4, + 0x59B33D17, + 0x2EB40D81, + 0xB7BD5C3B, + 0xC0BA6CAD, + 0xEDB88320, + 0x9ABFB3B6, + 0x03B6E20C, + 0x74B1D29A, + 0xEAD54739, + 0x9DD277AF, + 0x04DB2615, + 0x73DC1683, + 0xE3630B12, + 0x94643B84, + 0x0D6D6A3E, + 0x7A6A5AA8, + 0xE40ECF0B, + 0x9309FF9D, + 0x0A00AE27, + 0x7D079EB1, + 0xF00F9344, + 0x8708A3D2, + 0x1E01F268, + 0x6906C2FE, + 0xF762575D, + 0x806567CB, + 0x196C3671, + 0x6E6B06E7, + 0xFED41B76, + 0x89D32BE0, + 0x10DA7A5A, + 0x67DD4ACC, + 0xF9B9DF6F, + 0x8EBEEFF9, + 0x17B7BE43, + 0x60B08ED5, + 0xD6D6A3E8, + 0xA1D1937E, + 0x38D8C2C4, + 0x4FDFF252, + 0xD1BB67F1, + 0xA6BC5767, + 0x3FB506DD, + 0x48B2364B, + 0xD80D2BDA, + 0xAF0A1B4C, + 0x36034AF6, + 0x41047A60, + 0xDF60EFC3, + 0xA867DF55, + 0x316E8EEF, + 0x4669BE79, + 0xCB61B38C, + 0xBC66831A, + 0x256FD2A0, + 0x5268E236, + 0xCC0C7795, + 0xBB0B4703, + 0x220216B9, + 0x5505262F, + 0xC5BA3BBE, + 0xB2BD0B28, + 0x2BB45A92, + 0x5CB36A04, + 0xC2D7FFA7, + 0xB5D0CF31, + 0x2CD99E8B, + 0x5BDEAE1D, + 0x9B64C2B0, + 0xEC63F226, + 0x756AA39C, + 0x026D930A, + 0x9C0906A9, + 0xEB0E363F, + 0x72076785, + 0x05005713, + 0x95BF4A82, + 0xE2B87A14, + 0x7BB12BAE, + 0x0CB61B38, + 0x92D28E9B, + 0xE5D5BE0D, + 0x7CDCEFB7, + 0x0BDBDF21, + 0x86D3D2D4, + 0xF1D4E242, + 0x68DDB3F8, + 0x1FDA836E, + 0x81BE16CD, + 0xF6B9265B, + 0x6FB077E1, + 0x18B74777, + 0x88085AE6, + 0xFF0F6A70, + 0x66063BCA, + 0x11010B5C, + 0x8F659EFF, + 0xF862AE69, + 0x616BFFD3, + 0x166CCF45, + 0xA00AE278, + 0xD70DD2EE, + 0x4E048354, + 0x3903B3C2, + 0xA7672661, + 0xD06016F7, + 0x4969474D, + 0x3E6E77DB, + 0xAED16A4A, + 0xD9D65ADC, + 0x40DF0B66, + 0x37D83BF0, + 0xA9BCAE53, + 0xDEBB9EC5, + 0x47B2CF7F, + 0x30B5FFE9, + 0xBDBDF21C, + 0xCABAC28A, + 0x53B39330, + 0x24B4A3A6, + 0xBAD03605, + 0xCDD70693, + 0x54DE5729, + 0x23D967BF, + 0xB3667A2E, + 0xC4614AB8, + 0x5D681B02, + 0x2A6F2B94, + 0xB40BBE37, + 0xC30C8EA1, + 0x5A05DF1B, + 0x2D02EF8D +}; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c new file mode 100644 index 0000000..8a2cf3c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -0,0 +1,1168 @@ +/** @file + * + * Static SMBIOS Table for RK35xx based platforms + * Derived from the quartz64_uefi, RaspberryPi and EmulatorPkg packages. + * + * Note - Arm SBBR ver 1.2 required and recommended SMBIOS structures: + * BIOS Information (Type 0) + * System Information (Type 1) + * Board Information (Type 2) - Recommended + * System Enclosure (Type 3) + * Processor Information (Type 4) - CPU Driver + * Cache Information (Type 7) - For cache that is external to processor + * Port Information (Type 8) - Recommended for platforms with physical ports + * System Slots (Type 9) - If system has slots + * OEM Strings (Type 11) - Recommended + * BIOS Language Information (Type 13) - Recommended + * System Event Log (Type 15) - Recommended (does not exit on RPi) + * Physical Memory Array (Type 16) + * Memory Device (Type 17) - For each socketed system-memory Device + * Memory Array Mapped Address (Type 19) - One per contiguous block per Physical Memroy Array + * System Boot Information (Type 32) + * IPMI Device Information (Type 38) - Required for platforms with IPMIv1.0 BMC Host Interface (not applicable to RPi) + * Onboard Devices Extended Information (Type 41) - Recommended + * Redfish Host Interface (Type 42) - Required for platforms supporting Redfish Host Interface (not applicable to RPi) + * + * Copyright (c) 2017-2021, Andrey Warkentin + * Copyright (c) 2013, Linaro.org + * Copyright (c) 2012, Apple Inc. All rights reserved.
    + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2020, ARM Limited. All rights reserved. + * Copyright (c) 2021 Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "Crc32Table.h" + +#define SMB_IS_DIGIT(c) (((c) >= '0') && ((c) <= '9')) + +STATIC UINT64 mMemorySize = 0; + +UINT32 +EFIAPI +CalculateCrc32NoComp( + IN UINT32 Crc, + IN VOID *Buffer, + IN UINTN Length + ) +{ + UINTN Index; + UINT8 *Ptr; + + ASSERT (Buffer != NULL); + ASSERT (Length <= (MAX_ADDRESS - ((UINTN) Buffer) + 1)); + + // + // Compute CRC + // + for (Index = 0, Ptr = Buffer; Index < Length; Index++, Ptr++) { + Crc = (Crc >> 8) ^ mCrcTable[(UINT8) Crc ^ *Ptr]; + } + + return Crc; +} + +/*********************************************************************** + SMBIOS data definition TYPE0 BIOS Information +************************************************************************/ +SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = { + { EFI_SMBIOS_TYPE_BIOS_INFORMATION, sizeof (SMBIOS_TABLE_TYPE0), 0 }, + 1, // Vendor String + 2, // BiosVersion String + (UINT16) (FixedPcdGet32 (PcdFdBaseAddress) / 0x10000), // BiosSegment + 3, // BiosReleaseDate String + (UINT8) (FixedPcdGet32 (PcdFdSize) / 0x10000), // BiosSize (in 64KB) + { // BiosCharacteristics + 0, // Reserved :2; ///< Bits 0-1. + 0, // Unknown :1; + 0, // BiosCharacteristicsNotSupported :1; + 0, // IsaIsSupported :1; + 0, // McaIsSupported :1; + 0, // EisaIsSupported :1; + 0, // PciIsSupported :1; /// No PCIe support since we hide ECAM from the OS + 0, // PcmciaIsSupported :1; + 0, // PlugAndPlayIsSupported :1; + 0, // ApmIsSupported :1; + 1, // BiosIsUpgradable :1; + 0, // BiosShadowingAllowed :1; + 0, // VlVesaIsSupported :1; + 0, // EscdSupportIsAvailable :1; + 0, // BootFromCdIsSupported :1; + 1, // SelectableBootIsSupported :1; + 0, // RomBiosIsSocketed :1; + 0, // BootFromPcmciaIsSupported :1; + 0, // EDDSpecificationIsSupported :1; + 0, // JapaneseNecFloppyIsSupported :1; + 0, // JapaneseToshibaFloppyIsSupported :1; + 0, // Floppy525_360IsSupported :1; + 0, // Floppy525_12IsSupported :1; + 0, // Floppy35_720IsSupported :1; + 0, // Floppy35_288IsSupported :1; + 0, // PrintScreenIsSupported :1; + 0, // Keyboard8042IsSupported :1; + 0, // SerialIsSupported :1; + 0, // PrinterIsSupported :1; + 0, // CgaMonoIsSupported :1; + 0, // NecPc98 :1; + 0 // ReservedForVendor :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor + ///< and bits 48-63 reserved for System Vendor. + }, + { // BIOSCharacteristicsExtensionBytes[] + 0x01, // AcpiIsSupported :1; + // UsbLegacyIsSupported :1; + // AgpIsSupported :1; + // I2OBootIsSupported :1; + // Ls120BootIsSupported :1; + // AtapiZipDriveBootIsSupported :1; + // Boot1394IsSupported :1; + // SmartBatteryIsSupported :1; + // BIOSCharacteristicsExtensionBytes[1] + 0x0c, // BiosBootSpecIsSupported :1; + // FunctionKeyNetworkBootIsSupported :1; + // TargetContentDistributionEnabled :1; + // UefiSpecificationSupported :1; + // VirtualMachineSupported :1; + // ExtensionByte2Reserved :3; + }, + 0, // SystemBiosMajorRelease + 0, // SystemBiosMinorRelease + 0, // EmbeddedControllerFirmwareMajorRelease + 0, // EmbeddedControllerFirmwareMinorRelease + { (UINT16) (FixedPcdGet32 (PcdFdSize) / 0x100000) }, // BiosSize (in MB since Bits 15:14 = 00b) +}; + +CHAR8 mBiosVendor[128] = "EDK2"; +CHAR8 mBiosVersion[128] = "EDK2-DEV"; +CHAR8 mBiosDate[12] = "00/00/0000"; + +CHAR8 *mBIOSInfoType0Strings[] = { + mBiosVendor, // Vendor + mBiosVersion, // Version + mBiosDate, // Release Date + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE1 System Information +************************************************************************/ +SMBIOS_TABLE_TYPE1 mSysInfoType1 = { + { EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, sizeof (SMBIOS_TABLE_TYPE1), 0 }, + 1, // Manufacturer String + 2, // ProductName String + 3, // Version String + 4, // SerialNumber String + { 0x25EF0280, 0xEC82, 0x42B0, { 0x8F, 0xB6, 0x10, 0xAD, 0xCC, 0xC6, 0x7C, 0x02 } }, + SystemWakeupTypePowerSwitch, + 5, // SKUNumber String + 6, // Family String +}; + +CHAR8 mSysInfoManufName[128]; +CHAR8 mSysInfoProductName[128]; +CHAR8 mSysInfoFamilyName[128]; +CHAR8 mSysInfoVersionName[128]; +CHAR8 mSysInfoSerial[sizeof (UINT64) * 2 + 1]; +CHAR8 mSysInfoSKU[sizeof (UINT64) * 2 + 1]; + +CHAR8 *mSysInfoType1Strings[] = { + mSysInfoManufName, + mSysInfoProductName, + mSysInfoVersionName, + mSysInfoSerial, + mSysInfoSKU, + mSysInfoFamilyName, + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE2 Board Information +************************************************************************/ +SMBIOS_TABLE_TYPE2 mBoardInfoType2 = { + { EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, sizeof (SMBIOS_TABLE_TYPE2), 0 }, + 1, // Manufacturer String + 2, // ProductName String + 3, // Version String + 4, // SerialNumber String + 5, // AssetTag String + { // FeatureFlag + 1, // Motherboard :1; + 0, // RequiresDaughterCard :1; + 0, // Removable :1; + 0, // Replaceable :1; + 0, // HotSwappable :1; + 0, // Reserved :3; + }, + 6, // LocationInChassis String + 0, // ChassisHandle; + BaseBoardTypeMotherBoard, // BoardType; + 0, // NumberOfContainedObjectHandles; + { 0 } // ContainedObjectHandles[1]; +}; + +CHAR8 mBoardInfoManufName[128]; +CHAR8 mBoardInfoProductName[128]; +CHAR8 mChassisAssetTag[128]; + +CHAR8 *mBoardInfoType2Strings[] = { + mBoardInfoManufName, + mBoardInfoProductName, + mSysInfoVersionName, + mSysInfoSerial, + mChassisAssetTag, + "Internal", + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE3 Enclosure Information +************************************************************************/ +SMBIOS_TABLE_TYPE3 mEnclosureInfoType3 = { + { EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, sizeof (SMBIOS_TABLE_TYPE3), 0 }, + 1, // Manufacturer String + MiscChassisEmbeddedPc, // Type; + 2, // Version String + 3, // SerialNumber String + 4, // AssetTag String + ChassisStateSafe, // BootupState; + ChassisStateSafe, // PowerSupplyState; + ChassisStateSafe, // ThermalState; + ChassisSecurityStatusNone,// SecurityStatus; + { 0, 0, 0, 0 }, // OemDefined[4]; + 0, // Height; + 1, // NumberofPowerCords; + 0, // ContainedElementCount; + 0, // ContainedElementRecordLength; + { { 0 } }, // ContainedElements[1]; +}; +CHAR8 *mEnclosureInfoType3Strings[] = { + mSysInfoManufName, + mSysInfoProductName, + mSysInfoSerial, + mChassisAssetTag, + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE4 Processor Information +************************************************************************/ +SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = { + { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + CentralProcessor, // ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + { 0x00, 0x00, 0x00, 0x00 }, + { 0x00, 0x00, 0x00, 0x00 } + }, + 3, // ProcessorVersion String; + { // Voltage; + 1, // ProcessorVoltageCapability5V :1; + 1, // ProcessorVoltageCapability3_3V :1; + 1, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be zero. + 0 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 0, // MaxSpeed; + 0, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeNone, // ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE. + 0xFFFF, // L1CacheHandle; + 0xFFFF, // L2CacheHandle; + 0xFFFF, // L3CacheHandle; + 0, // SerialNumber; + 0, // AssetTag; + 0, // PartNumber; + 4, // CoreCount; + 4, // EnabledCoreCount; + 4, // ThreadCount; + 0x6C, // ProcessorCharacteristics; ///< The enumeration value from PROCESSOR_CHARACTERISTIC_FLAGS + // ProcessorReserved1 :1; + // ProcessorUnknown :1; + // Processor64BitCapble :1; + // ProcessorMultiCore :1; + // ProcessorHardwareThread :1; + // ProcessorExecuteProtection :1; + // ProcessorEnhancedVirtualization :1; + // ProcessorPowerPerformanceCtrl :1; + // Processor128bitCapble :1; + // ProcessorReserved2 :7; + ProcessorFamilyARM, // ARM Processor Family; + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +CHAR8 mCpuName[128] = "Unknown ARM CPU"; + +CHAR8 *mProcessorInfoType4Strings[] = { + "Socket", + "Rockchip", + mCpuName, + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE7 Cache Information +************************************************************************/ +SMBIOS_TABLE_TYPE7 mCacheInfoType7_L1I = { + { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 }, + 1, // SocketDesignation String + 0x380, // Cache Configuration + //Cache Level :3 (L1) + //Cache Socketed :1 (Not Socketed) + //Reserved :1 + //Location :2 (Internal) + //Enabled/Disabled :1 (Enabled) + //Operational Mode :2 (Unknown) + //Reserved :6 + 0x0020, // Maximum Size (32KB) + 0x0020, // Install Size (32KB) + { // Supported SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + { // Current SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorParity, // Error Correction + CacheTypeInstruction, // System Cache Type + CacheAssociativity2Way // Associativity (RPi4 L1 Instruction cache is 3-way set associative, but SMBIOS spec does not define that) +}; +CHAR8 *mCacheInfoType7Strings_L1I[] = { + "L1 Instruction", + NULL +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_L1D = { + { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 }, + 1, // SocketDesignation String + 0x180, // Cache Configuration + //Cache Level :3 (L1) + //Cache Socketed :1 (Not Socketed) + //Reserved :1 + //Location :2 (Internal) + //Enabled/Disabled :1 (Enabled) + //Operational Mode :2 (WB) + //Reserved :6 + 0x0020, // Maximum Size (32KB) + 0x0020, // Install Size (32KB) + { // Supported SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + { // Current SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction + CacheTypeData, // System Cache Type + CacheAssociativity4Way // Associativity +}; +CHAR8 *mCacheInfoType7Strings_L1D[] = { + "L1 Data", + NULL +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_L2 = { + { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 }, + 1, // SocketDesignation String + 0x0181, // Cache Configuration + //Cache Level :3 (L2) + //Cache Socketed :1 (Not Socketed) + //Reserved :1 + //Location :2 (Internal) + //Enabled/Disabled :1 (Enabled) + //Operational Mode :2 (WB) + //Reserved :6 + 0x0200, // Maximum Size (512KB) + 0x0200, // Install Size (512KB) + { // Supported SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + { // Current SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction Multi + CacheTypeUnified, // System Cache Type + CacheAssociativity16Way // Associativity +}; +CHAR8 *mCacheInfoType7Strings_L2[] = { + "L2", + NULL +}; +/*********************************************************************** + SMBIOS data definition TYPE9 System Slot Information +************************************************************************/ +SMBIOS_TABLE_TYPE9 mSysSlotInfoType9 = { + { EFI_SMBIOS_TYPE_SYSTEM_SLOTS, sizeof (SMBIOS_TABLE_TYPE9), 0 }, + 1, // SlotDesignation String + SlotTypeOther, // SlotType; ///< The enumeration value from MISC_SLOT_TYPE. + SlotDataBusWidthOther, // SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH. + SlotUsageAvailable, // CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE. + SlotLengthOther, // SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH. + 0, // SlotID; + { // SlotCharacteristics1; + 1, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2; + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0, // Reserved :5; ///< Set to 0. + }, + 0xFFFF, // SegmentGroupNum; + 0xFF, // BusNum; + 0xFF, // DevFuncNum; +}; +CHAR8 *mSysSlotInfoType9Strings[] = { + "SD Card", + NULL +}; + + +/*********************************************************************** + SMBIOS data definition TYPE 11 OEM Strings +************************************************************************/ + +CHAR8 mOemInfoProductUrl[128]; +CHAR8 mOemInfoDeviceTreeName[128]; + +SMBIOS_TABLE_TYPE11 mOemStringsType11 = { + { EFI_SMBIOS_TYPE_OEM_STRINGS, sizeof (SMBIOS_TABLE_TYPE11), 0 }, + 2 // StringCount +}; +CHAR8 *mOemStringsType11Strings[] = { + mOemInfoProductUrl, + mOemInfoDeviceTreeName, + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE16 Physical Memory ArrayInformation +************************************************************************/ +SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = { + { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 }, + MemoryArrayLocationSystemBoard, // Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION. + MemoryArrayUseSystemMemory, // Use; ///< The enumeration value from MEMORY_ARRAY_USE. + MemoryErrorCorrectionUnknown, // MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION. + 0x00000000, // MaximumCapacity; + 0xFFFE, // MemoryErrorInformationHandle; + 1, // NumberOfMemoryDevices; + 0x00000000ULL, // ExtendedMaximumCapacity; +}; +CHAR8 *mPhyMemArrayInfoType16Strings[] = { + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE17 Memory Device Information +************************************************************************/ +CHAR8 mMemDevInfoVendor[128]; + +SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { + { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 }, + 0, // MemoryArrayHandle; // Should match SMBIOS_TABLE_TYPE16.Handle, initialized at runtime, refer to PhyMemArrayInfoUpdateSmbiosType16() + 0xFFFE, // MemoryErrorInformationHandle; (not provided) + 0xFFFF, // TotalWidth; (unknown) + 0xFFFF, // DataWidth; (unknown) + 0xFFFF, // Size; // When bit 15 is 0: Size in MB + // When bit 15 is 1: Size in KB, and continues in ExtendedSize + // initialized at runtime, refer to PhyMemArrayInfoUpdateSmbiosType16() + MemoryFormFactorChip, // FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR. + 0, // DeviceSet; + 1, // DeviceLocator String + 0, // BankLocator String + MemoryTypeLpddr4, // MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE. + { // TypeDetail; + 0, // Reserved :1; + 0, // Other :1; + 1, // Unknown :1; + 0, // FastPaged :1; + 0, // StaticColumn :1; + 0, // PseudoStatic :1; + 0, // Rambus :1; + 0, // Synchronous :1; + 0, // Cmos :1; + 0, // Edo :1; + 0, // WindowDram :1; + 0, // CacheDram :1; + 0, // Nonvolatile :1; + 0, // Registered :1; + 0, // Unbuffered :1; + 0, // Reserved1 :1; + }, + 0, // Speed; (unknown) + 2, // Manufacturer String + 0, // SerialNumber String + 0, // AssetTag String + 0, // PartNumber String + 0, // Attributes; (unknown rank) + 0, // ExtendedSize; (since Size < 32GB-1) + 0, // ConfiguredMemoryClockSpeed; (unknown) + 0, // MinimumVoltage; (unknown) + 0, // MaximumVoltage; (unknown) + 0, // ConfiguredVoltage; (unknown) + MemoryTechnologyDram, // MemoryTechnology ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY + {{ // MemoryOperatingModeCapability + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 1, // VolatileMemory :1; + 0, // ByteAccessiblePersistentMemory :1; + 0, // BlockAccessiblePersistentMemory :1; + 0 // Reserved :10; + }}, + 0, // FirwareVersion + 0, // ModuleManufacturerID (unknown) + 0, // ModuleProductID (unknown) + 0, // MemorySubsystemControllerManufacturerID (unknown) + 0, // MemorySubsystemControllerProductID (unknown) + 0, // NonVolatileSize + 0xFFFFFFFFFFFFFFFFULL,// VolatileSize // initialized at runtime, refer to PhyMemArrayInfoUpdateSmbiosType16() + 0, // CacheSize + 0, // LogicalSize (since MemoryType is not MemoryTypeLogicalNonVolatileDevice) + 0, // ExtendedSpeed, + 0 // ExtendedConfiguredMemorySpeed +}; +CHAR8 *mMemDevInfoType17Strings[] = { + "SDRAM", + mMemDevInfoVendor, + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE19 Memory Array Mapped Address Information +************************************************************************/ +SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = { + { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 }, + 0x00000000, // StartingAddress; + 0x00000000, // EndingAddress; + 0, // MemoryArrayHandle; // Should match SMBIOS_TABLE_TYPE16.Handle, initialized at runtime, refer to PhyMemArrayInfoUpdateSmbiosType16() + 1, // PartitionWidth; + 0, // ExtendedStartingAddress; // not used + 0, // ExtendedEndingAddress; // not used +}; +CHAR8 *mMemArrMapInfoType19Strings[] = { + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE32 Boot Information +************************************************************************/ +SMBIOS_TABLE_TYPE32 mBootInfoType32 = { + { EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, sizeof (SMBIOS_TABLE_TYPE32), 0 }, + { 0, 0, 0, 0, 0, 0 }, // Reserved[6]; + BootInformationStatusNoError // BootStatus +}; + +CHAR8 *mBootInfoType32Strings[] = { + NULL +}; + + +/** + + Create SMBIOS record. + + Converts a fixed SMBIOS structure and an array of pointers to strings into + an SMBIOS record where the strings are cat'ed on the end of the fixed record + and terminated via a double NULL and add to SMBIOS table. + + SMBIOS_TABLE_TYPE32 gSmbiosType12 = { + { EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS, sizeof (SMBIOS_TABLE_TYPE12), 0 }, + 1 // StringCount + }; + + CHAR8 *gSmbiosType12Strings[] = { + "Not Found", + NULL + }; + + ... + + LogSmbiosData ( + (EFI_SMBIOS_TABLE_HEADER*)&gSmbiosType12, + gSmbiosType12Strings + ); + + @param Template Fixed SMBIOS structure, required. + @param StringPack Array of strings to convert to an SMBIOS string pack. + NULL is OK. + @param DataSmbiosHandle The new SMBIOS record handle. + NULL is OK. +**/ + +EFI_STATUS +EFIAPI +LogSmbiosData ( + IN EFI_SMBIOS_TABLE_HEADER *Template, + IN CHAR8 **StringPack, + OUT EFI_SMBIOS_HANDLE *DataSmbiosHandle + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_PROTOCOL *Smbios; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_TABLE_HEADER *Record; + UINTN Index; + UINTN StringSize; + UINTN Size; + CHAR8 *Str; + + // + // Locate Smbios protocol. + // + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios); + + if (EFI_ERROR (Status)) { + return Status; + } + + // Calculate the size of the fixed record and optional string pack + + Size = Template->Length; + if (StringPack == NULL) { + // At least a double null is required + Size += 2; + } else { + for (Index = 0; StringPack[Index] != NULL; Index++) { + StringSize = AsciiStrSize (StringPack[Index]); + Size += StringSize; + } + if (StringPack[0] == NULL) { + // At least a double null is required + Size += 1; + } + + // Don't forget the terminating double null + Size += 1; + } + + // Copy over Template + Record = (EFI_SMBIOS_TABLE_HEADER*)AllocateZeroPool (Size); + if (Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (Record, Template, Template->Length); + + // Append string pack + Str = ((CHAR8*)Record) + Record->Length; + + for (Index = 0; StringPack[Index] != NULL; Index++) { + StringSize = AsciiStrSize (StringPack[Index]); + CopyMem (Str, StringPack[Index], StringSize); + Str += StringSize; + } + + *Str = 0; + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + gImageHandle, + &SmbiosHandle, + Record + ); + + if ((Status == EFI_SUCCESS) && (DataSmbiosHandle != NULL)) { + *DataSmbiosHandle = SmbiosHandle; + } + + ASSERT_EFI_ERROR (Status); + FreePool (Record); + return Status; +} + +/*********************************************************************** + SMBIOS data update TYPE0 BIOS Information +************************************************************************/ +VOID +BIOSInfoUpdateSmbiosType0 ( + VOID + ) +{ + INTN i; + INTN State = 0; + INTN Value[2]; + INTN Year = TIME_BUILD_YEAR; + INTN Month = TIME_BUILD_MONTH; + INTN Day = TIME_BUILD_DAY; + + mBIOSInfoType0.EmbeddedControllerFirmwareMajorRelease = 0; + mBIOSInfoType0.EmbeddedControllerFirmwareMinorRelease = 0; + + // mBiosVendor and mBiosVersion, which are referenced in mBIOSInfoType0Strings, + // are left unchanged if the following calls fail. + UnicodeStrToAsciiStrS ((CHAR16*)PcdGetPtr (PcdFirmwareVendor), + mBiosVendor, sizeof (mBiosVendor)); + UnicodeStrToAsciiStrS ((CHAR16*)PcdGetPtr (PcdFirmwareVersionString), + mBiosVersion, sizeof (mBiosVersion)); + ASSERT (Year >= 0 && Year <= 9999); + ASSERT (Month >= 1 && Month <= 12); + ASSERT (Day >= 1 && Day <= 31); + AsciiSPrint (mBiosDate, sizeof (mBiosDate), "%02d/%02d/%04d", Month, Day, Year); + + // Look for a "x.y" numeric string anywhere in mBiosVersion and + // try to parse it to populate the BIOS major and minor. + for (i = 0; (i < AsciiStrLen (mBiosVersion)) && (State < 4); i++) { + switch (State) { + case 0: + if (!SMB_IS_DIGIT (mBiosVersion[i])) + break; + Value[0] = Value[1] = 0; + State++; + // Fall through + case 1: + case 3: + if (SMB_IS_DIGIT (mBiosVersion[i])) { + Value[State / 2] = (Value[State / 2] * 10) + (mBiosVersion[i] - '0'); + if (Value[State / 2] > 255) { + while (SMB_IS_DIGIT (mBiosVersion[i + 1])) + i++; + // Reset our state (we may have something like "Firmware X83737.1 v1.23") + State = 0; + } + } else { + State++; + } + if (State != 2) + break; + // Fall through + case 2: + if ((mBiosVersion[i] == '.') && (SMB_IS_DIGIT (mBiosVersion[i + 1]))) { + State++; + } else { + State = 0; + } + break; + } + } + if ((State == 3) || (State == 4)) { + mBIOSInfoType0.SystemBiosMajorRelease = (UINT8)Value[0]; + mBIOSInfoType0.SystemBiosMinorRelease = (UINT8)Value[1]; + } + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mBIOSInfoType0, mBIOSInfoType0Strings, NULL); +} + +/*********************************************************************** + SMBIOS data update TYPE1 System Information +************************************************************************/ +VOID +I64ToHexString ( + IN OUT CHAR8* TargetStringSz, + IN UINT32 TargetStringSize, + IN UINT64 Value + ) +{ + static CHAR8 ItoH[] = { '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F' }; + UINT8 StringInx; + INT8 NibbleInx; + + ZeroMem ((void*)TargetStringSz, TargetStringSize); + + // + // Convert each nibble to hex string, starting from + // the highest non-zero nibble. + // + StringInx = 0; + for (NibbleInx = sizeof (UINT64) * 2; NibbleInx > 0; --NibbleInx) { + UINT64 NibbleMask = (((UINT64)0xF) << ((NibbleInx - 1) * 4)); + UINT8 Nibble = (UINT8)((Value & NibbleMask) >> ((NibbleInx - 1) * 4)); + + ASSERT (Nibble <= 0xF); + + if (StringInx < (TargetStringSize - 1)) { + TargetStringSz[StringInx++] = ItoH[Nibble]; + } else { + break; + } + } +} + +VOID +SysInfoUpdateSmbiosType1 ( + VOID + ) +{ + UINT8 OtpData[16]; + UINT8 SerialLo[8]; + UINT8 SerialHi[8]; + UINT32 BoardRevision = 0; + UINT64 BoardSerial = 0; + UINTN Index; + + // Get serial number from OTP + OtpReadId (OtpData); + for (Index = 0; Index < 8; Index++) { + SerialLo[Index] = OtpData[Index * 2 + 1]; + SerialHi[Index] = OtpData[Index * 2]; + } + BoardSerial = CalculateCrc32NoComp (0, SerialLo, sizeof SerialLo); + BoardSerial |= (UINT64)CalculateCrc32NoComp (BoardSerial, SerialHi, sizeof SerialHi) << 32; + + AsciiStrCpyS (mSysInfoProductName, sizeof (mSysInfoProductName), (CHAR8 *) PcdGetPtr(PcdPlatformName)); + AsciiStrCpyS (mSysInfoFamilyName, sizeof (mSysInfoFamilyName), (CHAR8 *) PcdGetPtr(PcdFamilyName)); + AsciiStrCpyS (mSysInfoManufName, sizeof (mSysInfoManufName), (CHAR8 *) PcdGetPtr(PcdPlatformVendorName)); + AsciiSPrint (mSysInfoVersionName, sizeof (mSysInfoVersionName), "%X", BoardRevision); + + I64ToHexString (mSysInfoSKU, sizeof (mSysInfoSKU), BoardRevision); + I64ToHexString (mSysInfoSerial, sizeof (mSysInfoSerial), BoardSerial); + + DEBUG ((DEBUG_INFO, "Board Serial Number: %a\n", mSysInfoSerial)); + + mSysInfoType1.Uuid.Data1 = BoardRevision; + mSysInfoType1.Uuid.Data2 = 0x0; + mSysInfoType1.Uuid.Data3 = 0x0; + // Swap endianness, so that the serial is more user-friendly as a UUID + BoardSerial = SwapBytes64 (BoardSerial); + CopyMem (mSysInfoType1.Uuid.Data4, &BoardSerial, sizeof (BoardSerial)); + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mSysInfoType1, mSysInfoType1Strings, NULL); +} + +/*********************************************************************** + SMBIOS data update TYPE2 Board Information +************************************************************************/ +VOID +BoardInfoUpdateSmbiosType2 ( + VOID + ) +{ + CHAR8 *BoardName; + CHAR8 *BoardManuf; + CHAR8 *PlatformName; + CHAR8 *PlatformManuf; + + BoardName = (CHAR8 *) PcdGetPtr(PcdBoardName); + BoardManuf = (CHAR8 *) PcdGetPtr(PcdBoardVendorName); + PlatformName = (CHAR8 *) PcdGetPtr(PcdPlatformName); + PlatformManuf = (CHAR8 *) PcdGetPtr(PcdPlatformVendorName); + + AsciiStrCpyS (mBoardInfoProductName, sizeof (mBoardInfoProductName), + (AsciiStrCmp(BoardName, "Unknown") == 0) ? PlatformName : BoardName); + + AsciiStrCpyS (mBoardInfoManufName, sizeof (mBoardInfoManufName), + (AsciiStrCmp(BoardManuf, "Unknown") == 0) ? PlatformManuf : BoardManuf); + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mBoardInfoType2, mBoardInfoType2Strings, NULL); +} + +/*********************************************************************** + SMBIOS data update TYPE3 Enclosure Information +************************************************************************/ +VOID +EnclosureInfoUpdateSmbiosType3 ( + VOID + ) +{ + EFI_SMBIOS_HANDLE SmbiosHandle; + + // SMBIOS referenced strings cannot be NULL. If no AssetTag is set, default to a blank space. + UnicodeStrToAsciiStrS(L" ", mChassisAssetTag, sizeof(mChassisAssetTag)); + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mEnclosureInfoType3, mEnclosureInfoType3Strings, &SmbiosHandle); + + // Set Type2 ChassisHandle to point to the newly added Type3 handle + mBoardInfoType2.ChassisHandle = (UINT16) SmbiosHandle; +} + + +STATIC UINT32 +ProcessorGetRate ( + VOID + ) +{ + EFI_STATUS Status; + SCMI_CLOCK_PROTOCOL *ClockProtocol; + EFI_GUID ClockProtocolGuid = ARM_SCMI_CLOCK_PROTOCOL_GUID; + UINT64 Rate; + UINT32 ClockId = 0; + + // If we can't query SCMI, fallback to reading from CRU registers + //Rate = CruGetCoreClockRate (); + + Rate = 1200; + + Status = gBS->LocateProtocol ( + &ClockProtocolGuid, + NULL, + (VOID**)&ClockProtocol + ); + if (EFI_ERROR (Status)) { + return (UINT32)Rate; + } + + ClockProtocol->RateGet (ClockProtocol, ClockId, &Rate); + + DEBUG ((DEBUG_INFO, "SCMI: SMBIOS reported rate %luHz\n", Rate)); + + return (UINT32)Rate; +} + +/*********************************************************************** + SMBIOS data update TYPE4 Processor Information +************************************************************************/ +VOID +ProcessorInfoUpdateSmbiosType4 ( + IN UINTN MaxCpus + ) +{ + UINT32 Rate; + UINT64 *ProcessorId; + + mProcessorInfoType4.CoreCount = (UINT8)MaxCpus; + mProcessorInfoType4.CoreCount2 = (UINT8)MaxCpus; + mProcessorInfoType4.EnabledCoreCount = (UINT8)MaxCpus; + mProcessorInfoType4.EnabledCoreCount2 = (UINT8)MaxCpus; + mProcessorInfoType4.ThreadCount = (UINT8)MaxCpus; + mProcessorInfoType4.ThreadCount2 = (UINT8)MaxCpus; + + Rate = ProcessorGetRate (); + mProcessorInfoType4.MaxSpeed = Rate / 1000000; + mProcessorInfoType4.CurrentSpeed = Rate / 1000000; + + AsciiStrCpyS (mCpuName, sizeof(mCpuName), (CHAR8 *) PcdGetPtr (PcdProcessorName)); + + ProcessorId = (UINT64 *)&(mProcessorInfoType4.ProcessorId); + *ProcessorId = ArmReadMidr(); + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mProcessorInfoType4, mProcessorInfoType4Strings, NULL); +} + +/*********************************************************************** + SMBIOS data update TYPE7 Cache Information +************************************************************************/ +VOID +CacheInfoUpdateSmbiosType7 ( + VOID + ) +{ + EFI_SMBIOS_HANDLE SmbiosHandle; + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L1I, mCacheInfoType7Strings_L1I, NULL); + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L1D, mCacheInfoType7Strings_L1D, &SmbiosHandle); + // Set Type4 L1CacheHandle to point to the newly added L1 Data Cache + mProcessorInfoType4.L1CacheHandle = (UINT16) SmbiosHandle; + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mCacheInfoType7_L2, mCacheInfoType7Strings_L2, &SmbiosHandle); + // Set Type4 L2CacheHandle to point to the newly added L2 Cache + mProcessorInfoType4.L2CacheHandle = (UINT16) SmbiosHandle; +} + +/*********************************************************************** + SMBIOS data update TYPE9 System Slot Information +************************************************************************/ +VOID +SysSlotInfoUpdateSmbiosType9 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mSysSlotInfoType9, mSysSlotInfoType9Strings, NULL); +} + +/*********************************************************************** + SMBIOS data update TYPE11 OEM Strings +************************************************************************/ +VOID +OemStringsUpdateSmbiosType11 ( + VOID + ) +{ + AsciiStrCpyS (mOemInfoProductUrl, sizeof (mOemInfoProductUrl), (CHAR8 *) PcdGetPtr(PcdProductUrl)); + AsciiStrCpyS (mOemInfoDeviceTreeName, sizeof (mOemInfoDeviceTreeName), (CHAR8 *) PcdGetPtr(PcdDeviceTreeName)); + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mOemStringsType11, mOemStringsType11Strings, NULL); +} + +/*********************************************************************** + SMBIOS data update TYPE16 Physical Memory Array Information +************************************************************************/ +VOID +PhyMemArrayInfoUpdateSmbiosType16 ( + VOID + ) +{ + EFI_SMBIOS_HANDLE MemArraySmbiosHandle; + + // + // Update memory size fields: + // - Type 16 MaximumCapacity in KB + // - Type 17 size in MB (since bit 15 = 0) + // - Type 17 VolatileSize in Bytes + // + + mMemDevInfoType17.Size = mMemorySize / (1024 * 1024); + + mPhyMemArrayInfoType16.MaximumCapacity = mMemDevInfoType17.Size * 1024; // Size in KB + mMemDevInfoType17.VolatileSize = MultU64x32 (mMemDevInfoType17.Size, 1024 * 1024); // Size in Bytes + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mPhyMemArrayInfoType16, mPhyMemArrayInfoType16Strings, &MemArraySmbiosHandle); + + // + // Update the memory device information and memory array map with the newly added type 16 handle + // + mMemDevInfoType17.MemoryArrayHandle = MemArraySmbiosHandle; + mMemArrMapInfoType19.MemoryArrayHandle = MemArraySmbiosHandle; +} + +/*********************************************************************** + SMBIOS data update TYPE17 Memory Device Information +************************************************************************/ +VOID +MemDevInfoUpdateSmbiosType17 ( + VOID + ) +{ + AsciiStrCpyS (mMemDevInfoVendor, sizeof (mMemDevInfoVendor), (CHAR8 *) PcdGetPtr(PcdMemoryVendorName)); + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mMemDevInfoType17, mMemDevInfoType17Strings, NULL); +} + +/*********************************************************************** + SMBIOS data update TYPE19 Memory Array Map Information +************************************************************************/ +VOID +MemArrMapInfoUpdateSmbiosType19 ( + VOID + ) +{ + // Note: Type 19 addresses are expressed in KB, not bytes + mMemArrMapInfoType19.StartingAddress = PcdGet64(PcdSystemMemoryBase) / 1024; + + mMemArrMapInfoType19.EndingAddress = mMemArrMapInfoType19.StartingAddress + + mMemorySize / 1024 - 1; + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings, NULL); +} + + +/*********************************************************************** + SMBIOS data update TYPE32 Boot Information +************************************************************************/ +VOID +BootInfoUpdateSmbiosType32 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mBootInfoType32, mBootInfoType32Strings, NULL); +} + +/*********************************************************************** + Driver Entry +************************************************************************/ +EFI_STATUS +EFIAPI +PlatformSmbiosDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + DEBUG ((DEBUG_INFO, "PlatformSmbiosDriverEntryPoint() called\n")); + + mMemorySize = SdramGetMemorySize (); + + BIOSInfoUpdateSmbiosType0 (); + + SysInfoUpdateSmbiosType1 (); + + EnclosureInfoUpdateSmbiosType3 (); // Add Type 3 first to get chassis handle for use in Type 2 + + BoardInfoUpdateSmbiosType2 (); + + CacheInfoUpdateSmbiosType7 (); // Add Type 7 first to get Cache handle for use in Type 4 + + ProcessorInfoUpdateSmbiosType4 (4); //One example for creating and updating + + SysSlotInfoUpdateSmbiosType9 (); + + OemStringsUpdateSmbiosType11 (); + + PhyMemArrayInfoUpdateSmbiosType16 (); + + MemDevInfoUpdateSmbiosType17 (); + + MemArrMapInfoUpdateSmbiosType19 (); + + BootInfoUpdateSmbiosType32 (); + + DEBUG ((DEBUG_INFO, "PlatformSmbiosDriverEntryPoint() returning\n")); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf new file mode 100644 index 0000000..81b40e0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf @@ -0,0 +1,73 @@ + +#/** @file +# +# SMBIOS Table for RK35xx platforms +# +# Copyright (c) 2021 Jared McNeill +# Copyright (c) 2017-2021 Andrei Warkentin +# Copyright (c) Microsoft Corporation. All rights reserved. +# Copyright (c) 2013 Linaro.org +# Copyright (c) 2020, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformSmbiosDxe + FILE_GUID = 196E5BEB-983E-4B58-8292-BC310F6962DF + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformSmbiosDriverEntryPoint + +[Sources] + PlatformSmbiosDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + UefiBootServicesTableLib + MemoryAllocationLib + BaseMemoryLib + BaseLib + UefiLib + UefiDriverEntryPoint + DebugLib + PrintLib + TimeBaseLib + CruLib + SdramLib + OtpLib + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL SOMETIMES_CONSUMED + +[Guids] + +[Depex] + gEfiSmbiosProtocolGuid + +[Pcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gRockchipTokenSpaceGuid.PcdProcessorName + gRockchipTokenSpaceGuid.PcdPlatformName + gRockchipTokenSpaceGuid.PcdPlatformVendorName + gRockchipTokenSpaceGuid.PcdBoardName + gRockchipTokenSpaceGuid.PcdBoardVendorName + gRockchipTokenSpaceGuid.PcdProductUrl + gRockchipTokenSpaceGuid.PcdDeviceTreeName + gRockchipTokenSpaceGuid.PcdFamilyName + gRockchipTokenSpaceGuid.PcdMemoryVendorName + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.c new file mode 100644 index 0000000..ff5f768 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.c @@ -0,0 +1,1458 @@ +/** @file + * + * Firmware Volume Block driver for non-volatile data storage on + * SPI NOR (persistent at runtime) or SD/eMMC (persistent only at boot time). + * + * Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + * Copyright (c) 2017 Marvell International Ltd. + * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "RkFvbDxe.h" + +RKATAG_BOOTDEV_TYPE mBootDeviceType; +VOID *mDiskIoRegistration; +STATIC EFI_EVENT mFvbVirtualAddrChangeEvent; +STATIC FVB_DEVICE *mFvbDevice; +STATIC CONST FVB_DEVICE mRkFvbFlashInstanceTemplate = { + NULL, // SpiFlashProtocol ... NEED TO BE FILLED + FALSE, // IsSpiFlashAvailable ... NEED TO BE FILLED + FALSE, // IsFvbHeaderValid ... NEED TO BE FILLED + + NULL, // DiskDevice ... NEED TO BE FILLED + 0, // DiskMediaId ... NEED TO BE FILLED + FALSE, // DiskDataInvalidated ... NEED TO BE FILLED + + NULL, // Handle ... NEED TO BE FILLED + + FVB_FLASH_SIGNATURE, // Signature + + 0, // DeviceBaseAddress ... NEED TO BE FILLED + 0, // RegionBaseAddress ... NEED TO BE FILLED + SIZE_256KB, // Size + 0, // FvbOffset ... NEED TO BE FILLED + 0, // FvbSize ... NEED TO BE FILLED + 0, // StartLba + + { + 0, // MediaId ... NEED TO BE FILLED + FALSE, // RemovableMedia + TRUE, // MediaPresent + FALSE, // LogicalPartition + FALSE, // ReadOnly + FALSE, // WriteCaching; + 0, // BlockSize ... NEED TO BE FILLED + 4, // IoAlign + 0, // LastBlock ... NEED TO BE FILLED + 0, // LowestAlignedLba + 1, // LogicalBlocksPerPhysicalBlock + }, //Media; + + { + FvbGetAttributes, // GetAttributes + FvbSetAttributes, // SetAttributes + FvbGetPhysicalAddress, // GetPhysicalAddress + FvbGetBlockSize, // GetBlockSize + FvbRead, // Read + FvbWrite, // Write + FvbEraseBlocks, // EraseBlocks + NULL, // ParentHandle + }, // FvbProtocol; + + { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)sizeof (VENDOR_DEVICE_PATH), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + { 0xfc0cb972, 0x21df, 0x44d2, { 0x92, 0xa5, 0x78, 0x98, 0x99, 0xcb, 0xf6, 0x61 } } + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } + } + } // DevicePath +}; + +// +// The Firmware Volume Block Protocol is the low-level interface +// to a firmware volume. File-level access to a firmware volume +// should not be done using the Firmware Volume Block Protocol. +// Normal access to a firmware volume must use the Firmware +// Volume Protocol. Typically, only the file system driver that +// produces the Firmware Volume Protocol will bind to the +// Firmware Volume Block Protocol. +// + +/** + Initialises the FV Header and Variable Store Header + to support variable operations. + + @param[in] Ptr - Location to initialise the headers + +**/ +STATIC +EFI_STATUS +FvbInitFvAndVariableStoreHeaders ( + IN FVB_DEVICE *FlashInstance + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + EFI_STATUS Status; + VOID* Headers; + UINTN HeadersLength; + UINTN BlockSize; + + HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + + sizeof (EFI_FV_BLOCK_MAP_ENTRY) + + sizeof (VARIABLE_STORE_HEADER); + Headers = AllocateZeroPool (HeadersLength); + + BlockSize = FlashInstance->Media.BlockSize; + + // + // FirmwareVolumeHeader->FvLength is declared to have the Variable area + // AND the FTW working area AND the FTW Spare contiguous. + // + ASSERT (PcdGet64 (PcdFlashNvStorageVariableBase64) + + PcdGet32 (PcdFlashNvStorageVariableSize) == + PcdGet64 (PcdFlashNvStorageFtwWorkingBase64)); + ASSERT (PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) == + PcdGet64 (PcdFlashNvStorageFtwSpareBase64)); + + // Check if the size of the area is at least one block size + ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && + (PcdGet32 (PcdFlashNvStorageVariableSize) / BlockSize > 0)); + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && + (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / BlockSize > 0)); + ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && + (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / BlockSize > 0)); + + // Ensure the Variable areas are aligned on block size boundaries + //ASSERT ((PcdGet64 (PcdFlashNvStorageVariableBase64) % BlockSize) == 0); + ASSERT ((PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % BlockSize) == 0); + ASSERT ((PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % BlockSize) == 0); + + // + // EFI_FIRMWARE_VOLUME_HEADER + // + FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers; + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid); + FirmwareVolumeHeader->FvLength = FlashInstance->FvbSize; + FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE; + FirmwareVolumeHeader->Attributes = EFI_FVB2_READ_ENABLED_CAP | + EFI_FVB2_READ_STATUS | + EFI_FVB2_STICKY_WRITE | + EFI_FVB2_ERASE_POLARITY | + EFI_FVB2_WRITE_STATUS | + EFI_FVB2_WRITE_ENABLED_CAP | + EFI_FVB2_MEMORY_MAPPED; + + FirmwareVolumeHeader->HeaderLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + + sizeof (EFI_FV_BLOCK_MAP_ENTRY); + FirmwareVolumeHeader->Revision = EFI_FVH_REVISION; + FirmwareVolumeHeader->BlockMap[0].NumBlocks = FlashInstance->Media.LastBlock + 1; + FirmwareVolumeHeader->BlockMap[0].Length = FlashInstance->Media.BlockSize; + FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0; + FirmwareVolumeHeader->BlockMap[1].Length = 0; + FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ( + (UINT16 *)FirmwareVolumeHeader, + FirmwareVolumeHeader->HeaderLength); + + // + // VARIABLE_STORE_HEADER + // + VariableStoreHeader = (VOID *)((UINTN)Headers + + FirmwareVolumeHeader->HeaderLength); + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid); + VariableStoreHeader->Size = PcdGet32(PcdFlashNvStorageVariableSize) - + FirmwareVolumeHeader->HeaderLength; + VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED; + VariableStoreHeader->State = VARIABLE_STORE_HEALTHY; + + // Install the combined super-header in the flash device + Status = FvbWrite (&FlashInstance->FvbProtocol, 0, 0, &HeadersLength, Headers); + + FreePool (Headers); + + return Status; +} + +/** + Check the integrity of firmware volume header. + + @param[in] FwVolHeader - A pointer to a firmware volume header + + @retval EFI_SUCCESS - The firmware volume is consistent + @retval EFI_NOT_FOUND - The firmware volume has been corrupted. + +**/ +STATIC +EFI_STATUS +FvbValidateFvHeader ( + IN FVB_DEVICE *FlashInstance + ) +{ + UINT16 Checksum; + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + UINTN VariableStoreLength; + + FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *)FlashInstance->RegionBaseAddress; + + // Verify the header revision, header signature, length + if ((FwVolHeader->Revision != EFI_FVH_REVISION) || + (FwVolHeader->Signature != EFI_FVH_SIGNATURE) || + (FwVolHeader->FvLength != FlashInstance->FvbSize)) { + DEBUG ((DEBUG_ERROR, + "%a: No Firmware Volume header present\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + // Check the Firmware Volume Guid + if (!CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)) { + DEBUG ((DEBUG_ERROR, + "%a: Firmware Volume Guid non-compatible\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + // Verify the header checksum + Checksum = CalculateSum16 ((UINT16 *)FwVolHeader, FwVolHeader->HeaderLength); + if (Checksum != 0) { + DEBUG ((DEBUG_ERROR, + "%a: FV checksum is invalid (Checksum:0x%x)\n", + __FUNCTION__, + Checksum)); + return EFI_NOT_FOUND; + } + + VariableStoreHeader = (VOID *)((UINTN)FwVolHeader + FwVolHeader->HeaderLength); + + // Check the Variable Store Guid + if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) && + !CompareGuid (&VariableStoreHeader->Signature, + &gEfiAuthenticatedVariableGuid)) { + DEBUG ((DEBUG_ERROR, + "%a: Variable Store Guid non-compatible\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - + FwVolHeader->HeaderLength; + if (VariableStoreHeader->Size != VariableStoreLength) { + DEBUG ((DEBUG_ERROR, + "%a: Variable Store Length does not match\n", + __FUNCTION__)); + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + The GetAttributes() function retrieves the attributes and + current settings of the block. + + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and + current settings are returned. + Type EFI_FVB_ATTRIBUTES_2 is defined in + EFI_FIRMWARE_VOLUME_HEADER. + + @retval EFI_SUCCESS The firmware volume attributes were returned. + + **/ +EFI_STATUS +EFIAPI +FvbGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + EFI_FVB_ATTRIBUTES_2 *FlashFvbAttributes; + FVB_DEVICE *FlashInstance; + + FlashInstance = INSTANCE_FROM_FVB_THIS (This); + + FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *)FlashInstance->RegionBaseAddress; + FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2 *)&(FwVolHeader->Attributes); + + *Attributes = *FlashFvbAttributes; + + return EFI_SUCCESS; +} + +/** + The SetAttributes() function sets configurable firmware volume attributes + and returns the new settings of the firmware volume. + + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Attributes On input, Attributes is a pointer to + EFI_FVB_ATTRIBUTES_2 that contains the desired + firmware volume settings. + On successful return, it contains the new + settings of the firmware volume. + + @retval EFI_SUCCESS The firmware volume attributes were returned. + + @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with + the capabilities as declared in the firmware + volume header. + + **/ +EFI_STATUS +EFIAPI +FvbSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +{ + EFI_FVB_ATTRIBUTES_2 OldAttributes; + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; + EFI_FVB_ATTRIBUTES_2 UnchangedAttributes; + FVB_DEVICE *FlashInstance; + UINT32 Capabilities; + UINT32 OldStatus; + UINT32 NewStatus; + + FlashInstance = INSTANCE_FROM_FVB_THIS (This); + + // + // Obtain attributes from FVB header + // + FvbGetAttributes (This, &FlashFvbAttributes); + + OldAttributes = FlashFvbAttributes; + Capabilities = OldAttributes & EFI_FVB2_CAPABILITIES; + OldStatus = OldAttributes & EFI_FVB2_STATUS; + NewStatus = *Attributes & EFI_FVB2_STATUS; + + UnchangedAttributes = EFI_FVB2_READ_DISABLED_CAP | \ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP | \ + EFI_FVB2_STICKY_WRITE | \ + EFI_FVB2_ERASE_POLARITY | \ + EFI_FVB2_READ_LOCK_CAP | \ + EFI_FVB2_WRITE_LOCK_CAP | \ + EFI_FVB2_ALIGNMENT | \ + EFI_FVB2_MEMORY_MAPPED; + + // + // Some attributes of FV is read only can *not* be set + // + if ((OldAttributes & UnchangedAttributes) ^ + (*Attributes & UnchangedAttributes)) { + return EFI_INVALID_PARAMETER; + } + // + // If firmware volume is locked, no status bit can be updated + // + if (OldAttributes & EFI_FVB2_LOCK_STATUS) { + if (OldStatus ^ NewStatus) { + return EFI_ACCESS_DENIED; + } + } + // + // Test read disable + // + if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) == 0) { + if ((NewStatus & EFI_FVB2_READ_STATUS) == 0) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test read enable + // + if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) == 0) { + if (NewStatus & EFI_FVB2_READ_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test write disable + // + if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) == 0) { + if ((NewStatus & EFI_FVB2_WRITE_STATUS) == 0) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test write enable + // + if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) == 0) { + if (NewStatus & EFI_FVB2_WRITE_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test lock + // + if ((Capabilities & EFI_FVB2_LOCK_CAP) == 0) { + if (NewStatus & EFI_FVB2_LOCK_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + FlashFvbAttributes = FlashFvbAttributes & (0xFFFFFFFF & (~EFI_FVB2_STATUS)); + FlashFvbAttributes = FlashFvbAttributes | NewStatus; + *Attributes = FlashFvbAttributes; + + return EFI_SUCCESS; +} + +/** + The GetPhysicalAddress() function retrieves the base address of + a memory-mapped firmware volume. This function should be called + only for memory-mapped firmware volumes. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Address Pointer to a caller-allocated + EFI_PHYSICAL_ADDRESS that, on successful + return from GetPhysicalAddress(), contains the + base address of the firmware volume. + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped. + + **/ +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +{ + FVB_DEVICE *FlashInstance; + + ASSERT (Address != NULL); + + FlashInstance = INSTANCE_FROM_FVB_THIS (This); + + *Address = FlashInstance->RegionBaseAddress; + + return EFI_SUCCESS; +} + +/** + The GetBlockSize() function retrieves the size of the requested + block. It also returns the number of additional blocks with + the identical size. The GetBlockSize() function is used to + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER). + + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba Indicates the block whose size to return + + @param BlockSize Pointer to a caller-allocated UINTN in which + the size of the block is returned. + + @param NumberOfBlocks Pointer to a caller-allocated UINTN in + which the number of consecutive blocks, + starting with Lba, is returned. All + blocks in this range have a size of + BlockSize. + + + @retval EFI_SUCCESS The firmware volume base address was returned. + + @retval EFI_INVALID_PARAMETER The requested LBA is out of range. + + **/ +EFI_STATUS +EFIAPI +FvbGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumberOfBlocks + ) +{ + FVB_DEVICE *FlashInstance; + + FlashInstance = INSTANCE_FROM_FVB_THIS (This); + + if (Lba > FlashInstance->Media.LastBlock) { + DEBUG ((DEBUG_ERROR, + "%a: Error: Requested LBA %ld is beyond the last available LBA (%ld).\n", + __FUNCTION__, + Lba, + FlashInstance->Media.LastBlock)); + return EFI_INVALID_PARAMETER; + } else { + // Assume equal sized blocks in all flash devices + *BlockSize = (UINTN)FlashInstance->Media.BlockSize; + *NumberOfBlocks = (UINTN)(FlashInstance->Media.LastBlock - Lba + 1); + + return EFI_SUCCESS; + } +} + +/** + Reads the specified number of bytes into a buffer from the specified block. + + The Read() function reads the requested number of bytes from the + requested block and stores them in the provided buffer. + Implementations should be mindful that the firmware volume + might be in the ReadDisabled state. If it is in this state, + the Read() function must return the status code + EFI_ACCESS_DENIED without modifying the contents of the + buffer. The Read() function must also prevent spanning block + boundaries. If a read is requested that would span a block + boundary, the read must read up to the boundary but not + beyond. The output parameter NumBytes must be set to correctly + indicate the number of bytes actually read. The caller must be + aware that a read may be partially completed. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba The starting logical block index from which to read + + @param Offset Offset into the block at which to begin reading. + + @param NumBytes Pointer to a UINTN. + At entry, *NumBytes contains the total size of the + buffer. + At exit, *NumBytes contains the total number of + bytes read. + + @param Buffer Pointer to a caller-allocated buffer that will be + used to hold the data that is read. + + @retval EFI_SUCCESS The firmware volume was read successfully, and + contents are in Buffer. + + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. + On output, NumBytes contains the total number of + bytes returned in Buffer. + + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state. + + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and + could not be read. + + **/ +EFI_STATUS +EFIAPI +FvbRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN OUT UINT8 *Buffer + ) +{ + FVB_DEVICE *FlashInstance; + UINTN BlockSize; + UINTN DataOffset; + + FlashInstance = INSTANCE_FROM_FVB_THIS (This); + + // Cache the block size to avoid de-referencing pointers all the time + BlockSize = FlashInstance->Media.BlockSize; + + // + // The read must not span block boundaries. + // We need to check each variable individually because adding two large + // values together overflows. + // + if (Offset >= BlockSize || + *NumBytes > BlockSize || + (Offset + *NumBytes) > BlockSize) { + DEBUG ((DEBUG_ERROR, + "%a: Wrong buffer size: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", + __FUNCTION__, + Offset, + *NumBytes, + BlockSize)); + return EFI_BAD_BUFFER_SIZE; + } + + // No bytes to read + if (*NumBytes == 0) { + return EFI_SUCCESS; + } + + DataOffset = GET_DATA_OFFSET (FlashInstance->RegionBaseAddress + Offset, + FlashInstance->StartLba + Lba, + FlashInstance->Media.BlockSize); + + // Read the memory-mapped data + CopyMem (Buffer, (UINTN *)DataOffset, *NumBytes); + + return EFI_SUCCESS; +} + +/** + Writes the specified number of bytes from the input buffer to the block. + + The Write() function writes the specified number of bytes from + the provided buffer to the specified block and offset. If the + firmware volume is sticky write, the caller must ensure that + all the bits of the specified range to write are in the + EFI_FVB_ERASE_POLARITY state before calling the Write() + function, or else the result will be unpredictable. This + unpredictability arises because, for a sticky-write firmware + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY + state but cannot flip it back again. Before calling the + Write() function, it is recommended for the caller to first call + the EraseBlocks() function to erase the specified block to + write. A block erase cycle will transition bits from the + (NOT)EFI_FVB_ERASE_POLARITY state back to the + EFI_FVB_ERASE_POLARITY state. Implementations should be + mindful that the firmware volume might be in the WriteDisabled + state. If it is in this state, the Write() function must + return the status code EFI_ACCESS_DENIED without modifying the + contents of the firmware volume. The Write() function must + also prevent spanning block boundaries. If a write is + requested that spans a block boundary, the write must store up + to the boundary but not beyond. The output parameter NumBytes + must be set to correctly indicate the number of bytes actually + written. The caller must be aware that a write may be + partially completed. All writes, partial or otherwise, must be + fully flushed to the hardware before the Write() service + returns. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. + + @param Lba The starting logical block index to write to. + + @param Offset Offset into the block at which to begin writing. + + @param NumBytes The pointer to a UINTN. + At entry, *NumBytes contains the total size of the + buffer. + At exit, *NumBytes contains the total number of + bytes actually written. + + @param Buffer The pointer to a caller-allocated buffer that + contains the source for the write. + + @retval EFI_SUCCESS The firmware volume was written successfully. + + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary. + On output, NumBytes contains the total number of + bytes actually written. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state. + + @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be + written. + + + **/ +EFI_STATUS +EFIAPI +FvbWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + FVB_DEVICE *FlashInstance; + UINTN DataOffset; + + + FlashInstance = INSTANCE_FROM_FVB_THIS (This); + + DataOffset = GET_DATA_OFFSET (FlashInstance->FvbOffset + Offset, + FlashInstance->StartLba + Lba, + FlashInstance->Media.BlockSize); + + if (FlashInstance->IsSpiFlashAvailable) { + Status = FlashInstance->SpiFlashProtocol->Write (FlashInstance->SpiFlashProtocol, + DataOffset, + Buffer, + *NumBytes); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to write to Spi device\n", __FUNCTION__)); + return Status; + } + } + + // Update shadow buffer + DataOffset = GET_DATA_OFFSET (FlashInstance->RegionBaseAddress + Offset, + FlashInstance->StartLba + Lba, + FlashInstance->Media.BlockSize); + + CopyMem ((UINTN *)DataOffset, Buffer, *NumBytes); + + // Must sync the data if it's on a disk + FlashInstance->DiskDataInvalidated = TRUE; + + return EFI_SUCCESS; +} + +/** + Erases and initialises a firmware volume block. + + The EraseBlocks() function erases one or more blocks as denoted + by the variable argument list. The entire parameter list of + blocks must be verified before erasing any blocks. If a block is + requested that does not exist within the associated firmware + volume (it has a larger index than the last block of the + firmware volume), the EraseBlocks() function must return the + status code EFI_INVALID_PARAMETER without modifying the contents + of the firmware volume. Implementations should be mindful that + the firmware volume might be in the WriteDisabled state. If it + is in this state, the EraseBlocks() function must return the + status code EFI_ACCESS_DENIED without modifying the contents of + the firmware volume. All calls to EraseBlocks() must be fully + flushed to the hardware before the EraseBlocks() service + returns. + + @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL + instance. + + @param ... The variable argument list is a list of tuples. + Each tuple describes a range of LBAs to erase + and consists of the following: + - An EFI_LBA that indicates the starting LBA + - A UINTN that indicates the number of blocks + to erase. + + The list is terminated with an + EFI_LBA_LIST_TERMINATOR. + + @retval EFI_SUCCESS The erase request successfully completed. + + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled + state. + + @retval EFI_DEVICE_ERROR The block device is not functioning correctly + and could not be written. + The firmware device may have been partially + erased. + + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable + argument list do not exist in the firmware + volume. + + **/ +EFI_STATUS +EFIAPI +FvbEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, + ... + ) +{ + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; + FVB_DEVICE *FlashInstance; + EFI_STATUS Status; + VA_LIST Args; + UINTN BlockAddress; // Physical address of Lba to erase + EFI_LBA StartingLba; // Lba from which we start erasing + UINTN NumOfLba; // Number of Lba blocks to erase + + FlashInstance = INSTANCE_FROM_FVB_THIS (This); + + Status = EFI_SUCCESS; + + if(FlashInstance->IsFvbHeaderValid == TRUE) { + // Detect WriteDisabled state + FvbGetAttributes (This, &FlashFvbAttributes); + if ((FlashFvbAttributes & EFI_FVB2_WRITE_STATUS) == 0) { + DEBUG ((DEBUG_ERROR, + "%a: Device is in WriteDisabled state.\n", + __FUNCTION__)); + return EFI_ACCESS_DENIED; + } + } + + // + // Before erasing, check the entire list of parameters to ensure + // all specified blocks are valid. + // + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba = VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba == EFI_LBA_LIST_TERMINATOR) { + //Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba = VA_ARG (Args, UINT32); + + // All blocks must be within range + if (NumOfLba == 0 || + (FlashInstance->StartLba + StartingLba + NumOfLba - 1) > + FlashInstance->Media.LastBlock) { + + DEBUG ((DEBUG_ERROR, + "%a: Error: Requested LBA are beyond the last available LBA (%ld).\n", + __FUNCTION__, + FlashInstance->Media.LastBlock)); + + VA_END (Args); + + return EFI_INVALID_PARAMETER; + } + } while (TRUE); + VA_END (Args); + + // + // Start erasing + // + VA_START (Args, This); + do { + // Get the Lba from which we start erasing + StartingLba = VA_ARG (Args, EFI_LBA); + + // Have we reached the end of the list? + if (StartingLba == EFI_LBA_LIST_TERMINATOR) { + // Exit the while loop + break; + } + + // How many Lba blocks are we requested to erase? + NumOfLba = VA_ARG (Args, UINT32); + + // Go through each one and erase it + while (NumOfLba > 0) { + + // Get the physical address of Lba to erase + BlockAddress = GET_DATA_OFFSET (FlashInstance->FvbOffset, + FlashInstance->StartLba + StartingLba, + FlashInstance->Media.BlockSize); + // Erase single block + if (FlashInstance->IsSpiFlashAvailable) { + Status = FlashInstance->SpiFlashProtocol->Erase (FlashInstance->SpiFlashProtocol, + BlockAddress, + FlashInstance->Media.BlockSize); + if (EFI_ERROR (Status)) { + VA_END (Args); + return EFI_DEVICE_ERROR; + } + } + + // Update shadow buffer + BlockAddress = GET_DATA_OFFSET (FlashInstance->RegionBaseAddress, + FlashInstance->StartLba + StartingLba, + FlashInstance->Media.BlockSize); + + SetMem ((UINTN *)BlockAddress, FlashInstance->Media.BlockSize, 0xFF); + + // Must sync the data if it's on a disk + FlashInstance->DiskDataInvalidated = TRUE; + + // Move to the next Lba + StartingLba++; + NumOfLba--; + } + } while (TRUE); + VA_END (Args); + + return EFI_SUCCESS; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +STATIC +VOID +EFIAPI +FvbVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // Convert SPI memory mapped region + EfiConvertPointer (0x0, (VOID**)&mFvbDevice->RegionBaseAddress); + + // Convert SPI device description + //EfiConvertPointer (0x0, (VOID**)&mFvbDevice->SpiDevice.Info); + //EfiConvertPointer (0x0, (VOID**)&mFvbDevice->SpiDevice.HostRegisterBaseAddress); + //EfiConvertPointer (0x0, (VOID**)&mFvbDevice->SpiDevice); + + // Convert SpiFlashProtocol + EfiConvertPointer (0x0, (VOID**)&mFvbDevice->SpiFlashProtocol->Erase); + EfiConvertPointer (0x0, (VOID**)&mFvbDevice->SpiFlashProtocol->Write); + EfiConvertPointer (0x0, (VOID**)&mFvbDevice->SpiFlashProtocol->Read); + EfiConvertPointer (0x0, (VOID**)&mFvbDevice->SpiFlashProtocol->GetSize); + EfiConvertPointer (0x0, (VOID**)&mFvbDevice->SpiFlashProtocol); + + return; +} + +STATIC +EFI_STATUS +FvbPrepareFvHeader ( + IN FVB_DEVICE *FlashInstance + ) +{ + EFI_BOOT_MODE BootMode; + EFI_STATUS Status; + + // Check if it is required to use default environment + BootMode = GetBootModeHob (); + if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) { + Status = EFI_INVALID_PARAMETER; + } else { + // Validate header at the beginning of FV region + Status = FvbValidateFvHeader (FlashInstance); + } + + // Install the default FVB header if required + if (EFI_ERROR (Status)) { + // There is no valid header, so time to install one. + DEBUG ((DEBUG_ERROR, "%a: The FVB Header is not valid.\n", __FUNCTION__)); + DEBUG ((DEBUG_ERROR, + "%a: Installing a correct one for this volume.\n", + __FUNCTION__)); + + FlashInstance->IsFvbHeaderValid = FALSE; + + // Erase entire region that is reserved for variable storage + Status = FvbEraseBlocks (&FlashInstance->FvbProtocol, + (EFI_LBA) 0, + FlashInstance->FvbSize / FlashInstance->Media.BlockSize, + EFI_LBA_LIST_TERMINATOR); + if (EFI_ERROR (Status)) { + return Status; + } + + // Install all appropriate headers + Status = FvbInitFvAndVariableStoreHeaders (FlashInstance); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + FlashInstance->IsFvbHeaderValid = TRUE; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +FvbConfigureFlashInstance ( + IN OUT FVB_DEVICE *FlashInstance + ) +{ + EFI_STATUS Status; + UINTN DataOffset; + UINTN VariableSize, FtwWorkingSize, FtwSpareSize, MemorySize; + + // Locate SPI protocols + Status = gBS->LocateProtocol (&gUniNorFlashProtocolGuid, + NULL, + (VOID **)&FlashInstance->SpiFlashProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: Cannot locate SpiFlash protocol\n", __FUNCTION__)); + } else { + // Probe the SPI flash + if (FlashInstance->SpiFlashProtocol->GetSize(FlashInstance->SpiFlashProtocol)) { + FlashInstance->IsSpiFlashAvailable = TRUE; + } else { + DEBUG ((DEBUG_WARN, "%a: SPI flash not present.\n", __FUNCTION__)); + } + } + + // Fill remaining flash description + VariableSize = PcdGet32 (PcdFlashNvStorageVariableSize); + FtwWorkingSize = PcdGet32 (PcdFlashNvStorageFtwWorkingSize); + FtwSpareSize = PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + FlashInstance->FvbSize = VariableSize + FtwWorkingSize + FtwSpareSize; + FlashInstance->FvbOffset = PcdGet64 (PcdFlashNvStorageVariableBase64); + + FlashInstance->Media.MediaId = 0; + FlashInstance->Media.BlockSize = SIZE_4KB;//FlashInstance->SpiDevice.Info->SectorSize; + FlashInstance->Media.LastBlock = FlashInstance->Size / + FlashInstance->Media.BlockSize - 1; + + // U-Boot maps NV data into memory at the same address as in flash. + FlashInstance->RegionBaseAddress = FlashInstance->FvbOffset; + + if (FlashInstance->IsSpiFlashAvailable + && mBootDeviceType != RkAtagBootDevTypeSpiNor + && mBootDeviceType != RkAtagBootDevTypeMtdBlkSpiNor) { + // + // SPI flash is available but UEFI was booted from another storage, + // check if user still prefers the NV data to be on the flash. + // + if (FixedPcdGetBool (PcdNvStoragePreferSpiFlash)) { + // + // Ignore the memory mapped NV data from the boot device and + // read it directly from SPI flash. + // + DataOffset = GET_DATA_OFFSET (FlashInstance->FvbOffset, + FlashInstance->StartLba, + FlashInstance->Media.BlockSize); + Status = FlashInstance->SpiFlashProtocol->Read (FlashInstance->SpiFlashProtocol, + DataOffset, + (VOID *)FlashInstance->RegionBaseAddress, + FlashInstance->FvbSize); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + // + // Mark SPI flash as being unavailable, we'll dump the NV data on + // the boot device if possible. + // + FlashInstance->IsSpiFlashAvailable = FALSE; + } + } + + Status = gBS->InstallMultipleProtocolInterfaces (&FlashInstance->Handle, + &gEfiDevicePathProtocolGuid, &FlashInstance->DevicePath, + &gEfiFirmwareVolumeBlockProtocolGuid, &FlashInstance->FvbProtocol, + NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = FvbPrepareFvHeader (FlashInstance); + if (EFI_ERROR (Status)) { + gBS->UninstallMultipleProtocolInterfaces (&FlashInstance->Handle, + &gEfiDevicePathProtocolGuid, + &gEfiFirmwareVolumeBlockProtocolGuid, + NULL); + } + + return Status; +} + +STATIC +EFI_STATUS +FvbDiskDumpNvData ( + IN EFI_DEVICE_PATH_PROTOCOL *Device, + IN UINT32 MediaId + ) +{ + EFI_STATUS Status; + EFI_DISK_IO_PROTOCOL *DiskIo = NULL; + EFI_HANDLE Handle; + UINTN DataOffset; + + Status = gBS->LocateDevicePath (&gEfiDiskIoProtocolGuid, &Device, &Handle); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = gBS->HandleProtocol (Handle, &gEfiDiskIoProtocolGuid, (VOID **) &DiskIo); + if (EFI_ERROR (Status)) { + return Status; + } + + DataOffset = GET_DATA_OFFSET (mFvbDevice->FvbOffset, + mFvbDevice->StartLba, + mFvbDevice->Media.BlockSize); + + Status = DiskIo->WriteDisk (DiskIo, + MediaId, + DataOffset, + mFvbDevice->FvbSize, + (VOID *) mFvbDevice->FvbOffset); + + return Status; +} + +STATIC +VOID +EFIAPI +FvbDiskNvDumpEventHandler ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + if (mFvbDevice->DiskDevice == NULL) { + DEBUG ((DEBUG_WARN, "%a: NV disk device not found (yet?)\n", __FUNCTION__)); + return; + } + + if (!mFvbDevice->DiskDataInvalidated) { + return; + } + + Status = FvbDiskDumpNvData (mFvbDevice->DiskDevice, mFvbDevice->DiskMediaId); + if (EFI_ERROR (Status)) { + CHAR16* DevicePathText = ConvertDevicePathToText (mFvbDevice->DiskDevice, FALSE, FALSE); + DEBUG ((DEBUG_ERROR, "%a: Couldn't dump NV data to disk [%s]\n", + __FUNCTION__, DevicePathText)); + if (DevicePathText != NULL) { + gBS->FreePool (DevicePathText); + } + + ASSERT_EFI_ERROR (Status); + return; + } + + DEBUG ((DEBUG_INFO, "NV data dumped!\n")); + + mFvbDevice->DiskDataInvalidated = FALSE; +} + +STATIC +VOID +FvbReadyToBootEventHandler ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_EVENT ImageInstallEvent; + VOID *ImageRegistration; + + Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + FvbDiskNvDumpEventHandler, + NULL, + &ImageInstallEvent); + ASSERT_EFI_ERROR (Status); + + Status = gBS->RegisterProtocolNotify (&gEfiLoadedImageProtocolGuid, + ImageInstallEvent, + &ImageRegistration); + ASSERT_EFI_ERROR (Status); + + FvbDiskNvDumpEventHandler (NULL, NULL); + + Status = gBS->CloseEvent (Event); + ASSERT_EFI_ERROR (Status); +} + +STATIC +BOOLEAN +FvbCheckIsBootDevice ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_HANDLE DeviceHandle; + NON_DISCOVERABLE_DEVICE *Device; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + + DevicePath = DevicePathFromHandle (Handle); + + DEBUG ((DEBUG_INFO, "%a: DevPath type 0x%x subtype 0x%x\n", + __FUNCTION__, DevicePath->Type, DevicePath->SubType)); + + if (DevicePath->Type != HARDWARE_DEVICE_PATH + || DevicePath->SubType != HW_VENDOR_DP) { + return FALSE; + } + + Status = gBS->LocateDevicePath (&gEdkiiNonDiscoverableDeviceProtocolGuid, + &DevicePath, &DeviceHandle); + if (EFI_ERROR (Status)) { + return FALSE; + } + + Status = gBS->HandleProtocol (DeviceHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, (VOID **) &Device); + if (EFI_ERROR (Status)) { + return FALSE; + } + + Descriptor = &Device->Resources[0]; + + if (Descriptor->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR || + Descriptor->ResType != ACPI_ADDRESS_SPACE_TYPE_MEM) { + return FALSE; + } + + if (mBootDeviceType == RkAtagBootDevTypeEmmc) { + return Descriptor->AddrRangeMin == PcdGet32 (PcdDwcSdhciBaseAddress); + } + if (mBootDeviceType == RkAtagBootDevTypeSd0) { + return Descriptor->AddrRangeMin == PcdGet32 (PcdRkSdmmcBaseAddress); + } + + return FALSE; +} + +STATIC +VOID +EFIAPI +FvbDiskIoRegistrationHandler ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + UINTN HandleSize; + EFI_HANDLE Handle; + EFI_DEVICE_PATH_PROTOCOL *Device; + EFI_BLOCK_IO_PROTOCOL *BlkIo; + CHAR16 *DevicePathText = NULL; + + if (mFvbDevice->DiskDevice != NULL) { + // + // We've already found the NV disk before, + // and it is not removed from the system (hopefully). + // + return; + } + + while (TRUE) { + HandleSize = sizeof (EFI_HANDLE); + Status = gBS->LocateHandle (ByRegisterNotify, + NULL, + mDiskIoRegistration, + &HandleSize, + &Handle); + if (Status == EFI_NOT_FOUND) { + break; + } + + ASSERT_EFI_ERROR (Status); + + if (!FvbCheckIsBootDevice (Handle)) { + continue; + } + + Device = NULL; + Status = gBS->HandleProtocol (Handle, + &gEfiBlockIoProtocolGuid, + (VOID*)&BlkIo); + if (EFI_ERROR (Status)) { + continue; + } + Device = DuplicateDevicePath (DevicePathFromHandle (Handle)); + ASSERT (Device != NULL); + + if (DevicePathText != NULL) { + gBS->FreePool (DevicePathText); + } + DevicePathText = ConvertDevicePathToText (Device, FALSE, FALSE); + + if (!BlkIo->Media->MediaPresent) { + DEBUG ((DEBUG_ERROR, "%a: [%s] Media not present!\n", + __FUNCTION__, DevicePathText)); + continue; + } + if (BlkIo->Media->ReadOnly) { + DEBUG ((DEBUG_ERROR, "%a: [%s] Media is read-only!\n", + __FUNCTION__, DevicePathText)); + continue; + } + + Status = FvbDiskDumpNvData (Device, BlkIo->Media->MediaId); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: [%s] Couldn't update NV data!\n", + __FUNCTION__, DevicePathText)); + ASSERT_EFI_ERROR (Status); + continue; + } + + if (mFvbDevice->DiskDevice != NULL) { + gBS->FreePool (mFvbDevice->DiskDevice); + } + + DEBUG ((DEBUG_INFO, "%a: [%s] Found boot disk for NV storage!\n", + __FUNCTION__, DevicePathText)); + + mFvbDevice->DiskDevice = Device; + mFvbDevice->DiskMediaId = BlkIo->Media->MediaId; + break; + } + + if (DevicePathText != NULL) { + gBS->FreePool (DevicePathText); + } +} + +STATIC +VOID +FvbInstallDiskNvDumpEventHandlers ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT ResetEvent; + EFI_EVENT ReadyToBootEvent; + + Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + FvbDiskNvDumpEventHandler, + NULL, + &gRockchipEventResetGuid, + &ResetEvent); + ASSERT_EFI_ERROR (Status); + + Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + FvbReadyToBootEventHandler, + NULL, + &gEfiEventReadyToBootGuid, + &ReadyToBootEvent); + ASSERT_EFI_ERROR (Status); +} + +STATIC +VOID +FvbInstallDiskNotifyHandler ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + FvbDiskIoRegistrationHandler, + NULL, + &Event); + ASSERT_EFI_ERROR (Status); + + Status = gBS->RegisterProtocolNotify (&gEfiDiskIoProtocolGuid, + Event, + &mDiskIoRegistration); + ASSERT_EFI_ERROR (Status); +} + +EFI_STATUS +EFIAPI +RkFvbEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status = 0; + RKATAG_BOOTDEV *BootDevice; + + BootDevice = RkAtagsGetBootDev (); + if (BootDevice != NULL) { + mBootDeviceType = BootDevice->DevType; + DEBUG ((DEBUG_INFO, "%a: BootDevice->DevType = 0x%x\n", __FUNCTION__, mBootDeviceType)); + } else { + DEBUG ((DEBUG_ERROR, "%a: Couldn't identify boot device.\n", __FUNCTION__)); + mBootDeviceType = RkAtagBootDevTypeUnknown; + } + + // + // Create FVB flash device + // + mFvbDevice = AllocateRuntimeCopyPool (sizeof (mRkFvbFlashInstanceTemplate), + &mRkFvbFlashInstanceTemplate); + if (mFvbDevice == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + // + // Detect and configure flash device + // + Status = FvbConfigureFlashInstance (mFvbDevice); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Fail to configure Fvb device\n", __FUNCTION__)); + goto ErrorConfigureFlash; + } + + // + // The driver implementing the variable read service can now be dispatched; + // the varstore headers are in place. + // + Status = gBS->InstallProtocolInterface (&gImageHandle, + &gEdkiiNvVarStoreFormattedGuid, + EFI_NATIVE_INTERFACE, + NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "%a: Failed to install gEdkiiNvVarStoreFormattedGuid\n", + __FUNCTION__)); + goto ErrorInstallNvVarStoreFormatted; + } + + // + // Register for the virtual address change event + // + + Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + FvbVirtualNotifyEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &mFvbVirtualAddrChangeEvent); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to register VA change event\n", __FUNCTION__)); + goto ErrorSetMemAttr; + } + + // + // If SPI flash isn't available (or preferred), attempt to identify + // and set up persistent NV storage on the boot device. + // + if (!mFvbDevice->IsSpiFlashAvailable) { + FvbInstallDiskNotifyHandler (); + FvbInstallDiskNvDumpEventHandlers (); + } + + return Status; +ErrorSetMemAttr: + gBS->UninstallProtocolInterface (gImageHandle, + &gEdkiiNvVarStoreFormattedGuid, + NULL); + +ErrorInstallNvVarStoreFormatted: + gBS->UninstallMultipleProtocolInterfaces (&mFvbDevice->Handle, + &gEfiDevicePathProtocolGuid, + &gEfiFirmwareVolumeBlockProtocolGuid, + NULL); + +ErrorConfigureFlash: + FreePool (mFvbDevice); + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.h new file mode 100644 index 0000000..920053f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.h @@ -0,0 +1,126 @@ +/** @file + * + * Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. + * Copyright (c) 2017 Marvell International Ltd. + * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __FVB_FLASH_DXE_H__ +#define __FVB_FLASH_DXE_H__ + +#include +#include +#include + +#define GET_DATA_OFFSET(BaseAddr, Lba, LbaSize) ((BaseAddr) + (UINTN)((Lba) * (LbaSize))) + +#define FVB_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r') +#define INSTANCE_FROM_FVB_THIS(a) CR(a, FVB_DEVICE, FvbProtocol, FVB_FLASH_SIGNATURE) + +// +// Define two helper macro to extract the Capability field or Status field in FVB +// bit fields. +// +#define EFI_FVB2_CAPABILITIES (EFI_FVB2_READ_DISABLED_CAP | \ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP) + +#define EFI_FVB2_STATUS (EFI_FVB2_READ_STATUS | \ + EFI_FVB2_WRITE_STATUS | \ + EFI_FVB2_LOCK_STATUS) + +typedef struct { + VENDOR_DEVICE_PATH Vendor; + EFI_DEVICE_PATH_PROTOCOL End; +} FVB_DEVICE_PATH; + +typedef struct { + UNI_NOR_FLASH_PROTOCOL *SpiFlashProtocol; + BOOLEAN IsSpiFlashAvailable; + BOOLEAN IsFvbHeaderValid; + + EFI_DEVICE_PATH_PROTOCOL *DiskDevice; + UINT32 DiskMediaId; + BOOLEAN DiskDataInvalidated; + + EFI_HANDLE Handle; + + UINT32 Signature; + + UINTN DeviceBaseAddress; + UINTN RegionBaseAddress; + UINTN Size; + UINTN FvbOffset; + UINTN FvbSize; + EFI_LBA StartLba; + + EFI_BLOCK_IO_MEDIA Media; + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; + + FVB_DEVICE_PATH DevicePath; +} FVB_DEVICE; + +EFI_STATUS +EFIAPI +FvbGetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, + OUT EFI_FVB_ATTRIBUTES_2* Attributes +); + +EFI_STATUS +EFIAPI +FvbSetAttributes( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, + IN OUT EFI_FVB_ATTRIBUTES_2* Attributes +); + +EFI_STATUS +EFIAPI +FvbGetPhysicalAddress( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, + OUT EFI_PHYSICAL_ADDRESS* Address +); + +EFI_STATUS +EFIAPI +FvbGetBlockSize( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, + IN EFI_LBA Lba, + OUT UINTN* BlockSize, + OUT UINTN* NumberOfBlocks +); + +EFI_STATUS +EFIAPI +FvbRead( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN* NumBytes, + IN OUT UINT8* Buffer +); + +EFI_STATUS +EFIAPI +FvbWrite( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN* NumBytes, + IN UINT8* Buffer +); + +EFI_STATUS +EFIAPI +FvbEraseBlocks( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This, + ... +); + +#endif /* __FVB_FLASH_DXE_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf new file mode 100644 index 0000000..88dcb38 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf @@ -0,0 +1,82 @@ +#/** @file +# +# Firmware Volume Block driver for non-volatile data storage on +# SPI NOR (persistent at runtime) or SD/eMMC (persistent only at boot time). +# +# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2017 Marvell International Ltd. +# Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = RkFvbDxe + FILE_GUID = df325b7e-ae7c-11ec-a154-f42a7dcb925d + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 0.1 + ENTRY_POINT = RkFvbEntryPoint + +[Sources] + RkFvbDxe.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + IoLib + BaseLib + DebugLib + HobLib + UefiLib + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeLib + BaseMemoryLib + DevicePathLib + DxeServicesTableLib + MemoryAllocationLib + UefiRuntimeServicesTableLib + RkAtagsLib + +[Guids] + gEdkiiNvVarStoreFormattedGuid + gEfiAuthenticatedVariableGuid + gEfiEventVirtualAddressChangeGuid + gEfiSystemNvDataFvGuid + gEfiVariableGuid + gEfiEventReadyToBootGuid + gRockchipEventResetGuid + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiFirmwareVolumeBlockProtocolGuid + gUniNorFlashProtocolGuid + gEfiDiskIoProtocolGuid + gEfiBlockIoProtocolGuid + gEdkiiNonDiscoverableDeviceProtocolGuid + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gRockchipTokenSpaceGuid.PcdNvStoragePreferSpiFlash + gRockchipTokenSpaceGuid.PcdDwcSdhciBaseAddress + gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 + +[Depex] + TRUE + #gEfiCpuArchProtocolGuid AND + #gUniNorFlashProtocolGuid \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkSdmmcDxe/RkSdmmcDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkSdmmcDxe/RkSdmmcDxe.c new file mode 100644 index 0000000..a890fc3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkSdmmcDxe/RkSdmmcDxe.c @@ -0,0 +1,169 @@ +/** @file + * + * Synopsys DesignWare MSHC platform driver for Rockchip SDMMC + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include + +#include +#include + +#define DW_MMC_BASE FixedPcdGet32(PcdRkSdmmcBaseAddress) +#define DW_MMC_SIZE SIZE_16KB + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH Vendor; + UINT64 BaseAddress; + UINT8 ResourceType; + EFI_DEVICE_PATH_PROTOCOL End; +} NON_DISCOVERABLE_DEVICE_PATH; + +typedef struct { + NON_DISCOVERABLE_DEVICE_PATH DevicePath; + NON_DISCOVERABLE_DEVICE Device; +} DW_MMC_DEVICE; +#pragma pack () + +STATIC EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR mDwMmcDeviceDesc[] = { + { + ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3, // Len + ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType + 0, // GenFlag + 0, // SpecificFlag + 32, // AddrSpaceGranularity + DW_MMC_BASE, // AddrRangeMin + DW_MMC_SIZE + DW_MMC_SIZE - 1, // AddrRangeMax + 0, // AddrTranslationOffset + DW_MMC_SIZE // AddrLen + } +}; + +STATIC DW_MMC_DEVICE mDwMmcDevice = { + { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8) (OFFSET_OF (NON_DISCOVERABLE_DEVICE_PATH, End)), + (UINT8) ((OFFSET_OF (NON_DISCOVERABLE_DEVICE_PATH, End)) >> 8) + } + }, + EDKII_NON_DISCOVERABLE_DEVICE_PROTOCOL_GUID + }, + DW_MMC_BASE, + ACPI_ADDRESS_SPACE_TYPE_MEM, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + sizeof (EFI_DEVICE_PATH_PROTOCOL), + 0 + } + } + }, + { + &gDwMmcHcNonDiscoverableDeviceGuid, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + mDwMmcDeviceDesc + } +}; + +STATIC DW_MMC_HC_SLOT_CAP mDwMmcCapability = { + .HighSpeed = 1, + .BusWidth = 4, + .SlotType = RemovableSlot, + .CardType = SdCardType, + .Voltage30 = 1, + .BaseClkFreq = 52000 +}; + +STATIC +EFI_STATUS +EFIAPI +RkSdmmcGetCapability ( + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT DW_MMC_HC_SLOT_CAP *Capability + ) +{ + if (Controller != mDwMmcCapability.Controller || Capability == NULL) { + return EFI_INVALID_PARAMETER; + } + + CopyMem (Capability, &mDwMmcCapability, sizeof (DW_MMC_HC_SLOT_CAP)); + + return EFI_SUCCESS; +} + +STATIC +BOOLEAN +EFIAPI +RkSdmmcCardDetect ( + IN EFI_HANDLE Controller, + IN UINT8 Slot + ) +{ + RKSDMMC_CARD_PRESENCE_STATE PresenceState; + + if (Controller != mDwMmcCapability.Controller) { + return FALSE; + } + + PresenceState = RkSdmmcGetCardPresenceState (); + + if ((PresenceState == RkSdmmcCardPresenceUnsupported) || + FixedPcdGetBool (PcdRkSdmmcCardDetectBroken)) { + return TRUE; // let the driver do software detection + } + + return PresenceState == RkSdmmcCardPresent; +} + +STATIC PLATFORM_DW_MMC_PROTOCOL mDwMmcDeviceProtocol = { + RkSdmmcGetCapability, + RkSdmmcCardDetect +}; + +EFI_STATUS +EFIAPI +RkSdmmcDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + RkSdmmcSetIoMux (); + + RkSdmmcSetClockRate (mDwMmcCapability.BaseClkFreq * 1000); + + Status = gBS->InstallMultipleProtocolInterfaces(&mDwMmcCapability.Controller, + &gEfiDevicePathProtocolGuid, &mDwMmcDevice.DevicePath, + &gEdkiiNonDiscoverableDeviceProtocolGuid, &mDwMmcDevice.Device, + NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + Handle = NULL; + Status = gBS->InstallProtocolInterface ( + &Handle, + &gPlatformDwMmcProtocolGuid, + EFI_NATIVE_INTERFACE, + &mDwMmcDeviceProtocol + ); + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkSdmmcDxe/RkSdmmcDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkSdmmcDxe/RkSdmmcDxe.inf new file mode 100644 index 0000000..6143303 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/RkSdmmcDxe/RkSdmmcDxe.inf @@ -0,0 +1,49 @@ +#/** @file +# +# Synopsys DesignWare MSHC platform driver for Rockchip SDMMC +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RkSdmmcDxe + FILE_GUID = b6c84293-d505-4e5c-84ba-c7ff183fa566 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = RkSdmmcDxeInitialize + +[Sources.common] + RkSdmmcDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Synopsys/DesignWare/DesignWarePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + BaseMemoryLib + DebugLib + UefiBootServicesTableLib + RkSdmmcPlatformLib + +[Protocols] + gEfiDevicePathProtocolGuid ## PRODUCES + gEdkiiNonDiscoverableDeviceProtocolGuid ## PRODUCES + gPlatformDwMmcProtocolGuid ## PRODUCES + +[Guids] + gDwMmcHcNonDiscoverableDeviceGuid + +[Pcd] + gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Rtc8563PlatformDxe/Rtc8563PlatformDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Rtc8563PlatformDxe/Rtc8563PlatformDxe.c new file mode 100644 index 0000000..593663e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Rtc8563PlatformDxe/Rtc8563PlatformDxe.c @@ -0,0 +1,98 @@ +/** @file + * + * Pcf8563RealTimeClockLib initializer for Rockchip platforms. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include + +STATIC +VOID +EFIAPI +RockchipI2cMasterRegistrationEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN NumHandles; + ROCKCHIP_I2C_MASTER_PROTOCOL *RockchipI2cMaster; + UINTN Index; + + Handles = NULL; + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gRockchipI2cMasterProtocolGuid, + NULL, + &NumHandles, + &Handles + ); + if (EFI_ERROR(Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG((DEBUG_WARN, "%a: Failed to locate gRockchipI2cMasterProtocolGuid. Status=%r\n", + __FUNCTION__, Status)); + } + return; + } + + for (Index = 0; Index < NumHandles; Index++) { + Status = gBS->HandleProtocol ( + Handles[Index], + &gRockchipI2cMasterProtocolGuid, + (VOID **)&RockchipI2cMaster + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to get RockchipI2cMaster: %r\n", __FUNCTION__, Status)); + continue; + } + + if (RockchipI2cMaster->Bus != FixedPcdGet8 (PcdRtc8563Bus)) { + continue; + } + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handles[Index], + &gPcf8563RealTimeClockLibI2cMasterProtocolGuid, + NULL, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to install gPcf8563RealTimeClockLibI2cMasterProtocolGuid: %r\n", + __FUNCTION__, Status)); + continue; + } + + gBS->CloseEvent (Event); + } + + FreePool (Handles); +} + +EFI_STATUS +EFIAPI +Rtc8563PlatformDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + VOID *Registration = NULL; + + EfiCreateProtocolNotifyEvent ( + &gRockchipI2cMasterProtocolGuid, + TPL_CALLBACK, + RockchipI2cMasterRegistrationEvent, + NULL, + &Registration + ); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Rtc8563PlatformDxe/Rtc8563PlatformDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Rtc8563PlatformDxe/Rtc8563PlatformDxe.inf new file mode 100644 index 0000000..f944ec3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Rtc8563PlatformDxe/Rtc8563PlatformDxe.inf @@ -0,0 +1,42 @@ +#/** @file +# +# Pcf8563RealTimeClockLib initializer for Rockchip platforms. +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RtcPlatformDxe + FILE_GUID = b4d6e6b1-b2a0-4c79-8bf1-3af8c485ec3d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = Rtc8563PlatformDxeInitialize + +[Sources.common] + Rtc8563PlatformDxe.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiLib + UefiBootServicesTableLib + MemoryAllocationLib + DebugLib + +[Protocols] + gRockchipI2cMasterProtocolGuid ## CONSUMES + gPcf8563RealTimeClockLibI2cMasterProtocolGuid ## PRODUCES + +[Pcd] + gRockchipTokenSpaceGuid.PcdRtc8563Bus + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.c new file mode 100644 index 0000000..44d0431 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.c @@ -0,0 +1,278 @@ +/** @file + * + * Platform Status LED controller + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#define REPEAT_INFINITE MAX_UINT32 + +#define LONG_PULSE_PERIOD_MS 840 +#define SHORT_PULSE_PERIOD_MS 140 + +#define MILLIS_TO_MICROS(x) (x * 1000) + +// Timer for async execution +EFI_EVENT mTimerEvent; + +// Parameters +UINT32 mAsyncLongPulseCount; +UINT32 mAsyncShortPulseCount; +UINT32 mAsyncRepeatCount; +UINT32 mAsyncPatternDelayMs; +UINT32 mAsyncContinueWithIdlePattern; + +// State variables +UINT32 mAsyncRepeatIndex; +UINT32 mAsyncShortPulseIndex; +UINT32 mAsyncLongPulseIndex; + +BOOLEAN mLedEnabled; + +STATIC +VOID +SetLed ( + IN BOOLEAN Enable + ) +{ + PlatformSetStatusLed (Enable); + mLedEnabled = Enable; +} + +STATIC +VOID +InitLed ( + VOID + ) +{ + PlatformInitLeds (); +} + +STATIC +VOID +BlinkLedAsync ( + IN UINT32 LongPulseCount, + IN UINT32 ShortPulseCount, + IN UINT32 RepeatCount, + IN UINT32 PatternDelayMs, + IN BOOLEAN ContinueWithIdlePattern + ) +{ + gBS->SetTimer (mTimerEvent, TimerCancel, 0); + + mAsyncLongPulseCount = LongPulseCount; + mAsyncShortPulseCount = ShortPulseCount; + mAsyncRepeatCount = RepeatCount; + mAsyncPatternDelayMs = PatternDelayMs; + mAsyncContinueWithIdlePattern = ContinueWithIdlePattern; + mAsyncRepeatIndex = 0; + mAsyncShortPulseIndex = 0; + mAsyncLongPulseIndex = 0; + + SetLed (FALSE); + + gBS->SetTimer (mTimerEvent, TimerRelative, 0); +} + +STATIC +VOID +BlinkLedIdleAsync ( + VOID + ) +{ + BlinkLedAsync (0, 1, REPEAT_INFINITE, 2000, FALSE); +} + +STATIC +VOID +TimerHandler ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // Process long pulses + // + if (mAsyncLongPulseIndex < mAsyncLongPulseCount) { + if (mLedEnabled) { + mAsyncLongPulseIndex++; + } + SetLed (!mLedEnabled); + + gBS->SetTimer (mTimerEvent, TimerRelative, + EFI_TIMER_PERIOD_MILLISECONDS (LONG_PULSE_PERIOD_MS)); + return; + } + + // + // Process short pulses + // + if (mAsyncShortPulseIndex < mAsyncShortPulseCount) { + if (mLedEnabled) { + mAsyncShortPulseIndex++; + } + SetLed (!mLedEnabled); + + gBS->SetTimer (mTimerEvent, TimerRelative, + EFI_TIMER_PERIOD_MILLISECONDS (SHORT_PULSE_PERIOD_MS)); + return; + } + + // + // Completion happens at mAsyncRepeatCount + 1, because + // we schedule this routine one more time just to wait + // for mAsyncPatternDelayMs and thus introduce a pause + // before the next pattern. + // + if (mAsyncRepeatIndex > mAsyncRepeatCount) { + if (mAsyncContinueWithIdlePattern) { + BlinkLedIdleAsync (); + } + return; + } + + // + // Do we need to repeat the pattern? Reset the pulse indexes. + // + if (mAsyncRepeatIndex < mAsyncRepeatCount) { + mAsyncShortPulseIndex = 0; + mAsyncLongPulseIndex = 0; + } + + // + // Keep repeating until completion above. + // + if (mAsyncRepeatCount != REPEAT_INFINITE) { + mAsyncRepeatIndex++; + } + + gBS->SetTimer (mTimerEvent, TimerRelative, + EFI_TIMER_PERIOD_MILLISECONDS (mAsyncPatternDelayMs)); +} + +STATIC +VOID +BlinkLedSync ( + IN UINT32 LongPulseCount, + IN UINT32 ShortPulseCount, + IN UINT32 RepeatCount, + IN UINT32 PatternDelayMs, + IN BOOLEAN ContinueWithIdlePattern + ) +{ + UINT32 RepeatIndex = 0; + UINT32 PulseIndex = 0; + + gBS->SetTimer (mTimerEvent, TimerCancel, 0); + SetLed (FALSE); + + while (RepeatIndex <= RepeatCount) { + for (PulseIndex = 0; PulseIndex < LongPulseCount; PulseIndex++) { + SetLed (TRUE); + gBS->Stall (MILLIS_TO_MICROS(LONG_PULSE_PERIOD_MS)); + SetLed (FALSE); + gBS->Stall (MILLIS_TO_MICROS(LONG_PULSE_PERIOD_MS)); + } + + for (PulseIndex = 0; PulseIndex < ShortPulseCount; PulseIndex++) { + SetLed (TRUE); + gBS->Stall (MILLIS_TO_MICROS(SHORT_PULSE_PERIOD_MS)); + SetLed (FALSE); + gBS->Stall (MILLIS_TO_MICROS(SHORT_PULSE_PERIOD_MS)); + } + + gBS->Stall (MILLIS_TO_MICROS(PatternDelayMs)); + + if (RepeatCount != REPEAT_INFINITE) { + RepeatIndex++; + } + } + + if (ContinueWithIdlePattern) { + BlinkLedIdleAsync (); + } +} + +STATIC +VOID +EFIAPI +NotifyPlatformBmAfterConsole ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // All platform drivers have been dispatched and configured + // at this point. Start the idle pattern to indicate that the + // firmware is alive and (hopefully) well. + // + BlinkLedIdleAsync (); +} + +STATIC +VOID +EFIAPI +NotifyExitBootServices ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // Turn off the LED in case the timer didn't have a chance to. + // + SetLed (FALSE); +} + +EFI_STATUS +EFIAPI +StatusLedDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event = NULL; + + InitLed (); + + Status = gBS->CreateEvent ( + EVT_TIMER | EVT_NOTIFY_SIGNAL, // Type + TPL_NOTIFY, // NotifyTpl + TimerHandler, // NotifyFunction + NULL, // NotifyContext + &mTimerEvent // Event + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // Initial firmware loading pattern + BlinkLedAsync (0, 1, REPEAT_INFINITE, 0, FALSE); + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, // Type + TPL_NOTIFY, // NotifyTpl + NotifyPlatformBmAfterConsole, // NotifyFunction + NULL, // NotifyContext + &gRockchipEventPlatformBmAfterConsoleGuid, // EventGroup + &Event // Event + ); + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, // Type + TPL_NOTIFY, // NotifyTpl + NotifyExitBootServices, // NotifyFunction + NULL, // NotifyContext + &gEfiEventExitBootServicesGuid, // EventGroup + &Event // Event + ); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.inf new file mode 100644 index 0000000..0b319bb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Platform Status LED controller +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = StatusLedDxe + FILE_GUID = b1f3fd14-9bd1-48cc-9258-e2807ecb1b84 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = StatusLedDxeInitialize + +[Sources.common] + StatusLedDxe.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiLib + UefiBootServicesTableLib + RockchipPlatformLib + +[Pcd] + +[Protocols] + +[Guids] + gEfiEventExitBootServicesGuid + gRockchipEventPlatformBmAfterConsoleGuid + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c new file mode 100644 index 0000000..b05317a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.c @@ -0,0 +1,419 @@ +/** @file + + Copyright 2017, 2020 NXP + Copyright 2021, Jared McNeill + Copyright (c) 2023, Mario Bălănică + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "UsbHcd.h" + +STATIC +VOID +XhciSetBeatBurstLength ( + IN UINTN UsbReg + ) +{ + DWC3 *Dwc3Reg; + + Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET); + + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GSBusCfg0, ~USB3_ENABLE_BEAT_BURST_MASK, + USB3_ENABLE_BEAT_BURST); + + MmioOr32 ((UINTN)&Dwc3Reg->GSBusCfg1, USB3_SET_BEAT_BURST_LIMIT); +} + +STATIC +VOID +Dwc3SetFladj ( + IN DWC3 *Dwc3Reg, + IN UINT32 Val + ) +{ + MmioOr32 ((UINTN)&Dwc3Reg->GFLAdj, GFLADJ_30MHZ_REG_SEL | + GFLADJ_30MHZ (Val)); +} + +STATIC +VOID +Dwc3SetMode ( + IN DWC3 *Dwc3Reg, + IN UINT32 Mode + ) +{ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GCtl, + ~(DWC3_GCTL_PRTCAPDIR (DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR (Mode)); +} + +/** + This function issues phy reset and core soft reset + + @param Dwc3Reg Pointer to DWC3 register. + +**/ +STATIC +VOID +Dwc3CoreSoftReset ( + IN DWC3 *Dwc3Reg + ) +{ + // + // Put core in reset before resetting PHY + // + MmioOr32 ((UINTN)&Dwc3Reg->GCtl, DWC3_GCTL_CORESOFTRESET); + + // + // Assert USB2 PHY reset + // + MmioOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + // + // Assert USB3 PHY reset + // + MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST); + + MemoryFence (); + + // + // Clear USB3 PHY reset + // + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_PHYSOFTRST); + + // + // Clear USB2 PHY reset + // + MmioAnd32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_PHYSOFTRST); + + MemoryFence (); + + // + // Take core out of reset, PHYs are stable now + // + MmioAnd32 ((UINTN)&Dwc3Reg->GCtl, ~DWC3_GCTL_CORESOFTRESET); +} + +/** + This function performs low-level initialization of DWC3 Core + + @param Dwc3Reg Pointer to DWC3 register. + +**/ +STATIC +EFI_STATUS +Dwc3CoreInit ( + IN DWC3 *Dwc3Reg + ) +{ + UINT32 Revision; + UINT32 Reg; + UINTN Dwc3Hwparams1; + + Revision = MmioRead32 ((UINTN)&Dwc3Reg->GSnpsId); + // + // This should read as 0x5533, ascii of U3(DWC_usb3) followed by revision num + // + if ((Revision & DWC3_GSNPSID_MASK) != DWC3_SYNOPSYS_ID) { + DEBUG ((DEBUG_ERROR,"This is not a DesignWare USB3 DRD Core.\n")); + return EFI_NOT_FOUND; + } + + Dwc3CoreSoftReset (Dwc3Reg); + + Reg = MmioRead32 ((UINTN)&Dwc3Reg->GCtl); + Reg &= ~DWC3_GCTL_SCALEDOWN_MASK; + Reg &= ~DWC3_GCTL_DISSCRAMBLE; + + Dwc3Hwparams1 = MmioRead32 ((UINTN)&Dwc3Reg->GHwParams1); + + if (DWC3_GHWPARAMS1_EN_PWROPT (Dwc3Hwparams1) == + DWC3_GHWPARAMS1_EN_PWROPT_CLK) { + Reg &= ~DWC3_GCTL_DSBLCLKGTNG; + } else { + DEBUG ((DEBUG_WARN,"No power optimization available.\n")); + } + + if ((Revision & DWC3_RELEASE_MASK) < DWC3_RELEASE_190a) { + Reg |= DWC3_GCTL_U2RSTECN; + } + + MmioWrite32 ((UINTN)&Dwc3Reg->GCtl, Reg); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +XhciCoreInit ( + IN UINTN UsbReg + ) +{ + EFI_STATUS Status; + DWC3 *Dwc3Reg; + + Dwc3Reg = (VOID *)(UsbReg + DWC3_REG_OFFSET); + + Status = Dwc3CoreInit (Dwc3Reg); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Dwc3CoreInit Failed for controller 0x%x (0x%r) \n", + UsbReg, Status)); + + return Status; + } + + Dwc3SetMode (Dwc3Reg, DWC3_GCTL_PRTCAP_HOST); + + Dwc3SetFladj (Dwc3Reg, GFLADJ_30MHZ_DEFAULT); + + /* UTMI+ mode */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK, DWC3_GUSB2PHYCFG_USBTRDTIM(5)); + MmioOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], DWC3_GUSB2PHYCFG_PHYIF); + + /* snps,dis_enblslpm_quirk */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_ENBLSLPM, 0); + /* snps,dis-u2-freeclk-exists-quirk */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS, 0); + /* snps,dis_u2_susphy_quirk */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb2PhyCfg[0], ~DWC3_GUSB2PHYCFG_SUSPHY, 0); + /* snps,dis-del-phy-power-chg-quirk */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->GUsb3PipeCtl[0], ~DWC3_GUSB3PIPECTL_DEPOCHANGE, 0); + /* snps,dis-tx-ipgap-linecheck-quirk */ + MmioOr32 ((UINTN)&Dwc3Reg->GUctl1, DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS); + /* snps,parkmode-disable-ss-quirk */ + MmioOr32 ((UINTN)&Dwc3Reg->GUctl1, DWC3_GUCTL1_PARKMODE_DISABLE_SS); + + /* Set max speed */ + MmioAndThenOr32 ((UINTN)&Dwc3Reg->DCfg, ~DCFG_SPEED_MASK, DCFG_SPEED_SS); + + return Status; +} + +EFIAPI +EFI_STATUS +InitializeXhciController ( + IN NON_DISCOVERABLE_DEVICE *This + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS UsbReg = This->Resources->AddrRangeMin; + + DEBUG ((DEBUG_INFO, "XHCI: Initialize DWC3 at 0x%lX\n", UsbReg)); + + Status = XhciCoreInit (UsbReg); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "XHCI: Controller init Failed for 0x%lX (0x%r)\n", + UsbReg, Status)); + return EFI_DEVICE_ERROR; + } + + // + // Change beat burst and outstanding pipelined transfers requests + // + XhciSetBeatBurstLength (UsbReg); + + return EFI_SUCCESS; +} + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH Vendor; + UINT32 BaseAddress; + EFI_DEVICE_PATH_PROTOCOL End; +} OHCI_DEVICE_PATH; +#pragma pack () + +STATIC +EFI_STATUS +EFIAPI +RegisterOhciController ( + IN UINT32 BaseAddress + ) +{ + EFI_STATUS Status; + OHCI_DEVICE_PROTOCOL *OhciDevice; + OHCI_DEVICE_PATH *OhciDevicePath; + EFI_HANDLE Handle; + + OhciDevice = (OHCI_DEVICE_PROTOCOL*)AllocateZeroPool (sizeof(*OhciDevice)); + if (OhciDevice == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + OhciDevice->BaseAddress = BaseAddress; + + OhciDevicePath = (OHCI_DEVICE_PATH*)CreateDeviceNode ( + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + sizeof (*OhciDevicePath) + ); + if (OhciDevicePath == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto FreeOhciDevice; + } + + CopyGuid (&OhciDevicePath->Vendor.Guid, &gOhciDeviceProtocolGuid); + + /* Device paths must be unique */ + OhciDevicePath->BaseAddress = OhciDevice->BaseAddress; + + SetDevicePathNodeLength (&OhciDevicePath->Vendor, + sizeof (*OhciDevicePath) - sizeof (OhciDevicePath->End)); + SetDevicePathEndNode (&OhciDevicePath->End); + + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&Handle, + &gEfiDevicePathProtocolGuid, OhciDevicePath, + &gOhciDeviceProtocolGuid, OhciDevice, + NULL); + if (EFI_ERROR (Status)) { + goto FreeOhciDevicePath; + } + + return EFI_SUCCESS; + +FreeOhciDevicePath: + FreePool (OhciDevicePath); +FreeOhciDevice: + FreePool (OhciDevice); + + return Status; +} + +/** + This function gets registered as a callback to perform USB controller intialization + + @param Event Event whose notification function is being invoked. + @param Context Pointer to the notification function's context. + +**/ +VOID +EFIAPI +UsbEndOfDxeCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + UINT32 NumUsb2Controller; + UINTN XhciControllerAddrArraySize; + UINT8 *XhciControllerAddrArrayPtr; + UINT32 XhciControllerAddr; + UINT32 EhciControllerAddr; + UINT32 OhciControllerAddr; + UINT32 Index; + + gBS->CloseEvent (Event); + + XhciControllerAddrArrayPtr = PcdGetPtr (PcdDwc3BaseAddresses); + XhciControllerAddrArraySize = PcdGetSize (PcdDwc3BaseAddresses); + + if (XhciControllerAddrArraySize % sizeof(UINT32) != 0) { + DEBUG ((DEBUG_ERROR, "Invalid DWC3 address byte array size, skipping init.\n")); + XhciControllerAddrArraySize = 0; + } + + NumUsb2Controller = PcdGet32 (PcdNumEhciController); + + /* Enable USB PHYs */ + Usb2PhyResume (); + + UsbPortPowerEnable (); + + /* Register USB3 controllers */ + for (Index = 0; Index < XhciControllerAddrArraySize; Index += sizeof(UINT32)) { + XhciControllerAddr = XhciControllerAddrArrayPtr[Index] | + XhciControllerAddrArrayPtr[Index + 1] << 8 | + XhciControllerAddrArrayPtr[Index + 2] << 16 | + XhciControllerAddrArrayPtr[Index + 3] << 24; + + Status = RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeXhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + InitializeXhciController, + NULL, + 1, + XhciControllerAddr, PcdGet32 (PcdDwc3Size) + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register XHCI device 0x%x, error 0x%r \n", + XhciControllerAddr, Status)); + } + } + + /* Register USB2 controllers */ + for (Index = 0; Index < NumUsb2Controller; Index++) { + EhciControllerAddr = PcdGet32 (PcdEhciBaseAddress) + + (Index * (PcdGet32 (PcdEhciSize) + PcdGet32 (PcdOhciSize))); + OhciControllerAddr = EhciControllerAddr + PcdGet32 (PcdOhciSize); + + Status = RegisterNonDiscoverableMmioDevice ( + NonDiscoverableDeviceTypeEhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + EhciControllerAddr, PcdGet32 (PcdEhciSize) + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register EHCI device 0x%x, error 0x%r \n", + EhciControllerAddr, Status)); + } + + Status = RegisterOhciController (OhciControllerAddr); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to register OHCI device 0x%x, error 0x%r \n", + OhciControllerAddr, Status)); + } + } +} + +/** + The Entry Point of module. It follows the standard UEFI driver model. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval other Some error occurs when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +InitializeUsbHcd ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + UsbEndOfDxeCallback, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h new file mode 100644 index 0000000..216fa14 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.h @@ -0,0 +1,157 @@ +/** @file + + Copyright 2017, 2020 NXP + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef USB_HCD_H_ +#define USB_HCD_H_ + +#include + +/* Global constants */ +#define DWC3_GSNPSID_MASK 0xffff0000 +#define DWC3_SYNOPSYS_ID 0x55330000 +#define DWC3_RELEASE_MASK 0xffff +#define DWC3_REG_OFFSET 0xC100 +#define DWC3_RELEASE_190a 0x190a + +/* Global Configuration Register */ +#define DWC3_GCTL_U2RSTECN BIT16 +#define DWC3_GCTL_PRTCAPDIR(N) ((N) << 12) +#define DWC3_GCTL_PRTCAP_HOST 1 +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_CORESOFTRESET BIT11 +#define DWC3_GCTL_SCALEDOWN(N) ((N) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE BIT3 +#define DWC3_GCTL_DSBLCLKGTNG BIT0 + +/* Global HWPARAMS1 Register */ +#define DWC3_GHWPARAMS1_EN_PWROPT(N) (((N) & (3 << 24)) >> 24) +#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1 + +/* Global UCTL1 Register */ +#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT28 +#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT17 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT31 +#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT30 +#define DWC3_GUSB2PHYCFG_USBTRDTIM(N) (((N) & 0xf) << 10) +#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_SUSPHY BIT6 +#define DWC3_GUSB2PHYCFG_PHYIF BIT3 +#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT0 + +/* Global USB3 PIPE Control Register */ +#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT31 +#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT18 + +/* Global Frame Length Adjustment Register */ +#define GFLADJ_30MHZ_REG_SEL BIT7 +#define GFLADJ_30MHZ(N) ((N) & 0x3f) +#define GFLADJ_30MHZ_DEFAULT 0x20 + +/* Default to the FSL XHCI defines */ +#define USB3_ENABLE_BEAT_BURST 0xF +#define USB3_ENABLE_BEAT_BURST_MASK 0xFF +#define USB3_SET_BEAT_BURST_LIMIT 0xF00 + +/* DCFG Register */ +#define DCFG_SPEED_MASK (BIT2|BIT1|BIT0) +#define DCFG_SPEED_HS 0 +#define DCFG_SPEED_FS 1 +#define DCFG_SPEED_LS 2 +#define DCFG_SPEED_SS 4 +#define DCFG_SPEED_SS_PLUS 5 + +typedef struct { + UINT32 GEvntAdrLo; + UINT32 GEvntAdrHi; + UINT32 GEvntSiz; + UINT32 GEvntCount; +} G_EVENT_BUFFER; + +typedef struct { + UINT32 DDepCmdPar2; + UINT32 DDepCmdPar1; + UINT32 DDepCmdPar0; + UINT32 DDepCmd; +} D_PHYSICAL_EP; + +typedef struct { + UINT32 GSBusCfg0; + UINT32 GSBusCfg1; + UINT32 GTxThrCfg; + UINT32 GRxThrCfg; + UINT32 GCtl; + UINT32 Res1; + UINT32 GSts; + UINT32 GUctl1; + UINT32 GSnpsId; + UINT32 GGpio; + UINT32 GUid; + UINT32 GUctl; + UINT64 GBusErrAddr; + UINT64 GPrtbImap; + UINT32 GHwParams0; + UINT32 GHwParams1; + UINT32 GHwParams2; + UINT32 GHwParams3; + UINT32 GHwParams4; + UINT32 GHwParams5; + UINT32 GHwParams6; + UINT32 GHwParams7; + UINT32 GDbgFifoSpace; + UINT32 GDbgLtssm; + UINT32 GDbgLnmcc; + UINT32 GDbgBmu; + UINT32 GDbgLspMux; + UINT32 GDbgLsp; + UINT32 GDbgEpInfo0; + UINT32 GDbgEpInfo1; + UINT64 GPrtbImapHs; + UINT64 GPrtbImapFs; + UINT32 Res3[28]; + UINT32 GUsb2PhyCfg[16]; + UINT32 GUsb2I2cCtl[16]; + UINT32 GUsb2PhyAcc[16]; + UINT32 GUsb3PipeCtl[16]; + UINT32 GTxFifoSiz[32]; + UINT32 GRxFifoSiz[32]; + G_EVENT_BUFFER GEvntBuf[32]; + UINT32 GHwParams8; + UINT32 Res4[11]; + UINT32 GFLAdj; + UINT32 Res5[51]; + UINT32 DCfg; + UINT32 DCtl; + UINT32 DEvten; + UINT32 DSts; + UINT32 DGCmdPar; + UINT32 DGCmd; + UINT32 Res6[2]; + UINT32 DAlepena; + UINT32 Res7[55]; + D_PHYSICAL_EP DPhyEpCmd[32]; + UINT32 Res8[128]; + UINT32 OCfg; + UINT32 OCtl; + UINT32 OEvt; + UINT32 OEvtEn; + UINT32 OSts; + UINT32 Res9[3]; + UINT32 AdpCfg; + UINT32 AdpCtl; + UINT32 AdpEvt; + UINT32 AdpEvten; + UINT32 BcCfg; + UINT32 Res10; + UINT32 BcEvt; + UINT32 BcEvten; +} DWC3; + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf new file mode 100644 index 0000000..ff52c8c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf @@ -0,0 +1,53 @@ +# UsbHcd.inf +# +# Copyright 2017, 2020 NXP +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = UsbHcdDxe + FILE_GUID = 196e7c2a-37b2-4b85-8683-718588952449 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeUsbHcd + +[Sources.common] + UsbHcd.c + UsbHcd.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + MemoryAllocationLib + NonDiscoverableDeviceRegistrationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + RockchipPlatformLib + DevicePathLib + +[FixedPcd] + gRockchipTokenSpaceGuid.PcdOhciSize + gRockchipTokenSpaceGuid.PcdEhciBaseAddress + gRockchipTokenSpaceGuid.PcdNumEhciController + gRockchipTokenSpaceGuid.PcdEhciSize + gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses + gRockchipTokenSpaceGuid.PcdDwc3Size + +[Protocols] + gOhciDeviceProtocolGuid ## PRODUCES + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.c new file mode 100644 index 0000000..56592bc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.c @@ -0,0 +1,2574 @@ +/** @file + Vop2 DXE Driver, install RK_CRTC_PROTOCOL. + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "Vop2Dxe.h" + +STATIC VPS_CONFIG mVpsConfigs[][VOP2_VP_MAX] = { + { + { + .PlaneMask = (1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0), + .PrimaryPlane = ROCKCHIP_VOP2_ESMART0, + }, + { + .PlaneMask = (1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1), + .PrimaryPlane = ROCKCHIP_VOP2_ESMART1, + }, + { + .PlaneMask = (1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2), + .PrimaryPlane = ROCKCHIP_VOP2_ESMART2, + }, + { + .PlaneMask = (1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3), + .PrimaryPlane = ROCKCHIP_VOP2_ESMART3, + }, + }, + { + { + .PlaneMask = 0, + .PrimaryPlane = 0, + }, + { + .PlaneMask = (1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1), + .PrimaryPlane = ROCKCHIP_VOP2_ESMART1, + }, + { + .PlaneMask = (1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | + 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3), + .PrimaryPlane = ROCKCHIP_VOP2_ESMART2, + }, + { + .PlaneMask = 0, + .PrimaryPlane = 0, + }, + }, +}; + +STATIC UINT32 mVpsConfigsSize = ARRAY_SIZE (mVpsConfigs); + +STATIC CONST INT32 mSinTable[] = { + 0x00000000, 0x023be165, 0x04779632, 0x06b2f1d2, 0x08edc7b6, 0x0b27eb5c, + 0x0d61304d, 0x0f996a26, 0x11d06c96, 0x14060b67, 0x163a1a7d, 0x186c6ddd, + 0x1a9cd9ac, 0x1ccb3236, 0x1ef74bf2, 0x2120fb82, 0x234815ba, 0x256c6f9e, + 0x278dde6e, 0x29ac379f, 0x2bc750e8, 0x2ddf003f, 0x2ff31bdd, 0x32037a44, + 0x340ff241, 0x36185aee, 0x381c8bb5, 0x3a1c5c56, 0x3c17a4e7, 0x3e0e3ddb, + 0x3fffffff, 0x41ecc483, 0x43d464fa, 0x45b6bb5d, 0x4793a20f, 0x496af3e1, + 0x4b3c8c11, 0x4d084650, 0x4ecdfec6, 0x508d9210, 0x5246dd48, 0x53f9be04, + 0x55a6125a, 0x574bb8e5, 0x58ea90c2, 0x5a827999, 0x5c135399, 0x5d9cff82, + 0x5f1f5ea0, 0x609a52d1, 0x620dbe8a, 0x637984d3, 0x64dd894f, 0x6639b039, + 0x678dde6d, 0x68d9f963, 0x6a1de735, 0x6b598ea1, 0x6c8cd70a, 0x6db7a879, + 0x6ed9eba0, 0x6ff389de, 0x71046d3c, 0x720c8074, 0x730baeec, 0x7401e4bf, + 0x74ef0ebb, 0x75d31a5f, 0x76adf5e5, 0x777f903b, 0x7847d908, 0x7906c0af, + 0x79bc384c, 0x7a6831b8, 0x7b0a9f8c, 0x7ba3751c, 0x7c32a67c, 0x7cb82884, + 0x7d33f0c8, 0x7da5f5a3, 0x7e0e2e31, 0x7e6c924f, 0x7ec11aa3, 0x7f0bc095, + 0x7f4c7e52, 0x7f834ecf, 0x7fb02dc4, 0x7fd317b3, 0x7fec09e1, 0x7ffb025e, + 0x7fffffff +}; + +STATIC VOP2_VP_PLANE_MASK mVpPlaneMaskRK3588[VOP2_VP_MAX][VOP2_VP_MAX] = { + { /* one display policy */ + {/* main display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART0, + .AttachedLayersNr = 8, + .AttachedLayers = { + ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, + ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, + ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2, + ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 + }, + }, + {/* second display */}, + {/* third display */}, + {/* fourth display */}, + }, + + { /* two display policy */ + {/* main display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART0, + .AttachedLayersNr = 4, + .AttachedLayers = { + ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, + ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 + }, + }, + + {/* second display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART2, + .AttachedLayersNr = 4, + .AttachedLayers = { + ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2, + ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 + }, + }, + {/* third display */}, + {/* fourth display */}, + }, + + { /* three display policy */ + {/* main display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART0, + .AttachedLayersNr = 3, + .AttachedLayers = { + ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, + ROCKCHIP_VOP2_CLUSTER1 + }, + }, + + {/* second display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART1, + .AttachedLayersNr = 3, + .AttachedLayers = { + ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART1, + ROCKCHIP_VOP2_CLUSTER3 + }, + }, + + {/* third display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART2, + .AttachedLayersNr = 2, + .AttachedLayers = { ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 }, + }, + + {/* fourth display */}, + }, + + { /* four display policy */ + {/* main display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART0, + .AttachedLayersNr = 2, + .AttachedLayers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 }, + }, + + {/* second display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART1, + .AttachedLayersNr = 2, + .AttachedLayers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 }, + }, + + {/* third display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART2, + .AttachedLayersNr = 2, + .AttachedLayers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 }, + }, + + {/* fourth display */ + .PrimaryPlaneId = ROCKCHIP_VOP2_ESMART3, + .AttachedLayersNr = 2, + .AttachedLayers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 }, + }, + }, +}; + +STATIC VOP2_VP_DATA mVpDataRK3588[4] = { + { + .Feature = VOP_FEATURE_OUTPUT_10BIT, + .PreScanMaxDly = 42, + .MaxDclk = 600000, + .MaxOutput = {7680, 4320}, + }, + { + .Feature = VOP_FEATURE_OUTPUT_10BIT, + .PreScanMaxDly = 40, + .MaxDclk = 600000, + .MaxOutput = {4096, 2304}, + }, + { + .Feature = VOP_FEATURE_OUTPUT_10BIT, + .PreScanMaxDly = 52, + .MaxDclk = 600000, + .MaxOutput = {4096, 2304}, + }, + { + .Feature = 0, + .PreScanMaxDly = 52, + .MaxDclk = 200000, + .MaxOutput = {1920, 1080}, + }, +}; + +static VOP2_POWER_DOMAIN_DATA mCluster0PdDataRK3588 = { + .PdEnShift = RK3588_CLUSTER0_PD_EN_SHIFT, + .PdStatusShift = RK3588_CLUSTER0_PD_STATUS_SHIFT, + .PmuStatusShift = RK3588_PD_CLUSTER0_PWR_STAT_SHIFI, + .BisrEnStatusShift = RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT, +}; + +static VOP2_POWER_DOMAIN_DATA mCluster1PdDataRK3588 = { + .PdEnShift = RK3588_CLUSTER1_PD_EN_SHIFT, + .PdStatusShift = RK3588_CLUSTER1_PD_STATUS_SHIFT, + .PmuStatusShift = RK3588_PD_CLUSTER1_PWR_STAT_SHIFI, + .BisrEnStatusShift = RK3588_PD_CLUSTER1_REPAIR_EN_SHIFT, + .ParentPdData = &mCluster0PdDataRK3588, +}; + +static VOP2_POWER_DOMAIN_DATA mCluster2PdDataRK3588 = { + .PdEnShift = RK3588_CLUSTER2_PD_EN_SHIFT, + .PdStatusShift = RK3588_CLUSTER2_PD_STATUS_SHIFT, + .PmuStatusShift = RK3588_PD_CLUSTER2_PWR_STAT_SHIFI, + .BisrEnStatusShift = RK3588_PD_CLUSTER2_REPAIR_EN_SHIFT, + .ParentPdData = &mCluster0PdDataRK3588, +}; + +static VOP2_POWER_DOMAIN_DATA mCluster3PdDataRK3588 = { + .PdEnShift = RK3588_CLUSTER3_PD_EN_SHIFT, + .PdStatusShift = RK3588_CLUSTER3_PD_STATUS_SHIFT, + .PmuStatusShift = RK3588_PD_CLUSTER3_PWR_STAT_SHIFI, + .BisrEnStatusShift = RK3588_PD_CLUSTER3_REPAIR_EN_SHIFT, + .ParentPdData = &mCluster0PdDataRK3588, +}; + +static VOP2_POWER_DOMAIN_DATA mEsmartPdDataRK3588 = { + .PdEnShift = RK3588_ESMART_PD_EN_SHIFT, + .PdStatusShift = RK3588_ESMART_PD_STATUS_SHIFT, + .PmuStatusShift = RK3588_PD_ESMART_PWR_STAT_SHIFI, + .BisrEnStatusShift = RK3588_PD_ESMART_REPAIR_EN_SHIFT, +}; + +static VOP2_POWER_DOMAIN_DATA mDsc8KPdDataRK3588 = { + .PdEnShift = RK3588_DSC_8K_PD_EN_SHIFT, + .PdStatusShift = RK3588_DSC_8K_PD_STATUS_SHIFT, + .PmuStatusShift = RK3588_PD_DSC_8K_PWR_STAT_SHIFI, + .BisrEnStatusShift = RK3588_PD_DSC_8K_REPAIR_EN_SHIFT, +}; + +static VOP2_POWER_DOMAIN_DATA mDsc4KPdDataRK3588 = { + .PdEnShift = RK3588_DSC_4K_PD_EN_SHIFT, + .PdStatusShift = RK3588_DSC_4K_PD_STATUS_SHIFT, + .PmuStatusShift = RK3588_PD_DSC_4K_PWR_STAT_SHIFI, + .BisrEnStatusShift = RK3588_PD_DSC_4K_REPAIR_EN_SHIFT, +}; + +static VOP2_WIN_DATA mWinDataRK3588[8] = { + { + .Name = "Cluster0", + .PhysID = ROCKCHIP_VOP2_CLUSTER0, + .Type = CLUSTER_LAYER, + .WinSelPortOffset = 0, + .LayerSelWinID = 0, + .RegOffset = 0, + .PdData = &mCluster0PdDataRK3588, + }, + + { + .Name = "Cluster1", + .PhysID = ROCKCHIP_VOP2_CLUSTER1, + .Type = CLUSTER_LAYER, + .WinSelPortOffset = 1, + .LayerSelWinID = 1, + .RegOffset = 0x200, + .PdData = &mCluster1PdDataRK3588, + }, + + { + .Name = "Cluster2", + .PhysID = ROCKCHIP_VOP2_CLUSTER2, + .Type = CLUSTER_LAYER, + .WinSelPortOffset = 2, + .LayerSelWinID = 4, + .RegOffset = 0x400, + .PdData = &mCluster2PdDataRK3588, + }, + + { + .Name = "Cluster3", + .PhysID = ROCKCHIP_VOP2_CLUSTER3, + .Type = CLUSTER_LAYER, + .WinSelPortOffset = 3, + .LayerSelWinID = 5, + .RegOffset = 0x600, + .PdData = &mCluster3PdDataRK3588, + }, + + { + .Name = "Esmart0", + .PhysID = ROCKCHIP_VOP2_ESMART0, + .Type = ESMART_LAYER, + .WinSelPortOffset = 4, + .LayerSelWinID = 2, + .RegOffset = 0, + .PdData = &mEsmartPdDataRK3588, + }, + + { + .Name = "Esmart1", + .PhysID = ROCKCHIP_VOP2_ESMART1, + .Type = ESMART_LAYER, + .WinSelPortOffset = 5, + .LayerSelWinID = 3, + .RegOffset = 0x200, + .PdData = &mEsmartPdDataRK3588, + }, + + { + .Name = "Esmart2", + .PhysID = ROCKCHIP_VOP2_ESMART2, + .Type = ESMART_LAYER, + .WinSelPortOffset = 6, + .LayerSelWinID = 6, + .RegOffset = 0x400, + .PdData = &mEsmartPdDataRK3588, + }, + + { + .Name = "Esmart3", + .PhysID = ROCKCHIP_VOP2_ESMART3, + .Type = ESMART_LAYER, + .WinSelPortOffset = 7, + .LayerSelWinID = 7, + .RegOffset = 0x600, + .PdData = &mEsmartPdDataRK3588, + }, +}; + +STATIC VOP2_DSC_DATA mDscDataRK3588[] = { + { + .id = ROCKCHIP_VOP2_DSC_8K, + .PdData = &mDsc8KPdDataRK3588, + .max_slice_num = 8, + .max_linebuf_depth = 11, + .min_bits_per_pixel = 8, + .dsc_txp_clk_src_name = "dsc_8k_txp_clk_src", + .dsc_txp_clk_name = "dsc_8k_txp_clk", + .dsc_pxl_clk_name = "dsc_8k_pxl_clk", + .dsc_cds_clk_name = "dsc_8k_cds_clk", + }, + + { + .id = ROCKCHIP_VOP2_DSC_4K, + .PdData = &mDsc4KPdDataRK3588, + .max_slice_num = 2, + .max_linebuf_depth = 11, + .min_bits_per_pixel = 8, + .dsc_txp_clk_src_name = "dsc_4k_txp_clk_src", + .dsc_txp_clk_name = "dsc_4k_txp_clk", + .dsc_pxl_clk_name = "dsc_4k_pxl_clk", + .dsc_cds_clk_name = "dsc_4k_cds_clk", + }, +}; + +STATIC VOP2_DATA mVop2RK3588 = { + .Version = VOP_VERSION_RK3588, + .NrVps = 4, + .VpData = mVpDataRK3588, + .WinData = mWinDataRK3588, + .DscData = mDscDataRK3588, +/* + .plane_table = rk3588_plane_table, +*/ + .PlaneMask = mVpPlaneMaskRK3588[0], + .NrLayers = 8, + .NrMixers = 7, + .NrGammas = 4, + .NrDscs = 2, +}; + +STATIC UINT8 RK3588Vop2VpPrimaryPlaneOrder[VOP2_VP_MAX] = { + ROCKCHIP_VOP2_ESMART0, + ROCKCHIP_VOP2_ESMART1, + ROCKCHIP_VOP2_ESMART2, + ROCKCHIP_VOP2_ESMART3, +}; + +STATIC UINT8 RK3568Vop2VpPrimaryPlaneOrder[VOP2_VP_MAX] = { + ROCKCHIP_VOP2_SMART0, + ROCKCHIP_VOP2_SMART1, + ROCKCHIP_VOP2_ESMART1, +}; + +STATIC UINT32 mRegsBackup[RK3568_MAX_REG] = {0}; + +STATIC CHAR8* mDisplayIfName[] = { + " RGB", + " BT1120", + " BT656", + " LVDS0", + " LVDS1", + " MIPI0", + " MIPI1", + " eDP0", + " eDP1", + " DP0", + " DP1", + " HDMI0", + " HDMI1" +}; + +STATIC VOP2 *RockchipVop2; + +INLINE +UINT32 +LogCalculate ( + IN UINT32 Input + ) +{ + INT32 Count = -1; + + if (Input == 0) + return 0; + + while (Input) { + Input >>= 1; + Count++; + } + + return Count; +} + +INLINE +VOID +Vop2MaskWrite ( + IN UINTN Address, + IN UINT32 Offset, + IN UINT32 Mask, + IN UINT32 Shift, + IN UINT32 Value, + IN BOOLEAN WriteMask + ) +{ + UINT32 CachedVal; + + if (!Mask) + return; + + if (WriteMask) { + Value = ((Value & Mask) << Shift) | (Mask << (Shift + 16)); + } else { + CachedVal = mRegsBackup[Offset >> 2]; + + Value = (CachedVal & ~(Mask << Shift)) | ((Value & Mask) << Shift); + mRegsBackup[Offset >> 2] = Value; + } + + MmioWrite32(Address + Offset, Value); +} + +INLINE +VOID +Vop2Writel ( + IN UINTN Address, + IN UINT32 Offset, + IN UINT32 Value +) +{ + MmioWrite32(Address + Offset, Value); + mRegsBackup[Offset >> 2] = Value; +} + +INLINE +VOID +Vop2GrfWrite ( + IN UINTN Address, + IN UINT32 Offset, + IN UINT32 Mask, + IN UINT32 Shift, + IN UINT32 Value + ) +{ + UINT32 TempVal = 0; + + TempVal = (Value << Shift) | (Mask << (Shift + 16)); + MmioWrite32(Address + Offset, TempVal); +} + +INLINE +UINT32 +Vop2GrfRead ( + IN UINTN Address, + IN UINT32 Offset, + IN UINT32 Mask, + IN UINT32 Shift + ) +{ + return (MmioRead32(Address + Offset) >> Shift) & Mask; +} + +INLINE +UINT32 GenericHWeight32 ( + IN UINT32 W + ) +{ + UINT32 Res = (W & 0x55555555) + ((W >> 1) & 0x55555555); + Res = (Res & 0x33333333) + ((Res >> 2) & 0x33333333); + Res = (Res & 0x0F0F0F0F) + ((Res >> 4) & 0x0F0F0F0F); + Res = (Res & 0x00FF00FF) + ((Res >> 8) & 0x00FF00FF); + return (Res & 0x0000FFFF) + ((Res >> 16) & 0x0000FFFF); +} + +INLINE +INT32 FFS(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) + r += 1; + return r; +} + +STATIC +INT32 +Vop2GetPrimaryPlane ( + OUT VOP2 *Vop2, + IN UINT32 PlaneMask + ) +{ + UINT32 i = 0; + UINT8 *Vop2VpPrimaryPlaneOrder; + UINT8 DefaultPrimaryPlane; + + if (Vop2->Version == VOP_VERSION_RK3588) { + Vop2VpPrimaryPlaneOrder = RK3588Vop2VpPrimaryPlaneOrder; + DefaultPrimaryPlane = ROCKCHIP_VOP2_ESMART0; + } else { + Vop2VpPrimaryPlaneOrder = RK3568Vop2VpPrimaryPlaneOrder; + DefaultPrimaryPlane = ROCKCHIP_VOP2_SMART0; + } + + for (i = 0; i < Vop2->Data->NrVps; i++) { + if (PlaneMask & BIT(Vop2VpPrimaryPlaneOrder[i])) + return Vop2VpPrimaryPlaneOrder[i]; + } + + return DefaultPrimaryPlane; +} + +STATIC +CHAR8 * +GetPlaneName ( + IN UINT32 PlaneID + ) +{ + CHAR8 *Name = NULL; + + switch (PlaneID) { + case ROCKCHIP_VOP2_CLUSTER0: + Name = "Cluster0"; + break; + case ROCKCHIP_VOP2_CLUSTER1: + Name = "Cluster1"; + break; + case ROCKCHIP_VOP2_ESMART0: + Name = "Esmart0"; + break; + case ROCKCHIP_VOP2_ESMART1: + Name = "Esmart1"; + break; + case ROCKCHIP_VOP2_SMART0: + Name = "Smart0"; + break; + case ROCKCHIP_VOP2_SMART1: + Name = "Smart1"; + break; + case ROCKCHIP_VOP2_CLUSTER2: + Name = "Cluster2"; + break; + case ROCKCHIP_VOP2_CLUSTER3: + Name = "Cluster3"; + break; + case ROCKCHIP_VOP2_ESMART2: + Name = "Esmart2"; + break; + case ROCKCHIP_VOP2_ESMART3: + Name = "Esmart3"; + break; + } + + return Name; +} + +VOID +Vop2DumpRegisters ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2_WIN_DATA *WinData + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + VOP2 *Vop2 = CrtcState->Private; + UINT32 VPOffset = CrtcState->CrtcID * 0x100; + UINT32 WinOffset = 0; + UINT8 PrimaryPlaneID = 0; + INT32 i = 0; + UINT32 Reg = 0; + + /* sys registers */ + Reg = RK3588_VOP2_REG_BASE; + DEBUG ((DEBUG_WARN, "SYS:")); + for (i = 0; i < 0x100; i += 4) { + if (i % 0x10 == 0) { + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "%x:", Reg + i)); + } + + DEBUG ((DEBUG_WARN, " %08x", MmioRead32(Reg + i))); + } + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "\n")); + + /* ovl registers */ + Reg = RK3588_VOP2_REG_BASE + RK3568_OVL_CTRL; + DEBUG ((DEBUG_WARN, "OVL:")); + for (i = 0; i < 0x100; i += 4) { + if (i % 0x10 == 0) { + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "%x:", Reg + i)); + } + + DEBUG ((DEBUG_WARN, " %08x", MmioRead32(Reg + i))); + } + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "\n")); + + /* hdr registers */ + Reg = RK3588_VOP2_REG_BASE + 0x2000; + DEBUG ((DEBUG_WARN, "HDR:")); + for (i = 0; i < 0x40; i += 4) { + if (i % 0x10 == 0) { + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "%x:", Reg + i)); + } + + DEBUG ((DEBUG_WARN, " %08x", MmioRead32(Reg + i))); + } + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "\n")); + + /* vp registers */ + Reg = RK3588_VOP2_REG_BASE + RK3568_VP0_DSP_CTRL + VPOffset; + DEBUG ((DEBUG_WARN, "VP%d:", CrtcState->CrtcID)); + for (i = 0; i < 0x100; i += 4) { + if (i % 0x10 == 0) { + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "%x:", Reg + i)); + } + + DEBUG ((DEBUG_WARN, " %08x", MmioRead32(Reg + i))); + } + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "\n")); + + /* plane registers */ + if (WinData) { + WinOffset = WinData->RegOffset; + if (WinData->Type == CLUSTER_LAYER) + Reg = RK3588_VOP2_REG_BASE + RK3568_CLUSTER0_WIN0_CTRL0 + WinOffset; + else + Reg = RK3588_VOP2_REG_BASE + RK3568_ESMART0_CTRL0 + WinOffset; + PrimaryPlaneID = Vop2->VpPlaneMask[CrtcState->CrtcID].PrimaryPlaneId; + + DEBUG ((DEBUG_WARN, "%a:", GetPlaneName(PrimaryPlaneID))); + for (i = 0; i < 0x100; i += 4) { + if (i % 0x10 == 0) { + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "%x:", Reg + i)); + } + + DEBUG ((DEBUG_WARN, " %08x", MmioRead32(Reg + i))); + } + DEBUG ((DEBUG_WARN, "\n")); + DEBUG ((DEBUG_WARN, "\n")); + } +} + +STATIC +VOP2_WIN_DATA * +Vop2FindWinByPhysID ( + OUT VOP2 *Vop2, + IN INT32 PhysID + ) +{ + INT32 i = 0; + for (i = 0; i < Vop2->Data->NrLayers; i++) { + if (Vop2->Data->WinData[i].PhysID == PhysID) + return &Vop2->Data->WinData[i]; + } + + return NULL; +} + +INLINE +BOOLEAN +IsHotPlugDevices ( + IN INT32 OutputType + ) +{ + switch (OutputType) { + case DRM_MODE_CONNECTOR_HDMIA: + case DRM_MODE_CONNECTOR_HDMIB: + case DRM_MODE_CONNECTOR_TV: + case DRM_MODE_CONNECTOR_DisplayPort: + case DRM_MODE_CONNECTOR_VGA: + case DRM_MODE_CONNECTOR_Unknown: + return TRUE; + default: + return FALSE; + } +} + +STATIC +VOID +Vop2GlobalInitial ( + OUT DISPLAY_STATE *DisplayState + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + VOP2 *Vop2 = CrtcState->Private; + ROCKCHIP_CRTC_PROTOCOL *Crtc = (ROCKCHIP_CRTC_PROTOCOL*)CrtcState->Crtc; + VOP2_WIN_DATA *WinData; + VOP2_VP_PLANE_MASK *PlaneMask; + UINT32 BakIndex; + UINT32 i = 0, j = 0; + UINT32 LayerNr = 0; + UINT8 Shift = 0, TotalUsedLayer = 0; + INT32 PortMux = 0; + INT32 LayerPhyID = 0; + + if (Vop2->GlobalInit) + return; + + /* open the vop global pd */ + MmioWrite32 (0xfd8d8150, 0xffff0000); + MicroSecondDelay (10); + + if (DisplayState->VpsConfigModeID < 0 || DisplayState->VpsConfigModeID >= mVpsConfigsSize) { + INT32 MainVpIndex = -1; + INT32 ActiveVpNum = 0; + + for (i = 0; i < Vop2->Data->NrVps; i++) { + if (Crtc->Vps[i].Enable) + ActiveVpNum++; + } + + PlaneMask = Vop2->Data->PlaneMask; + PlaneMask += (ActiveVpNum - 1) * VOP2_VP_MAX; + + /* find the first unplug devices and set it as main display */ + for (i = 0; i < Vop2->Data->NrVps; i++) { + if (!IsHotPlugDevices (Crtc->Vps[i].OutputType)) { + Vop2->VpPlaneMask[i] = PlaneMask[0]; + MainVpIndex = i; + break; + } + } + + /* if no find unplug devices, use vp0 as main display */ + if (MainVpIndex < 0) { + ActiveVpNum = 0; + Vop2->VpPlaneMask[0] = PlaneMask[0]; + } + + /* plane_mask[0] store main display, so we from plane_mask[1] */ + j = 1; + + /* init other display except main display */ + for (i = 0; i < Vop2->Data->NrVps; i++) { + if (i == MainVpIndex || !Crtc->Vps[i].Enable) { + continue; + } + Vop2->VpPlaneMask[i] = PlaneMask[j++]; + } + + for (i = 0; i < Vop2->Data->NrVps; i++) { + LayerNr = Vop2->VpPlaneMask[i].AttachedLayersNr; + for (j = 0; j < LayerNr; j++) { + LayerPhyID = Vop2->VpPlaneMask[i].AttachedLayers[j]; + Vop2->VpPlaneMask[i].PlaneMask |= BIT(LayerPhyID); + } + } + } else { + UINT32 PlaneMask; + UINT32 PrimaryPlaneID; + + for (i = 0; i < Vop2->Data->NrVps; i++) { + PlaneMask = mVpsConfigs[DisplayState->VpsConfigModeID][i].PlaneMask; + Vop2->VpPlaneMask[i].PlaneMask = PlaneMask; + LayerNr = GenericHWeight32 (PlaneMask); + Vop2->VpPlaneMask[i].AttachedLayersNr = LayerNr; + PrimaryPlaneID = Vop2GetPrimaryPlane (Vop2, PlaneMask); + Vop2->VpPlaneMask[i].PrimaryPlaneId = PrimaryPlaneID; + Vop2->VpPlaneMask[i].PlaneMask = PlaneMask; + for (j = 0; j < LayerNr; j++) { + Vop2->VpPlaneMask[i].AttachedLayers[j] = FFS (PlaneMask) - 1; + PlaneMask &= ~BIT(Vop2->VpPlaneMask[i].AttachedLayers[j]); + } + } + } + + /* open the vop plane pd(esmart) */ + /* status checkout --- todo */ + MmioWrite32 (0xfdd90034, 0x00000000); + MicroSecondDelay (10); + + /* vop2 regs backup */ + for (BakIndex = 0; BakIndex < (RK3568_MAX_REG >> 2); BakIndex++) { + mRegsBackup[BakIndex] = MmioRead32(Vop2->BaseAddress + 4 * BakIndex); + } + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_OVL_CTRL, EN_MASK, + OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_POL, EN_MASK, + IF_CTRL_REG_DONE_IMD_SHIFT, 1, FALSE); + + for (i = 0; i < Vop2->Data->NrVps; i++) { + DEBUG ((DEBUG_INIT, "vp%d have layer nr:%d[", i, Vop2->VpPlaneMask[i].AttachedLayersNr)); + for (j = 0; j < Vop2->VpPlaneMask[i].AttachedLayersNr; j++) + DEBUG ((DEBUG_INIT, "%d ", Vop2->VpPlaneMask[i].AttachedLayers[j])); + DEBUG ((DEBUG_INIT, "], primary plane: %d\n", Vop2->VpPlaneMask[i].PrimaryPlaneId)); + } + + Shift = 0; + /* layer sel win id */ + for (i = 0; i < Vop2->Data->NrVps; i++) { + LayerNr = Vop2->VpPlaneMask[i].AttachedLayersNr; + for (j = 0; j < LayerNr; j++) { + LayerPhyID = Vop2->VpPlaneMask[i].AttachedLayers[j]; + WinData = Vop2FindWinByPhysID (Vop2, LayerPhyID); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, + Shift, WinData->LayerSelWinID, FALSE); + Shift += 4; + } + } + + /* win sel port */ + for (i = 0; i < Vop2->Data->NrVps; i++) { + LayerNr = Vop2->VpPlaneMask[i].AttachedLayersNr; + for (j = 0; j < LayerNr; j++) { + if (!Vop2->VpPlaneMask[i].AttachedLayers[j]) + continue; + LayerPhyID = Vop2->VpPlaneMask[i].AttachedLayers[j]; + WinData = Vop2FindWinByPhysID (Vop2, LayerPhyID); + Shift = WinData->WinSelPortOffset * 2; + Vop2MaskWrite (Vop2->BaseAddress, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, + LAYER_SEL_PORT_SHIFT + Shift, i, FALSE); + } + } + + /* + * port mux config + */ + for (i = 0; i < Vop2->Data->NrVps; i++) { + Shift = i * 4; + if (Vop2->VpPlaneMask[i].AttachedLayersNr) { + TotalUsedLayer += Vop2->VpPlaneMask[i].AttachedLayersNr; + PortMux = TotalUsedLayer - 1; + } else { + PortMux = 8; + } + + if (i == (Vop2->Data->NrVps - 1)) + PortMux = Vop2->Data->NrMixers; + + Crtc->Vps[i].BgOvlDly = (Vop2->Data->NrMixers - PortMux) << 1; + Vop2MaskWrite (Vop2->BaseAddress, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, + PORT_MUX_SHIFT + Shift, PortMux, FALSE); + } + + Vop2->GlobalInit = TRUE; +} + +STATIC +UINT64 +Vop2CalcDclk ( + IN UINT32 ChildClk, + IN UINT32 MaxDclk + ) +{ + if (ChildClk * 4 <= MaxDclk) + return ChildClk * 4; + else if (ChildClk * 2 <= MaxDclk) + return ChildClk * 2; + else if (ChildClk <= MaxDclk) + return ChildClk; + else + return 0; +} + +STATIC +UINT64 +Vop2CalcCruConfig ( + IN DISPLAY_STATE *DisplayState, + OUT UINT32 *DclkCoreDiv, + OUT UINT32 *DclkOutDiv, + OUT UINT32 *IfPixclkDiv, + OUT UINT32 *IfDclkDiv + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + DRM_DISPLAY_MODE *DisplayMode = &ConnectorState->DisplayMode; + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + VOP2 *Vop2 = CrtcState->Private; + UINT64 VPixclk = DisplayMode->Clock; + UINT64 DclkCoreRate = VPixclk >> 2; + UINT64 DclkRate = VPixclk; + UINT64 IfDclkRate; + UINT64 IfPixclkRate; + UINT64 DclkOutRate; + INT32 OutputType = ConnectorState->Type; + INT32 OutputMode = ConnectorState->OutputMode; + UINT8 K = 1; + + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE && + OutputMode == ROCKCHIP_OUT_MODE_YUV420) { + DEBUG ((DEBUG_ERROR, "Dual channel and YUV420 can't work together\n")); + return -RETURN_INVALID_PARAMETER; + } + + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || + OutputMode == ROCKCHIP_OUT_MODE_YUV420) + K = 2; + + if (OutputType == DRM_MODE_CONNECTOR_HDMIA) { + /* + * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate + * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate + */ + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || + OutputMode == ROCKCHIP_OUT_MODE_YUV420) { + DclkRate = DclkRate >> 1; + K = 2; + } + + IfPixclkRate = (DclkCoreRate << 1) / K; + IfDclkRate = DclkCoreRate / K; + + if (VPixclk > VOP2_MAX_DCLK_RATE) + DclkRate = Vop2CalcDclk (DclkCoreRate, Vop2->Data->VpData->MaxDclk); + + if (!DclkRate) { + DEBUG ((DEBUG_ERROR, "DP IfPixclkRate out of range(MaxDclk: %d KHZ, DclkCore: %lld KHZ)\n", + Vop2->Data->VpData->MaxDclk, IfPixclkRate)); + return -RETURN_INVALID_PARAMETER; + } + *IfPixclkDiv = DclkRate / IfPixclkRate; + *IfDclkDiv = DclkRate / IfDclkRate; + *DclkCoreDiv = DclkRate / DclkCoreRate; + DEBUG ((DEBUG_INFO, "DclkRate:%lu,IfPixclkDiv;%d,IfDclkDiv:%d\n", + DclkRate, *IfPixclkDiv, *IfDclkDiv)); + } else if (OutputType == DRM_MODE_CONNECTOR_eDP) { + /* edp_pixclk = edp_dclk > dclk_core */ + IfPixclkRate = VPixclk / K; + IfDclkRate = VPixclk / K; + DclkRate = IfPixclkRate * K; + *DclkCoreDiv = DclkRate / DclkCoreRate; + *IfPixclkDiv = DclkRate / IfPixclkRate; + *IfDclkDiv = *IfPixclkDiv; + } else if (OutputType == DRM_MODE_CONNECTOR_DisplayPort) { + DclkOutRate = VPixclk >> 2; + DclkOutRate = DclkOutRate / K; + + DclkRate = Vop2CalcDclk(DclkOutRate, + Vop2->Data->VpData->MaxDclk); + if (!DclkRate) { + DEBUG ((DEBUG_ERROR, "DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n", + Vop2->Data->VpData->MaxDclk, DclkCoreRate)); + return EFI_INVALID_PARAMETER; + } + *DclkOutDiv = DclkRate / DclkOutRate; + *DclkCoreDiv = DclkRate / DclkCoreRate; + } else if (OutputType == DRM_MODE_CONNECTOR_DSI) { + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) + K = 2; + if (CrtcState->dsc_enable) + /* dsc output is 96bit, dsi input is 192 bit */ + IfPixclkRate = CrtcState->dsc_cds_clk_rate >> 1; + else + IfPixclkRate = DclkCoreRate / K; + /* dclk_core = dclk_out * K = if_pixclk * K = VPixclk / 4 */ + DclkOutRate = DclkCoreRate / K; + /* DclkRate = N * DclkCoreRate N = (1,2,4 ), we get a little factor here */ + DclkRate = Vop2CalcDclk(DclkOutRate, + Vop2->Data->VpData->MaxDclk); + if (!DclkRate) { + DEBUG ((DEBUG_INFO, "MIPI dclk out of range(max_dclk: %d KHZ, DclkRate: %ld KHZ)\n", + Vop2->Data->VpData->MaxDclk, DclkRate)); + return -EINVAL; + } + + if (CrtcState->dsc_enable) + DclkRate /= CrtcState->dsc_slice_num; + + *DclkOutDiv = DclkRate / DclkOutRate; + *DclkCoreDiv = DclkRate / DclkCoreRate; + *IfPixclkDiv = 1; /*mipi pixclk == dclk_out*/ + if (CrtcState->dsc_enable) + *IfPixclkDiv = DclkOutRate * 1000LL / IfPixclkRate; + } + + *IfPixclkDiv = LogCalculate(*IfPixclkDiv); + *IfDclkDiv = LogCalculate(*IfDclkDiv); + *DclkCoreDiv = LogCalculate(*DclkCoreDiv); + *DclkOutDiv = LogCalculate(*DclkOutDiv); + + DEBUG ((DEBUG_INFO, "[VOP2](CalcCru)DclkRate = %ld(divide: %d)\n", DclkRate, *DclkOutDiv)); + DEBUG ((DEBUG_INFO, " DclkCoreRate = %ld(divide: %d)\n", DclkCoreRate, *DclkCoreDiv)); + DEBUG ((DEBUG_INFO, " IfDclkRate = %ld(divide: %d)\n", IfDclkRate, *IfDclkDiv)); + DEBUG ((DEBUG_INFO, " IfPixclkRate = %ld(divide: %d)\n", IfPixclkRate, *IfPixclkDiv)); + + return DclkRate; +} + +STATIC +EFI_STATUS +Vop2CalcDscClk ( + OUT DISPLAY_STATE *DisplayState + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + DRM_DISPLAY_MODE *DisplayMode = &ConnectorState->DisplayMode; + UINT64 VPixclk = DisplayMode->CrtcClock * 1000LL; /* video timing pixclk */ + UINT8 K = 1; + + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) + K = 2; + + CrtcState->dsc_txp_clk_rate = VPixclk; + do_div(CrtcState->dsc_txp_clk_rate, (CrtcState->dsc_pixel_num * K)); + + CrtcState->dsc_pxl_clk_rate = VPixclk; + do_div(CrtcState->dsc_pxl_clk_rate, (CrtcState->dsc_slice_num * K)); + + /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel) + * cds_dat_width = 96; + * bits_per_pixel = [8-12]; + * As cds clk is div from txp clk and only support 1/2/4 div, + * so when txp_clk is equal to VPixclk, we set dsc_cds = crtc_clock / 4, + * otherwise dsc_cds = crtc_clock / 8; + */ + CrtcState->dsc_cds_clk_rate = VPixclk / (CrtcState->dsc_txp_clk_rate == VPixclk ? 4 : 8); + + return 0; +} + +STATIC +UINT32 +Vop2IfConfig ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2 *Vop2 + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + DRM_DISPLAY_MODE *DisplayMode = &ConnectorState->DisplayMode; + struct rockchip_dsc_sink_cap *dsc_sink_cap = &CrtcState->dsc_sink_cap; + UINT32 VPOffset = CrtcState->CrtcID * 0x100; + UINT32 OutputIf = ConnectorState->OutputInterface; + UINT32 DclkCoreDiv = 0; + UINT32 DclkOutDiv = 0; + UINT32 IfPixclkDiv = 0; + UINT32 IfDclkDiv = 0; + UINT32 DclkRate; + UINT32 Val; + + if (OutputIf & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { + Val = (DisplayMode->Flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; + Val |= (DisplayMode->Flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; + } else { + Val = (DisplayMode->Flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); + Val |= (DisplayMode->Flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); + } + + if (CrtcState->dsc_enable) { + UINT32 K = 1; + + if (!Vop2->Data->NrDscs) { + DEBUG ((DEBUG_ERROR, "Unsupported DSC\n")); + return 0; + } + + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) + K = 2; + + CrtcState->dsc_id = OutputIf & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_HDMI0) ? 0 : 1; + CrtcState->dsc_slice_num = DisplayMode->CrtcHDisplay / dsc_sink_cap->slice_width / K; + CrtcState->dsc_pixel_num = CrtcState->dsc_slice_num > 4 ? 4 : CrtcState->dsc_slice_num; + + Vop2CalcDscClk(DisplayState); + DEBUG ((DEBUG_INFO, "Enable DSC%d slice:%dx%d, slice num:%d\n", + CrtcState->dsc_id, dsc_sink_cap->slice_width, + dsc_sink_cap->slice_height, CrtcState->dsc_slice_num)); + } + + DclkRate = Vop2CalcCruConfig(DisplayState, &DclkCoreDiv, &DclkOutDiv, &IfPixclkDiv, &IfDclkDiv); + CrtcState->DclkCoreDiv = DclkCoreDiv; + CrtcState->DclkOutDiv = DclkOutDiv; + + if (OutputIf & VOP_OUTPUT_IF_MIPI0) { + if (CrtcState->CrtcID == 2) + Val = 0; + else + Val = 1; + + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, EN_MASK, + RK3588_MIPI_DSI0_MODE_SEL_SHIFT, 1, FALSE); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, + 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, Val, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 3, MIPI0_PIXCLK_DIV_SHIFT, + IfPixclkDiv, FALSE); + + if (ConnectorState->hold_mode) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_MIPI_CTRL + VPOffset, + EN_MASK, EDPI_TE_EN, TRUE, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_MIPI_CTRL + VPOffset, + EN_MASK, EDPI_WMS_HOLD_EN, 1, FALSE); + } + } + + if (OutputIf & VOP_OUTPUT_IF_MIPI1) { + if (CrtcState->CrtcID == 2) + Val = 0; + else if (CrtcState->CrtcID == 3) + Val = 1; + else + Val = 3; /*VP1*/ + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, EN_MASK, + RK3588_MIPI_DSI1_MODE_SEL_SHIFT, 1, FALSE); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, + 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT, + Val, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 3, MIPI1_PIXCLK_DIV_SHIFT, + IfPixclkDiv, FALSE); + + if (ConnectorState->hold_mode) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_MIPI_CTRL + VPOffset, + EN_MASK, EDPI_TE_EN, TRUE, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_MIPI_CTRL + VPOffset, + EN_MASK, EDPI_WMS_HOLD_EN, 1, FALSE); + } + } + + if (OutputIf & VOP_OUTPUT_IF_eDP0) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK, + RK3588_EDP0_EN_SHIFT, 1, FALSE); + /* temp eDP0 fixed vp2 */ + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK, + RK3588_HDMI_EDP0_MUX_SHIFT, CrtcState->CrtcID, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 0x3, + HDMI_EDP0_DCLK_DIV_SHIFT, IfDclkDiv, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 0x3, + HDMI_EDP0_PIXCLK_DIV_SHIFT, IfPixclkDiv, FALSE); + Vop2GrfWrite (RK3588_VOP_GRF_BASE, RK3588_GRF_VOP_CON2, EN_MASK, + RK3588_GRF_EDP0_ENABLE_SHIFT, 1); + } + + if (OutputIf & VOP_OUTPUT_IF_eDP1) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK, + RK3588_EDP1_EN_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK, + RK3588_HDMI_EDP1_MUX_SHIFT, CrtcState->CrtcID, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 0x3, + HDMI_EDP1_DCLK_DIV_SHIFT, IfDclkDiv, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 0x3, + HDMI_EDP1_PIXCLK_DIV_SHIFT, IfPixclkDiv, FALSE); + Vop2GrfWrite (RK3588_VOP_GRF_BASE, RK3588_GRF_VOP_CON2, EN_MASK, + RK3588_GRF_EDP1_ENABLE_SHIFT, 1); + } + + if (OutputIf & VOP_OUTPUT_IF_HDMI0) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK, + RK3588_HDMI0_EN_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK, + RK3588_HDMI_EDP0_MUX_SHIFT, CrtcState->CrtcID, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 0x3, + HDMI_EDP0_DCLK_DIV_SHIFT, IfDclkDiv, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 0x3, + HDMI_EDP0_PIXCLK_DIV_SHIFT, IfPixclkDiv, FALSE); + Vop2GrfWrite (RK3588_VOP_GRF_BASE, RK3588_GRF_VOP_CON2, EN_MASK, + RK3588_GRF_HDMITX0_ENABLE_SHIFT, 1); + Vop2GrfWrite (RK3588_VO1_GRF_BASE, RK3588_GRF_VO1_CON0, HDMI_SYNC_POL_MASK, + HDMI0_SYNC_POL_SHIFT, Val); + } + + if (OutputIf & VOP_OUTPUT_IF_HDMI1) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK, + RK3588_HDMI1_EN_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK, + RK3588_HDMI_EDP1_MUX_SHIFT, CrtcState->CrtcID, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 0x3, + HDMI_EDP1_DCLK_DIV_SHIFT, IfDclkDiv, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_CTRL, 0x3, + HDMI_EDP1_PIXCLK_DIV_SHIFT, IfPixclkDiv, FALSE); + Vop2GrfWrite (RK3588_VOP_GRF_BASE, RK3588_GRF_VOP_CON2, EN_MASK, + RK3588_GRF_HDMITX1_ENABLE_SHIFT, 1); + Vop2GrfWrite (RK3588_VO1_GRF_BASE, RK3588_GRF_VO1_CON0, HDMI_SYNC_POL_MASK, + HDMI1_SYNC_POL_SHIFT, Val); + } + + if (OutputIf & VOP_OUTPUT_IF_DP0) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK, + RK3588_DP0_EN_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK, + RK3588_DP0_MUX_SHIFT, CrtcState->CrtcID, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, + RK3588_DP0_PIN_POL_SHIFT, Val, FALSE); + } + + if (OutputIf & VOP_OUTPUT_IF_DP1) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK, + RK3588_DP1_EN_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK, + RK3588_DP1_MUX_SHIFT, CrtcState->CrtcID, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, + RK3588_DP1_PIN_POL_SHIFT, Val, FALSE); + } + + Vop2MaskWrite (Vop2->BaseAddress, RK3588_VP0_CLK_CTRL + VPOffset, 0x3, + DCLK_CORE_DIV_SHIFT, DclkCoreDiv, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_VP0_CLK_CTRL + VPOffset, 0x3, + DCLK_OUT_DIV_SHIFT, DclkOutDiv, FALSE); + + return DclkRate; +} + +STATIC +BOOLEAN +IsUVSwap ( + IN UINT32 BusFormat, + IN UINT32 OutputMode + ) +{ + /* + * FIXME: + * + * There is no media type for YUV444 output, + * so when out_mode is AAAA or P888, assume output is YUV444 on + * yuv format. + * + * From H/W testing, YUV444 mode need a rb swap. + */ + if ((BusFormat == MEDIA_BUS_FMT_YUV8_1X24 || + BusFormat == MEDIA_BUS_FMT_YUV10_1X30) && + (OutputMode == ROCKCHIP_OUT_MODE_AAAA || + OutputMode == ROCKCHIP_OUT_MODE_P888)) + return TRUE; + else + return FALSE; +} + +STATIC +BOOLEAN +IsYUVOutput ( + IN UINT32 BusFormat + ) +{ + switch (BusFormat) { + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_YUV10_1X30: + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + case MEDIA_BUS_FMT_YUYV8_2X8: + case MEDIA_BUS_FMT_YVYU8_2X8: + case MEDIA_BUS_FMT_UYVY8_2X8: + case MEDIA_BUS_FMT_VYUY8_2X8: + case MEDIA_BUS_FMT_YUYV8_1X16: + case MEDIA_BUS_FMT_YVYU8_1X16: + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_VYUY8_1X16: + return TRUE; + default: + return FALSE; +} +} + +INLINE +UINT32 +Vop2ConvertCSCMode ( + IN UINT32 CSCMode + ) +{ + switch (CSCMode) { + case V4L2_COLORSPACE_SMPTE170M: + case V4L2_COLORSPACE_470_SYSTEM_M: + case V4L2_COLORSPACE_470_SYSTEM_BG: + return CSC_BT601L; + case V4L2_COLORSPACE_REC709: + case V4L2_COLORSPACE_SMPTE240M: + case V4L2_COLORSPACE_DEFAULT: + return CSC_BT709L; + case V4L2_COLORSPACE_JPEG: + return CSC_BT601F; + case V4L2_COLORSPACE_BT2020: + return CSC_BT2020; + default: + return CSC_BT709L; + } +} + +INLINE +INT32 +Interpolate ( + IN INT32 X1, + IN INT32 Y1, + IN INT32 X2, + IN INT32 Y2, + IN INT32 X + ) +{ + return Y1 + (Y2 - Y1) * (X - X1) / (X2 - X1); +} + +INLINE +INT32 +__Fixp_Sin32 ( + IN UINT32 Degrees + ) +{ + INT32 Ret; + BOOLEAN Negative = FALSE; + + if (Degrees > 180) { + Negative = TRUE; + Degrees -= 180; + } + if (Degrees > 90) + Degrees = 180 - Degrees; + + Ret = mSinTable[Degrees]; + + return Negative ? -Ret : Ret; +} + +INLINE +INT32 +FixpSin32 ( + IN UINT32 Degrees + ) +{ + Degrees = (Degrees % 360 + 360) % 360; + + return __Fixp_Sin32(Degrees); +} +#define FixpCos32(v) FixpSin32((v) + 90) +#define FixpSin16(v) (FixpSin32(v) >> 16) +#define FixpCos16(v) (FixpCos32(v) >> 16) + +STATIC +VOID +Vop2TVConfigUpdate ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2 *Vop2 + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + BASE_BCSH_INFO *BCSHInfo; + UINT32 Brightness, Contrast, Saturation, Hue, SinHue, CosHue; + BOOLEAN BCSHEnable = FALSE; + BOOLEAN R2YEnable = FALSE; + BOOLEAN Y2REnable = FALSE; + UINT32 VPOffset = CrtcState->CrtcID * 0x100; + UINT32 PostCSCMode; + + /* base2_disp_info --- todo */ + if (!ConnectorState->DispInfo) + return; + + BCSHInfo = &ConnectorState->DispInfo->BCSHInfo; + if (!BCSHInfo) + return; + + if (BCSHInfo->Brightness != 50 || + BCSHInfo->Contrast != 50 || + BCSHInfo->Saturation != 50 || + BCSHInfo->Hue != 50) + BCSHEnable = TRUE; + + if (BCSHEnable) { + if (!CrtcState->YUVOverlay) + R2YEnable = TRUE; + if (!IsYUVOutput(ConnectorState->BusFormat)) + Y2REnable = TRUE; + } else { + if (!CrtcState->YUVOverlay && IsYUVOutput(ConnectorState->BusFormat)) + R2YEnable = TRUE; + if (CrtcState->YUVOverlay && !IsYUVOutput(ConnectorState->BusFormat)) + Y2REnable = TRUE; + } + + PostCSCMode = Vop2ConvertCSCMode(ConnectorState->ColorSpace); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_CTRL + VPOffset, BCSH_CTRL_R2Y_MASK, + BCSH_CTRL_R2Y_SHIFT, R2YEnable, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_CTRL + VPOffset, BCSH_CTRL_Y2R_MASK, + BCSH_CTRL_Y2R_SHIFT, Y2REnable, FALSE); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_CTRL + VPOffset, BCSH_CTRL_R2Y_CSC_MODE_MASK, + BCSH_CTRL_R2Y_CSC_MODE_SHIFT, PostCSCMode, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_CTRL + VPOffset, BCSH_CTRL_Y2R_CSC_MODE_MASK, + BCSH_CTRL_Y2R_CSC_MODE_SHIFT, PostCSCMode, FALSE); + if (!BCSHEnable) { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_COLOR + VPOffset, BCSH_EN_MASK, + BCSH_EN_SHIFT, 0, FALSE); + return; + } + + if (CrtcState->Feature & VOP_FEATURE_OUTPUT_10BIT) + Brightness = Interpolate(0, -128, 100, 127, BCSHInfo->Brightness); + else + Brightness = Interpolate(0, -32, 100, 31, BCSHInfo->Brightness); + Contrast = Interpolate(0, 0, 100, 511, BCSHInfo->Contrast); + Saturation = Interpolate(0, 0, 100, 511, BCSHInfo->Saturation); + Hue = Interpolate(0, -30, 100, 30, BCSHInfo->Hue); + + /* + * a:[-30~0): + * sin_hue = 0x100 - sin(a)*256; + * cos_hue = cos(a)*256; + * a:[0~30] + * sin_hue = sin(a)*256; + * cos_hue = cos(a)*256; + */ + SinHue = FixpSin32(Hue) >> 23; + CosHue = FixpCos32(Hue) >> 23; + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_BCS + VPOffset, BCSH_BRIGHTNESS_MASK, + BCSH_BRIGHTNESS_SHIFT, Brightness, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_BCS + VPOffset, BCSH_CONTRAST_MASK, + BCSH_CONTRAST_SHIFT, Contrast, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_BCS + VPOffset, BCSH_SATURATION_MASK, + BCSH_SATURATION_SHIFT, Saturation, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_H + VPOffset, BCSH_SIN_HUE_MASK, + BCSH_SIN_HUE_SHIFT, SinHue, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_H + VPOffset, BCSH_COS_HUE_MASK, + BCSH_COS_HUE_SHIFT, CosHue, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_BCS + VPOffset, BCSH_OUT_MODE_MASK, + BCSH_OUT_MODE_SHIFT, BCSH_OUT_MODE_NORMAL_VIDEO, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BCSH_COLOR + VPOffset, BCSH_EN_MASK, + BCSH_EN_SHIFT, 1, FALSE); +} + +INLINE +UINT16 SclCalScale2 ( + IN INT32 Src, + IN INT32 Dst + ) +{ + return ((Src - 1) << 12) / (Dst - 1); +} + +STATIC +VOID +Vop2PostConfig ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2 *Vop2 + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + ROCKCHIP_CRTC_PROTOCOL *Crtc = (ROCKCHIP_CRTC_PROTOCOL *)CrtcState->Crtc; + DRM_DISPLAY_MODE *Mode = &ConnectorState->DisplayMode; + UINT32 VPOffset = CrtcState->CrtcID * 0x100; + UINT16 HDisplay = Mode->CrtcHDisplay; + UINT16 HActStart = Mode->CrtcHTotal - Mode->CrtcHSyncStart; + UINT16 VDisplay = Mode->CrtcVDisplay; + UINT16 VTotal = Mode->CrtcVTotal; + UINT16 VActStart = Mode->CrtcVTotal - Mode->CrtcVSyncStart; + UINT16 HSize = HDisplay * (ConnectorState->OverScan.LeftMargin + + ConnectorState->OverScan.RightMargin) /200; + UINT16 VSize = VDisplay * (ConnectorState->OverScan.TopMargin + + ConnectorState->OverScan.BottomMargin) /200; + UINT16 HActEnd, VActEnd; + UINT32 Val; + + UINT32 BgOvlDly, BgDly, PreScanDly; + UINT16 HSyncLen = Mode->CrtcHSyncEnd - Mode->CrtcHSyncStart; + + HSize = ROUNDDOWN (HSize, 2); + VSize = ROUNDDOWN (VSize, 2); + + HActStart += HDisplay * (100 - ConnectorState->OverScan.LeftMargin) / 200; + HActEnd = HActStart + HSize; + Val = HActStart << 16; + Val |= HActEnd; + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_POST_DSP_HACT_INFO + VPOffset, Val); + + VActStart += VDisplay * (100 - ConnectorState->OverScan.TopMargin) / 200; + VActEnd = VActStart + VSize; + Val = VActStart << 16; + Val |= VActEnd; + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_POST_DSP_VACT_INFO + VPOffset, Val); + + Val = SclCalScale2 (VDisplay, VSize) << 16; + Val |= SclCalScale2 (VDisplay, VSize); + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_POST_SCL_FACTOR_YRGB + VPOffset, Val); + +#define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) +#define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_POST_SCL_CTRL + VPOffset, + POST_HORIZONTAL_SCALEDOWN_EN(HDisplay != HSize) | + POST_VERTICAL_SCALEDOWN_EN(VDisplay != VSize)); + + if (Mode->Flags & DRM_MODE_FLAG_INTERLACE) { + UINT16 VActStartF1 = VTotal + VActStart + 1; + UINT16 VActEndF1 = VActStartF1 + VDisplay; + + Val = VActStartF1 << 16 | VActEndF1; + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_POST_DSP_VACT_INFO_F1 + VPOffset, Val); + } + + BgOvlDly = Crtc->Vps[CrtcState->CrtcID].BgOvlDly; + BgDly = Vop2->Data->VpData[CrtcState->CrtcID].PreScanMaxDly; + BgDly -= BgOvlDly; + PreScanDly = BgDly + (HDisplay >> 1) - 1; + if (Vop2->Version == VOP_VERSION_RK3588 && HSyncLen < 8) + HSyncLen = 8; + PreScanDly = (PreScanDly << 16) | HSyncLen; + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_BG_MIX_CTRL + CrtcState->CrtcID * 4, BG_MIX_CTRL_MASK, + BG_MIX_CTRL_SHIFT, BgDly, FALSE); + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_PRE_SCAN_HTIMING + VPOffset, PreScanDly); + + MmioWrite32 (0xfdd906e8, 0x34000000); +} + +STATIC +INT32 +Vop2WaitPowerDomainOn ( + OUT VOP2 *Vop2, + OUT VOP2_POWER_DOMAIN_DATA *PdData + ) +{ + UINT32 Val = 0; + BOOLEAN IsBisrEn = FALSE; + + IsBisrEn = Vop2GrfRead (Vop2->SysPmu, RK3588_PMU_BISR_CON3, EN_MASK, PdData->BisrEnStatusShift); + if (IsBisrEn) { + return readl_poll_timeout(Vop2->SysPmu + RK3588_PMU_BISR_STATUS5, Val, + ((Val >> PdData->PmuStatusShift) & 0x1), 50 * 1000); + } else { + return readl_poll_timeout(Vop2->BaseAddress + RK3568_SYS_STATUS0, Val, + !((Val >> PdData->PdStatusShift) & 0x1), 50 * 1000); + } +} + +STATIC +EFI_STATUS +Vop2PowerDomainOn ( + OUT VOP2 *Vop2, + OUT VOP2_POWER_DOMAIN_DATA *PdData + ) +{ + INT32 Ret = 0; + + if (!PdData) + return 0; + + if (PdData->ParentPdData) { + Ret = Vop2PowerDomainOn (Vop2, PdData->ParentPdData); + if (Ret) { + DEBUG ((DEBUG_ERROR, "can't open parent power domain\n")); + return EFI_INVALID_PARAMETER; + } + } + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_SYS_PD_CTRL, EN_MASK, + PdData->PdEnShift, 0, FALSE); + Ret = Vop2WaitPowerDomainOn(Vop2, PdData); + if (Ret) { + DEBUG ((DEBUG_ERROR, "wait vop2 power domain timeout\n")); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +Vop2SetClk ( + IN UINT32 CrtcId, + IN UINT64 Rate +) +{ + /* only support VP2 for now */ + ASSERT (CrtcId == 2); + + /* CRU_MODE_CON00: set clock modes */ + MmioWrite32(CRU_BASE + 0x0280, 0xFFFF0155); + + HAL_CRU_ClkSetFreq (DCLK_VOP2_SRC, Rate); + + DEBUG ((DEBUG_INFO, "%a: V0PLL=%lu, DCLK_VOP2_SRC=%lu\n", + __func__, HAL_CRU_ClkGetFreq (PLL_V0PLL), HAL_CRU_ClkGetFreq (DCLK_VOP2_SRC))); + + return EFI_SUCCESS; +} + +STATIC +CHAR8 * +GetOutputIfName ( + IN UINT32 OutputIf + ) +{ + INT32 i = 0; + INT32 Shift = 0; + + for (i = 0; i < VOP_OUTPUT_IF_NUMS; i++) { + Shift = 1 << i; + if (OutputIf & Shift) { + return mDisplayIfName[i]; + } + } + + return mDisplayIfName[0]; +} + +EFI_STATUS +Vop2PreInit ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + + if (!RockchipVop2) { + RockchipVop2 = AllocatePool (sizeof(*RockchipVop2)); + RockchipVop2->BaseAddress = RK3588_VOP2_REG_BASE; + RockchipVop2->SysPmu = SYS_PMU_BASE; + RockchipVop2->Version = mVop2RK3588.Version; + RockchipVop2->Data = &mVop2RK3588; + RockchipVop2->GlobalInit = FALSE; + ZeroMem (RockchipVop2->VpPlaneMask, sizeof(VOP2_VP_PLANE_MASK) * VOP2_VP_MAX); + } + + CrtcState->Private = RockchipVop2; + CrtcState->MaxOutput = RockchipVop2->Data->VpData[CrtcState->CrtcID].MaxOutput; + CrtcState->Feature = RockchipVop2->Data->VpData[CrtcState->CrtcID].Feature; + + /* fix the plane mask about */ + Vop2GlobalInitial (DisplayState); + + return EFI_SUCCESS; +} + +#define OUTPUT_IF_IS_HDMI(x) ((x) & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) +#define OUTPUT_IF_IS_DP(x) ((x) & (VOP_OUTPUT_IF_DP0 | VOP_OUTPUT_IF_DP1)) + +STATIC +VOID +Vop2PostColorSwap ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2 *Vop2 + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + UINT32 VPOffset = CrtcState->CrtcID * 0x100; + UINT32 OutputIf = ConnectorState->OutputInterface; + UINT32 DateSwap = 0; + + if (IsUVSwap(ConnectorState->BusFormat, ConnectorState->OutputMode)) + DateSwap = DSP_RB_SWAP; + + if (Vop2->Version == VOP_VERSION_RK3588 && + (OUTPUT_IF_IS_HDMI(OutputIf) || OUTPUT_IF_IS_DP(OutputIf)) && + (ConnectorState->BusFormat == MEDIA_BUS_FMT_YUV8_1X24 || + ConnectorState->BusFormat == MEDIA_BUS_FMT_YUV10_1X30)) + DateSwap |= DSP_RG_SWAP; + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, DATA_SWAP_MASK, + DATA_SWAP_SHIFT, DateSwap, FALSE); +} + +STATIC +VOID +Vop2CalcDscCruCfg ( + OUT DISPLAY_STATE *DisplayState, + OUT UINT32 *dsc_txp_clk_div, + OUT UINT32 *dsc_pxl_clk_div, + OUT UINT32 *dsc_cds_clk_div, + IN UINT64 dclk_rate + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + + *dsc_txp_clk_div = dclk_rate / CrtcState->dsc_txp_clk_rate; + *dsc_pxl_clk_div = dclk_rate / CrtcState->dsc_pxl_clk_rate; + *dsc_cds_clk_div = dclk_rate / CrtcState->dsc_cds_clk_rate; + + *dsc_txp_clk_div = LogCalculate(*dsc_txp_clk_div); + *dsc_pxl_clk_div = LogCalculate(*dsc_pxl_clk_div); + *dsc_cds_clk_div = LogCalculate(*dsc_cds_clk_div); +} + +STATIC +VOID +Vop2LoadPps ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2 *Vop2, + IN UINT8 dsc_id + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + struct drm_dsc_picture_parameter_set *pps = &CrtcState->pps; + struct drm_dsc_picture_parameter_set config_pps; + const VOP2_DSC_DATA *dsc_data = &Vop2->Data->DscData[dsc_id]; + UINT32 *pps_val = (UINT32 *)&config_pps; + UINT32 decoder_regs_offset = (dsc_id * 0x100); + UINT32 i = 0; + + memcpy(&config_pps, pps, sizeof(config_pps)); + + if ((config_pps.pps_3 & 0xf) > dsc_data->max_linebuf_depth) { + config_pps.pps_3 &= 0xf0; + config_pps.pps_3 |= dsc_data->max_linebuf_depth; + DEBUG((DEBUG_INFO, "DSC%d max_linebuf_depth is: %d, current set value is: %d\n", + dsc_id, dsc_data->max_linebuf_depth, config_pps.pps_3 & 0xf)); + } + + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + config_pps.rc_range_parameters[i] = + (pps->rc_range_parameters[i] >> 3 & 0x1f) | + ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) | + ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) | + ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10); + } + + for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++) + Vop2Writel (Vop2->BaseAddress, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++); +} + +STATIC +VOID +Vop2DscEnable ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2 *Vop2, + IN UINT8 dsc_id, + IN UINT64 dclk_rate + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + DRM_DISPLAY_MODE *Mode = &ConnectorState->DisplayMode; + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + struct rockchip_dsc_sink_cap *dsc_sink_cap = &CrtcState->dsc_sink_cap; + const VOP2_DSC_DATA *dsc_data = &Vop2->Data->DscData[dsc_id]; + BOOLEAN mipi_ds_mode = FALSE; + UINT8 dsc_interface_mode = 0; + UINT16 hsync_len = Mode->CrtcHSyncEnd - Mode->CrtcHSyncStart; + UINT16 hdisplay = Mode->CrtcHDisplay; + UINT16 htotal = Mode->CrtcHTotal; + UINT16 hact_st = Mode->CrtcHTotal - Mode->CrtcHSyncStart; + UINT16 vdisplay = Mode->CrtcVDisplay; + UINT16 vtotal = Mode->CrtcVTotal; + UINT16 vsync_len = Mode->CrtcVSyncEnd - Mode->CrtcVSyncStart; + UINT16 vact_st = Mode->CrtcVTotal - Mode->CrtcVSyncStart; + UINT16 vact_end = vact_st + vdisplay; + UINT32 ctrl_regs_offset = (dsc_id * 0x30); + UINT32 decoder_regs_offset = (dsc_id * 0x100); + UINT32 dsc_txp_clk_div = 0; + UINT32 dsc_pxl_clk_div = 0; + UINT32 dsc_cds_clk_div = 0; + UINT32 val = 0; + + if (!Vop2->Data->NrDscs) { + DEBUG ((DEBUG_ERROR, "Unsupported DSC\n")); + return; + } + + if (CrtcState->dsc_slice_num > dsc_data->max_slice_num) + DEBUG ((DEBUG_INFO, "DSC%d supported max slice is: %d, current is: %d\n", + dsc_data->id, dsc_data->max_slice_num, CrtcState->dsc_slice_num)); + + if (dsc_data->PdData) { + if (Vop2PowerDomainOn (Vop2, dsc_data->PdData)) + DEBUG ((DEBUG_ERROR, "open dsc%d pd fail\n", dsc_id)); + } + + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, + SCAN_TIMING_PARA_IMD_EN_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PORT_SEL_MASK, + DSC_PORT_SEL_SHIFT, CrtcState->CrtcID, FALSE); + if (ConnectorState->OutputInterface & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { + dsc_interface_mode = VOP_DSC_IF_HDMI; + } else { + mipi_ds_mode = !!(ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_MIPI_DS_MODE); + if (mipi_ds_mode) + dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE; + else + dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE; + } + + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, + DSC_MAN_MODE_SHIFT, 0, FALSE); + else + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, + DSC_MAN_MODE_SHIFT, 1, FALSE); + + Vop2CalcDscCruCfg(DisplayState, &dsc_txp_clk_div, &dsc_pxl_clk_div, &dsc_cds_clk_div, dclk_rate); + + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_INTERFACE_MODE_MASK, + DSC_INTERFACE_MODE_SHIFT, dsc_interface_mode, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PIXEL_NUM_MASK, + DSC_PIXEL_NUM_SHIFT, CrtcState->dsc_pixel_num >> 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_TXP_CLK_DIV_MASK, + DSC_TXP_CLK_DIV_SHIFT, dsc_txp_clk_div, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PXL_CLK_DIV_MASK, + DSC_PXL_CLK_DIV_SHIFT, dsc_pxl_clk_div, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, + DSC_CDS_CLK_DIV_SHIFT, dsc_cds_clk_div, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, + DSC_SCAN_EN_SHIFT, !mipi_ds_mode, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, + DSC_HALT_EN_SHIFT, mipi_ds_mode, FALSE); + + if (!mipi_ds_mode) { + UINT16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end; + UINT32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16; + UINT64 dsc_cds_rate = CrtcState->dsc_cds_clk_rate; + UINT32 v_pixclk_mhz = Mode->CrtcClock / 1000; /* video timing pixclk */ + UINT32 dly_num, dsc_cds_rate_mhz, val = 0; + UINT32 k = 1; + + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) + k = 2; + + if (target_bpp >> 4 < dsc_data->min_bits_per_pixel) + DEBUG ((DEBUG_WARN, "Unsupported bpp less than: %d\n", dsc_data->min_bits_per_pixel)); + + /* + * dly_num = delay_line_num * T(one-line) / T (dsc_cds) + * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz + * T (dsc_cds) = 1 / dsc_cds_rate_mhz + * + * HDMI: + * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay + * delay_line_num = 4 - BPP / 8 + * = (64 - target_bpp / 8) / 16 + * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; + * + * MIPI DSI[4320 and 9216 is buffer size for DSC]: + * DSC0:delay_line_num = 4320 * 8 / slince_num / chunk_size; + * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num; + * DSC1:delay_line_num = 9216 * 2 / slince_num / chunk_size; + * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num; + * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num + */ + do_div(dsc_cds_rate, 1000000); /* hz to Mhz */ + dsc_cds_rate_mhz = dsc_cds_rate; + dsc_hsync = hsync_len / 2; + if (dsc_interface_mode == VOP_DSC_IF_HDMI) { + dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; + } else { + UINT32 dsc_buf_size = dsc_id == 0 ? 4320 * 8 : 9216 * 2; + UINT32 delay_line_num = dsc_buf_size / CrtcState->dsc_slice_num / + be16_to_cpu(CrtcState->pps.chunk_size); + + delay_line_num = delay_line_num > 5 ? 5 : delay_line_num; + dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num; + + /* The dsc mipi video mode dsc_hsync minimum size is 8 pixels */ + if (dsc_hsync < 8) + dsc_hsync = 8; + } + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK, + DSC_INIT_DLY_MODE_SHIFT, 0, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK, + DSC_INIT_DLY_NUM_SHIFT, dly_num, FALSE); + + /* + * htotal / dclk_core = dsc_htotal /cds_clk + * + * dclk_core = DCLK / (1 << dclk_core->div_val) + * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val) + * txp_clk = DCLK / (1 << dsc_txp_clk->div_val) + * + * dsc_htotal = htotal * (1 << dclk_core->div_val) / + * ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val)) + */ + dsc_htotal = htotal * (1 << CrtcState->DclkCoreDiv) / + ((1 << dsc_txp_clk_div) * (1 << dsc_cds_clk_div)); + val = dsc_htotal << 16 | dsc_hsync; + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_HTOTAL_HS_END + ctrl_regs_offset, DSC_HTOTAL_PW_MASK, + DSC_HTOTAL_PW_SHIFT, val, FALSE); + + dsc_hact_st = hact_st / 2; + dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st; + val = dsc_hact_end << 16 | dsc_hact_st; + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_HACT_ST_END + ctrl_regs_offset, DSC_HACT_ST_END_MASK, + DSC_HACT_ST_END_SHIFT, val, FALSE); + + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_VTOTAL_VS_END + ctrl_regs_offset, DSC_VTOTAL_PW_MASK, + DSC_VTOTAL_PW_SHIFT, vtotal << 16 | vsync_len, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_VACT_ST_END + ctrl_regs_offset, DSC_VACT_ST_END_MASK, + DSC_VACT_ST_END_SHIFT, vact_end << 16 | vact_st, FALSE); + } + + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK, + RST_DEASSERT_SHIFT, 1, FALSE); + udelay(10); + + val |= DSC_CTRL0_DEF_CON | (LogCalculate(CrtcState->dsc_slice_num) << DSC_NSLC_SHIFT) | + ((dsc_sink_cap->version_minor == 2 ? 1 : 0) << DSC_IFEP_SHIFT); + Vop2Writel (Vop2->BaseAddress, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val); + + Vop2LoadPps(DisplayState, Vop2, dsc_id); + + val |= (1 << DSC_PPS_UPD_SHIFT); + Vop2Writel (Vop2->BaseAddress, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val); + + DEBUG ((DEBUG_INFO, "DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n", + dsc_id, + CrtcState->dsc_txp_clk_rate, dsc_txp_clk_div, + CrtcState->dsc_pxl_clk_rate, dsc_pxl_clk_div, + CrtcState->dsc_cds_clk_rate, dsc_cds_clk_div)); +} + +EFI_STATUS +Vop2Init ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + DRM_DISPLAY_MODE *Mode = &ConnectorState->DisplayMode; + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + VOP2 *Vop2 = CrtcState->Private;; + UINT32 VPOffset = CrtcState->CrtcID * 0x100; + UINT32 LineFlagOffset = CrtcState->CrtcID * 0x4; + UINT16 HSyncLen, HDisplay, HTotal, HActStart, HActEnd; + UINT16 VSyncLen, VDisplay, VTotal, VActStart, VActEnd; + UINT32 Val, ActEnd; + UINT8 DitherDownEn; + UINT8 PreDitherDownEn; + BOOLEAN YUVOverlay; + UINT64 DclkRate; + + HSyncLen = Mode->CrtcHSyncEnd - Mode->CrtcHSyncStart; + HDisplay = Mode->CrtcHDisplay; + HTotal = Mode->CrtcHTotal; + HActStart = Mode->CrtcHTotal - Mode->CrtcHSyncStart; + HActEnd = HActStart + HDisplay; + + VSyncLen = Mode->CrtcVSyncEnd - Mode->CrtcVSyncStart; + VDisplay = Mode->CrtcVDisplay; + VTotal = Mode->CrtcVTotal; + VActStart = Mode->CrtcVTotal - Mode->CrtcVSyncStart; + VActEnd = VActStart + VDisplay; + + DEBUG((DEBUG_INIT, "[INIT]VOP update mode to: %dx%d%a%d, type:%a for VP%d\n", + Mode->HDisplay, Mode->VDisplay, + Mode->Flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", + Mode->VScan, + GetOutputIfName(ConnectorState->OutputInterface), + CrtcState->CrtcID)); + + DclkRate = Vop2IfConfig (DisplayState, Vop2); + + if (ConnectorState->OutputMode == ROCKCHIP_OUT_MODE_AAAA && + !(CrtcState->Feature & VOP_FEATURE_OUTPUT_10BIT)) + ConnectorState->OutputMode = ROCKCHIP_OUT_MODE_P888; + + Vop2PostColorSwap (DisplayState, Vop2); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, OUT_MODE_MASK, + OUT_MODE_SHIFT, ConnectorState->OutputMode, FALSE); + + switch (ConnectorState->BusFormat) { + case MEDIA_BUS_FMT_RGB565_1X16: + DitherDownEn = 1; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: + DitherDownEn = 1; + break; + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + DitherDownEn = 0; + PreDitherDownEn = 1; + break; + case MEDIA_BUS_FMT_YUV10_1X30: + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + default: + DitherDownEn = 0; + PreDitherDownEn = 0; + break; + } + + if (ConnectorState->OutputMode == ROCKCHIP_OUT_MODE_AAAA) + PreDitherDownEn = 0; + else + PreDitherDownEn = 1; + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + DITHER_DOWN_EN_SHIFT, DitherDownEn, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + PRE_DITHER_DOWN_EN_SHIFT, PreDitherDownEn, FALSE); + + YUVOverlay = IsYUVOutput (ConnectorState->BusFormat) ? 1 : 0; + Vop2MaskWrite (Vop2->BaseAddress, RK3568_OVL_CTRL, EN_MASK, + CrtcState->CrtcID, YUVOverlay, FALSE); + CrtcState->YUVOverlay = YUVOverlay; + + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_DSP_HTOTAL_HS_END + VPOffset, + (HTotal << 16) | HSyncLen); + Val = HActStart << 16; + Val |= HActEnd; + + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_DSP_HACT_ST_END + VPOffset, Val); + Val = VActStart << 16; + Val |= VActEnd; + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_DSP_VACT_ST_END + VPOffset, Val); + if (Mode->Flags & DRM_MODE_FLAG_INTERLACE) { + UINT16 VActStartF1 = VTotal + VActStart + 1; + UINT16 VActEndF1 = VActStartF1 + VDisplay; + + Val = VActStartF1 << 16 | VActEndF1; + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_DSP_VACT_ST_END_F1 + VPOffset, Val); + Val = VTotal << 16 | (VTotal + VSyncLen); + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_DSP_VS_ST_END_F1 + VPOffset, Val); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + INTERLACE_EN_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + DSP_FILED_POL, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + P2I_EN_SHIFT, 1, FALSE); + VTotal += VTotal + 1; + ActEnd = VActEndF1; + } + else { + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + INTERLACE_EN_SHIFT, 0, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + P2I_EN_SHIFT, 0, FALSE); + ActEnd = VActEnd; + } + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_DSP_VTOTAL_VS_END + VPOffset, + (VTotal << 16) | VSyncLen); + + if (Vop2->Version == VOP_VERSION_RK3568) { + if (Mode->Flags & DRM_MODE_FLAG_DBLCLK || + ConnectorState->OutputInterface & VOP_OUTPUT_IF_BT656) + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + CORE_DCLK_DIV_EN_SHIFT, 1, FALSE); + else + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + CORE_DCLK_DIV_EN_SHIFT, 0, FALSE); + } + + if (ConnectorState->OutputMode == ROCKCHIP_OUT_MODE_YUV420) + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_MIPI_CTRL + VPOffset, DCLK_DIV2_MASK, + DCLK_DIV2_SHIFT, 0x3, FALSE); + else + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_MIPI_CTRL + VPOffset, DCLK_DIV2_MASK, + DCLK_DIV2_SHIFT, 0x0, FALSE); + + if (YUVOverlay) + Val = 0x20010200; + else + Val = 0; + + Vop2Writel (Vop2->BaseAddress, RK3568_VP0_DSP_BG + VPOffset, 0); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + POST_DSP_OUT_R2Y_SHIFT, YUVOverlay, FALSE); + + Vop2TVConfigUpdate (DisplayState, Vop2); + Vop2PostConfig (DisplayState, Vop2); + + if (CrtcState->dsc_enable) { + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { + Vop2DscEnable(DisplayState, Vop2, 0, DclkRate * 1000LL); + Vop2DscEnable(DisplayState, Vop2, 1, DclkRate * 1000LL); + } else { + Vop2DscEnable(DisplayState, Vop2, CrtcState->dsc_id, DclkRate * 1000LL); + } + } + + Vop2SetClk (CrtcState->CrtcID, DclkRate * 1000); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_SYS_CTRL_LINE_FLAG0 + LineFlagOffset, LINE_FLAG_NUM_MASK, + RK3568_DSP_LINE_FLAG_NUM0_SHIFT, ActEnd, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_SYS_CTRL_LINE_FLAG0 + LineFlagOffset, LINE_FLAG_NUM_MASK, + RK3568_DSP_LINE_FLAG_NUM0_SHIFT, ActEnd, FALSE); + + return EFI_SUCCESS; +} + +INLINE +SCALE_MODE +GetSclMode ( + IN UINT32 Src, + IN UINT32 Dst + ) +{ + if (Src < Dst) + return SCALE_UP; + else if (Src > Dst) + return SCALE_DOWN; + + return SCALE_NONE; +} + +/* + * bli_sd_factor = (src - 1) / (dst - 1) << 12; + * avg_sd_factor: + * bli_su_factor: + * bic_su_factor: + * = (src - 1) / (dst - 1) << 16; + * + * gt2 enable: dst get one line from two line of the src + * gt4 enable: dst get one line from four line of the src. + * + */ +#define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) +#define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) + +#define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ + (fac * (dst - 1) >> 12 < (src - 1)) +#define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ + (fac * (dst - 1) >> 16 < (src - 1)) + +STATIC +UINT16 +Vop2ScaleFactor ( + IN SCALE_MODE Mode, + IN VOP2_SCALE_DOWN_MODE FilterMode, + IN UINT32 Src, + IN UINT32 Dst + ) +{ + UINT32 Factor = 0; + INT32 i = 0; + + if (Mode == SCALE_NONE) + return 0; + + if ((Mode == SCALE_DOWN) && (FilterMode == VOP2_SCALE_DOWN_BIL)) { + Factor = VOP2_BILI_SCL_DN(Src, Dst); + for (i = 0; i < 100; i++) { + if (VOP2_BILI_SCL_FAC_CHECK(Src, Dst, Factor)) + break; + Factor -= 1; + DEBUG ((DEBUG_INFO, "down fac cali: src:%d, dst:%d, fac:0x%x\n", Src, Dst, Factor)); + } + } else { + for (i = 0; i < 100; i++) { + if (VOP2_COMMON_SCL_FAC_CHECK(Src, Dst, Factor)) + break; + Factor -= 1; + DEBUG ((DEBUG_INFO, "up fac cali: src:%d, dst:%d, fac:0x%x\n", Src, Dst, Factor)); + } + } + + return Factor; +} + +STATIC +VOID +Vop2SetupScale ( + OUT VOP2 *Vop2, + OUT VOP2_WIN_DATA *WinData, + IN UINT32 SrcW, + IN UINT32 SrcH, + IN UINT32 DstW, + IN UINT32 DstH + ) +{ + UINT16 YrgbHorSclMode, YrgbVerSclMode; + UINT16 HsclFilterMode, VsclFilterMode; + UINT8 GT2 = 0, GT4 =0; + UINT32 XFac = 0, YFac = 0; + VOP2_SCALE_UP_MODE HSUFilterMode = VOP2_SCALE_UP_BIC; + VOP2_SCALE_DOWN_MODE HSDFilterMode = VOP2_SCALE_DOWN_BIL; + VOP2_SCALE_UP_MODE VSUFilterMode = VOP2_SCALE_UP_BIL; + VOP2_SCALE_DOWN_MODE VSDFilterMode = VOP2_SCALE_DOWN_BIL; + UINT32 WinOffset = WinData->RegOffset; + + if (SrcH > (4 * DstH)) + GT4 = 1; + else if (SrcH >= (2 * DstH)) + GT2 = 1; + + if (GT4) + SrcH >>= 2; + else if (GT2) + SrcH >>= 1; + + YrgbHorSclMode = GetSclMode(SrcW, DstW); + YrgbVerSclMode = GetSclMode(SrcH, DstH); + + if (YrgbHorSclMode == SCALE_UP) + HsclFilterMode = HSUFilterMode; + else + HsclFilterMode = HSDFilterMode; + + if (YrgbVerSclMode == SCALE_UP) + VsclFilterMode = VSUFilterMode; + else + VsclFilterMode = VSDFilterMode; + + /* + * RK3568 VOP Esmart/Smart DstW should be even pixel + * at scale down mode + */ + if ((YrgbHorSclMode == SCALE_DOWN) && (DstW & 0x1)) { + DEBUG ((DEBUG_INFO, "win dst_w[%d] should align as 2 pixel\n", DstW)); + DstW += 1; + } + + XFac = Vop2ScaleFactor (YrgbHorSclMode, HsclFilterMode, SrcW, DstW); + YFac = Vop2ScaleFactor (YrgbVerSclMode, VsclFilterMode, SrcH, DstH); + + if (WinData->Type == CLUSTER_LAYER) { + Vop2Writel (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + WinOffset, YFac << 16 | XFac); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_CTRL1 + WinOffset, YRGB_GT2_MASK, + CLUSTER_YRGB_GT2_SHIFT, GT2, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_CTRL1 + WinOffset, YRGB_GT4_MASK, + CLUSTER_YRGB_GT4_SHIFT, GT4, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_CTRL1 + WinOffset, YRGB_XSCL_MODE_MASK, + CLUSTER_YRGB_XSCL_MODE_SHIFT, YrgbHorSclMode, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_CTRL1 + WinOffset, YRGB_YSCL_MODE_MASK, + CLUSTER_YRGB_YSCL_MODE_SHIFT, YrgbVerSclMode, FALSE); + } else { + Vop2Writel (Vop2->BaseAddress, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + WinOffset, YFac << 16 | XFac); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_REGION0_CTRL + WinOffset, YRGB_GT2_MASK, + YRGB_GT2_SHIFT, GT2, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_REGION0_CTRL + WinOffset, YRGB_GT4_MASK, + YRGB_GT4_SHIFT, GT4, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_REGION0_SCL_CTRL + WinOffset, YRGB_XSCL_MODE_MASK, + YRGB_XSCL_MODE_SHIFT, YrgbHorSclMode, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_REGION0_SCL_CTRL + WinOffset, YRGB_YSCL_MODE_MASK, + YRGB_YSCL_MODE_SHIFT, YrgbVerSclMode, FALSE); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_REGION0_SCL_CTRL + WinOffset, YRGB_XSCL_FILTER_MODE_MASK, + YRGB_XSCL_FILTER_MODE_SHIFT, HsclFilterMode, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_REGION0_SCL_CTRL + WinOffset, YRGB_YSCL_FILTER_MODE_MASK, + YRGB_YSCL_FILTER_MODE_SHIFT, VsclFilterMode, FALSE); + } +} + +STATIC +VOID +Vop2SetClusterWin ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2_WIN_DATA *WinData + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + DRM_DISPLAY_MODE *Mode = &ConnectorState->DisplayMode; + VOP2 *Vop2 = CrtcState->Private; + INT32 SrcW = CrtcState->SrcW; + INT32 SrcH = CrtcState->SrcH; + INT32 CrtcW = CrtcState->CrtcW; + INT32 CrtcH = CrtcState->CrtcH; + INT32 CrtcX = CrtcState->CrtcX; + INT32 CrtcY = CrtcState->CrtcY; + INT32 XVirtual = CrtcState->XVirtual; + INT32 YMirror = 0; + INT32 CSCMode; + UINT32 ActInfo, DspInfo, DspSt, DspStx, DspSty; + UINT32 WinOffset = WinData->RegOffset; + UINT32 CfgDone = CFG_DONE_EN | BIT(CrtcState->CrtcID) | (BIT(CrtcState->CrtcID) << 16); + + ActInfo = (SrcH - 1) << 16; + ActInfo |= (SrcW - 1) & 0xffff; + + DspInfo = (CrtcH - 1) << 16; + DspInfo |= (CrtcW - 1) & 0xffff; + + DspStx = CrtcX; + DspSty = CrtcY; + DspSt = DspSty << 16 | (DspStx & 0xffff); + + if (Mode->Flags & DRM_MODE_FLAG_YMIRROR) + YMirror = 1; + else + YMirror = 0; + + Vop2SetupScale(Vop2, WinData, SrcW, SrcH, CrtcW, CrtcH); + + if (YMirror) + DEBUG ((DEBUG_WARN, "WARN: y mirror is unsupported by cluster window\n")); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_CTRL0 + WinOffset, WIN_FORMAT_MASK, + WIN_FORMAT_SHIFT, CrtcState->Format, FALSE); + Vop2Writel (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_VIR + WinOffset, XVirtual); + Vop2Writel (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_YRGB_MST + WinOffset, CrtcState->DMAAddress); + + Vop2Writel (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_ACT_INFO + WinOffset, ActInfo); + Vop2Writel (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_DSP_INFO + WinOffset, DspInfo); + Vop2Writel (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_DSP_ST + WinOffset, DspSt); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_CTRL0 + WinOffset, EN_MASK, + WIN_EN_SHIFT, 1, FALSE); + + CSCMode = Vop2ConvertCSCMode(ConnectorState->ColorSpace); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_CTRL0 + WinOffset, EN_MASK, + CLUSTER_RGB2YUV_EN_SHIFT, IsYUVOutput(ConnectorState->BusFormat), FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_WIN0_CTRL0 + WinOffset, CSC_MODE_MASK, + CLUSTER_CSC_MODE_SHIFT, CSCMode, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_CLUSTER0_CTRL + WinOffset, EN_MASK, + CLUSTER_EN_SHIFT, 1, FALSE); + + Vop2Writel (Vop2->BaseAddress, RK3568_REG_CFG_DONE, CfgDone); +} + +STATIC +VOID +Vop2SetSmartWin ( + OUT DISPLAY_STATE *DisplayState, + OUT VOP2_WIN_DATA *WinData + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + DRM_DISPLAY_MODE *Mode = &ConnectorState->DisplayMode; + VOP2 *Vop2 = CrtcState->Private; + INT32 SrcW = CrtcState->SrcW; + INT32 SrcH = CrtcState->SrcH; + INT32 CrtcW = CrtcState->CrtcW; + INT32 CrtcH = CrtcState->CrtcH; + INT32 CrtcX = CrtcState->CrtcX; + INT32 CrtcY = CrtcState->CrtcY; + INT32 XVirtual = CrtcState->XVirtual; + INT32 YMirror = 0; + INT32 CSCMode; + UINT32 ActInfo, DspInfo, DspSt, DspStx, DspSty; + UINT32 WinOffset = WinData->RegOffset; + UINT32 CfgDone = CFG_DONE_EN | BIT(CrtcState->CrtcID) | (BIT(CrtcState->CrtcID) << 16); + + /* + * This is workaround solution for IC design: + * esmart can't support scale down when actual_w % 16 == 1. + */ + if (SrcW > CrtcW && (SrcW & 0xf) == 1) { + DEBUG ((DEBUG_WARN, "WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", CrtcState->CrtcID, SrcW)); + SrcW -= 1; + } + + ActInfo = (SrcH - 1) << 16; + ActInfo |= (SrcW - 1) & 0xffff; + + DspInfo = (CrtcH - 1) << 16; + DspInfo |= (CrtcW - 1) & 0xffff; + + DspStx = CrtcX; + DspSty = CrtcY; + DspSt = DspSty << 16 | (DspStx & 0xffff); + + if (Mode->Flags & DRM_MODE_FLAG_YMIRROR) + YMirror = 1; + else + YMirror = 0; + + Vop2SetupScale(Vop2, WinData, SrcW, SrcH, CrtcW, CrtcH); + + if (YMirror) + CrtcState->DMAAddress += (SrcH - 1) * XVirtual * 4; + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_CTRL1 + WinOffset, EN_MASK, + YMIRROR_EN_SHIFT, YMirror, FALSE); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_REGION0_CTRL + WinOffset, WIN_FORMAT_MASK, + WIN_FORMAT_SHIFT, CrtcState->Format, FALSE); + Vop2Writel (Vop2->BaseAddress, RK3568_ESMART0_REGION0_VIR + WinOffset, XVirtual); + Vop2Writel (Vop2->BaseAddress, RK3568_ESMART0_REGION0_YRGB_MST + WinOffset, CrtcState->DMAAddress); + + Vop2Writel (Vop2->BaseAddress, RK3568_ESMART0_REGION0_ACT_INFO + WinOffset, ActInfo); + Vop2Writel (Vop2->BaseAddress, RK3568_ESMART0_REGION0_DSP_INFO + WinOffset, DspInfo); + Vop2Writel (Vop2->BaseAddress, RK3568_ESMART0_REGION0_DSP_ST + WinOffset, DspSt); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_REGION0_CTRL + WinOffset, EN_MASK, + WIN_EN_SHIFT, 1, FALSE); + + CSCMode = Vop2ConvertCSCMode(ConnectorState->ColorSpace); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_CTRL0 + WinOffset, EN_MASK, + RGB2YUV_EN_SHIFT, IsYUVOutput(ConnectorState->BusFormat), FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3568_ESMART0_CTRL0 + WinOffset, CSC_MODE_MASK, + CSC_MODE_SHIFT, CSCMode, FALSE); + + Vop2Writel (Vop2->BaseAddress, RK3568_REG_CFG_DONE, CfgDone); +} + +EFI_STATUS +Vop2SetPlane ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + VOP2 *Vop2 = CrtcState->Private; + VOP2_WIN_DATA *WinData; + UINT8 PrimaryPlaneID = Vop2->VpPlaneMask[CrtcState->CrtcID].PrimaryPlaneId; + + if (CrtcState->CrtcW > CrtcState->MaxOutput.Width) { + DEBUG ((DEBUG_ERROR, "ERROR: output w[%d] exceeded max width[%d]\n", + CrtcState->CrtcW, CrtcState->MaxOutput.Width)); + return -EFI_INVALID_PARAMETER; + } + + WinData = Vop2FindWinByPhysID (Vop2, PrimaryPlaneID); + if (!WinData) { + DEBUG ((DEBUG_ERROR, "invalid win id %d\n", PrimaryPlaneID)); + return -EFI_INVALID_PARAMETER; + } + + if (WinData->Type == CLUSTER_LAYER) + Vop2SetClusterWin (DisplayState, WinData); + else + Vop2SetSmartWin (DisplayState, WinData); + + DEBUG ((DEBUG_INFO, "VOP VP%d enable %a[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", + CrtcState->CrtcID, GetPlaneName(PrimaryPlaneID), + CrtcState->SrcW, CrtcState->SrcH, CrtcState->CrtcW, CrtcState->CrtcH, + CrtcState->CrtcX, CrtcState->CrtcY, CrtcState->Format, + CrtcState->DMAAddress)); + + return EFI_SUCCESS; +} + +STATIC +VOID +Vop2DscCfgDone ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + VOP2 *Vop2 = CrtcState->Private; + UINT8 dsc_id = CrtcState->dsc_id; + UINT32 ctrl_regs_offset = (dsc_id * 0x30); + + if (ConnectorState->OutputFlags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_CFG_DONE, EN_MASK, + DSC_CFG_DONE_SHIFT, 1, FALSE); + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, + DSC_CFG_DONE_SHIFT, 1, FALSE); + } else { + Vop2MaskWrite (Vop2->BaseAddress, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, + DSC_CFG_DONE_SHIFT, 1, FALSE); + } +} + +EFI_STATUS +Vop2Enable ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + VOP2 *Vop2 = CrtcState->Private; + UINT32 VPOffset = CrtcState->CrtcID * 0x100; + UINT32 CfgDone = CFG_DONE_EN | BIT(CrtcState->CrtcID) | (BIT(CrtcState->CrtcID) << 16); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + STANDBY_EN_SHIFT, 0, FALSE); + Vop2Writel (Vop2->BaseAddress, RK3568_REG_CFG_DONE, CfgDone); + + if (CrtcState->dsc_enable) { + Vop2DscCfgDone(This, DisplayState); + } + +#ifdef DEBUG_DUMP_REG + Vop2DumpRegisters (DisplayState, Vop2FindWinByPhysID (Vop2, Vop2->VpPlaneMask[CrtcState->CrtcID].PrimaryPlaneId)); +#endif + + return EFI_SUCCESS; +} + +EFI_STATUS +Vop2Disable ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CRTC_STATE *CrtcState = &DisplayState->CrtcState; + VOP2 *Vop2 = CrtcState->Private; + UINT32 VPOffset = CrtcState->CrtcID * 0x100; + UINT32 CfgDone = CFG_DONE_EN | BIT(CrtcState->CrtcID) | (BIT(CrtcState->CrtcID) << 16); + + Vop2MaskWrite (Vop2->BaseAddress, RK3568_VP0_DSP_CTRL + VPOffset, EN_MASK, + STANDBY_EN_SHIFT, 1, FALSE); + Vop2Writel (Vop2->BaseAddress, RK3568_REG_CFG_DONE, CfgDone); + + return EFI_SUCCESS; +} + +STATIC ROCKCHIP_CRTC_PROTOCOL mVop2 = { + &mVop2RK3588, + Vop2PreInit, + Vop2Init, + NULL, + Vop2SetPlane, + NULL, + Vop2Enable, + Vop2Disable, + NULL, + { + }, + {}, + FALSE, + FALSE, + FALSE +}; + +EFI_STATUS +Vop2DxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + Handle = NULL; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gRockchipCrtcProtocolGuid, + &mVop2, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.h new file mode 100644 index 0000000..92b1375 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.h @@ -0,0 +1,230 @@ +/** @file + Vop2 DXE Driver, install RK_CRTC_PROTOCOL. + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef __VOP2_H__ +#define __VOP2_H__ + +#include + +/* + * major: IP major vertion, used for IP structure + * minor: big feature change under same structure + */ +#define VOP_VERSION(major, minor) ((major) << 8 | (minor)) +#define VOP_MAJOR(version) ((version) >> 8) +#define VOP_MINOR(version) ((version) & 0xFF) + +#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15) +#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17) + +/* + * display output interface supported by rockchip lcdc + */ +#define ROCKCHIP_OUT_MODE_P888 0 +#define ROCKCHIP_OUT_MODE_BT1120 0 +#define ROCKCHIP_OUT_MODE_P666 1 +#define ROCKCHIP_OUT_MODE_P565 2 +#define ROCKCHIP_OUT_MODE_BT656 5 +#define ROCKCHIP_OUT_MODE_S888 8 +#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 +#define ROCKCHIP_OUT_MODE_YUV420 14 +/* for use special outface */ +#define ROCKCHIP_OUT_MODE_AAAA 15 + +#define VOP_OUTPUT_IF_RGB BIT(0) +#define VOP_OUTPUT_IF_BT1120 BIT(1) +#define VOP_OUTPUT_IF_BT656 BIT(2) +#define VOP_OUTPUT_IF_LVDS0 BIT(3) +#define VOP_OUTPUT_IF_LVDS1 BIT(4) +#define VOP_OUTPUT_IF_MIPI0 BIT(5) +#define VOP_OUTPUT_IF_MIPI1 BIT(6) +#define VOP_OUTPUT_IF_eDP0 BIT(7) +#define VOP_OUTPUT_IF_eDP1 BIT(8) +#define VOP_OUTPUT_IF_DP0 BIT(9) +#define VOP_OUTPUT_IF_DP1 BIT(10) +#define VOP_OUTPUT_IF_HDMI0 BIT(11) +#define VOP_OUTPUT_IF_HDMI1 BIT(12) + +#define VOP_OUTPUT_IF_NUMS 13 + +#define VOP2_LAYER_MAX 8 + +#define VOP_FEATURE_OUTPUT_10BIT BIT(0) + +/* KHz */ +#define VOP2_MAX_DCLK_RATE 600000 + +/* + * vop2 dsc id + */ +#define ROCKCHIP_VOP2_DSC_8K 0 +#define ROCKCHIP_VOP2_DSC_4K 1 + +/* + * vop2 internal power domain id, + * should be all none zero, 0 will be + * treat as invalid; + */ +#define VOP2_PD_CLUSTER0 BIT(0) +#define VOP2_PD_CLUSTER1 BIT(1) +#define VOP2_PD_CLUSTER2 BIT(2) +#define VOP2_PD_CLUSTER3 BIT(3) +#define VOP2_PD_DSC_8K BIT(5) +#define VOP2_PD_DSC_4K BIT(6) +#define VOP2_PD_ESMART BIT(7) + +typedef enum { + CSC_BT601L, + CSC_BT709L, + CSC_BT601F, + CSC_BT2020, +} VOP2_CSC_FORMAT; + +typedef enum { + HSYNC_POSITIVE = 0, + VSYNC_POSITIVE = 1, + DEN_NEGATIVE = 2, + DCLK_INVERT = 3 +} VOP2_POL; + +typedef enum { + BCSH_OUT_MODE_BLACK, + BCSH_OUT_MODE_BLUE, + BCSH_OUT_MODE_COLOR_BAR, + BCSH_OUT_MODE_NORMAL_VIDEO, +} VOP2_BCSH_OUT_MODE; + +typedef enum { + VOP2_VP0, + VOP2_VP1, + VOP2_VP2, + VOP2_VP3, + VOP2_VP_MAX, +} VOP2_VIDEO_PORTS_ID; + +typedef enum { + ROCKCHIP_VOP2_CLUSTER0 = 0, + ROCKCHIP_VOP2_CLUSTER1, + ROCKCHIP_VOP2_ESMART0, + ROCKCHIP_VOP2_ESMART1, + ROCKCHIP_VOP2_SMART0, + ROCKCHIP_VOP2_SMART1, + ROCKCHIP_VOP2_CLUSTER2, + ROCKCHIP_VOP2_CLUSTER3, + ROCKCHIP_VOP2_ESMART2, + ROCKCHIP_VOP2_ESMART3, + ROCKCHIP_VOP2_LAYER_MAX, +} VOP2_LAYER_PHY_ID; + +typedef enum { + CLUSTER_LAYER = 0, + ESMART_LAYER = 1, + SMART_LAYER = 2, +} VOP2_LAYER_TYPE; + +typedef enum { + VOP2_SCALE_UP_NRST_NBOR, + VOP2_SCALE_UP_BIL, + VOP2_SCALE_UP_BIC, +} VOP2_SCALE_UP_MODE; + +typedef enum { + VOP2_SCALE_DOWN_NRST_NBOR, + VOP2_SCALE_DOWN_BIL, + VOP2_SCALE_DOWN_AVG, +} VOP2_SCALE_DOWN_MODE; + +typedef enum { + SCALE_NONE = 0x0, + SCALE_UP = 0x1, + SCALE_DOWN = 0x2, +} SCALE_MODE; + +typedef enum { + VOP_DSC_IF_DISABLE = 0, + VOP_DSC_IF_HDMI = 1, + VOP_DSC_IF_MIPI_DS_MODE = 2, + VOP_DSC_IF_MIPI_VIDEO_MODE = 3, +} VOP2_DSC_INTERFACE_MODE; + +typedef struct VOP2_POWER_DOMAIN_DATA { + CHAR8 PdEnShift; + CHAR8 PdStatusShift; + CHAR8 PmuStatusShift; + CHAR8 BisrEnStatusShift; + struct VOP2_POWER_DOMAIN_DATA *ParentPdData; +} VOP2_POWER_DOMAIN_DATA; + +typedef struct { + VOP2_LAYER_TYPE Type; + CHAR8 *Name; + UINT8 PhysID; + UINT8 WinSelPortOffset; + UINT8 LayerSelWinID; + UINT32 RegOffset; + VOP2_POWER_DOMAIN_DATA *PdData; +} VOP2_WIN_DATA; + +typedef struct { + UINT32 Feature; + UINT32 MaxDclk; + UINT8 PreScanMaxDly; + VOP_RECT MaxOutput; +} VOP2_VP_DATA; + +typedef struct { + UINT8 PrimaryPlaneId; /* use this win to show logo */ + UINT8 AttachedLayersNr; /* number layers attach to this vp */ + UINT8 AttachedLayers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ + UINT32 PlaneMask; + INT32 CursorPlaneID; +} VOP2_VP_PLANE_MASK; + +typedef struct { + UINT8 id; + VOP2_POWER_DOMAIN_DATA *PdData; + UINT8 max_slice_num; + UINT8 max_linebuf_depth; /* used to generate the bitstream */ + UINT8 min_bits_per_pixel; /* bit num after encoder compress */ + const CHAR8 *dsc_txp_clk_src_name; + const CHAR8 *dsc_txp_clk_name; + const CHAR8 *dsc_pxl_clk_name; + const CHAR8 *dsc_cds_clk_name; +} VOP2_DSC_DATA; + +typedef struct { + UINT32 Version; + VOP2_VP_DATA *VpData; + VOP2_WIN_DATA *WinData; + /* + struct vop2_plane_table *plane_table; + */ + VOP2_VP_PLANE_MASK *PlaneMask; + + VOP2_DSC_DATA *DscData; + + UINT8 NrVps; + UINT8 NrLayers; + UINT8 NrMixers; + UINT8 NrGammas; + UINT8 NrDscs; + UINT32 RegLen; +} VOP2_DATA; + +typedef struct { + UINT32 BaseAddress; + UINTN SysPmu; + UINT32 Version; + BOOLEAN GlobalInit; + VOP2_DATA *Data; + VOP2_VP_PLANE_MASK VpPlaneMask[VOP2_VP_MAX]; +} VOP2; + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf new file mode 100644 index 0000000..b247971 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf @@ -0,0 +1,44 @@ +## @file +# The Vop2 driver file. +# +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = Vop2Dxe + FILE_GUID = 1cbb3666-99fe-11ec-9927-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = Vop2DxeInitialize + +[Sources] + Vop2Dxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + TimerLib + IoLib + DebugLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + RockchipDisplayLib + UefiDriverEntryPoint + CruLib + +[Protocols] + gRockchipCrtcProtocolGuid + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvCompactModules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvCompactModules.fdf.inc new file mode 100644 index 0000000..e6a95a6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvCompactModules.fdf.inc @@ -0,0 +1,9 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + INF ArmPlatformPkg/PrePi/PeiUniCore.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvMainAprioriDxe.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvMainAprioriDxe.fdf.inc new file mode 100644 index 0000000..1e5f9fd --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvMainAprioriDxe.fdf.inc @@ -0,0 +1,13 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +!if $(RK_STATUS_LED_ENABLE) == TRUE + INF Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.inf +!endif + + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvMainModules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvMainModules.fdf.inc new file mode 100644 index 0000000..6c0a264 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvMainModules.fdf.inc @@ -0,0 +1,229 @@ +## @file +# +# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +!if $(SECURE_BOOT_ENABLE) == TRUE +!include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!endif + INF SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf + INF SecurityPkg/Hash2DxeCrypto/Hash2DxeCrypto.inf + + # + # Status LED support + # +!if $(RK_STATUS_LED_ENABLE) == TRUE + INF Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.inf +!endif + + # + # Non-volatile FVB support + # + # RkFvbDxe does not have a hard dependency on NorFlashDxe to provide + # its services, but we want it to load earlier so the protocol can + # get installed by the time RkFvbDxe tries to locate it on initialization. + # +!if $(RK_NOR_FLASH_ENABLE) == TRUE + INF Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf +!endif + INF Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Arm GIC + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + # + # Timer + # + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # SCMI Support + # + INF ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf + + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + + # + # SMBIOS Support + # + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf + + # + # I2C Bus & Devices + # + INF MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf + INF Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf +!if $(RK_860X_REGULATOR_ENABLE) == TRUE + INF Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf +!endif +!if $(RK_RTC8563_ENABLE) == TRUE + INF Silicon/Rockchip/Drivers/Rtc8563PlatformDxe/Rtc8563PlatformDxe.inf +!endif +!if $(RK_PCA9555_ENABLE) == TRUE + INF Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.inf +!endif + # INF Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf + + # + # Display Support + # + INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf + # INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf +!if $(RK_DW_HDMI_QP_ENABLE) == TRUE + INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf +!endif + INF Silicon/Rockchip/Library/DisplayLib/DwDpLib.inf + INF Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.inf + INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf + + # + # USB Support + # + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf + + # USB controllers installer + INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf + + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf + + # + # PCI Support + # + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # + # SD/eMMC upper layer drivers + # +!if $(RK_SD_ENABLE) == TRUE || $(RK_EMMC_ENABLE) == TRUE + INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf +!endif + + # + # SD Support + # +!if $(RK_SD_ENABLE) == TRUE + INF Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.inf + INF Silicon/Rockchip/Drivers/RkSdmmcDxe/RkSdmmcDxe.inf +!endif + + # + # eMMC Support + # +!if $(RK_EMMC_ENABLE) == TRUE + INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + INF Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.inf +!endif + + # + # AHCI Support + # +!if $(RK_AHCI_ENABLE) == TRUE + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # RAM Disk Support + # + INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # + # UEFI Network Stack + # +!include NetworkPkg/Network.fdf.inc + +!if $(NETWORK_ENABLE) == TRUE + # + # Realtek PCIe UNDI Driver + # + INF Drivers/Realtek/Bus/Pcie/PcieNetworking/RtkUndiDxe.inf + + # + # Realtek USB UNDI Driver + # + INF Drivers/Realtek/Bus/Usb/UsbNetworking/RtkUsbUndiDxe.inf + + # + # AX88772 Ethernet Driver for Apple Ethernet Adapter + # + INF Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf +!endif + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf +!ifdef $(INCLUDE_TFTP_COMMAND) + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + # I2C Demo application + # INF Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf + + # SPI Flash Cmd application + # INF Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvRules.fdf.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvRules.fdf.inc new file mode 100644 index 0000000..e15b127 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/FvRules.fdf.inc @@ -0,0 +1,139 @@ +#/** @file +# +# Copyright (c) 2021, Rockchip Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.BINARY] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = Auto |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.FMP_IMAGE_DESC] + FILE PEIM = $(NAMED_GUID) { + RAW BIN |.acpi + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/AcpiNextLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/AcpiNextLib.h new file mode 100644 index 0000000..ea2aa34 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/AcpiNextLib.h @@ -0,0 +1,98 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + + + +#ifndef __ACPI_NEXT_LIB_H__ +#define __ACPI_NEXT_LIB_H__ + +#include + +/// +/// ITS Affinity Structure Definition +/// +#pragma pack(1) +typedef struct { + UINT8 Type; + UINT8 Length; + UINT32 ProximityDomain; + UINT16 Reserved; + UINT32 ItsHwId; +} EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE; +#pragma pack() + +#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ + { \ + EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD\ + } + +#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( \ + GicRBase, GicRlength) \ + { \ + EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicRBase, GicRlength \ + } + +#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ + { \ + 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \ + ACPIProcessorUID, Flags, ClockDomain \ + } + +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, ItsId) \ + { \ + 4, sizeof (EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE), ProximityDomain, \ + EFI_ACPI_RESERVED_WORD, ItsId \ + } + +#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \ + ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \ + { \ + 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \ + AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \ + EFI_ACPI_RESERVED_QWORD \ + } + +#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \ + GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \ + { \ + EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \ + GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \ + } + +#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \ + { \ + EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ + GicDistHwId, GicDistBase, GicDistVector, GicVersion, \ + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \ + } + + +#pragma pack(1) +// +// Define the number of each table type. +// This is where the table layout is modified. +// +#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT (MAX_SOCKET*CORE_NUM_PER_SOCKET) + +typedef struct { + EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; + EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]; + EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT]; + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT]; +} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE; + +#pragma pack() +#endif + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/AnalogixDpLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/AnalogixDpLib.h new file mode 100644 index 0000000..6ae5ea3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/AnalogixDpLib.h @@ -0,0 +1,1032 @@ +/** @file LcdHwLib.h + + This file contains interface functions for LcdHwLib of ArmPlatformPkg + + Copyright (c) 2017, ARM Ltd. All rights reserved.
    + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __ANALOGIXDP_H__ +#define __ANALOGIXDP_H__ + +#include +#include +#include +#include +#include +#include + +#define REG_DUMP 0 + +#define EREMOTEIO 121 /* Remote I/O error */ +#define EINVAL 22 /* Invalid argument */ +#define ETIMEDOUT 110 /* Connection timed out */ + +#define ANALOGIX_DP0_REG_BASE 0xFDEC0000 +#define ANALOGIX_DP1_REG_BASE 0xFDED0000 + +#define ANALOGIX_DP_TX_SW_RESET 0x14 +#define ANALOGIX_DP_FUNC_EN_1 0x18 +#define ANALOGIX_DP_FUNC_EN_2 0x1C +#define ANALOGIX_DP_VIDEO_CTL_1 0x20 +#define ANALOGIX_DP_VIDEO_CTL_2 0x24 +#define ANALOGIX_DP_VIDEO_CTL_3 0x28 + +#define ANALOGIX_DP_VIDEO_CTL_8 0x3C +#define ANALOGIX_DP_VIDEO_CTL_10 0x44 + +#define ANALOGIX_DP_TOTAL_LINE_CFG_L 0x48 +#define ANALOGIX_DP_TOTAL_LINE_CFG_H 0x4C +#define ANALOGIX_DP_ACTIVE_LINE_CFG_L 0x50 +#define ANALOGIX_DP_ACTIVE_LINE_CFG_H 0x54 +#define ANALOGIX_DP_V_F_PORCH_CFG 0x58 +#define ANALOGIX_DP_V_SYNC_WIDTH_CFG 0x5C +#define ANALOGIX_DP_V_B_PORCH_CFG 0x60 +#define ANALOGIX_DP_TOTAL_PIXEL_CFG_L 0x64 +#define ANALOGIX_DP_TOTAL_PIXEL_CFG_H 0x68 +#define ANALOGIX_DP_ACTIVE_PIXEL_CFG_L 0x6C +#define ANALOGIX_DP_ACTIVE_PIXEL_CFG_H 0x70 +#define ANALOGIX_DP_H_F_PORCH_CFG_L 0x74 +#define ANALOGIX_DP_H_F_PORCH_CFG_H 0x78 +#define ANALOGIX_DP_H_SYNC_CFG_L 0x7C +#define ANALOGIX_DP_H_SYNC_CFG_H 0x80 +#define ANALOGIX_DP_H_B_PORCH_CFG_L 0x84 +#define ANALOGIX_DP_H_B_PORCH_CFG_H 0x88 + +#define ANALOGIX_DP_PLL_REG_1 0xfc +#define ANALOGIX_DP_PLL_REG_2 0x9e4 +#define ANALOGIX_DP_PLL_REG_3 0x9e8 +#define ANALOGIX_DP_PLL_REG_4 0x9ec +#define ANALOGIX_DP_PLL_REG_5 0xa00 + +#define ANALOGIX_DP_BIAS 0x124 +#define ANALOGIX_DP_PD 0x12c + +#define ANALOGIX_DP_LANE_MAP 0x35C + +#define ANALOGIX_DP_ANALOG_CTL_1 0x370 +#define ANALOGIX_DP_ANALOG_CTL_2 0x374 +#define ANALOGIX_DP_ANALOG_CTL_3 0x378 +#define ANALOGIX_DP_PLL_FILTER_CTL_1 0x37C +#define ANALOGIX_DP_TX_AMP_TUNING_CTL 0x380 + +#define ANALOGIX_DP_AUX_HW_RETRY_CTL 0x390 + +#define ANALOGIX_DP_COMMON_INT_STA_1 0x3C4 +#define ANALOGIX_DP_COMMON_INT_STA_2 0x3C8 +#define ANALOGIX_DP_COMMON_INT_STA_3 0x3CC +#define ANALOGIX_DP_COMMON_INT_STA_4 0x3D0 + +#define ANALOGIX_DP_INT_STA 0x3DC +#define ANALOGIX_DP_COMMON_INT_MASK_1 0x3E0 +#define ANALOGIX_DP_COMMON_INT_MASK_2 0x3E4 +#define ANALOGIX_DP_COMMON_INT_MASK_3 0x3E8 +#define ANALOGIX_DP_COMMON_INT_MASK_4 0x3EC +#define ANALOGIX_DP_INT_STA_MASK 0x3F8 +#define ANALOGIX_DP_INT_CTL 0x3FC + +#define ANALOGIX_DP_SYS_CTL_1 0x600 +#define ANALOGIX_DP_SYS_CTL_2 0x604 +#define ANALOGIX_DP_SYS_CTL_3 0x608 +#define ANALOGIX_DP_SYS_CTL_4 0x60C + +#define ANALOGIX_DP_PKT_SEND_CTL 0x640 +#define ANALOGIX_DP_HDCP_CTL 0x648 + +#define ANALOGIX_DP_LINK_BW_SET 0x680 +#define ANALOGIX_DP_LANE_COUNT_SET 0x684 +#define ANALOGIX_DP_TRAINING_PTN_SET 0x688 +#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL 0x68C +#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL 0x690 +#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL 0x694 +#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL 0x698 + +#define ANALOGIX_DP_DEBUG_CTL 0x6C0 +#define ANALOGIX_DP_HPD_DEGLITCH_L 0x6C4 +#define ANALOGIX_DP_HPD_DEGLITCH_H 0x6C8 +#define ANALOGIX_DP_LINK_DEBUG_CTL 0x6E0 + +#define ANALOGIX_DP_M_VID_0 0x700 +#define ANALOGIX_DP_M_VID_1 0x704 +#define ANALOGIX_DP_M_VID_2 0x708 +#define ANALOGIX_DP_N_VID_0 0x70C +#define ANALOGIX_DP_N_VID_1 0x710 +#define ANALOGIX_DP_N_VID_2 0x714 + +#define ANALOGIX_DP_PLL_CTL 0x71C +#define ANALOGIX_DP_PHY_PD 0x720 +#define ANALOGIX_DP_PHY_TEST 0x724 + +#define ANALOGIX_DP_VIDEO_FIFO_THRD 0x730 +#define ANALOGIX_DP_AUDIO_MARGIN 0x73C + +#define ANALOGIX_DP_M_VID_GEN_FILTER_TH 0x764 +#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH 0x778 +#define ANALOGIX_DP_AUX_CH_STA 0x780 +#define ANALOGIX_DP_AUX_CH_DEFER_CTL 0x788 +#define ANALOGIX_DP_AUX_RX_COMM 0x78C +#define ANALOGIX_DP_BUFFER_DATA_CTL 0x790 +#define ANALOGIX_DP_AUX_CH_CTL_1 0x794 +#define ANALOGIX_DP_AUX_ADDR_7_0 0x798 +#define ANALOGIX_DP_AUX_ADDR_15_8 0x79C +#define ANALOGIX_DP_AUX_ADDR_19_16 0x7A0 +#define ANALOGIX_DP_AUX_CH_CTL_2 0x7A4 + +#define ANALOGIX_DP_BUF_DATA_0 0x7C0 + +#define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 + +/* ANALOGIX_DP_TX_SW_RESET */ +#define RESET_DP_TX (0x1 << 0) + +/* ANALOGIX_DP_FUNC_EN_1 */ +#define MASTER_VID_FUNC_EN_N (0x1 << 7) +#define SLAVE_VID_FUNC_EN_N (0x1 << 5) +#define AUD_FIFO_FUNC_EN_N (0x1 << 4) +#define AUD_FUNC_EN_N (0x1 << 3) +#define HDCP_FUNC_EN_N (0x1 << 2) +#define CRC_FUNC_EN_N (0x1 << 1) +#define SW_FUNC_EN_N (0x1 << 0) + +/* ANALOGIX_DP_FUNC_EN_2 */ +#define SSC_FUNC_EN_N (0x1 << 7) +#define AUX_FUNC_EN_N (0x1 << 2) +#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) +#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) + +/* ANALOGIX_DP_VIDEO_CTL_1 */ +#define VIDEO_EN (0x1 << 7) +#define HDCP_VIDEO_MUTE (0x1 << 6) + +/* ANALOGIX_DP_VIDEO_CTL_1 */ +#define IN_D_RANGE_MASK (0x1 << 7) +#define IN_D_RANGE_SHIFT (7) +#define IN_D_RANGE_CEA (0x1 << 7) +#define IN_D_RANGE_VESA (0x0 << 7) +#define IN_BPC_MASK (0x7 << 4) +#define IN_BPC_SHIFT (4) +#define IN_BPC_12_BITS (0x3 << 4) +#define IN_BPC_10_BITS (0x2 << 4) +#define IN_BPC_8_BITS (0x1 << 4) +#define IN_BPC_6_BITS (0x0 << 4) +#define IN_COLOR_F_MASK (0x3 << 0) +#define IN_COLOR_F_SHIFT (0) +#define IN_COLOR_F_YCBCR444 (0x2 << 0) +#define IN_COLOR_F_YCBCR422 (0x1 << 0) +#define IN_COLOR_F_RGB (0x0 << 0) + +/* ANALOGIX_DP_VIDEO_CTL_3 */ +#define IN_YC_COEFFI_MASK (0x1 << 7) +#define IN_YC_COEFFI_SHIFT (7) +#define IN_YC_COEFFI_ITU709 (0x1 << 7) +#define IN_YC_COEFFI_ITU601 (0x0 << 7) +#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) +#define VID_CHK_UPDATE_TYPE_SHIFT (4) +#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) +#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) + +/* ANALOGIX_DP_VIDEO_CTL_8 */ +#define VID_HRES_TH(x) (((x) & 0xf) << 4) +#define VID_VRES_TH(x) (((x) & 0xf) << 0) + +/* ANALOGIX_DP_VIDEO_CTL_10 */ +#define FORMAT_SEL (0x1 << 4) +#define INTERACE_SCAN_CFG (0x1 << 2) +#define VSYNC_POLARITY_CFG (0x1 << 1) +#define HSYNC_POLARITY_CFG (0x1 << 0) + +/* ANALOGIX_DP_TOTAL_LINE_CFG_L */ +#define TOTAL_LINE_CFG_L(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_TOTAL_LINE_CFG_H */ +#define TOTAL_LINE_CFG_H(x) (((x) & 0xf) << 0) + +/* ANALOGIX_DP_ACTIVE_LINE_CFG_L */ +#define ACTIVE_LINE_CFG_L(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_ACTIVE_LINE_CFG_H */ +#define ACTIVE_LINE_CFG_H(x) (((x) & 0xf) << 0) + +/* ANALOGIX_DP_V_F_PORCH_CFG */ +#define V_F_PORCH_CFG(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_V_SYNC_WIDTH_CFG */ +#define V_SYNC_WIDTH_CFG(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_V_B_PORCH_CFG */ +#define V_B_PORCH_CFG(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_TOTAL_PIXEL_CFG_L */ +#define TOTAL_PIXEL_CFG_L(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_TOTAL_PIXEL_CFG_H */ +#define TOTAL_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) + +/* ANALOGIX_DP_ACTIVE_PIXEL_CFG_L */ +#define ACTIVE_PIXEL_CFG_L(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_ACTIVE_PIXEL_CFG_H */ +#define ACTIVE_PIXEL_CFG_H(x) (((x) & 0x3f) << 0) + +/* ANALOGIX_DP_H_F_PORCH_CFG_L */ +#define H_F_PORCH_CFG_L(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_H_F_PORCH_CFG_H */ +#define H_F_PORCH_CFG_H(x) (((x) & 0xf) << 0) + +/* ANALOGIX_DP_H_SYNC_CFG_L */ +#define H_SYNC_CFG_L(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_H_SYNC_CFG_H */ +#define H_SYNC_CFG_H(x) (((x) & 0xf) << 0) + +/* ANALOGIX_DP_H_B_PORCH_CFG_L */ +#define H_B_PORCH_CFG_L(x) (((x) & 0xff) << 0) + +/* ANALOGIX_DP_H_B_PORCH_CFG_H */ +#define H_B_PORCH_CFG_H(x) (((x) & 0xf) << 0) + +/* ANALOGIX_DP_PLL_REG_1 */ +#define REF_CLK_24M (0x1 << 0) +#define REF_CLK_27M (0x0 << 0) +#define REF_CLK_MASK (0x1 << 0) + +/* ANALOGIX_DP_LANE_MAP */ +#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) +#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) +#define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6) +#define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6) +#define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4) +#define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4) +#define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4) +#define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4) +#define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2) +#define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2) +#define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2) +#define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2) +#define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0) +#define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0) +#define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0) +#define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0) + +/* ANALOGIX_DP_ANALOG_CTL_1 */ +#define TX_TERMINAL_CTRL_50_OHM (0x1 << 4) + +/* ANALOGIX_DP_ANALOG_CTL_2 */ +#define SEL_24M (0x1 << 3) +#define TX_DVDD_BIT_1_0625V (0x4 << 0) + +/* ANALOGIX_DP_ANALOG_CTL_3 */ +#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) +#define VCO_BIT_600_MICRO (0x5 << 0) + +/* ANALOGIX_DP_PLL_FILTER_CTL_1 */ +#define PD_RING_OSC (0x1 << 6) +#define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4) +#define TX_CUR1_2X (0x1 << 2) +#define TX_CUR_16_MA (0x3 << 0) + +/* ANALOGIX_DP_TX_AMP_TUNING_CTL */ +#define CH3_AMP_400_MV (0x0 << 24) +#define CH2_AMP_400_MV (0x0 << 16) +#define CH1_AMP_400_MV (0x0 << 8) +#define CH0_AMP_400_MV (0x0 << 0) + +/* ANALOGIX_DP_AUX_HW_RETRY_CTL */ +#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) +#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) +#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) +#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) +#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) +#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) +#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) + +/* ANALOGIX_DP_COMMON_INT_STA_1 */ +#define VSYNC_DET (0x1 << 7) +#define PLL_LOCK_CHG (0x1 << 6) +#define SPDIF_ERR (0x1 << 5) +#define SPDIF_UNSTBL (0x1 << 4) +#define VID_FORMAT_CHG (0x1 << 3) +#define AUD_CLK_CHG (0x1 << 2) +#define VID_CLK_CHG (0x1 << 1) +#define SW_INT (0x1 << 0) + +/* ANALOGIX_DP_COMMON_INT_STA_2 */ +#define ENC_EN_CHG (0x1 << 6) +#define HW_BKSV_RDY (0x1 << 3) +#define HW_SHA_DONE (0x1 << 2) +#define HW_AUTH_STATE_CHG (0x1 << 1) +#define HW_AUTH_DONE (0x1 << 0) + +/* ANALOGIX_DP_COMMON_INT_STA_3 */ +#define AFIFO_UNDER (0x1 << 7) +#define AFIFO_OVER (0x1 << 6) +#define R0_CHK_FLAG (0x1 << 5) + +/* ANALOGIX_DP_COMMON_INT_STA_4 */ +#define PSR_ACTIVE (0x1 << 7) +#define PSR_INACTIVE (0x1 << 6) +#define SPDIF_BI_PHASE_ERR (0x1 << 5) +#define HOTPLUG_CHG (0x1 << 2) +#define HPD_LOST (0x1 << 1) +#define PLUG (0x1 << 0) + +/* ANALOGIX_DP_INT_STA */ +#define INT_HPD (0x1 << 6) +#define HW_TRAINING_FINISH (0x1 << 5) +#define RPLY_RECEIV (0x1 << 1) +#define AUX_ERR (0x1 << 0) + +/* ANALOGIX_DP_INT_CTL */ +#define SOFT_INT_CTRL (0x1 << 2) +#define INT_POL1 (0x1 << 1) +#define INT_POL0 (0x1 << 0) + +/* ANALOGIX_DP_SYS_CTL_1 */ +#define DET_STA (0x1 << 2) +#define FORCE_DET (0x1 << 1) +#define DET_CTRL (0x1 << 0) + +/* ANALOGIX_DP_SYS_CTL_2 */ +#define CHA_CRI(x) (((x) & 0xf) << 4) +#define CHA_STA (0x1 << 2) +#define FORCE_CHA (0x1 << 1) +#define CHA_CTRL (0x1 << 0) + +/* ANALOGIX_DP_SYS_CTL_3 */ +#define HPD_STATUS (0x1 << 6) +#define F_HPD (0x1 << 5) +#define HPD_CTRL (0x1 << 4) +#define HDCP_RDY (0x1 << 3) +#define STRM_VALID (0x1 << 2) +#define F_VALID (0x1 << 1) +#define VALID_CTRL (0x1 << 0) + +/* ANALOGIX_DP_SYS_CTL_4 */ +#define FIX_M_AUD (0x1 << 4) +#define ENHANCED (0x1 << 3) +#define FIX_M_VID (0x1 << 2) +#define M_VID_UPDATE_CTRL (0x3 << 0) + +/* ANALOGIX_DP_TRAINING_PTN_SET */ +#define SCRAMBLER_TYPE (0x1 << 9) +#define HW_LINK_TRAINING_PATTERN (0x1 << 8) +#define SCRAMBLING_DISABLE (0x1 << 5) +#define SCRAMBLING_ENABLE (0x0 << 5) +#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) +#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) +#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) +#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) +#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) +#define SW_TRAINING_PATTERN_SET_PTN3 (0x3 << 0) +#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) +#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) +#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) + +/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */ +#define PRE_EMPHASIS_SET_MASK (0x3 << 3) +#define PRE_EMPHASIS_SET_SHIFT (3) + +/* ANALOGIX_DP_DEBUG_CTL */ +#define PLL_LOCK (0x1 << 4) +#define F_PLL_LOCK (0x1 << 3) +#define PLL_LOCK_CTRL (0x1 << 2) +#define PN_INV (0x1 << 0) + +/* ANALOGIX_DP_PLL_CTL */ +#define DP_PLL_PD (0x1 << 7) +#define DP_PLL_RESET (0x1 << 6) +#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) +#define DP_PLL_REF_BIT_1_1250V (0x5 << 0) +#define DP_PLL_REF_BIT_1_2500V (0x7 << 0) + +/* ANALOGIX_DP_PHY_PD */ +#define DP_PHY_PD (0x1 << 5) +#define AUX_PD (0x1 << 4) +#define CH3_PD (0x1 << 3) +#define CH2_PD (0x1 << 2) +#define CH1_PD (0x1 << 1) +#define CH0_PD (0x1 << 0) + +/* ANALOGIX_DP_PHY_TEST */ +#define MACRO_RST (0x1 << 5) +#define CH1_TEST (0x1 << 1) +#define CH0_TEST (0x1 << 0) + +/* ANALOGIX_DP_AUX_CH_STA */ +#define AUX_BUSY (0x1 << 4) +#define AUX_STATUS_MASK (0xf << 0) + +/* ANALOGIX_DP_AUX_CH_DEFER_CTL */ +#define DEFER_CTRL_EN (0x1 << 7) +#define DEFER_COUNT(x) (((x) & 0x7f) << 0) + +/* ANALOGIX_DP_AUX_RX_COMM */ +#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) +#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) + +/* ANALOGIX_DP_BUFFER_DATA_CTL */ +#define BUF_CLR (0x1 << 7) +#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) + +/* ANALOGIX_DP_AUX_CH_CTL_1 */ +#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) +#define AUX_TX_COMM_MASK (0xf << 0) +#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) +#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) +#define AUX_TX_COMM_MOT (0x1 << 2) +#define AUX_TX_COMM_WRITE (0x0 << 0) +#define AUX_TX_COMM_READ (0x1 << 0) + +/* ANALOGIX_DP_AUX_ADDR_7_0 */ +#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) + +/* ANALOGIX_DP_AUX_ADDR_15_8 */ +#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) + +/* ANALOGIX_DP_AUX_ADDR_19_16 */ +#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) + +/* ANALOGIX_DP_AUX_CH_CTL_2 */ +#define ADDR_ONLY (0x1 << 1) +#define AUX_EN (0x1 << 0) + +/* ANALOGIX_DP_SOC_GENERAL_CTL */ +#define AUDIO_MODE_SPDIF_MODE (0x1 << 8) +#define AUDIO_MODE_MASTER_MODE (0x0 << 8) +#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) +#define VIDEO_MASTER_CLK_SEL (0x1 << 2) +#define VIDEO_MASTER_MODE_EN (0x1 << 1) +#define VIDEO_MODE_MASK (0x1 << 0) +#define VIDEO_MODE_SLAVE_MODE (0x1 << 0) +#define VIDEO_MODE_MASTER_MODE (0x0 << 0) + +#define DP_TIMEOUT_LOOP_COUNT 100 +#define MAX_CR_LOOP 5 +#define MAX_EQ_LOOP 5 + +/* I2C EDID Chip ID, Slave Address */ +#define I2C_EDID_DEVICE_ADDR 0x50 +#define I2C_E_EDID_DEVICE_ADDR 0x30 + +#define EDID_BLOCK_LENGTH 0x80 +#define EDID_HEADER_PATTERN 0x00 +#define EDID_EXTENSION_FLAG 0x7e +#define EDID_CHECKSUM 0x7f + +/* DP_MAX_LANE_COUNT */ +#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) +#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) + +/* DP_LANE_COUNT_SET */ +#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) + +/* DP_TRAINING_LANE0_SET */ +#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) +#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) +#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) +#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) + +/* HDPTXPHy_GRF*/ +#define HDPTXPHY0_GRF_BASE 0xFD5E0000 +#define HDPTXPHY1_GRF_BASE 0xFD5E4000 +#define HDPTXPHY_GRF_CON0 0x00 +#define HDPTXPHY_GRF_CON1 0x04 +#define HDPTXPHY_GRF_STATUS0 0x80 +#define PCS_BIASES 0x27c +#define O_PLL_LOCK 0x280 +#define O_PLL_LOCK_done (0x1<<3) +#define O_PHY_RDY ((0x1<<1)&(0x1<<3)) + +/* ENABLE_BIASES */ +#define ENABLE_BIASES_LANE6 (0x1<<6) +#define ENABLE_BIASES_LANE7 (0x1<<7) + +/* INITIAL POR RESET*/ +#define INITIAL_POR_RESET_LANE2 (0x1<<2) +#define INITIAL_POR_RESET_LANE3 (0x1<<3) + +/* DRM_DP_HELPER */ +#define DP_RECEIVER_CAP_SIZE 0xf +#define EDP_PSR_RECEIVER_CAP_SIZE 2 +#define EDP_DISPLAY_CTL_CAP_SIZE 3 + +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ +# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */ +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ + +#define DP_SET_POWER 0x600 +# define DP_SET_POWER_D0 0x1 +# define DP_SET_POWER_D3 0x2 +# define DP_SET_POWER_MASK 0x3 +# define DP_SET_POWER_D3_AUX_ON 0x5 + +#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ +# define DP_EDP_11 0x00 +# define DP_EDP_12 0x01 +# define DP_EDP_13 0x02 +# define DP_EDP_14 0x03 + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) + +# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) + +# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) + +#define DP_TEST_REQUEST 0x218 +# define DP_TEST_LINK_TRAINING (1 << 0) +# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) +# define DP_TEST_LINK_EDID_READ (1 << 2) +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ + +#define DP_ADJUST_REQUEST_LANE0_1 0x206 +#define DP_TEST_RESPONSE 0x260 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_TEST_EDID_CHECKSUM 0x261 + +/* AUX CH addresses */ +/* DPCD */ +#define DP_DPCD_REV 0x000 +# define DP_DPCD_REV_10 0x10 +# define DP_DPCD_REV_11 0x11 +# define DP_DPCD_REV_12 0x12 +# define DP_DPCD_REV_13 0x13 +# define DP_DPCD_REV_14 0x14 + +#define EDP0TX_PHY_BASE 0xFED60000 +#define EDP1TX_PHY_BASE 0xFED70000 + +#define DP_MAX_LANE_COUNT 0x002 +# define DP_MAX_LANE_COUNT_MASK 0x1f +# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ +# define DP_ENHANCED_FRAME_CAP (1 << 7) +#define DP_INC_BG (0x1 << 7) +#define DP_EXP_BG (0x1 << 6) +#define RK_AUX_PD (0x1 << 5) +#define AUX_PD (0x1 << 4) +#define RK_PLL_PD (0x1 << 4) +#define CH3_PD (0x1 << 3) +#define CH2_PD (0x1 << 2) +#define CH1_PD (0x1 << 1) +#define CH0_PD (0x1 << 0) + +enum LinkLaneCountType { + LANE_COUNT1 = 1, + LANE_COUNT2 = 2, + LANE_COUNT4 = 4 +}; + +enum LinkTrainingState { + START, + CLOCK_RECOVERY, + EQUALIZER_TRAINING, + FINISHED, + FAILED +}; + +enum VoltageSwingLevel { + VOLTAGE_LEVEL_0, + VOLTAGE_LEVEL_1, + VOLTAGE_LEVEL_2, + VOLTAGE_LEVEL_3, +}; + +enum PreEmphasisLevel { + PRE_EMPHASIS_LEVEL_0, + PRE_EMPHASIS_LEVEL_1, + PRE_EMPHASIS_LEVEL_2, + PRE_EMPHASIS_LEVEL_3, +}; + +enum PatternSet { + PRBS7, + D10_2, + TRAINING_PTN1, + TRAINING_PTN2, + TRAINING_PTN3, + DP_NONE +}; + +enum ColorSpace { + COLOR_RGB, + COLOR_YCBCR422, + COLOR_YCBCR444 +}; + +enum ColorDepth { + COLOR_6, + COLOR_8, + COLOR_10, + COLOR_12 +}; + +enum ColorCoefficient { + COLOR_YCBCR601, + COLOR_YCBCR709 +}; + +enum DynamicRange { + VESA, + CEA +}; + +enum PllStatus { + PLL_UNLOCKED, + PLL_LOCKED +}; + +enum ClockRecoveryMValueType { + CALCULATED_M, + REGISTER_M +}; + +enum VideoTimingRecognitionType { + VIDEO_TIMING_FROM_CAPTURE, + VIDEO_TIMING_FROM_REGISTER +}; + +enum AnalogPowerBlock { + AUX_BLOCK, + CH0_BLOCK, + CH1_BLOCK, + CH2_BLOCK, + CH3_BLOCK, + ANALOG_TOTAL, + POWER_ALL +}; + +struct VideoInfo { + char *Name; + + BOOLEAN HSyncPolarity; + BOOLEAN VSyncPolarity; + BOOLEAN Interlaced; + + enum ColorSpace ColorSpace; + enum DynamicRange DynamicRange; + enum ColorCoefficient Ycbcr_Coeff; + enum ColorDepth ColorDepth; + + UINTN MaxLinkRate; + enum LinkLaneCountType MaxLaneCount; +}; + +struct LinkTrain { + INT32 EqLoop; + INT32 CrLoop[4]; + UINT8 LinkRate; + UINT8 LaneCount; + UINT8 TrainingLane[4]; + BOOLEAN SSC; + + enum LinkTrainingState LtState; +}; + +struct AnalogixDpDevice { + UINT32 Id; + BOOLEAN ForceHpd; + struct VideoInfo VideoInfo; + struct LinkTrain LinkTrain; + struct DrmDisplayMode *MODE; + unsigned char EDID[EDID_BLOCK_LENGTH * 2]; + UINT8 Dpcd[DP_RECEIVER_CAP_SIZE]; + UINT8 Edid[EDID_BLOCK_LENGTH * 2]; + UINT32 LaneMap[4]; +}; + +/* Rockchip Htx Phy */ + +struct RockchipHdptxPhy { + UINT32 Id; + UINT32 LANE_POLARITY_INVERT[4]; +}; + +struct PhyConfigureOptsDp { + UINTN LINKRATE; + UINTN LANES; + UINTN VOLTAGE[4]; + UINTN PRE[4]; + UINT8 SSC : 1; + UINT8 SETRATE : 1; + UINT8 SETLANES : 1; + UINT8 SETVOLTAGES : 1; +}; + +/* AnalogixDpReg.c */ +VOID +AnalogixDpRegWrite ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 Offset, + IN UINT32 Value + ); + +UINT32 +AnalogixDpRegRead ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 Offset + ); + +VOID +AnalogixDpEnableVideoMute ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ); + +VOID +AnalogixDpLaneSwap ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ); + +VOID +AnalogixDpStopVideo ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpReset ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpSwreset ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpInitAnalogParam ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpInitInterrupt ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpEnableSwFunction ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpConfigInterrupt ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpSetPllPowerDown ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ); + +VOID +AnalogixDpInitHpd ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpClearHotplugInterrupts ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpInitAux ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpResetAux ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpInitAnalogFunc ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpSetAnalogPowerDown ( + OUT struct AnalogixDpDevice *Dp, + enum AnalogPowerBlock Block, + BOOLEAN Enable + ); + +BOOLEAN +AnalogixDpTps3Supported ( + OUT struct AnalogixDpDevice *Dp + ); + +INT32 +AnalogixDpReadByteFromDpcd ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 RegAddr, + IN UINT8 *Data + ); + +INT32 +AnalogixDpWriteByteToDpcd ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 RegAddr, + IN UINT8 Data + ); + +INT32 +AnalogixDpStartAuxTransaction ( + OUT struct AnalogixDpDevice *Dp + ); + +INT32 +AnalogixDpReadBytesFromDpcd ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 RegAddr, + IN UINT32 Count, + IN UINT8 Data[] + ); + +INT32 +AnalogixDpWriteBytesToDpcd ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 RegAddr, + IN UINT32 Count, + IN UINT8 Data[] + ); + +VOID +AnalogixDpSetTrainingPattern ( + OUT struct AnalogixDpDevice *Dp, + OUT enum PatternSet Pattern + ); + +UINT32 +AnalogixDpGetLaneLinkTraining ( + OUT struct AnalogixDpDevice *Dp, + IN UINT8 Lane + ); + +VOID +AnalogixDpGetLinkBandwidth ( + OUT struct AnalogixDpDevice *Dp, + UINT32 *BwType + ); + +VOID +AnalogixDpGetLaneCount ( + OUT struct AnalogixDpDevice *Dp, + UINT32 *Count + ); + +VOID +AnalogixDpEnableVideoMaster ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ); + +VOID +AnalogixDpStartVideo ( + OUT struct AnalogixDpDevice *Dp + ); + +INTN AnalogixDpIsVideoStreamOn ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpEnableScrambling ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpDisableScrambling ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +AnalogixDpSetVideoFormat ( + OUT struct AnalogixDpDevice *Dp, + OUT CONST DRM_DISPLAY_MODE *Mode + ); + +INTN +AnalogixDpSelectI2cDevice ( + OUT struct AnalogixDpDevice *Dp, + UINTN DeviceAddr, + UINTN RegAddr + ); + +INTN +AnalogixDpReadByteFromI2c ( + struct AnalogixDpDevice *dp, + UINTN DeviceAddr, + UINTN RegAddr, + UINTN *DATA + ); + +INTN +AnalogixDpReadBytesFromI2c ( + OUT struct AnalogixDpDevice *Dp, + UINTN DeviceAddr, + UINTN RegAddr, + UINTN Count, + UINT8 Edid[] + ); + +VOID +AnalogixDpSetLaneLinkTraining ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +RockchipHdptxPhyInit ( + OUT struct RockchipHdptxPhy *Hdptx + ); + +INTN +RockchipHdptxPhySetRate ( + OUT struct RockchipHdptxPhy *Hdptx, + OUT struct PhyConfigureOptsDp *Dp + ); + +INTN +RockchipHdptxPhySetVoltages ( + OUT struct RockchipHdptxPhy *Hdptx, + OUT struct PhyConfigureOptsDp *Dp + ); + +INTN +RockchipHdptxPhyConfigure ( + OUT struct RockchipHdptxPhy *Hdptx, + OUT struct PhyConfigureOptsDp *Dp + ); + +INT32 +AnalogixDpIsSlaveVideoStreamClockOn ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +DumpDpRegisters ( + OUT struct AnalogixDpDevice *Dp + ); + +VOID +DumpHdptxPhyRegisters ( + OUT struct AnalogixDpDevice *Dp + ); + +EFI_STATUS +AnalogixDpConnectorPreInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +AnalogixDpConnectorInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +AnalogixDpConnectorGetEdid ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +AnalogixDpConnectorEnable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +AnalogixDpConnectorDisable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +AnalogixDpConnectorDetect ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/BaseVariableLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/BaseVariableLib.h new file mode 100644 index 0000000..7cfdf92 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/BaseVariableLib.h @@ -0,0 +1,90 @@ +/** @file + * + * Read-only non-volatile variable service library for early SEC phase. + * Based on FaultTolerantWritePei and VariablePei, without using any HOBs. + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
    + * Copyright (c) Microsoft Corporation.
    + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __BASE_VARIABLE_LIB_H__ +#define __BASE_VARIABLE_LIB_H__ + +#include + +/** + This service retrieves a variable's value using its name and GUID. + + Read the specified variable from the UEFI variable store. If the Data + buffer is too small to hold the contents of the variable, the error + EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the required buffer + size to obtain the data. + + @param VariableName A pointer to a null-terminated string that is the variable's name. + @param VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of + VariableGuid and VariableName must be unique. + @param Attributes If non-NULL, on return, points to the variable's attributes. + @param DataSize On entry, points to the size in bytes of the Data buffer. + On return, points to the size of the data returned in Data. + @param Data Points to the buffer which will hold the returned variable value. + May be NULL with a zero DataSize in order to determine the size of the buffer needed. + + @retval EFI_SUCCESS The variable was read successfully. + @retval EFI_NOT_FOUND The variable was not found. + @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data. + DataSize is updated with the size required for + the specified variable. + @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL. + @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error. + +**/ +EFI_STATUS +EFIAPI +BaseGetVariable ( + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VariableGuid, + OUT UINT32 *Attributes, + IN OUT UINTN *DataSize, + OUT VOID *Data OPTIONAL + ); + +/** + Return the next variable name and GUID. + + This function is called multiple times to retrieve the VariableName + and VariableGuid of all variables currently available in the system. + On each call, the previous results are passed into the interface, + and, on return, the interface returns the data for the next + interface. When the entire variable list has been returned, + EFI_NOT_FOUND is returned. + + @param VariableNameSize On entry, points to the size of the buffer pointed to by VariableName. + @param VariableName On entry, a pointer to a null-terminated string that is the variable's name. + On return, points to the next variable's null-terminated name string. + + @param VariableGuid On entry, a pointer to an UEFI _GUID that is the variable's GUID. + On return, a pointer to the next variable's GUID. + + @retval EFI_SUCCESS The variable was read successfully. + @retval EFI_NOT_FOUND The variable could not be found. + @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the resulting + data. VariableNameSize is updated with the size + required for the specified variable. + @retval EFI_INVALID_PARAMETER VariableName, VariableGuid or + VariableNameSize is NULL. + @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error. + +**/ +EFI_STATUS +EFIAPI +BaseGetNextVariableName ( + IN OUT UINTN *VariableNameSize, + IN OUT CHAR16 *VariableName, + IN OUT EFI_GUID *VariableGuid + ); + +#endif // __BASE_VARIABLE_LIB_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/CruLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/CruLib.h new file mode 100644 index 0000000..606cfe3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/CruLib.h @@ -0,0 +1,304 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +#ifndef _HAL_CRU_H_ +#define _HAL_CRU_H_ + +#include "HalDef.h" + +/*************************** MACRO Definition ****************************/ +/** @defgroup CRU_Exported_Definition_Group1 Basic Definition + * @{ + */ + +#define MHZ 1000000 +#define KHZ 1000 + +#ifndef PLL_INPUT_OSC_RATE +#define PLL_INPUT_OSC_RATE (24 * MHZ) +#endif + +#define CRU_CON_REG_ADDRESS(_regBase, _offset, _index) \ + ((_regBase) + (_offset) + ((_index) * sizeof(uint32_t))) + +#define CLK_RESET_GET_REG_OFFSET(x) ((uint32_t)((x) / 16)) +#define CLK_RESET_GET_BITS_SHIFT(x) ((uint32_t)((x) % 16)) + +#define CLK_GATE_GET_REG_OFFSET(x) ((uint32_t)((x) / 16)) +#define CLK_GATE_GET_BITS_SHIFT(x) ((uint32_t)((x) % 16)) + +#define WIDTH_TO_MASK(width) ((1 << (width)) - 1) + +#define CLK_MUX_REG_OFFSET_SHIFT 0U +#define CLK_MUX_REG_OFFSET_MASK 0x0000FFFFU +#define CLK_MUX_SHIFT_SHIFT 16U +#define CLK_MUX_SHIFT_MASK 0x00FF0000U +#define CLK_MUX_WIDTH_SHIFT 24U +#define CLK_MUX_WIDTH_MASK 0xFF000000U + +#define CLK_MUX_GET_REG_OFFSET(x) \ + (((uint32_t)(x) & CLK_MUX_REG_OFFSET_MASK) >> CLK_MUX_REG_OFFSET_SHIFT) +#define CLK_MUX_GET_BITS_SHIFT(x) \ + (((uint32_t)(x) & CLK_MUX_SHIFT_MASK) >> CLK_MUX_SHIFT_SHIFT) +#define CLK_MUX_GET_MASK(x) \ + WIDTH_TO_MASK((((uint32_t)(x) & CLK_MUX_WIDTH_MASK) >> CLK_MUX_WIDTH_SHIFT)) \ + << CLK_MUX_GET_BITS_SHIFT(x) + +#define CLK_DIV_REG_OFFSET_SHIFT 0U +#define CLK_DIV_REG_OFFSET_MASK 0x0000FFFFU +#define CLK_DIV_SHIFT_SHIFT 16U +#define CLK_DIV_SHIFT_MASK 0x00FF0000U +#define CLK_DIV_WIDTH_SHIFT 24U +#define CLK_DIV_WIDTH_MASK 0xFF000000U + +#define CLK_DIV_GET_REG_OFFSET(x) \ + (((uint32_t)(x) & CLK_DIV_REG_OFFSET_MASK) >> CLK_DIV_REG_OFFSET_SHIFT) +#define CLK_DIV_GET_BITS_SHIFT(x) \ + (((uint32_t)(x) & CLK_DIV_SHIFT_MASK) >> CLK_DIV_SHIFT_SHIFT) +#define CLK_DIV_GET_MASK(x) \ + WIDTH_TO_MASK((((uint32_t)(x) & CLK_DIV_WIDTH_MASK) >> CLK_DIV_WIDTH_SHIFT)) \ + << CLK_DIV_GET_BITS_SHIFT(x) + +#define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, \ + _frac) \ + { \ + .rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1, \ + .refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd, \ + .frac = _frac, \ + } + +#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ + { \ + .rate = _rate##U, .p = _p, .m = _m, \ + .s = _s, .k = _k, \ + } + +struct PLL_CONFIG { + uint32_t rate; + uint32_t fbDiv; + uint32_t postDiv1; + uint32_t refDiv; + uint32_t postDiv2; + uint32_t dsmpd; + uint32_t frac; + uint32_t m; + uint32_t p; + uint32_t s; + uint32_t k; +}; + +struct PLL_SETUP { + __IO uint32_t *conOffset0; + __IO uint32_t *conOffset1; + __IO uint32_t *conOffset2; + __IO uint32_t *conOffset3; + __IO uint32_t *conOffset6; + __IO uint32_t *modeOffset; + __I uint32_t *stat0; + uint32_t modeShift; + uint32_t lockShift; + uint32_t modeMask; + const struct PLL_CONFIG *rateTable; +}; + +typedef enum { + GLB_SRST_FST = 0xfdb9, + GLB_SRST_SND = 0xeca8, +} eCRU_GlbSrstType; + +typedef enum { + GLB_RST_FST_WDT0 = 0U, + GLB_RST_SND_WDT0, + GLB_RST_FST_WDT1, + GLB_RST_SND_WDT1, + GLB_RST_FST_WDT2, + GLB_RST_SND_WDT2, +} eCRU_WdtRstType; + +typedef enum { + CLOCK_SUPPORT_MUX = 1 << 0, + CLOCK_SUPPORT_DIV = 1 << 1, + CLOCK_SUPPORT_GATE = 1 << 2, + CLOCK_SUPPORT_ALL = 0xFFFFFFFF +} CRU_CLOCK_SUPPORT_FLAGS; + +#define CRU_CLOCK_INIT(_id, _regBase, _muxOffset, _mux, \ + _divOffset, _div, _gateOffset, _gate) \ + [_id] = { \ + .regBase = _regBase, \ + .flags = CLOCK_SUPPORT_ALL, \ + .muxOffset = _muxOffset, \ + .mux = _mux, \ + .divOffset = _divOffset, \ + .div = _div, \ + .gateOffset = _gateOffset, \ + .gate = _gate, \ + } + +#define CRU_CLOCK_NOMUX_INIT(_id, _regBase, \ + _divOffset, _div, _gateOffset, _gate) \ + [_id] = { \ + .regBase = _regBase, \ + .flags = CLOCK_SUPPORT_ALL & ~CLOCK_SUPPORT_MUX, \ + .divOffset = _divOffset, \ + .div = _div, \ + .gateOffset = _gateOffset, \ + .gate = _gate, \ + } + +#define CRU_CLOCK_NODIV_INIT(_id, _regBase, _muxOffset, _mux, \ + _gateOffset, _gate) \ + [_id] = { \ + .regBase = _regBase, \ + .flags = CLOCK_SUPPORT_ALL & ~CLOCK_SUPPORT_DIV, \ + .muxOffset = _muxOffset, \ + .mux = _mux, \ + .gateOffset = _gateOffset, \ + .gate = _gate, \ + } + +#define CRU_CLOCK_NOGATE_INIT(_id, _regBase, _muxOffset, _mux, \ + _divOffset, _div) \ + [_id] = { \ + .regBase = _regBase, \ + .flags = CLOCK_SUPPORT_ALL & ~CLOCK_SUPPORT_GATE, \ + .muxOffset = _muxOffset, \ + .mux = _mux, \ + .divOffset = _divOffset, \ + .div = _div, \ + } + +#define CRU_CLOCK_MUX_INIT(_id, _regBase, _muxOffset, _mux) \ + [_id] = { \ + .regBase = _regBase, \ + .flags = CLOCK_SUPPORT_MUX, \ + .muxOffset = _muxOffset, \ + .mux = _mux, \ + } + +#define CRU_CLOCK_DIV_INIT(_id, _regBase, _divOffset, _div) \ + [_id] = { \ + .regBase = _regBase, \ + .flags = CLOCK_SUPPORT_DIV, \ + .divOffset = _divOffset, \ + .div = _div, \ + } + +#define CRU_CLOCK_GATE_INIT(_id, _regBase, _gateOffset, _gate) \ + [_id] = { \ + .regBase = _regBase, \ + .flags = CLOCK_SUPPORT_GATE, \ + .gateOffset = _gateOffset, \ + .gate = _gate, \ + } + +#define CRU_RESET_INIT(id, _regBase, _srstOffset, _srst) \ + [_id] = { \ + .regBase = _regBase, \ + .srstOffset = _srstOffset, \ + .srst = _srst, \ + } + +/***************************** Structure Definition **************************/ + +typedef struct { + uint64_t regBase; + CRU_CLOCK_SUPPORT_FLAGS flags; + uint32_t muxOffset; + uint32_t mux; + uint32_t divOffset; + uint32_t div; + uint32_t gateOffset; + uint32_t gate; +} CRU_CLOCK; + +typedef struct { + uint64_t regBase; + uint32_t srstOffset; + uint32_t srst; +} CRU_RESET; + +/** @} */ +/***************************** Function Declare ******************************/ +/** @defgroup CRU_Public_Function_Declare Public Function Declare + * @{ + */ + +CRU_CLOCK * HAL_CRU_ClkGetById(uint32_t clockId); +CRU_RESET * HAL_CRU_RstGetById(uint32_t resetId); + +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup); +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate); +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup); +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup); + +uint32_t HAL_CRU_GetPllV1Freq(struct PLL_SETUP *pSetup); +HAL_Status HAL_CRU_SetPllV1Freq(struct PLL_SETUP *pSetup, uint32_t rate); + +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clockId); +HAL_Status HAL_CRU_ClkEnable(uint32_t clockId); +HAL_Status HAL_CRU_ClkDisable(uint32_t clockId); + +HAL_Status HAL_CRU_ClkSetDiv(uint32_t clockId, uint32_t divValue); +uint32_t HAL_CRU_ClkGetDiv(uint32_t clockId); + +HAL_Status HAL_CRU_ClkSetMux(uint32_t clockId, uint32_t muxValue); +uint32_t HAL_CRU_ClkGetMux(uint32_t clockId); + +HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator); + +uint32_t HAL_CRU_ClkGetFreq(uint32_t clockId); +HAL_Status HAL_CRU_ClkSetFreq(uint32_t clockId, uint32_t rate); + +HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId); +HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId); + +HAL_Status HAL_CRU_ClkNp5BestDiv(uint32_t clockId, uint32_t rate, uint32_t pRate, uint32_t *bestdiv); + +HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type); + +HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType); + +HAL_Status HAL_CRU_PllCompensation(uint32_t clockId, int ppm); + +HAL_Check HAL_CRU_RstIsAsserted(uint32_t resetId); +HAL_Status HAL_CRU_RstAssert(uint32_t resetId); +HAL_Status HAL_CRU_RstDeassert(uint32_t resetId); + +#ifdef HAL_CRU_AS_FEATURE_ENABLED +/** + * @brief it is for AS init. + */ +void HAL_CRU_AsInit(void); + +/** + * @brief it is for AS enable. + * @param ch: channel + * @param en: 1 is enable, 0 is disable. + */ +void HAL_CRU_AsEnable(uint8_t ch, uint8_t en); +#endif + +/** @} */ + +#endif + +/** @} */ + +/** @} */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DrmModes.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DrmModes.h new file mode 100644 index 0000000..88a8247 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DrmModes.h @@ -0,0 +1,161 @@ +/** @file + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _DRM_MODES_H +#define _DRM_MODES_H + +#define DRM_DISPLAY_INFO_LEN 32 +#define DRM_CONNECTOR_NAME_LEN 32 +#define DRM_DISPLAY_MODE_LEN 32 +#define DRM_PROP_NAME_LEN 32 + +#define DRM_MODE_TYPE_BUILTIN (1<<0) +#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) +#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) +#define DRM_MODE_TYPE_PREFERRED (1<<3) +#define DRM_MODE_TYPE_DEFAULT (1<<4) +#define DRM_MODE_TYPE_USERDEF (1<<5) +#define DRM_MODE_TYPE_DRIVER (1<<6) + +/* Video mode flags */ +/* bit compatible with the xorg definitions. */ +#define DRM_MODE_FLAG_PHSYNC (1 << 0) +#define DRM_MODE_FLAG_NHSYNC (1 << 1) +#define DRM_MODE_FLAG_PVSYNC (1 << 2) +#define DRM_MODE_FLAG_NVSYNC (1 << 3) +#define DRM_MODE_FLAG_INTERLACE (1 << 4) +#define DRM_MODE_FLAG_DBLSCAN (1 << 5) +#define DRM_MODE_FLAG_CSYNC (1 << 6) +#define DRM_MODE_FLAG_PCSYNC (1 << 7) +#define DRM_MODE_FLAG_NCSYNC (1 << 8) +#define DRM_MODE_FLAG_HSKEW (1 << 9) /* hskew provided */ +#define DRM_MODE_FLAG_BCAST (1 << 10) +#define DRM_MODE_FLAG_PIXMUX (1 << 11) +#define DRM_MODE_FLAG_DBLCLK (1 << 12) +#define DRM_MODE_FLAG_CLKDIV2 (1 << 13) +#define DRM_MODE_FLAG_PPIXDATA BIT(31) + +/* Panel Mirror control */ +#define DRM_MODE_FLAG_XMIRROR (1<<28) +#define DRM_MODE_FLAG_YMIRROR (1<<29) +#define DRM_MODE_FLAG_XYMIRROR (DRM_MODE_FLAG_XMIRROR | DRM_MODE_FLAG_YMIRROR) + +/* Picture aspect ratio options */ +#define DRM_MODE_PICTURE_ASPECT_NONE 0 +#define DRM_MODE_PICTURE_ASPECT_4_3 1 +#define DRM_MODE_PICTURE_ASPECT_16_9 2 +#define DRM_MODE_PICTURE_ASPECT_64_27 3 +#define DRM_MODE_PICTURE_ASPECT_256_135 4 + +/* Aspect ratio flag bitmask (4 bits 22:19) */ +#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19) +#define DRM_MODE_FLAG_PIC_AR_NONE \ + (DRM_MODE_PICTURE_ASPECT_NONE << 19) +#define DRM_MODE_FLAG_PIC_AR_4_3 \ + (DRM_MODE_PICTURE_ASPECT_4_3 << 19) +#define DRM_MODE_FLAG_PIC_AR_16_9 \ + (DRM_MODE_PICTURE_ASPECT_16_9 << 19) +#define DRM_MODE_FLAG_PIC_AR_64_27 \ + (DRM_MODE_PICTURE_ASPECT_64_27 << 19) +#define DRM_MODE_FLAG_PIC_AR_256_135 \ + (DRM_MODE_PICTURE_ASPECT_256_135 << 19) + +#define DRM_MODE_CONNECTOR_Unknown 0 +#define DRM_MODE_CONNECTOR_VGA 1 +#define DRM_MODE_CONNECTOR_DVII 2 +#define DRM_MODE_CONNECTOR_DVID 3 +#define DRM_MODE_CONNECTOR_DVIA 4 +#define DRM_MODE_CONNECTOR_Composite 5 +#define DRM_MODE_CONNECTOR_SVIDEO 6 +#define DRM_MODE_CONNECTOR_LVDS 7 +#define DRM_MODE_CONNECTOR_Component 8 +#define DRM_MODE_CONNECTOR_9PinDIN 9 +#define DRM_MODE_CONNECTOR_DisplayPort 10 +#define DRM_MODE_CONNECTOR_HDMIA 11 +#define DRM_MODE_CONNECTOR_HDMIB 12 +#define DRM_MODE_CONNECTOR_TV 13 +#define DRM_MODE_CONNECTOR_eDP 14 +#define DRM_MODE_CONNECTOR_VIRTUA 15 +#define DRM_MODE_CONNECTOR_DSI 16 +#define DRM_MODE_CONNECTOR_DPI 17 + +#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) +#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) +#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) +#define DRM_EDID_PT_STEREO (1 << 5) +#define DRM_EDID_PT_INTERLACED (1 << 7) + + /* see also http://vektor.theorem.ca/graphics/ycbcr/ */ + enum v4l2_colorspace { + /* + * Default colorspace, i.e. let the driver figure it out. + * Can only be used with video capture. + */ + V4L2_COLORSPACE_DEFAULT = 0, + + /* SMPTE 170M: used for broadcast NTSC/PAL SDTV */ + V4L2_COLORSPACE_SMPTE170M = 1, + + /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */ + V4L2_COLORSPACE_SMPTE240M = 2, + + /* Rec.709: used for HDTV */ + V4L2_COLORSPACE_REC709 = 3, + + /* + * Deprecated, do not use. No driver will ever return this. This was + * based on a misunderstanding of the bt878 datasheet. + */ + V4L2_COLORSPACE_BT878 = 4, + + /* + * NTSC 1953 colorspace. This only makes sense when dealing with + * really, really old NTSC recordings. Superseded by SMPTE 170M. + */ + V4L2_COLORSPACE_470_SYSTEM_M = 5, + + /* + * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when + * dealing with really old PAL/SECAM recordings. Superseded by + * SMPTE 170M. + */ + V4L2_COLORSPACE_470_SYSTEM_BG = 6, + + /* + * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601 + * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG. + */ + V4L2_COLORSPACE_JPEG = 7, + + /* For RGB colorspaces such as produces by most webcams. */ + V4L2_COLORSPACE_SRGB = 8, + + /* AdobeRGB colorspace */ + V4L2_COLORSPACE_ADOBERGB = 9, + + /* BT.2020 colorspace, used for UHDTV. */ + V4L2_COLORSPACE_BT2020 = 10, + + /* Raw colorspace: for RAW unprocessed images */ + V4L2_COLORSPACE_RAW = 11, + + /* DCI-P3 colorspace, used by cinema projectors */ + V4L2_COLORSPACE_DCI_P3 = 12, + }; + +#define CRTC_INTERLACE_HALVE_V (1 << 0) /* halve V values for interlacing */ +#define CRTC_STEREO_DOUBLE (1 << 1) /* adjust timings for stereo modes */ +#define CRTC_NO_DBLSCAN (1 << 2) /* don't adjust doublescan */ +#define CRTC_NO_VSCAN (1 << 3) /* don't adjust doublescan */ +#define CRTC_STEREO_DOUBLE_ONLY (CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | \ + CRTC_NO_VSCAN) + +#define DRM_MODE_FLAG_3D_MAX DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DwHdmiQpLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DwHdmiQpLib.h new file mode 100644 index 0000000..c0127fd --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DwHdmiQpLib.h @@ -0,0 +1,1000 @@ +/** @file LcdHwLib.h + + This file contains interface functions for LcdHwLib of ArmPlatformPkg + + Copyright (c) 2017, ARM Ltd. All rights reserved.
    + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __DWHDMIQP_H__ +#define __DWHDMIQP_H__ + +#include +#include +#include +#include +#include +#include + +#define EREMOTEIO 121 /* Remote I/O error */ +#define EINVAL 22 /* Invalid argument */ +#define ETIMEDOUT 110 /* Connection timed out */ + +/* Main Unit Registers */ +#define CORE_ID 0x0 +#define VER_NUMBER 0x4 +#define VER_TYPE 0x8 +#define CONFIG_REG 0xc +#define CONFIG_CEC BIT(28) +#define CONFIG_AUD_UD BIT(23) +#define CORE_TIMESTAMP_HHMM 0x14 +#define CORE_TIMESTAMP_MMDD 0x18 +#define CORE_TIMESTAMP_YYYY 0x1c +/* Reset Manager Registers */ +#define GLOBAL_SWRESET_REQUEST 0x40 +#define EARCRX_CMDC_SWINIT_P BIT(27) +#define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) +#define AVP_DATAPATH_SWINIT_P BIT(6) +#define GLOBAL_SWDISABLE 0x44 +#define CEC_SWDISABLE BIT(17) +#define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) +#define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) +#define RESET_MANAGER_CONFIG0 0x48 +#define RESET_MANAGER_STATUS0 0x50 +#define RESET_MANAGER_STATUS1 0x54 +#define RESET_MANAGER_STATUS2 0x58 +/* Timer Base Registers */ +#define TIMER_BASE_CONFIG0 0x80 +#define TIMER_BASE_STATUS0 0x84 +/* CMU Registers */ +#define CMU_CONFIG0 0xa0 +#define CMU_CONFIG1 0xa4 +#define CMU_CONFIG2 0xa8 +#define CMU_CONFIG3 0xac +#define CMU_STATUS 0xb0 +#define EARC_BPCLK_OFF BIT(9) +#define AUDCLK_OFF BIT(7) +#define LINKQPCLK_OFF BIT(5) +#define VIDQPCLK_OFF BIT(3) +#define IPI_CLK_OFF BIT(1) +#define CMU_IPI_CLK_FREQ 0xb4 +#define CMU_VIDQPCLK_FREQ 0xb8 +#define CMU_LINKQPCLK_FREQ 0xbc +#define CMU_AUDQPCLK_FREQ 0xc0 +#define CMU_EARC_BPCLK_FREQ 0xc4 +/* I2CM Registers */ +#define I2CM_SM_SCL_CONFIG0 0xe0 +#define I2CM_FM_SCL_CONFIG0 0xe4 +#define I2CM_CONFIG0 0xe8 +#define I2CM_CONTROL0 0xec +#define I2CM_STATUS0 0xf0 +#define I2CM_INTERFACE_CONTROL0 0xf4 +#define I2CM_ADDR 0xff000 +#define I2CM_SLVADDR 0xfe0 +#define I2CM_WR_MASK 0x1e +#define I2CM_EXT_READ BIT(4) +#define I2CM_SHORT_READ BIT(3) +#define I2CM_FM_READ BIT(2) +#define I2CM_FM_WRITE BIT(1) +#define I2CM_FM_EN BIT(0) +#define I2CM_INTERFACE_CONTROL1 0xf8 +#define I2CM_SEG_PTR 0x7f80 +#define I2CM_SEG_ADDR 0x7f +#define I2CM_INTERFACE_WRDATA_0_3 0xfc +#define I2CM_INTERFACE_WRDATA_4_7 0x100 +#define I2CM_INTERFACE_WRDATA_8_11 0x104 +#define I2CM_INTERFACE_WRDATA_12_15 0x108 +#define I2CM_INTERFACE_RDDATA_0_3 0x10c +#define I2CM_INTERFACE_RDDATA_4_7 0x110 +#define I2CM_INTERFACE_RDDATA_8_11 0x114 +#define I2CM_INTERFACE_RDDATA_12_15 0x118 +/* SCDC Registers */ +#define SCDC_CONFIG0 0x140 +#define SCDC_I2C_FM_EN BIT(12) +#define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) +#define SCDC_UPD_FLAGS_POLL_EN BIT(4) +#define SCDC_CONTROL0 0x148 +#define SCDC_STATUS0 0x150 +#define STATUS_UPDATE BIT(0) +#define FRL_START BIT(4) +#define FLT_UPDATE BIT(5) +/* FLT Registers */ +#define FLT_CONFIG0 0x160 +#define FLT_CONFIG1 0x164 +#define FLT_CONFIG2 0x168 +#define FLT_CONTROL0 0x170 +/* Main Unit 2 Registers */ +#define MAINUNIT_STATUS0 0x180 +/* Video Interface Registers */ +#define VIDEO_INTERFACE_CONFIG0 0x800 +#define VIDEO_INTERFACE_CONFIG1 0x804 +#define VIDEO_INTERFACE_CONFIG2 0x808 +#define VIDEO_INTERFACE_CONTROL0 0x80c +#define VIDEO_INTERFACE_STATUS0 0x814 +/* Video Packing Registers */ +#define VIDEO_PACKING_CONFIG0 0x81c +/* Audio Interface Registers */ +#define AUDIO_INTERFACE_CONFIG0 0x820 +#define AUD_IF_SEL_MSK 0x3 +#define AUD_IF_SPDIF 0x2 +#define AUD_IF_I2S 0x1 +#define AUD_IF_PAI 0x0 +#define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) +#define AUD_FIFO_INIT_ON_OVF_EN BIT(2) +#define I2S_LINES_EN_MSK GENMASK(7, 4) +#define I2S_LINES_EN(x) BIT((x) + 4) +#define I2S_BPCUV_RCV_MSK BIT(12) +#define I2S_BPCUV_RCV_EN BIT(12) +#define I2S_BPCUV_RCV_DIS 0 +#define SPDIF_LINES_EN GENMASK(19, 16) +#define AUD_FORMAT_MSK GENMASK(26, 24) +#define AUD_3DOBA (0x7 << 24) +#define AUD_3DASP (0x6 << 24) +#define AUD_MSOBA (0x5 << 24) +#define AUD_MSASP (0x4 << 24) +#define AUD_HBR (0x3 << 24) +#define AUD_DST (0x2 << 24) +#define AUD_OBA (0x1 << 24) +#define AUD_ASP (0x0 << 24) +#define AUDIO_INTERFACE_CONFIG1 0x824 +#define AUDIO_INTERFACE_CONTROL0 0x82c +#define AUDIO_FIFO_CLR_P BIT(0) +#define AUDIO_INTERFACE_STATUS0 0x834 +/* Frame Composer Registers */ +#define FRAME_COMPOSER_CONFIG0 0x840 +#define FRAME_COMPOSER_CONFIG1 0x844 +#define FRAME_COMPOSER_CONFIG2 0x848 +#define FRAME_COMPOSER_CONFIG3 0x84c +#define FRAME_COMPOSER_CONFIG4 0x850 +#define FRAME_COMPOSER_CONFIG5 0x854 +#define FRAME_COMPOSER_CONFIG6 0x858 +#define FRAME_COMPOSER_CONFIG7 0x85c +#define FRAME_COMPOSER_CONFIG8 0x860 +#define FRAME_COMPOSER_CONFIG9 0x864 +#define KEEPOUT_REKEY_CFG GENMASK(9, 8) +#define KEEPOUT_REKEY_ALWAYS (0x2 << 8) +#define FRAME_COMPOSER_CONTROL0 0x86c +/* Video Monitor Registers */ +#define VIDEO_MONITOR_CONFIG0 0x880 +#define VIDEO_MONITOR_STATUS0 0x884 +#define VIDEO_MONITOR_STATUS1 0x888 +#define VIDEO_MONITOR_STATUS2 0x88c +#define VIDEO_MONITOR_STATUS3 0x890 +#define VIDEO_MONITOR_STATUS4 0x894 +#define VIDEO_MONITOR_STATUS5 0x898 +#define VIDEO_MONITOR_STATUS6 0x89c +/* HDCP2 Logic Registers */ +#define HDCP2LOGIC_CONFIG0 0x8e0 +#define HDCP2_BYPASS BIT(0) +#define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 +#define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 +/* HDCP14 Registers */ +#define HDCP14_CONFIG0 0x900 +#define HDCP14_CONFIG1 0x904 +#define HDCP14_CONFIG2 0x908 +#define HDCP14_CONFIG3 0x90c +#define HDCP14_KEY_SEED 0x914 +#define HDCP14_KEY_H 0x918 +#define HDCP14_KEY_L 0x91c +#define HDCP14_KEY_STATUS 0x920 +#define HDCP14_AKSV_H 0x924 +#define HDCP14_AKSV_L 0x928 +#define HDCP14_AN_H 0x92c +#define HDCP14_AN_L 0x930 +#define HDCP14_STATUS0 0x934 +#define HDCP14_STATUS1 0x938 +/* Scrambler Registers */ +#define SCRAMB_CONFIG0 0x960 +/* Video Configuration Registers */ +#define LINK_CONFIG0 0x968 +#define OPMODE_FRL_4LANES BIT(8) +#define OPMODE_DVI BIT(4) +#define OPMODE_FRL BIT(0) +/* TMDS FIFO Registers */ +#define TMDS_FIFO_CONFIG0 0x970 +#define TMDS_FIFO_CONTROL0 0x974 +/* FRL RSFEC Registers */ +#define FRL_RSFEC_CONFIG0 0xa20 +#define FRL_RSFEC_STATUS0 0xa30 +/* FRL Packetizer Registers */ +#define FRL_PKTZ_CONFIG0 0xa40 +#define FRL_PKTZ_CONTROL0 0xa44 +#define FRL_PKTZ_CONTROL1 0xa50 +#define FRL_PKTZ_STATUS1 0xa54 +/* Packet Scheduler Registers */ +#define PKTSCHED_CONFIG0 0xa80 +#define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 +#define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 +#define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c +#define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 +#define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 +#define PKTSCHED_PKT_CONFIG0 0xa98 +#define PKTSCHED_PKT_CONFIG1 0xa9c +#define PKTSCHED_VSI_FIELDRATE BIT(14) +#define PKTSCHED_AVI_FIELDRATE BIT(12) +#define PKTSCHED_PKT_CONFIG2 0xaa0 +#define PKTSCHED_PKT_CONFIG3 0xaa4 +#define PKTSCHED_PKT_EN 0xaa8 +#define PKTSCHED_DRMI_TX_EN BIT(17) +#define PKTSCHED_AUDI_TX_EN BIT(15) +#define PKTSCHED_AVI_TX_EN BIT(13) +#define PKTSCHED_VSI_TX_EN BIT(12) +#define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) +#define PKTSCHED_AMD_TX_EN BIT(8) +#define PKTSCHED_GCP_TX_EN BIT(3) +#define PKTSCHED_AUDS_TX_EN BIT(2) +#define PKTSCHED_ACR_TX_EN BIT(1) +#define PKTSCHED_NULL_TX_EN BIT(0) +#define PKTSCHED_PKT_CONTROL0 0xaac +#define PKTSCHED_PKT_SEND 0xab0 +#define PKTSCHED_PKT_STATUS0 0xab4 +#define PKTSCHED_PKT_STATUS1 0xab8 +#define PKT_NULL_CONTENTS0 0xb00 +#define PKT_NULL_CONTENTS1 0xb04 +#define PKT_NULL_CONTENTS2 0xb08 +#define PKT_NULL_CONTENTS3 0xb0c +#define PKT_NULL_CONTENTS4 0xb10 +#define PKT_NULL_CONTENTS5 0xb14 +#define PKT_NULL_CONTENTS6 0xb18 +#define PKT_NULL_CONTENTS7 0xb1c +#define PKT_ACP_CONTENTS0 0xb20 +#define PKT_ACP_CONTENTS1 0xb24 +#define PKT_ACP_CONTENTS2 0xb28 +#define PKT_ACP_CONTENTS3 0xb2c +#define PKT_ACP_CONTENTS4 0xb30 +#define PKT_ACP_CONTENTS5 0xb34 +#define PKT_ACP_CONTENTS6 0xb38 +#define PKT_ACP_CONTENTS7 0xb3c +#define PKT_ISRC1_CONTENTS0 0xb40 +#define PKT_ISRC1_CONTENTS1 0xb44 +#define PKT_ISRC1_CONTENTS2 0xb48 +#define PKT_ISRC1_CONTENTS3 0xb4c +#define PKT_ISRC1_CONTENTS4 0xb50 +#define PKT_ISRC1_CONTENTS5 0xb54 +#define PKT_ISRC1_CONTENTS6 0xb58 +#define PKT_ISRC1_CONTENTS7 0xb5c +#define PKT_ISRC2_CONTENTS0 0xb60 +#define PKT_ISRC2_CONTENTS1 0xb64 +#define PKT_ISRC2_CONTENTS2 0xb68 +#define PKT_ISRC2_CONTENTS3 0xb6c +#define PKT_ISRC2_CONTENTS4 0xb70 +#define PKT_ISRC2_CONTENTS5 0xb74 +#define PKT_ISRC2_CONTENTS6 0xb78 +#define PKT_ISRC2_CONTENTS7 0xb7c +#define PKT_GMD_CONTENTS0 0xb80 +#define PKT_GMD_CONTENTS1 0xb84 +#define PKT_GMD_CONTENTS2 0xb88 +#define PKT_GMD_CONTENTS3 0xb8c +#define PKT_GMD_CONTENTS4 0xb90 +#define PKT_GMD_CONTENTS5 0xb94 +#define PKT_GMD_CONTENTS6 0xb98 +#define PKT_GMD_CONTENTS7 0xb9c +#define PKT_AMD_CONTENTS0 0xba0 +#define PKT_AMD_CONTENTS1 0xba4 +#define PKT_AMD_CONTENTS2 0xba8 +#define PKT_AMD_CONTENTS3 0xbac +#define PKT_AMD_CONTENTS4 0xbb0 +#define PKT_AMD_CONTENTS5 0xbb4 +#define PKT_AMD_CONTENTS6 0xbb8 +#define PKT_AMD_CONTENTS7 0xbbc +#define PKT_VSI_CONTENTS0 0xbc0 +#define PKT_VSI_CONTENTS1 0xbc4 +#define PKT_VSI_CONTENTS2 0xbc8 +#define PKT_VSI_CONTENTS3 0xbcc +#define PKT_VSI_CONTENTS4 0xbd0 +#define PKT_VSI_CONTENTS5 0xbd4 +#define PKT_VSI_CONTENTS6 0xbd8 +#define PKT_VSI_CONTENTS7 0xbdc +#define PKT_AVI_CONTENTS0 0xbe0 +#define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) +#define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 +#define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 +#define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 +#define PKT_AVI_CONTENTS1 0xbe4 +#define PKT_AVI_CONTENTS2 0xbe8 +#define PKT_AVI_CONTENTS3 0xbec +#define PKT_AVI_CONTENTS4 0xbf0 +#define PKT_AVI_CONTENTS5 0xbf4 +#define PKT_AVI_CONTENTS6 0xbf8 +#define PKT_AVI_CONTENTS7 0xbfc +#define PKT_SPDI_CONTENTS0 0xc00 +#define PKT_SPDI_CONTENTS1 0xc04 +#define PKT_SPDI_CONTENTS2 0xc08 +#define PKT_SPDI_CONTENTS3 0xc0c +#define PKT_SPDI_CONTENTS4 0xc10 +#define PKT_SPDI_CONTENTS5 0xc14 +#define PKT_SPDI_CONTENTS6 0xc18 +#define PKT_SPDI_CONTENTS7 0xc1c +#define PKT_AUDI_CONTENTS0 0xc20 +#define PKT_AUDI_CONTENTS1 0xc24 +#define PKT_AUDI_CONTENTS2 0xc28 +#define PKT_AUDI_CONTENTS3 0xc2c +#define PKT_AUDI_CONTENTS4 0xc30 +#define PKT_AUDI_CONTENTS5 0xc34 +#define PKT_AUDI_CONTENTS6 0xc38 +#define PKT_AUDI_CONTENTS7 0xc3c +#define PKT_NVI_CONTENTS0 0xc40 +#define PKT_NVI_CONTENTS1 0xc44 +#define PKT_NVI_CONTENTS2 0xc48 +#define PKT_NVI_CONTENTS3 0xc4c +#define PKT_NVI_CONTENTS4 0xc50 +#define PKT_NVI_CONTENTS5 0xc54 +#define PKT_NVI_CONTENTS6 0xc58 +#define PKT_NVI_CONTENTS7 0xc5c +#define PKT_DRMI_CONTENTS0 0xc60 +#define PKT_DRMI_CONTENTS1 0xc64 +#define PKT_DRMI_CONTENTS2 0xc68 +#define PKT_DRMI_CONTENTS3 0xc6c +#define PKT_DRMI_CONTENTS4 0xc70 +#define PKT_DRMI_CONTENTS5 0xc74 +#define PKT_DRMI_CONTENTS6 0xc78 +#define PKT_DRMI_CONTENTS7 0xc7c +#define PKT_GHDMI1_CONTENTS0 0xc80 +#define PKT_GHDMI1_CONTENTS1 0xc84 +#define PKT_GHDMI1_CONTENTS2 0xc88 +#define PKT_GHDMI1_CONTENTS3 0xc8c +#define PKT_GHDMI1_CONTENTS4 0xc90 +#define PKT_GHDMI1_CONTENTS5 0xc94 +#define PKT_GHDMI1_CONTENTS6 0xc98 +#define PKT_GHDMI1_CONTENTS7 0xc9c +#define PKT_GHDMI2_CONTENTS0 0xca0 +#define PKT_GHDMI2_CONTENTS1 0xca4 +#define PKT_GHDMI2_CONTENTS2 0xca8 +#define PKT_GHDMI2_CONTENTS3 0xcac +#define PKT_GHDMI2_CONTENTS4 0xcb0 +#define PKT_GHDMI2_CONTENTS5 0xcb4 +#define PKT_GHDMI2_CONTENTS6 0xcb8 +#define PKT_GHDMI2_CONTENTS7 0xcbc +/* EMP Packetizer Registers */ +#define PKT_EMP_CONFIG0 0xce0 +#define PKT_EMP_CONTROL0 0xcec +#define PKT_EMP_CONTROL1 0xcf0 +#define PKT_EMP_CONTROL2 0xcf4 +#define PKT_EMP_VTEM_CONTENTS0 0xd00 +#define PKT_EMP_VTEM_CONTENTS1 0xd04 +#define PKT_EMP_VTEM_CONTENTS2 0xd08 +#define PKT_EMP_VTEM_CONTENTS3 0xd0c +#define PKT_EMP_VTEM_CONTENTS4 0xd10 +#define PKT_EMP_VTEM_CONTENTS5 0xd14 +#define PKT_EMP_VTEM_CONTENTS6 0xd18 +#define PKT_EMP_VTEM_CONTENTS7 0xd1c +#define PKT0_EMP_CVTEM_CONTENTS0 0xd20 +#define PKT0_EMP_CVTEM_CONTENTS1 0xd24 +#define PKT0_EMP_CVTEM_CONTENTS2 0xd28 +#define PKT0_EMP_CVTEM_CONTENTS3 0xd2c +#define PKT0_EMP_CVTEM_CONTENTS4 0xd30 +#define PKT0_EMP_CVTEM_CONTENTS5 0xd34 +#define PKT0_EMP_CVTEM_CONTENTS6 0xd38 +#define PKT0_EMP_CVTEM_CONTENTS7 0xd3c +#define PKT1_EMP_CVTEM_CONTENTS0 0xd40 +#define PKT1_EMP_CVTEM_CONTENTS1 0xd44 +#define PKT1_EMP_CVTEM_CONTENTS2 0xd48 +#define PKT1_EMP_CVTEM_CONTENTS3 0xd4c +#define PKT1_EMP_CVTEM_CONTENTS4 0xd50 +#define PKT1_EMP_CVTEM_CONTENTS5 0xd54 +#define PKT1_EMP_CVTEM_CONTENTS6 0xd58 +#define PKT1_EMP_CVTEM_CONTENTS7 0xd5c +#define PKT2_EMP_CVTEM_CONTENTS0 0xd60 +#define PKT2_EMP_CVTEM_CONTENTS1 0xd64 +#define PKT2_EMP_CVTEM_CONTENTS2 0xd68 +#define PKT2_EMP_CVTEM_CONTENTS3 0xd6c +#define PKT2_EMP_CVTEM_CONTENTS4 0xd70 +#define PKT2_EMP_CVTEM_CONTENTS5 0xd74 +#define PKT2_EMP_CVTEM_CONTENTS6 0xd78 +#define PKT2_EMP_CVTEM_CONTENTS7 0xd7c +#define PKT3_EMP_CVTEM_CONTENTS0 0xd80 +#define PKT3_EMP_CVTEM_CONTENTS1 0xd84 +#define PKT3_EMP_CVTEM_CONTENTS2 0xd88 +#define PKT3_EMP_CVTEM_CONTENTS3 0xd8c +#define PKT3_EMP_CVTEM_CONTENTS4 0xd90 +#define PKT3_EMP_CVTEM_CONTENTS5 0xd94 +#define PKT3_EMP_CVTEM_CONTENTS6 0xd98 +#define PKT3_EMP_CVTEM_CONTENTS7 0xd9c +#define PKT4_EMP_CVTEM_CONTENTS0 0xda0 +#define PKT4_EMP_CVTEM_CONTENTS1 0xda4 +#define PKT4_EMP_CVTEM_CONTENTS2 0xda8 +#define PKT4_EMP_CVTEM_CONTENTS3 0xdac +#define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 +#define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 +#define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 +#define PKT4_EMP_CVTEM_CONTENTS7 0xdbc +#define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 +#define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 +#define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 +#define PKT5_EMP_CVTEM_CONTENTS3 0xdcc +#define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 +#define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 +#define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 +#define PKT5_EMP_CVTEM_CONTENTS7 0xddc +/* Audio Packetizer Registers */ +#define AUDPKT_CONTROL0 0xe20 +#define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) +#define AUDPKT_CHSTATUS_OVR_EN BIT(0) +#define AUDPKT_CONTROL1 0xe24 +#define AUDPKT_ACR_CONTROL0 0xe40 +#define AUDPKT_ACR_N_VALUE 0xfffff +#define AUDPKT_ACR_CONTROL1 0xe44 +#define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) +#define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) +#define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) +#define AUDPKT_ACR_CTS_OVR_EN BIT(1) +#define AUDPKT_ACR_STATUS0 0xe4c +#define AUDPKT_CHSTATUS_OVR0 0xe60 +#define AUDPKT_CHSTATUS_OVR1 0xe64 +/* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ +#define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) +#define AUDPKT_CHSTATUS_SR_22050 0x4 +#define AUDPKT_CHSTATUS_SR_24000 0x6 +#define AUDPKT_CHSTATUS_SR_32000 0x3 +#define AUDPKT_CHSTATUS_SR_44100 0x0 +#define AUDPKT_CHSTATUS_SR_48000 0x2 +#define AUDPKT_CHSTATUS_SR_88200 0x8 +#define AUDPKT_CHSTATUS_SR_96000 0xa +#define AUDPKT_CHSTATUS_SR_176400 0xc +#define AUDPKT_CHSTATUS_SR_192000 0xe +#define AUDPKT_CHSTATUS_SR_768000 0x9 +#define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 +/* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ +#define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) +#define AUDPKT_CHSTATUS_OSR_8000 0x6 +#define AUDPKT_CHSTATUS_OSR_11025 0xa +#define AUDPKT_CHSTATUS_OSR_12000 0x2 +#define AUDPKT_CHSTATUS_OSR_16000 0x8 +#define AUDPKT_CHSTATUS_OSR_22050 0xb +#define AUDPKT_CHSTATUS_OSR_24000 0x9 +#define AUDPKT_CHSTATUS_OSR_32000 0xc +#define AUDPKT_CHSTATUS_OSR_44100 0xf +#define AUDPKT_CHSTATUS_OSR_48000 0xd +#define AUDPKT_CHSTATUS_OSR_88200 0x7 +#define AUDPKT_CHSTATUS_OSR_96000 0x5 +#define AUDPKT_CHSTATUS_OSR_176400 0x3 +#define AUDPKT_CHSTATUS_OSR_192000 0x1 +#define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 +#define AUDPKT_CHSTATUS_OVR2 0xe68 +#define AUDPKT_CHSTATUS_OVR3 0xe6c +#define AUDPKT_CHSTATUS_OVR4 0xe70 +#define AUDPKT_CHSTATUS_OVR5 0xe74 +#define AUDPKT_CHSTATUS_OVR6 0xe78 +#define AUDPKT_CHSTATUS_OVR7 0xe7c +#define AUDPKT_CHSTATUS_OVR8 0xe80 +#define AUDPKT_CHSTATUS_OVR9 0xe84 +#define AUDPKT_CHSTATUS_OVR10 0xe88 +#define AUDPKT_CHSTATUS_OVR11 0xe8c +#define AUDPKT_CHSTATUS_OVR12 0xe90 +#define AUDPKT_CHSTATUS_OVR13 0xe94 +#define AUDPKT_CHSTATUS_OVR14 0xe98 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac +#define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc +#define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc +#define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc +#define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec +#define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc +#define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c +#define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 +#define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c +#define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 +#define AUDPKT_VBIT_OVR0 0xf24 +/* CEC Registers */ +#define CEC_TX_CONTROL 0x1000 +#define CEC_STATUS 0x1004 +#define CEC_CONFIG 0x1008 +#define CEC_ADDR 0x100c +#define CEC_TX_COUNT 0x1020 +#define CEC_TX_DATA3_0 0x1024 +#define CEC_TX_DATA7_4 0x1028 +#define CEC_TX_DATA11_8 0x102c +#define CEC_TX_DATA15_12 0x1030 +#define CEC_RX_COUNT_STATUS 0x1040 +#define CEC_RX_DATA3_0 0x1044 +#define CEC_RX_DATA7_4 0x1048 +#define CEC_RX_DATA11_8 0x104c +#define CEC_RX_DATA15_12 0x1050 +#define CEC_LOCK_CONTROL 0x1054 +#define CEC_RXQUAL_BITTIME_CONFIG 0x1060 +#define CEC_RX_BITTIME_CONFIG 0x1064 +#define CEC_TX_BITTIME_CONFIG 0x1068 +/* eARC RX CMDC Registers */ +#define EARCRX_CMDC_CONFIG0 0x1800 +#define EARCRX_XACTREAD_STOP_CFG BIT(26) +#define EARCRX_XACTREAD_RETRY_CFG BIT(25) +#define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) +#define EARCRX_CMDC_XACT_RESTART_EN BIT(18) +#define EARCRX_CMDC_CONFIG1 0x1804 +#define EARCRX_CMDC_CONTROL 0x1808 +#define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) +#define EARCRX_CMDC_DISCOVERY_EN BIT(3) +#define EARCRX_CONNECTOR_HPD BIT(1) +#define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c +#define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 +#define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 +#define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 +#define EARCRX_CMDC_STATUS 0x181c +#define EARCRX_CMDC_XACT_INFO 0x1820 +#define EARCRX_CMDC_XACT_ACTION 0x1824 +#define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 +#define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c +#define EARCRX_CMDC_XACT_WR0 0x1840 +#define EARCRX_CMDC_XACT_WR1 0x1844 +#define EARCRX_CMDC_XACT_WR2 0x1848 +#define EARCRX_CMDC_XACT_WR3 0x184c +#define EARCRX_CMDC_XACT_WR4 0x1850 +#define EARCRX_CMDC_XACT_WR5 0x1854 +#define EARCRX_CMDC_XACT_WR6 0x1858 +#define EARCRX_CMDC_XACT_WR7 0x185c +#define EARCRX_CMDC_XACT_WR8 0x1860 +#define EARCRX_CMDC_XACT_WR9 0x1864 +#define EARCRX_CMDC_XACT_WR10 0x1868 +#define EARCRX_CMDC_XACT_WR11 0x186c +#define EARCRX_CMDC_XACT_WR12 0x1870 +#define EARCRX_CMDC_XACT_WR13 0x1874 +#define EARCRX_CMDC_XACT_WR14 0x1878 +#define EARCRX_CMDC_XACT_WR15 0x187c +#define EARCRX_CMDC_XACT_WR16 0x1880 +#define EARCRX_CMDC_XACT_WR17 0x1884 +#define EARCRX_CMDC_XACT_WR18 0x1888 +#define EARCRX_CMDC_XACT_WR19 0x188c +#define EARCRX_CMDC_XACT_WR20 0x1890 +#define EARCRX_CMDC_XACT_WR21 0x1894 +#define EARCRX_CMDC_XACT_WR22 0x1898 +#define EARCRX_CMDC_XACT_WR23 0x189c +#define EARCRX_CMDC_XACT_WR24 0x18a0 +#define EARCRX_CMDC_XACT_WR25 0x18a4 +#define EARCRX_CMDC_XACT_WR26 0x18a8 +#define EARCRX_CMDC_XACT_WR27 0x18ac +#define EARCRX_CMDC_XACT_WR28 0x18b0 +#define EARCRX_CMDC_XACT_WR29 0x18b4 +#define EARCRX_CMDC_XACT_WR30 0x18b8 +#define EARCRX_CMDC_XACT_WR31 0x18bc +#define EARCRX_CMDC_XACT_WR32 0x18c0 +#define EARCRX_CMDC_XACT_WR33 0x18c4 +#define EARCRX_CMDC_XACT_WR34 0x18c8 +#define EARCRX_CMDC_XACT_WR35 0x18cc +#define EARCRX_CMDC_XACT_WR36 0x18d0 +#define EARCRX_CMDC_XACT_WR37 0x18d4 +#define EARCRX_CMDC_XACT_WR38 0x18d8 +#define EARCRX_CMDC_XACT_WR39 0x18dc +#define EARCRX_CMDC_XACT_WR40 0x18e0 +#define EARCRX_CMDC_XACT_WR41 0x18e4 +#define EARCRX_CMDC_XACT_WR42 0x18e8 +#define EARCRX_CMDC_XACT_WR43 0x18ec +#define EARCRX_CMDC_XACT_WR44 0x18f0 +#define EARCRX_CMDC_XACT_WR45 0x18f4 +#define EARCRX_CMDC_XACT_WR46 0x18f8 +#define EARCRX_CMDC_XACT_WR47 0x18fc +#define EARCRX_CMDC_XACT_WR48 0x1900 +#define EARCRX_CMDC_XACT_WR49 0x1904 +#define EARCRX_CMDC_XACT_WR50 0x1908 +#define EARCRX_CMDC_XACT_WR51 0x190c +#define EARCRX_CMDC_XACT_WR52 0x1910 +#define EARCRX_CMDC_XACT_WR53 0x1914 +#define EARCRX_CMDC_XACT_WR54 0x1918 +#define EARCRX_CMDC_XACT_WR55 0x191c +#define EARCRX_CMDC_XACT_WR56 0x1920 +#define EARCRX_CMDC_XACT_WR57 0x1924 +#define EARCRX_CMDC_XACT_WR58 0x1928 +#define EARCRX_CMDC_XACT_WR59 0x192c +#define EARCRX_CMDC_XACT_WR60 0x1930 +#define EARCRX_CMDC_XACT_WR61 0x1934 +#define EARCRX_CMDC_XACT_WR62 0x1938 +#define EARCRX_CMDC_XACT_WR63 0x193c +#define EARCRX_CMDC_XACT_WR64 0x1940 +#define EARCRX_CMDC_XACT_RD0 0x1960 +#define EARCRX_CMDC_XACT_RD1 0x1964 +#define EARCRX_CMDC_XACT_RD2 0x1968 +#define EARCRX_CMDC_XACT_RD3 0x196c +#define EARCRX_CMDC_XACT_RD4 0x1970 +#define EARCRX_CMDC_XACT_RD5 0x1974 +#define EARCRX_CMDC_XACT_RD6 0x1978 +#define EARCRX_CMDC_XACT_RD7 0x197c +#define EARCRX_CMDC_XACT_RD8 0x1980 +#define EARCRX_CMDC_XACT_RD9 0x1984 +#define EARCRX_CMDC_XACT_RD10 0x1988 +#define EARCRX_CMDC_XACT_RD11 0x198c +#define EARCRX_CMDC_XACT_RD12 0x1990 +#define EARCRX_CMDC_XACT_RD13 0x1994 +#define EARCRX_CMDC_XACT_RD14 0x1998 +#define EARCRX_CMDC_XACT_RD15 0x199c +#define EARCRX_CMDC_XACT_RD16 0x19a0 +#define EARCRX_CMDC_XACT_RD17 0x19a4 +#define EARCRX_CMDC_XACT_RD18 0x19a8 +#define EARCRX_CMDC_XACT_RD19 0x19ac +#define EARCRX_CMDC_XACT_RD20 0x19b0 +#define EARCRX_CMDC_XACT_RD21 0x19b4 +#define EARCRX_CMDC_XACT_RD22 0x19b8 +#define EARCRX_CMDC_XACT_RD23 0x19bc +#define EARCRX_CMDC_XACT_RD24 0x19c0 +#define EARCRX_CMDC_XACT_RD25 0x19c4 +#define EARCRX_CMDC_XACT_RD26 0x19c8 +#define EARCRX_CMDC_XACT_RD27 0x19cc +#define EARCRX_CMDC_XACT_RD28 0x19d0 +#define EARCRX_CMDC_XACT_RD29 0x19d4 +#define EARCRX_CMDC_XACT_RD30 0x19d8 +#define EARCRX_CMDC_XACT_RD31 0x19dc +#define EARCRX_CMDC_XACT_RD32 0x19e0 +#define EARCRX_CMDC_XACT_RD33 0x19e4 +#define EARCRX_CMDC_XACT_RD34 0x19e8 +#define EARCRX_CMDC_XACT_RD35 0x19ec +#define EARCRX_CMDC_XACT_RD36 0x19f0 +#define EARCRX_CMDC_XACT_RD37 0x19f4 +#define EARCRX_CMDC_XACT_RD38 0x19f8 +#define EARCRX_CMDC_XACT_RD39 0x19fc +#define EARCRX_CMDC_XACT_RD40 0x1a00 +#define EARCRX_CMDC_XACT_RD41 0x1a04 +#define EARCRX_CMDC_XACT_RD42 0x1a08 +#define EARCRX_CMDC_XACT_RD43 0x1a0c +#define EARCRX_CMDC_XACT_RD44 0x1a10 +#define EARCRX_CMDC_XACT_RD45 0x1a14 +#define EARCRX_CMDC_XACT_RD46 0x1a18 +#define EARCRX_CMDC_XACT_RD47 0x1a1c +#define EARCRX_CMDC_XACT_RD48 0x1a20 +#define EARCRX_CMDC_XACT_RD49 0x1a24 +#define EARCRX_CMDC_XACT_RD50 0x1a28 +#define EARCRX_CMDC_XACT_RD51 0x1a2c +#define EARCRX_CMDC_XACT_RD52 0x1a30 +#define EARCRX_CMDC_XACT_RD53 0x1a34 +#define EARCRX_CMDC_XACT_RD54 0x1a38 +#define EARCRX_CMDC_XACT_RD55 0x1a3c +#define EARCRX_CMDC_XACT_RD56 0x1a40 +#define EARCRX_CMDC_XACT_RD57 0x1a44 +#define EARCRX_CMDC_XACT_RD58 0x1a48 +#define EARCRX_CMDC_XACT_RD59 0x1a4c +#define EARCRX_CMDC_XACT_RD60 0x1a50 +#define EARCRX_CMDC_XACT_RD61 0x1a54 +#define EARCRX_CMDC_XACT_RD62 0x1a58 +#define EARCRX_CMDC_XACT_RD63 0x1a5c +#define EARCRX_CMDC_XACT_RD64 0x1a60 +#define EARCRX_CMDC_SYNC_CONFIG 0x1b00 +/* eARC RX DMAC Registers */ +#define EARCRX_DMAC_PHY_CONTROL 0x1c00 +#define EARCRX_DMAC_CONFIG 0x1c08 +#define EARCRX_DMAC_CONTROL0 0x1c0c +#define EARCRX_DMAC_AUDIO_EN BIT(1) +#define EARCRX_DMAC_EN BIT(0) +#define EARCRX_DMAC_CONTROL1 0x1c10 +#define EARCRX_DMAC_STATUS 0x1c14 +#define EARCRX_DMAC_CHSTATUS0 0x1c18 +#define EARCRX_DMAC_CHSTATUS1 0x1c1c +#define EARCRX_DMAC_CHSTATUS2 0x1c20 +#define EARCRX_DMAC_CHSTATUS3 0x1c24 +#define EARCRX_DMAC_CHSTATUS4 0x1c28 +#define EARCRX_DMAC_CHSTATUS5 0x1c2c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 +#define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc +#define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc +#define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc +#define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec +#define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc +#define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c +#define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c +#define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c +#define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 +#define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c +#define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 +#define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 +#define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 +#define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c +#define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 +#define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 +#define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 +#define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c +#define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 +#define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 +#define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 +#define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c +#define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 +#define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 +#define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 +#define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c +#define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 +/* Main Unit Interrupt Registers */ +#define MAIN_INTVEC_INDEX 0x3000 +#define MAINUNIT_0_INT_STATUS 0x3010 +#define MAINUNIT_0_INT_MASK_N 0x3014 +#define MAINUNIT_0_INT_CLEAR 0x3018 +#define MAINUNIT_0_INT_FORCE 0x301c +#define MAINUNIT_1_INT_STATUS 0x3020 +#define FLT_EXIT_TO_LTSL_IRQ BIT(22) +#define FLT_EXIT_TO_LTS4_IRQ BIT(21) +#define FLT_EXIT_TO_LTSP_IRQ BIT(20) +#define SCDC_NACK_RCVD_IRQ BIT(12) +#define SCDC_RR_REPLY_STOP_IRQ BIT(11) +#define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) +#define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) +#define SCDC_UPD_FLAGS_RD_IRQ BIT(8) +#define I2CM_NACK_RCVD_IRQ BIT(2) +#define I2CM_READ_REQUEST_IRQ BIT(1) +#define I2CM_OP_DONE_IRQ BIT(0) +#define MAINUNIT_1_INT_MASK_N 0x3024 +#define I2CM_NACK_RCVD_MASK_N BIT(2) +#define I2CM_READ_REQUEST_MASK_N BIT(1) +#define I2CM_OP_DONE_MASK_N BIT(0) +#define MAINUNIT_1_INT_CLEAR 0x3028 +#define I2CM_NACK_RCVD_CLEAR BIT(2) +#define I2CM_READ_REQUEST_CLEAR BIT(1) +#define I2CM_OP_DONE_CLEAR BIT(0) +#define MAINUNIT_1_INT_FORCE 0x302c +/* AVPUNIT Interrupt Registers */ +#define AVP_INTVEC_INDEX 0x3800 +#define AVP_0_INT_STATUS 0x3810 +#define AVP_0_INT_MASK_N 0x3814 +#define AVP_0_INT_CLEAR 0x3818 +#define AVP_0_INT_FORCE 0x381c +#define AVP_1_INT_STATUS 0x3820 +#define AVP_1_INT_MASK_N 0x3824 +#define HDCP14_AUTH_CHG_MASK_N BIT(6) +#define AVP_1_INT_CLEAR 0x3828 +#define AVP_1_INT_FORCE 0x382c +#define AVP_2_INT_STATUS 0x3830 +#define AVP_2_INT_MASK_N 0x3834 +#define AVP_2_INT_CLEAR 0x3838 +#define AVP_2_INT_FORCE 0x383c +#define AVP_3_INT_STATUS 0x3840 +#define AVP_3_INT_MASK_N 0x3844 +#define AVP_3_INT_CLEAR 0x3848 +#define AVP_3_INT_FORCE 0x384c +#define AVP_4_INT_STATUS 0x3850 +#define AVP_4_INT_MASK_N 0x3854 +#define AVP_4_INT_CLEAR 0x3858 +#define AVP_4_INT_FORCE 0x385c +#define AVP_5_INT_STATUS 0x3860 +#define AVP_5_INT_MASK_N 0x3864 +#define AVP_5_INT_CLEAR 0x3868 +#define AVP_5_INT_FORCE 0x386c +#define AVP_6_INT_STATUS 0x3870 +#define AVP_6_INT_MASK_N 0x3874 +#define AVP_6_INT_CLEAR 0x3878 +#define AVP_6_INT_FORCE 0x387c +/* CEC Interrupt Registers */ +#define CEC_INT_STATUS 0x4000 +#define CEC_INT_MASK_N 0x4004 +#define CEC_INT_CLEAR 0x4008 +#define CEC_INT_FORCE 0x400c +/* eARC RX Interrupt Registers */ +#define EARCRX_INTVEC_INDEX 0x4800 +#define EARCRX_0_INT_STATUS 0x4810 +#define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) +#define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) +#define EARCRX_0_INT_MASK_N 0x4814 +#define EARCRX_0_INT_CLEAR 0x4818 +#define EARCRX_0_INT_FORCE 0x481c +#define EARCRX_1_INT_STATUS 0x4820 +#define EARCRX_1_INT_MASK_N 0x4824 +#define EARCRX_1_INT_CLEAR 0x4828 +#define EARCRX_1_INT_FORCE 0x482c + +/* SCDC Registers */ +#define SCDC_SINK_VERSION 0x01 +#define SCDC_SOURCE_VERSION 0x02 + +#define SCDC_UPDATE_0 0x10 +#define SCDC_READ_REQUEST_TEST BIT(2) +#define SCDC_CED_UPDATE BIT(1) +#define SCDC_STATUS_UPDATE BIT(0) +#define SCDC_UPDATE_1 0x11 + +#define SCDC_TMDS_CONFIG 0x20 +#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 BIT(1) +#define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1) +#define SCDC_SCRAMBLING_ENABLE BIT(0) +#define SCDC_SCRAMBLER_STATUS 0x21 +#define SCDC_SCRAMBLING_STATUS BIT(0) + +#define SCDC_CONFIG_0 0x30 +#define SCDC_READ_REQUEST_ENABLE BIT(0) + +#define SCDC_STATUS_FLAGS_0 0x40 +#define SCDC_CH2_LOCK BIT(3) +#define SCDC_CH1_LOCK BIT(2) +#define SCDC_CH0_LOCK BIT(1) +#define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK) +#define SCDC_CLOCK_DETECT BIT(0) +#define SCDC_STATUS_FLAGS_1 0x41 + +#define SCDC_ERR_DET_0_L 0x50 +#define SCDC_ERR_DET_0_H 0x51 +#define SCDC_ERR_DET_1_L 0x52 +#define SCDC_ERR_DET_1_H 0x53 +#define SCDC_ERR_DET_2_L 0x54 +#define SCDC_ERR_DET_2_H 0x55 +#define SCDC_CHANNEL_VALID BIT(7) +#define SCDC_ERR_DET_CHECKSUM 0x56 + +#define SCDC_TEST_CONFIG_0 0xc0 +#define SCDC_TEST_READ_REQUEST BIT(7) +#define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f) + +#define SCDC_MANUFACTURER_IEEE_OUI 0xd0 +#define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3 +#define SCDC_DEVICE_ID 0xd3 +#define SCDC_DEVICE_ID_SIZE 8 +#define SCDC_DEVICE_HARDWARE_REVISION 0xdb +#define SCDC_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf) +#define SCDC_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf) +#define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc +#define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd + +#define SCDC_MANUFACTURER_SPECIFIC 0xde +#define SCDC_MANUFACTURER_SPECIFIC_SIZE 34 + +#define HDMI0_BASE 0xFDE80000 +#define HDMI1_BASE 0xFDEA0000 + +#define HDMI0TX_PHY_BASE 0xFED60000 +#define HDMI1TX_PHY_BASE 0xFED70000 + +#define HDPTXPHY0_GRF_BASE 0xFD5E0000 +#define HDPTXPHY1_GRF_BASE 0xFD5E4000 + +#define PMU1CRU_SOFTRST_CON03 0xA0C +#define PMU1CRU_SOFTRST_CON04 0xA10 + +struct DwHdmiQpI2c { + BOOLEAN Cmp; + UINT32 Stat; + UINT32 PinMux; + + UINT8 SlaveReg; + BOOLEAN IsSegment; + BOOLEAN IsRegAddr; +}; + +struct DwHdmiQpDevice { + UINT32 Id; + BOOLEAN ForceHpd; + struct DwHdmiQpI2c I2c; + UINT32 ScdcIntr; + UINT32 FltIntr; + UINT32 EarcIntr; + + BOOLEAN FltCmp; +}; + +struct i2c_msg { + UINT16 addr; + UINT16 flags; +#define I2C_M_RD 0x0001 /* guaranteed to be 0x0001! */ +#define I2C_M_TEN 0x0010 /* use only if I2C_FUNC_10BIT_ADDR */ +#define I2C_M_DMA_SAFE 0x0200 /* use only in kernel space */ +#define I2C_M_RECV_LEN 0x0400 /* use only if I2C_FUNC_SMBUS_READ_BLOCK_DATA */ +#define I2C_M_NO_RD_ACK 0x0800 /* use only if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_IGNORE_NAK 0x1000 /* use only if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_REV_DIR_ADDR 0x2000 /* use only if I2C_FUNC_PROTOCOL_MANGLING */ +#define I2C_M_NOSTART 0x4000 /* use only if I2C_FUNC_NOSTART */ +#define I2C_M_STOP 0x8000 /* use only if I2C_FUNC_PROTOCOL_MANGLING */ + UINT16 len; + UINT8 *buf; +}; + +/* Rockchip Htx Phy */ + +struct RockchipHdptxPhyHdmi { + UINT32 Id; +}; + +EFI_STATUS +DwHdmiQpConnectorPreInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +DwHdmiQpConnectorInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +DwHdmiQpConnectorGetEdid ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +DwHdmiQpConnectorEnable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +DwHdmiQpConnectorDisable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +EFI_STATUS +DwHdmiQpConnectorDetect ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ); + +UINT32 +HdptxRopllTmdsModeConfig ( + OUT struct RockchipHdptxPhyHdmi *Hdptx + ); + +UINT32 +HdptxRopllCmnConfig ( + OUT struct RockchipHdptxPhyHdmi *Hdptx + ); +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DwcSdhciPlatformLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DwcSdhciPlatformLib.h new file mode 100644 index 0000000..6e53ccf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/DwcSdhciPlatformLib.h @@ -0,0 +1,21 @@ +/** @file + * + * DwcSdhciDxe platform helper library. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +EFI_STATUS +EFIAPI +DwcSdhciSetClockRate ( + IN UINTN Frequency + ); + +VOID +EFIAPI +DwcSdhciSetIoMux ( + VOID + ); diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Fspi.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Fspi.h new file mode 100644 index 0000000..9ec2bc9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Fspi.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ +#ifndef _HAL_FSPI_H_ +#define _HAL_FSPI_H_ + +#define HAL_FSPI_QUAD_ENABLE +#define HAL_FSPI_SPEED_THRESHOLD 100000000 + +/***************************** Structure Definition **************************/ +/** FSPI_CTRL register datalines, addrlines and cmdlines value */ +#define FSPI_LINES_X1 (0) +#define FSPI_LINES_X2 (1) +#define FSPI_LINES_X4 (2) + +/** FSPI_CTRL bit union */ +typedef union { + UINT32 d32; + struct { + unsigned mode : 1; /**< spi mode select */ + unsigned sps : 1; /**< shift in phase at: posedge 1: negedge */ + unsigned reserved3_2 : 2; + unsigned scic : 4; /**< sclk_idle_level_cycles */ + unsigned cmdlines : 2; /**< cmd bits number */ + unsigned addrlines : 2; /**< address bits number */ + unsigned datalines : 2; /**< data bits number */ + unsigned reserved14_15 : 2; + unsigned addrbits : 5; + unsigned reserved31_21 : 11; + } b; +} FSPICTRL_DATA; + +/** FSPI_CMD register rw value without shift */ +#define FSPI_READ (0) +#define FSPI_WRITE (1) + +/** FSPI_CMD regitser addrbits value without shift */ +#define FSPI_ADDR_0BITS (0) +#define FSPI_ADDR_24BITS (1) +#define FSPI_ADDR_32BITS (2) +#define FSPI_ADDR_XBITS (3) + +/** FSPI_CMD bit union */ +typedef union { + UINT32 d32; + struct { + unsigned cmd : 8; /**< command that will send to Serial Flash */ + unsigned dummybits : 4; /**< dummy bits number */ + unsigned rw : 1; /**< 0:read, 1: write */ + unsigned readmode : 1; /**< continuous read mode */ + unsigned addrbits : 2; /**< address bits number */ + unsigned datasize : 14; /**< transferred bytes number */ + unsigned cs : 2; /**< chip select */ + } b; +} FSPICMD_DATA; + +typedef enum { + DEV_UNKNON = 0, + DEV_NOR, + DEV_PSRAM, +} eFSPI_devType; + +struct HAL_FSPI_XMMC_DEV { + eFSPI_devType type; + UINT32 ctrl; + UINT32 readCmd; + UINT32 writeCmd; +}; + +/** XIP may be not accessble, so place it in sram or psram */ +struct HAL_FSPI_HOST { + struct FSPI_REG *instance; + UINT32 *CruBase; + UINT8 cs; /**< Should be defined by user in each operation */ + UINT8 mode; /**< Should be defined by user, referring to hal_spi_mem.h */ + UINT8 cell; /**< Record DLL cell for PM resume, Set depend on corresponding device */ +}; + +#define HAL_FSPI_MAX_DELAY_LINE_CELLS (0xFFU) +RETURN_STATUS HAL_FSPI_Init(struct HAL_FSPI_HOST *host); +RETURN_STATUS HAL_FSPI_DeInit(struct HAL_FSPI_HOST *host); +RETURN_STATUS HAL_FSPI_XferStart(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op); +RETURN_STATUS HAL_FSPI_XferData(struct HAL_FSPI_HOST *host, UINT32 len, void *data, UINT32 dir); +RETURN_STATUS HAL_FSPI_XferData_DMA(struct HAL_FSPI_HOST *host, UINT32 len, void *data, UINT32 dir); +RETURN_STATUS HAL_FSPI_XferDone(struct HAL_FSPI_HOST *host); +RETURN_STATUS HAL_FSPI_SpiXfer(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op); +RETURN_STATUS HAL_FSPI_IRQHelper(struct HAL_FSPI_HOST *host); +RETURN_STATUS HAL_FSPI_MaskDMAInterrupt(struct HAL_FSPI_HOST *host); +RETURN_STATUS HAL_FSPI_UnmaskDMAInterrupt(struct HAL_FSPI_HOST *host); +RETURN_STATUS HAL_FSPI_XmmcSetting(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op); +RETURN_STATUS HAL_FSPI_XmmcRequest(struct HAL_FSPI_HOST *host, UINT8 on); +RETURN_STATUS HAL_FSPI_SetDelayLines(struct HAL_FSPI_HOST *host, UINT8 cells); +RETURN_STATUS HAL_FSPI_DLLDisable(struct HAL_FSPI_HOST *host); +UINT32 HAL_FSPI_GetXMMCStatus(struct HAL_FSPI_HOST *host); +UINT32 HAL_FSPI_GetMaxIoSize(struct HAL_FSPI_HOST *host); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/HalDef.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/HalDef.h new file mode 100644 index 0000000..c43e341 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/HalDef.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_DEF_H_ +#define _HAL_DEF_H_ + +#include "Soc.h" + +/* SOC OPS Marco */ +#define SET_BIT(REG, BIT) ((*(volatile uint32_t *)&(REG)) |= (BIT)) +#define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK)) +#define READ_BIT(REG, MASK) ((*(volatile const uint32_t *)&(REG)) & (MASK)) +#define CLEAR_REG(REG) ((*(volatile uint32_t *)&(REG)) = (0x0)) +#define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL)) +#define READ_REG(REG) ((*(volatile const uint32_t *)&(REG))) +#define MODIFY_REG(REG, CLEARMASK, SETMASK) \ + WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + +#if defined(__GNUC__) || defined(__CC_ARM) +#define MASK_TO_WE(msk) (__builtin_constant_p(msk) ? ((msk) > 0xFFFFU ? 0 : ((msk) << 16)) : ((msk) << 16)) +#else +#define MASK_TO_WE(msk) ((msk) << 16) +#endif +#define VAL_MASK_WE(msk, val) ((MASK_TO_WE(msk)) | (val)) +#define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val))) + +/* Misc OPS Marco */ +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define RESET 0 +#define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET) +#define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET) + +#define HAL_BIT(nr) (1UL << (nr)) +#define HAL_ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0])) +#define HAL_MAX(x, y) ((x) > (y) ? (x) : (y)) +#define HAL_MIN(x, y) ((x) < (y) ? (x) : (y)) + +#define HAL_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) + +#define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0) +#ifdef CACHE_LINE_SIZE +#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), CACHE_LINE_SIZE) +#else +#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), 4) +#endif + +/* Compiller Macro */ +#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) || defined(__ICCARM__) +#define HAL_UNUSED __attribute__((__unused__)) +#else +#define HAL_UNUSED +#endif + +#ifdef CACHE_LINE_SIZE +#define HAL_CACHELINE_ALIGNED __ALIGNED(CACHE_LINE_SIZE) +#else +#define HAL_CACHELINE_ALIGNED +#endif + +#ifdef HAL_SRAM_SECTION_ENABLED +#define HAL_SECTION_SRAM_CODE __attribute__((section(".sram_code"))) +#define HAL_SECTION_SRAM_RODATA __attribute__((section(".sram_rodata"))) +#define HAL_SECTION_SRAM_DATA __attribute__((section(".sram_data"))) +#define HAL_SECTION_SRAM_BSS __attribute__((section(".sram_bss"))) +#else +#define HAL_SECTION_SRAM_CODE +#define HAL_SECTION_SRAM_RODATA +#define HAL_SECTION_SRAM_DATA +#define HAL_SECTION_SRAM_BSS +#endif + +#ifdef HAL_PSRAM_SECTION_ENABLED +#define HAL_SECTION_PSRAM_CODE __attribute__((section(".psram_code"))) +#define HAL_SECTION_PSRAM_RODATA __attribute__((section(".psram_rodata"))) +#define HAL_SECTION_PSRAM_DATA __attribute__((section(".psram_data"))) +#define HAL_SECTION_PSRAM_BSS __attribute__((section(".psram_bss"))) +#else +#define HAL_SECTION_PSRAM_CODE +#define HAL_SECTION_PSRAM_RODATA +#define HAL_SECTION_PSRAM_DATA +#define HAL_SECTION_PSRAM_BSS +#endif + +#ifdef HAL_XIP_SECTION_ENABLED +#define HAL_SECTION_XIP_CODE __attribute__((section(".xip_code"))) +#define HAL_SECTION_XIP_RODATA __attribute__((section(".xip_rodata"))) +#else +#define HAL_SECTION_XIP_CODE +#define HAL_SECTION_XIP_RODATA +#endif + +typedef enum { + HAL_SYSTICK_CLKSRC_CORE, + HAL_SYSTICK_CLKSRC_EXT +} eHAL_systickClkSource; + +#define IS_SYSTICK_SOURCE(s) (((s) == HAL_SYSTICK_CLKSRC_CORE) || ((s) == HAL_SYSTICK_CLKSRC_EXT)) + +/***************************** Structure Definition **************************/ +typedef enum { + HAL_FALSE = 0x00U, + HAL_TRUE = 0x01U +} HAL_Check; + +typedef enum { + HAL_OK = 0x00U, + HAL_ERROR = (-1), + HAL_BUSY = (-16), + HAL_NODEV = (-19), + HAL_INVAL = (-22), + HAL_NOSYS = (-38), + HAL_TIMEOUT = (-110) +} HAL_Status; + +typedef enum { + HAL_DISABLE = 0x00U, + HAL_ENABLE = 0x01U +} HAL_FuncStatus; + +typedef enum { + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockStatus; + +typedef enum { + GPIO_BANK0 = 0, + GPIO_BANK1 = 1, + GPIO_BANK2 = 2, + GPIO_BANK3 = 3, + GPIO_BANK4 = 4, + GPIO_BANK_NUM +} eGPIO_bankId; + +typedef void (*pFunc)(void); + +/***************************** Function Declare ******************************/ + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/MediaBusFormat.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/MediaBusFormat.h new file mode 100644 index 0000000..405514b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/MediaBusFormat.h @@ -0,0 +1,163 @@ +/* + * Media Bus API header + * + * Copyright (C) 2009, Guennadi Liakhovetski + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + */ + +#ifndef __LINUX_MEDIA_BUS_FORMAT_H +#define __LINUX_MEDIA_BUS_FORMAT_H + +/* + * These bus formats uniquely identify data formats on the data bus. Format 0 + * is reserved, MEDIA_BUS_FMT_FIXED shall be used by host-client pairs, where + * the data format is fixed. Additionally, "2X8" means that one pixel is + * transferred in two 8-bit samples, "BE" or "LE" specify in which order those + * samples are transferred over the bus: "LE" means that the least significant + * bits are transferred first, "BE" means that the most significant bits are + * transferred first, and "PADHI" and "PADLO" define which bits - low or high, + * in the incomplete high byte, are filled with padding bits. + * + * The bus formats are grouped by type, bus_width, bits per component, samples + * per pixel and order of subsamples. Numerical values are sorted using generic + * numerical sort order (8 thus comes before 10). + * + * As their value can't change when a new bus format is inserted in the + * enumeration, the bus formats are explicitly given a numerical value. The next + * free values for each category are listed below, update them when inserting + * new pixel codes. + */ + +#define MEDIA_BUS_FMT_FIXED 0x0001 + +/* RGB - next is 0x1024 */ +#define MEDIA_BUS_FMT_RGB444_1X12 0x1016 +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 +#define MEDIA_BUS_FMT_RGB565_1X16 0x1017 +#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 +#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006 +#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007 +#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008 +#define MEDIA_BUS_FMT_RGB666_1X18 0x1009 +#define MEDIA_BUS_FMT_RBG888_1X24 0x100e +#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015 +#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010 +#define MEDIA_BUS_FMT_BGR888_1X24 0x1013 +#define MEDIA_BUS_FMT_GBR888_1X24 0x1014 +#define MEDIA_BUS_FMT_RGB888_1X24 0x100a +#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b +#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c +#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 +#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 +#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d +#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f +#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 +#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 +#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a +#define MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA 0x101b +#define MEDIA_BUS_FMT_SRGB888_3X8 0x101c +#define MEDIA_BUS_FMT_SBGR888_3X8 0x101d +#define MEDIA_BUS_FMT_SRBG888_3X8 0x101e +#define MEDIA_BUS_FMT_SRGB888_DUMMY_4X8 0x101f +#define MEDIA_BUS_FMT_SBGR888_DUMMY_4X8 0x1020 +#define MEDIA_BUS_FMT_SRBG888_DUMMY_4X8 0x1021 +#define MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG 0x1022 +#define MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA 0x1023 + +/* YUV (including grey) - next is 0x2026 */ +#define MEDIA_BUS_FMT_Y8_1X8 0x2001 +#define MEDIA_BUS_FMT_UV8_1X8 0x2015 +#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 +#define MEDIA_BUS_FMT_VYUY8_1_5X8 0x2003 +#define MEDIA_BUS_FMT_YUYV8_1_5X8 0x2004 +#define MEDIA_BUS_FMT_YVYU8_1_5X8 0x2005 +#define MEDIA_BUS_FMT_UYVY8_2X8 0x2006 +#define MEDIA_BUS_FMT_VYUY8_2X8 0x2007 +#define MEDIA_BUS_FMT_YUYV8_2X8 0x2008 +#define MEDIA_BUS_FMT_YVYU8_2X8 0x2009 +#define MEDIA_BUS_FMT_Y10_1X10 0x200a +#define MEDIA_BUS_FMT_UYVY10_2X10 0x2018 +#define MEDIA_BUS_FMT_VYUY10_2X10 0x2019 +#define MEDIA_BUS_FMT_YUYV10_2X10 0x200b +#define MEDIA_BUS_FMT_YVYU10_2X10 0x200c +#define MEDIA_BUS_FMT_Y12_1X12 0x2013 +#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c +#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d +#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e +#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f +#define MEDIA_BUS_FMT_UYVY8_1X16 0x200f +#define MEDIA_BUS_FMT_VYUY8_1X16 0x2010 +#define MEDIA_BUS_FMT_YUYV8_1X16 0x2011 +#define MEDIA_BUS_FMT_YVYU8_1X16 0x2012 +#define MEDIA_BUS_FMT_YDYUYDYV8_1X16 0x2014 +#define MEDIA_BUS_FMT_UYVY10_1X20 0x201a +#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b +#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d +#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e +#define MEDIA_BUS_FMT_VUY8_1X24 0x2024 +#define MEDIA_BUS_FMT_YUV8_1X24 0x2025 +#define MEDIA_BUS_FMT_UYYVYY8_0_5X24 0x2026 +#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020 +#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021 +#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 +#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 +#define MEDIA_BUS_FMT_YUV10_1X30 0x2016 +#define MEDIA_BUS_FMT_UYYVYY10_0_5X30 0x2027 +#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 +#define MEDIA_BUS_FMT_UYYVYY12_0_5X36 0x2028 +#define MEDIA_BUS_FMT_YUV12_1X36 0x2029 +#define MEDIA_BUS_FMT_YUV16_1X48 0x202a +#define MEDIA_BUS_FMT_UYYVYY16_0_5X48 0x202b + +/* Bayer - next is 0x3019 */ +#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 +#define MEDIA_BUS_FMT_SGBRG8_1X8 0x3013 +#define MEDIA_BUS_FMT_SGRBG8_1X8 0x3002 +#define MEDIA_BUS_FMT_SRGGB8_1X8 0x3014 +#define MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8 0x3015 +#define MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8 0x3016 +#define MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8 0x3017 +#define MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8 0x3018 +#define MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 0x300b +#define MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 0x300c +#define MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 0x3009 +#define MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 0x300d +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE 0x3003 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE 0x3004 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE 0x3005 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE 0x3006 +#define MEDIA_BUS_FMT_SBGGR10_1X10 0x3007 +#define MEDIA_BUS_FMT_SGBRG10_1X10 0x300e +#define MEDIA_BUS_FMT_SGRBG10_1X10 0x300a +#define MEDIA_BUS_FMT_SRGGB10_1X10 0x300f +#define MEDIA_BUS_FMT_SBGGR12_1X12 0x3008 +#define MEDIA_BUS_FMT_SGBRG12_1X12 0x3010 +#define MEDIA_BUS_FMT_SGRBG12_1X12 0x3011 +#define MEDIA_BUS_FMT_SRGGB12_1X12 0x3012 + +/* JPEG compressed formats - next is 0x4002 */ +#define MEDIA_BUS_FMT_JPEG_1X8 0x4001 + +/* Vendor specific formats - next is 0x5002 */ + +/* S5C73M3 sensor specific interleaved UYVY and JPEG */ +#define MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8 0x5001 + +/* HSV - next is 0x6002 */ +#define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001 + +/* Panel Mirror control */ +#define DRM_MODE_FLAG_XMIRROR (1<<28) +#define DRM_MODE_FLAG_YMIRROR (1<<29) +#define DRM_MODE_FLAG_XYMIRROR (DRM_MODE_FLAG_XMIRROR | DRM_MODE_FLAG_YMIRROR) + +#endif /* __LINUX_MEDIA_BUS_FORMAT_H */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/OtpLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/OtpLib.h new file mode 100644 index 0000000..4af1358 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/OtpLib.h @@ -0,0 +1,35 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef OTPLIB_H__ +#define OTPLIB_H__ + +VOID +OtpRead ( + IN UINT16 Offset, + IN UINT16 Length, + OUT UINT8 *Data + ); + +VOID +OtpReadCpuCode ( + OUT UINT16 *CpuCode + ); + +VOID +OtpReadId ( + OUT UINT8 Id[16] + ); + +VOID +OtpReadCpuVersion ( + OUT UINT8 *Version + ); + +#endif /* OTPLIB_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/PWMLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/PWMLib.h new file mode 100644 index 0000000..e4e0e8e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/PWMLib.h @@ -0,0 +1,423 @@ +/** @file + Rockchip PWM Driver. + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PWM_H__ +#define __PWM_H__ + +/******************************************PWM*******************************************/ +/* PWM0_CNT */ +#define PWM_PWM0_CNT_OFFSET (0x0U) +#define PWM_PWM0_CNT (0x0U) +#define PWM_PWM0_CNT_CNT_SHIFT (0U) +#define PWM_PWM0_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM0_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_PERIOD_HPR */ +#define PWM_PWM0_PERIOD_HPR_OFFSET (0x4U) +#define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM0_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM0_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_DUTY_LPR */ +#define PWM_PWM0_DUTY_LPR_OFFSET (0x8U) +#define PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM0_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM0_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM0_CTRL */ +#define PWM_PWM0_CTRL_OFFSET (0xCU) +#define PWM_PWM0_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM0_CTRL_PWM_EN_MASK (0x1U << PWM_PWM0_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM0_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM0_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM0_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM0_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM0_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM0_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM0_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM0_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM0_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM0_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM0_CTRL_CONLOCK_MASK (0x1U << PWM_PWM0_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM0_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM0_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM0_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM0_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM0_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM0_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM0_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM0_CTRL_CLK_SRC_SEL_SHIFT (10U) +#define PWM_PWM0_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM0_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */ +#define PWM_PWM0_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM0_CTRL_PRESCALE_MASK (0x7U << PWM_PWM0_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM0_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM0_CTRL_SCALE_MASK (0xFFU << PWM_PWM0_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM0_CTRL_RPT_SHIFT (24U) +#define PWM_PWM0_CTRL_RPT_MASK (0xFFU << PWM_PWM0_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM1_CNT */ +#define PWM_PWM1_CNT_OFFSET (0x10U) +#define PWM_PWM1_CNT (0x0U) +#define PWM_PWM1_CNT_CNT_SHIFT (0U) +#define PWM_PWM1_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM1_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_PERIOD_HPR */ +#define PWM_PWM1_PERIOD_HPR_OFFSET (0x14U) +#define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM1_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM1_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_DUTY_LPR */ +#define PWM_PWM1_DUTY_LPR_OFFSET (0x18U) +#define PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM1_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM1_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM1_CTRL */ +#define PWM_PWM1_CTRL_OFFSET (0x1CU) +#define PWM_PWM1_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM1_CTRL_PWM_EN_MASK (0x1U << PWM_PWM1_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM1_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM1_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM1_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM1_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM1_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM1_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM1_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM1_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM1_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM1_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM1_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM1_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM1_CTRL_CONLOCK_MASK (0x1U << PWM_PWM1_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM1_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM1_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM1_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM1_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM1_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM1_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM1_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM1_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM1_CTRL_CLK_SRC_SEL_SHIFT (10U) +#define PWM_PWM1_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM1_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */ +#define PWM_PWM1_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM1_CTRL_PRESCALE_MASK (0x7U << PWM_PWM1_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM1_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM1_CTRL_SCALE_MASK (0xFFU << PWM_PWM1_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM1_CTRL_RPT_SHIFT (24U) +#define PWM_PWM1_CTRL_RPT_MASK (0xFFU << PWM_PWM1_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM2_CNT */ +#define PWM_PWM2_CNT_OFFSET (0x20U) +#define PWM_PWM2_CNT (0x0U) +#define PWM_PWM2_CNT_CNT_SHIFT (0U) +#define PWM_PWM2_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM2_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_PERIOD_HPR */ +#define PWM_PWM2_PERIOD_HPR_OFFSET (0x24U) +#define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM2_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM2_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_DUTY_LPR */ +#define PWM_PWM2_DUTY_LPR_OFFSET (0x28U) +#define PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM2_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM2_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM2_CTRL */ +#define PWM_PWM2_CTRL_OFFSET (0x2CU) +#define PWM_PWM2_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM2_CTRL_PWM_EN_MASK (0x1U << PWM_PWM2_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM2_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM2_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM2_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM2_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM2_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM2_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM2_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM2_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM2_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM2_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM2_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM2_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM2_CTRL_CONLOCK_MASK (0x1U << PWM_PWM2_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM2_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM2_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM2_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM2_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM2_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM2_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM2_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM2_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM2_CTRL_CLK_SRC_SEL_SHIFT (10U) +#define PWM_PWM2_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM2_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */ +#define PWM_PWM2_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM2_CTRL_PRESCALE_MASK (0x7U << PWM_PWM2_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM2_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM2_CTRL_SCALE_MASK (0xFFU << PWM_PWM2_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM2_CTRL_RPT_SHIFT (24U) +#define PWM_PWM2_CTRL_RPT_MASK (0xFFU << PWM_PWM2_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* PWM3_CNT */ +#define PWM_PWM3_CNT_OFFSET (0x30U) +#define PWM_PWM3_CNT (0x0U) +#define PWM_PWM3_CNT_CNT_SHIFT (0U) +#define PWM_PWM3_CNT_CNT_MASK (0xFFFFFFFFU << PWM_PWM3_CNT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_PERIOD_HPR */ +#define PWM_PWM3_PERIOD_HPR_OFFSET (0x34U) +#define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT (0U) +#define PWM_PWM3_PERIOD_HPR_PERIOD_HPR_MASK (0xFFFFFFFFU << PWM_PWM3_PERIOD_HPR_PERIOD_HPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_DUTY_LPR */ +#define PWM_PWM3_DUTY_LPR_OFFSET (0x38U) +#define PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT (0U) +#define PWM_PWM3_DUTY_LPR_DUTY_LPR_MASK (0xFFFFFFFFU << PWM_PWM3_DUTY_LPR_DUTY_LPR_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_CTRL */ +#define PWM_PWM3_CTRL_OFFSET (0x3CU) +#define PWM_PWM3_CTRL_PWM_EN_SHIFT (0U) +#define PWM_PWM3_CTRL_PWM_EN_MASK (0x1U << PWM_PWM3_CTRL_PWM_EN_SHIFT) /* 0x00000001 */ +#define PWM_PWM3_CTRL_PWM_MODE_SHIFT (1U) +#define PWM_PWM3_CTRL_PWM_MODE_MASK (0x3U << PWM_PWM3_CTRL_PWM_MODE_SHIFT) /* 0x00000006 */ +#define PWM_PWM3_CTRL_DUTY_POL_SHIFT (3U) +#define PWM_PWM3_CTRL_DUTY_POL_MASK (0x1U << PWM_PWM3_CTRL_DUTY_POL_SHIFT) /* 0x00000008 */ +#define PWM_PWM3_CTRL_INACTIVE_POL_SHIFT (4U) +#define PWM_PWM3_CTRL_INACTIVE_POL_MASK (0x1U << PWM_PWM3_CTRL_INACTIVE_POL_SHIFT) /* 0x00000010 */ +#define PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT (5U) +#define PWM_PWM3_CTRL_OUTPUT_MODE_MASK (0x1U << PWM_PWM3_CTRL_OUTPUT_MODE_SHIFT) /* 0x00000020 */ +#define PWM_PWM3_CTRL_CONLOCK_SHIFT (6U) +#define PWM_PWM3_CTRL_CONLOCK_MASK (0x1U << PWM_PWM3_CTRL_CONLOCK_SHIFT) /* 0x00000040 */ +#define PWM_PWM3_CTRL_CH_CNT_EN_SHIFT (7U) +#define PWM_PWM3_CTRL_CH_CNT_EN_MASK (0x1U << PWM_PWM3_CTRL_CH_CNT_EN_SHIFT) /* 0x00000080 */ +#define PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT (8U) +#define PWM_PWM3_CTRL_FORCE_CLK_EN_MASK (0x1U << PWM_PWM3_CTRL_FORCE_CLK_EN_SHIFT) /* 0x00000100 */ +#define PWM_PWM3_CTRL_CLK_SEL_SHIFT (9U) +#define PWM_PWM3_CTRL_CLK_SEL_MASK (0x1U << PWM_PWM3_CTRL_CLK_SEL_SHIFT) /* 0x00000200 */ +#define PWM_PWM3_CTRL_CLK_SRC_SEL_SHIFT (10U) +#define PWM_PWM3_CTRL_CLK_SRC_SEL_MASK (0x1U << PWM_PWM3_CTRL_CLK_SRC_SEL_SHIFT) /* 0x00000400 */ +#define PWM_PWM3_CTRL_PRESCALE_SHIFT (12U) +#define PWM_PWM3_CTRL_PRESCALE_MASK (0x7U << PWM_PWM3_CTRL_PRESCALE_SHIFT) /* 0x00007000 */ +#define PWM_PWM3_CTRL_SCALE_SHIFT (16U) +#define PWM_PWM3_CTRL_SCALE_MASK (0xFFU << PWM_PWM3_CTRL_SCALE_SHIFT) /* 0x00FF0000 */ +#define PWM_PWM3_CTRL_RPT_SHIFT (24U) +#define PWM_PWM3_CTRL_RPT_MASK (0xFFU << PWM_PWM3_CTRL_RPT_SHIFT) /* 0xFF000000 */ +/* INTSTS */ +#define PWM_INTSTS_OFFSET (0x40U) +#define PWM_INTSTS_CH0_INTSTS_SHIFT (0U) +#define PWM_INTSTS_CH0_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_INTSTS_SHIFT) /* 0x00000001 */ +#define PWM_INTSTS_CH1_INTSTS_SHIFT (1U) +#define PWM_INTSTS_CH1_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_INTSTS_SHIFT) /* 0x00000002 */ +#define PWM_INTSTS_CH2_INTSTS_SHIFT (2U) +#define PWM_INTSTS_CH2_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_INTSTS_SHIFT) /* 0x00000004 */ +#define PWM_INTSTS_CH3_INTSTS_SHIFT (3U) +#define PWM_INTSTS_CH3_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_INTSTS_SHIFT) /* 0x00000008 */ +#define PWM_INTSTS_CH0_PWR_INTSTS_SHIFT (4U) +#define PWM_INTSTS_CH0_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH0_PWR_INTSTS_SHIFT) /* 0x00000010 */ +#define PWM_INTSTS_CH1_PWR_INTSTS_SHIFT (5U) +#define PWM_INTSTS_CH1_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH1_PWR_INTSTS_SHIFT) /* 0x00000020 */ +#define PWM_INTSTS_CH2_PWR_INTSTS_SHIFT (6U) +#define PWM_INTSTS_CH2_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH2_PWR_INTSTS_SHIFT) /* 0x00000040 */ +#define PWM_INTSTS_CH3_PWR_INTSTS_SHIFT (7U) +#define PWM_INTSTS_CH3_PWR_INTSTS_MASK (0x1U << PWM_INTSTS_CH3_PWR_INTSTS_SHIFT) /* 0x00000080 */ +#define PWM_INTSTS_CH0_POL_SHIFT (8U) +#define PWM_INTSTS_CH0_POL_MASK (0x1U << PWM_INTSTS_CH0_POL_SHIFT) /* 0x00000100 */ +#define PWM_INTSTS_CH1_POL_SHIFT (9U) +#define PWM_INTSTS_CH1_POL_MASK (0x1U << PWM_INTSTS_CH1_POL_SHIFT) /* 0x00000200 */ +#define PWM_INTSTS_CH2_POL_SHIFT (10U) +#define PWM_INTSTS_CH2_POL_MASK (0x1U << PWM_INTSTS_CH2_POL_SHIFT) /* 0x00000400 */ +#define PWM_INTSTS_CH3_POL_SHIFT (11U) +#define PWM_INTSTS_CH3_POL_MASK (0x1U << PWM_INTSTS_CH3_POL_SHIFT) /* 0x00000800 */ +/* INT_EN */ +#define PWM_INT_EN_OFFSET (0x44U) +#define PWM_INT_EN_CH0_INT_EN_SHIFT (0U) +#define PWM_INT_EN_CH0_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_INT_EN_SHIFT) /* 0x00000001 */ +#define PWM_INT_EN_CH1_INT_EN_SHIFT (1U) +#define PWM_INT_EN_CH1_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_INT_EN_SHIFT) /* 0x00000002 */ +#define PWM_INT_EN_CH2_INT_EN_SHIFT (2U) +#define PWM_INT_EN_CH2_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_INT_EN_SHIFT) /* 0x00000004 */ +#define PWM_INT_EN_CH3_INT_EN_SHIFT (3U) +#define PWM_INT_EN_CH3_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_INT_EN_SHIFT) /* 0x00000008 */ +#define PWM_INT_EN_CH0_PWR_INT_EN_SHIFT (4U) +#define PWM_INT_EN_CH0_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH0_PWR_INT_EN_SHIFT) /* 0x00000010 */ +#define PWM_INT_EN_CH1_PWR_INT_EN_SHIFT (5U) +#define PWM_INT_EN_CH1_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH1_PWR_INT_EN_SHIFT) /* 0x00000020 */ +#define PWM_INT_EN_CH2_PWR_INT_EN_SHIFT (6U) +#define PWM_INT_EN_CH2_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH2_PWR_INT_EN_SHIFT) /* 0x00000040 */ +#define PWM_INT_EN_CH3_PWR_INT_EN_SHIFT (7U) +#define PWM_INT_EN_CH3_PWR_INT_EN_MASK (0x1U << PWM_INT_EN_CH3_PWR_INT_EN_SHIFT) /* 0x00000080 */ +/* FIFO_CTRL */ +#define PWM_FIFO_CTRL_OFFSET (0x50U) +#define PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT (0U) +#define PWM_FIFO_CTRL_FIFO_MODE_SEL_MASK (0x1U << PWM_FIFO_CTRL_FIFO_MODE_SEL_SHIFT) /* 0x00000001 */ +#define PWM_FIFO_CTRL_FULL_INT_EN_SHIFT (1U) +#define PWM_FIFO_CTRL_FULL_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_FULL_INT_EN_SHIFT) /* 0x00000002 */ +#define PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT (2U) +#define PWM_FIFO_CTRL_OVERFLOW_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_OVERFLOW_INT_EN_SHIFT) /* 0x00000004 */ +#define PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT (3U) +#define PWM_FIFO_CTRL_WATERMARK_INT_EN_MASK (0x1U << PWM_FIFO_CTRL_WATERMARK_INT_EN_SHIFT) /* 0x00000008 */ +#define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT (4U) +#define PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_MASK (0x7U << PWM_FIFO_CTRL_ALMOST_FULL_WATERMARK_SHIFT) /* 0x00000070 */ +#define PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT (8U) +#define PWM_FIFO_CTRL_DMA_MODE_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_MODE_EN_SHIFT) /* 0x00000100 */ +#define PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT (9U) +#define PWM_FIFO_CTRL_TIMEOUT_EN_MASK (0x1U << PWM_FIFO_CTRL_TIMEOUT_EN_SHIFT) /* 0x00000200 */ +#define PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT (10U) +#define PWM_FIFO_CTRL_DMA_CH_SEL_EN_MASK (0x1U << PWM_FIFO_CTRL_DMA_CH_SEL_EN_SHIFT) /* 0x00000400 */ +#define PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT (12U) +#define PWM_FIFO_CTRL_DMA_CH_SEL_MASK (0x3U << PWM_FIFO_CTRL_DMA_CH_SEL_SHIFT) /* 0x00003000 */ +/* FIFO_INTSTS */ +#define PWM_FIFO_INTSTS_OFFSET (0x54U) +#define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT (0U) +#define PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_FULL_INTSTS_SHIFT) /* 0x00000001 */ +#define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT (1U) +#define PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_OVERFLOW_INTSTS_SHIFT) /* 0x00000002 */ +#define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT (2U) +#define PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_WATERMARK_FULL_INTSTS_SHIFT) /* 0x00000004 */ +#define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT (3U) +#define PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_MASK (0x1U << PWM_FIFO_INTSTS_TIMIEOUT_INTSTS_SHIFT) /* 0x00000008 */ +#define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT (4U) +#define PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_MASK (0x1U << PWM_FIFO_INTSTS_FIFO_EMPTY_STATUS_SHIFT) /* 0x00000010 */ +/* FIFO_TOUTTHR */ +#define PWM_FIFO_TOUTTHR_OFFSET (0x58U) +#define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT (0U) +#define PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_MASK (0xFFFFFU << PWM_FIFO_TOUTTHR_TIMEOUT_THRESHOLD_SHIFT) /* 0x000FFFFF */ +/* VERSION_ID */ +#define PWM_VERSION_ID_OFFSET (0x5CU) +#define PWM_VERSION_ID_SVN_VERSION_SHIFT (0U) +#define PWM_VERSION_ID_SVN_VERSION_MASK (0xFFFFU << PWM_VERSION_ID_SVN_VERSION_SHIFT) /* 0x0000FFFF */ +#define PWM_VERSION_ID_MINOR_VERSION_SHIFT (16U) +#define PWM_VERSION_ID_MINOR_VERSION_MASK (0xFFU << PWM_VERSION_ID_MINOR_VERSION_SHIFT) /* 0x00FF0000 */ +#define PWM_VERSION_ID_MAIN_VERSION_SHIFT (24U) +#define PWM_VERSION_ID_MAIN_VERSION_MASK (0xFFU << PWM_VERSION_ID_MAIN_VERSION_SHIFT) /* 0xFF000000 */ +/* FIFO */ +#define PWM_FIFO_OFFSET (0x60U) +#define PWM_FIFO (0x0U) +#define PWM_FIFO_CYCLE_CNT_SHIFT (0U) +#define PWM_FIFO_CYCLE_CNT_MASK (0x7FFFFFFFU << PWM_FIFO_CYCLE_CNT_SHIFT) /* 0x7FFFFFFF */ +#define PWM_FIFO_POL_SHIFT (31U) +#define PWM_FIFO_POL_MASK (0x1U << PWM_FIFO_POL_SHIFT) /* 0x80000000 */ +/* PWRMATCH_CTRL */ +#define PWM_PWRMATCH_CTRL_OFFSET (0x80U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT (3U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_ENABLE_SHIFT) /* 0x00000008 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT (7U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_POLARITY_SHIFT) /* 0x00000080 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT (11U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_CAPTURE_CTRL_SHIFT) /* 0x00000800 */ +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT (15U) +#define PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_MASK (0x1U << PWM_PWRMATCH_CTRL_CH3_PWRKEY_INT_CTRL_SHIFT) /* 0x00008000 */ +/* PWRMATCH_LPRE */ +#define PWM_PWRMATCH_LPRE_OFFSET (0x84U) +#define PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_LPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_LPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LPRE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HPRE */ +#define PWM_PWRMATCH_HPRE_OFFSET (0x88U) +#define PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HPRE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HPRE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HPRE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_LD */ +#define PWM_PWRMATCH_LD_OFFSET (0x8CU) +#define PWM_PWRMATCH_LD_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_LD_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_LD_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_LD_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_LD_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HD_ZERO */ +#define PWM_PWRMATCH_HD_ZERO_OFFSET (0x90U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HD_ZERO_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ZERO_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_HD_ONE */ +#define PWM_PWRMATCH_HD_ONE_OFFSET (0x94U) +#define PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT (0U) +#define PWM_PWRMATCH_HD_ONE_CNT_MIN_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MIN_SHIFT) /* 0x0000FFFF */ +#define PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT (16U) +#define PWM_PWRMATCH_HD_ONE_CNT_MAX_MASK (0xFFFFU << PWM_PWRMATCH_HD_ONE_CNT_MAX_SHIFT) /* 0xFFFF0000 */ +/* PWRMATCH_VALUE0 */ +#define PWM_PWRMATCH_VALUE0_OFFSET (0x98U) +#define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE0_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE1 */ +#define PWM_PWRMATCH_VALUE1_OFFSET (0x9CU) +#define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE1_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE2 */ +#define PWM_PWRMATCH_VALUE2_OFFSET (0xA0U) +#define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE2_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE3 */ +#define PWM_PWRMATCH_VALUE3_OFFSET (0xA4U) +#define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE3_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE4 */ +#define PWM_PWRMATCH_VALUE4_OFFSET (0xA8U) +#define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE4_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE5 */ +#define PWM_PWRMATCH_VALUE5_OFFSET (0xACU) +#define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE5_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE6 */ +#define PWM_PWRMATCH_VALUE6_OFFSET (0xB0U) +#define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE6_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE7 */ +#define PWM_PWRMATCH_VALUE7_OFFSET (0xB4U) +#define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE7_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE8 */ +#define PWM_PWRMATCH_VALUE8_OFFSET (0xB8U) +#define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE8_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWRMATCH_VALUE9 */ +#define PWM_PWRMATCH_VALUE9_OFFSET (0xBCU) +#define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT (0U) +#define PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_MASK (0xFFFFFFFFU << PWM_PWRMATCH_VALUE9_PWRKEY_MATCH_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* PWM3_PWRCAPTURE_VALUE */ +#define PWM_PWM3_PWRCAPTURE_VALUE_OFFSET (0xCCU) +#define PWM_PWM3_PWRCAPTURE_VALUE (0x0U) +#define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT (0U) +#define PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_MASK (0xFFFFFFFFU << PWM_PWM3_PWRCAPTURE_VALUE_PWRKEY_CAPTURE_VALUE_SHIFT) /* 0xFFFFFFFF */ +/* FILTER_CTRL */ +#define PWM_FILTER_CTRL_OFFSET (0xD0U) +#define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT (0U) +#define PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH0_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000001 */ +#define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT (1U) +#define PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH1_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000002 */ +#define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT (2U) +#define PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH2_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000004 */ +#define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT (3U) +#define PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_MASK (0x1U << PWM_FILTER_CTRL_CH3_INPUT_FILTER_ENABLE_SHIFT) /* 0x00000008 */ +#define PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT (4U) +#define PWM_FILTER_CTRL_FILTER_NUMBER_MASK (0x1FFU << PWM_FILTER_CTRL_FILTER_NUMBER_SHIFT) /* 0x00001FF0 */ +#define PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_SHIFT (16U) +#define PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH0_AND_CH3_SWITCH_EN_SHIFT) /* 0x00010000 */ +#define PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_SHIFT (17U) +#define PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH1_AND_CH3_SWITCH_EN_SHIFT) /* 0x00020000 */ +#define PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_SHIFT (18U) +#define PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_MASK (0x1U << PWM_FILTER_CTRL_CH2_AND_CH3_SWITCH_EN_SHIFT) /* 0x00040000 */ + +#define RK3588_PWM0_BASE 0xfd8b0000 +#define RK3588_PWM1_BASE 0xfebd0000 +#define RK3588_PWM2_BASE 0xfebe0000 +#define RK3588_PWM3_BASE 0xfebf0000 +#define RK3588_PWM_SIZE 0x10000 + +enum PWM_CONTROLLER_ID { + PWM_CONTROLLER0, + PWM_CONTROLLER1, + PWM_CONTROLLER2, + PWM_CONTROLLER3 +}; + +enum PWM_CHANNEL_ID { + PWM_CHANNEL0, + PWM_CHANNEL1, + PWM_CHANNEL2, + PWM_CHANNEL3 +}; + +typedef struct { + UINT8 ControllerID; + UINT8 ChannelID; + UINT32 PeriodNs; + UINT32 DutyNs; + BOOLEAN Polarity; +} PWM_DATA; + +RETURN_STATUS +EFIAPI +RkPwmSetConfig ( + IN PWM_DATA *Data + ); + +RETURN_STATUS +EFIAPI +RkPwmEnable ( + IN PWM_DATA *Data + ); + +RETURN_STATUS +EFIAPI +RkPwmDisable ( + IN PWM_DATA *Data + ); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RK806.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RK806.h new file mode 100644 index 0000000..cf49bd4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RK806.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __RK_806_H +#define __RK_806_H + +#include +#include "Soc.h" + +/* Not used or exisit register and configure */ +#define NA -1 +#define BIT(n) (1 << (n)) +/* rk806 buck*/ +#define RK806_BUCK_ON_VSEL(n) (0x1a + n - 1) +#define RK806_BUCK_SLP_VSEL(n) (0x24 + n - 1) +#define RK806_BUCK_CONFIG(n) (0x10 + n - 1) +#define RK806_BUCK_VSEL_MASK 0xff + +/* RK806 LDO */ +#define RK806_NLDO_ON_VSEL(n) (0x43 + n - 1) +#define RK806_NLDO_SLP_VSEL(n) (0x48 + n - 1) +#define RK806_NLDO_VSEL_MASK 0xff +#define RK806_PLDO_ON_VSEL(n) (0x4e + n - 1) +#define RK806_PLDO_SLP_VSEL(n) (0x54 + n - 1) +#define RK806_PLDO_VSEL_MASK 0xff + +/* RK806 ENABLE */ +#define RK806_POWER_EN(n) (0x00 + n) +#define RK806_NLDO_EN(n) (0x03 + n) +#define RK806_PLDO_EN(n) (0x04 + n) +#define RK806_RAMP_RATE_MASK1 0xc0 +#define RK806_RAMP_RATE_REG1(n) (0x10 + n) +#define RK806_RAMP_RATE_REG1_8 0xeb +#define RK806_RAMP_RATE_REG9_10 0xea + +#define RK806_RAMP_RATE_4LSB_PER_1CLK 0x00/* LDO 100mV/uS buck 50mV/us */ +#define RK806_RAMP_RATE_2LSB_PER_1CLK 0x01/* LDO 50mV/uS buck 25mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_1CLK 0x02/* LDO 25mV/uS buck 12.5mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_2CLK 0x03/* LDO 12.5mV/uS buck 6.25mV/us */ + +#define RK806_RAMP_RATE_1LSB_PER_4CLK 0x04/* LDO 6.28/2mV/uS buck 3.125mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_8CLK 0x05/* LDO 3.12mV/uS buck 1.56mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_13CLK 0x06/* LDO 1.9mV/uS buck 961mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_32CLK 0x07/* LDO 0.78mV/uS buck 0.39mV/us */ + +#define RK806_PLDO0_2_MSK(pldo) (BIT(pldo + 5)) +#define RK806_PLDO0_2_SET(pldo) (BIT(pldo + 1) | RK806_PLDO0_2_MSK(pldo)) +#define RK806_PLDO0_2_CLR(pldo) RK806_PLDO0_2_MSK(pldo) + +#define RK806_CHIP_NAME 0x5A +#define RK806_CHIP_VER 0x5B + +#define RK806_CMD_READ 0 +#define RK806_CMD_WRITE BIT(7) +#define RK806_CMD_CRC_EN BIT(6) +#define RK806_CMD_CRC_DIS 0 +#define RK806_CMD_LEN_MSK 0x0f +#define RK806_REG_H 0x00 + +#define RK806_SYS_CFG1 0x5f +#define RK806_SYS_CFG3 0x72 +#define RK806_PWRON_KEY 0x76 +#define RK806_INT_STS0 0x77 +#define RK806_INT_MSK0 0x78 +#define RK806_INT_STS1 0x79 +#define RK806_INT_MSK1 0x7A +#define RK806_GPIO_INT_CONFIG 0x7B +#define RK806_IRQ_PWRON_FALL_MSK BIT(0) +#define RK806_IRQ_PWRON_RISE_MSK BIT(1) +#define RK806_DEV_OFF BIT(0) +#define RK806_RST_MODE1 0x01 +#define RK806_RST_MODE2 0x02 +#define VERSION_AB 0x01 + +struct regulator_init_data { + const char *supply_regulator; /* or NULL for system supply */ + INT32 reg_id; + INT32 init_voltage_mv; +}; + +struct rk8xx_reg_info { + UINT32 min_uv; + UINT32 step_uv; + UINT8 vsel_reg; + UINT8 vsel_sleep_reg; + UINT8 config_reg; + UINT8 vsel_mask; + UINT8 min_sel; + /* only for buck now */ + UINT8 max_sel; + UINT8 range_num; +}; + +#define RK8XX_DESC_COM(_name, _reg_info, _ops) \ +{ \ + .reg_info = (_reg_info), \ + .name = (_reg_id), \ + .ops = _ops, \ +} + +#define RK8XX_VOLTAGE_INIT(_id, _voltage) \ +{ \ + .reg_id = (_id),\ + .init_voltage_mv = (_voltage),\ +} + +/****************************************** +8 -12: MASTER, SLAVE +4 -7: BUCK, NLDO, PLDO +0 -3: num +******************************************/ +#define MASTER (0x0 << 8) +#define SLAVER (0x1 << 8) +#define BUCK (0x0 << 4) +#define NLDO (0x1 << 4) +#define PLDO (0x2 << 4) + +enum master_num { + MASTER_BUCK1 = (MASTER | BUCK | 0), + MASTER_BUCK2 = (MASTER | BUCK | 1), + MASTER_BUCK3 = (MASTER | BUCK | 2), + MASTER_BUCK4 = (MASTER | BUCK | 3), + MASTER_BUCK5 = (MASTER | BUCK | 4), + MASTER_BUCK6 = (MASTER | BUCK | 5), + MASTER_BUCK7 = (MASTER | BUCK | 6), + MASTER_BUCK8 = (MASTER | BUCK | 7), + MASTER_BUCK9 = (MASTER | BUCK | 8), + MASTER_BUCK10 = (MASTER | BUCK | 9), + + MASTER_NLDO1 = (MASTER | NLDO | 0), + MASTER_NLDO2 = (MASTER | NLDO | 1), + MASTER_NLDO3 = (MASTER | NLDO | 2), + MASTER_NLDO4 = (MASTER | NLDO | 3), + MASTER_NLDO5 = (MASTER | NLDO | 4), + + MASTER_PLDO1 = (MASTER | PLDO | 0), + MASTER_PLDO2 = (MASTER | PLDO | 1), + MASTER_PLDO3 = (MASTER | PLDO | 2), + MASTER_PLDO4 = (MASTER | PLDO | 3), + MASTER_PLDO5 = (MASTER | PLDO | 4), + MASTER_PLDO6 = (MASTER | PLDO | 5), +}; + +enum slaver_num { + SLAVER_BUCK1 = (SLAVER | BUCK | 0), + SLAVER_BUCK2 = (SLAVER | BUCK | 1), + SLAVER_BUCK3 = (SLAVER | BUCK | 2), + SLAVER_BUCK4 = (SLAVER | BUCK | 3), + SLAVER_BUCK5 = (SLAVER | BUCK | 4), + SLAVER_BUCK6 = (SLAVER | BUCK | 5), + SLAVER_BUCK7 = (SLAVER | BUCK | 6), + SLAVER_BUCK8 = (SLAVER | BUCK | 7), + SLAVER_BUCK9 = (SLAVER | BUCK | 8), + SLAVER_BUCK10 = (SLAVER | BUCK | 9), + + SLAVER_NLDO1 = (SLAVER | NLDO | 0), + SLAVER_NLDO2 = (SLAVER | NLDO | 1), + SLAVER_NLDO3 = (SLAVER | NLDO | 2), + SLAVER_NLDO4 = (SLAVER | NLDO | 3), + SLAVER_NLDO5 = (SLAVER | NLDO | 4), + + SLAVER_PLDO1 = (SLAVER | PLDO | 0), + SLAVER_PLDO2 = (SLAVER | PLDO | 1), + SLAVER_PLDO3 = (SLAVER | PLDO | 2), + SLAVER_PLDO4 = (SLAVER | PLDO | 3), + SLAVER_PLDO5 = (SLAVER | PLDO | 4), + SLAVER_PLDO6 = (SLAVER | PLDO | 5), +}; + +extern RETURN_STATUS RK806Init(void); +extern void RK806RegulatorInit(struct regulator_init_data init_data); + +#endif \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RkAtagsLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RkAtagsLib.h new file mode 100644 index 0000000..a333219 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RkAtagsLib.h @@ -0,0 +1,208 @@ +/** @file + * + * Rockchip ATAGS library. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef RKATAGSLIB_H__ +#define RKATAGSLIB_H__ + +/* + These Atags get populated by earlier boot stages (U-Boot, ATF). + Some may be unavailable depending on the platform. + + It's also possible to write new/existing tags, but we won't support that + since there are more appropriate ways to pass configuration data around + from the UEFI. +*/ + +typedef enum { + RkAtagSerialMuxM0 = 0, + RkAtagSerialMuxM1 = 1, + RkAtagSerialMuxM2 = 2 +} RKATAG_SERIAL_MUX_MODE; + +typedef enum { + RkAtagBootDevTypeUnknown = 0, + RkAtagBootDevTypeNand = BIT0, + RkAtagBootDevTypeEmmc = BIT1, + RkAtagBootDevTypeSd0 = BIT2, + RkAtagBootDevTypeSd1 = BIT3, + RkAtagBootDevTypeSpiNor = BIT4, + RkAtagBootDevTypeSpiNand = BIT5, + RkAtagBootDevTypeRam = BIT6, + RkAtagBootDevTypeMtdBlkNand = BIT7, + RkAtagBootDevTypeMtdBlkSpiNand = BIT8, + RkAtagBootDevTypeMtdBlkSpiNor = BIT9, + RkAtagBootDevTypeSata = BIT10, + RkAtagBootDevTypePcie = BIT11 +} RKATAG_BOOTDEV_TYPE; + +typedef enum { + RkAtagBootDevSdCardUnknown = 0, + RkAtagBootDevSdCardUpdate = 1 +} RKATAG_BOOTDEV_SDCARD_UPDATE; + +typedef enum { + RkAtagDdrMemExtTop = 1 +} RKATAG_DDR_MEM_FLAG; + +typedef enum { + RkAtagPubKeyFuseProgrammed = 0x4B415352 +} RKATAG_PUB_KEY_FLAG; + +typedef enum { + RkAtagSocInfoFlagTdbt = BIT0 +} RKATAG_SOC_INFO_FLAG; + +#define BOOT1_PARAM2_BOOT_CPU_HWID_MASK 0x0000001F + +#pragma pack(1) + +typedef struct { + UINT32 Version; + UINT32 Enable; + UINT64 Address; + UINT32 BaudRate; + RKATAG_SERIAL_MUX_MODE MuxMode; + UINT32 Id; + UINT32 Reserved[2]; +} RKATAG_SERIAL; + +typedef struct { + UINT32 Version; + RKATAG_BOOTDEV_TYPE DevType; + UINT32 DevNum; + UINT32 Mode; + RKATAG_BOOTDEV_SDCARD_UPDATE SdUpdate; + UINT32 Reserved[6]; +} RKATAG_BOOTDEV; + +typedef struct { + UINT32 Count; + UINT32 Version; + UINT64 Bank[20]; + RKATAG_DDR_MEM_FLAG Flags; + UINT32 Data[2]; +} RKATAG_DDR_MEM; + +typedef struct { + UINT32 Version; + struct { + CHAR8 Name[8]; + UINT64 PhyAddr; + UINT32 Size; + UINT32 Flags; + } TeeMem; + + struct { + CHAR8 Name[8]; + UINT64 PhyAddr; + UINT32 Size; + UINT32 Flags; + } DrmMem; + + UINT32 Reserved[15]; +} RKATAG_TOS_MEM; + +typedef struct { + UINT32 Version; + UINT32 Count; + UINT32 Reserved[4]; + + struct { + CHAR8 Name[16]; + UINT64 Start; + UINT64 Size; + } Partition[6]; + + UINT32 Reserved1[3]; +} RKATAG_RAM_PARTITION; + +typedef struct { + UINT32 Version; + UINT64 PhyAddr; + UINT32 Size; + UINT32 Flags; + UINT32 Reserved[2]; +} RKATAG_ATF_MEM; + +typedef struct { + UINT32 Version; + UINT32 Len; + + struct { + UINT32 RsaN[64]; + UINT32 RsaE[64]; + UINT32 RsaC[64]; + } Data; + + UINT32 Flags; + UINT32 Reserved[5]; +} RKATAG_PUB_KEY; + +typedef struct { + UINT32 Version; + UINT32 HexName; + RKATAG_SOC_INFO_FLAG Flags; + UINT32 Reserved[6]; +} RKATAG_SOC_INFO; + +typedef struct { + UINT32 Version; + UINT32 Param[8]; + UINT32 Reserved[4]; +} RKATAG_BOOT1_PARAM; + +#pragma pack() + +RKATAG_SERIAL * +RkAtagsGetSerial ( + VOID + ); + +RKATAG_BOOTDEV * +RkAtagsGetBootDev ( + VOID + ); + +RKATAG_DDR_MEM * +RkAtagsGetDdrMem ( + VOID + ); + +RKATAG_TOS_MEM * +RkAtagsGetTosMem ( + VOID + ); + +RKATAG_RAM_PARTITION * +RkAtagsGetRamPartition ( + VOID + ); + +RKATAG_ATF_MEM * +RkAtagsGetAtfMem ( + VOID + ); + +RKATAG_PUB_KEY * +RkAtagsGetPubKey ( + VOID + ); + +RKATAG_SOC_INFO * +RkAtagsGetSocInfo ( + VOID + ); + +RKATAG_BOOT1_PARAM * +RkAtagsGetBoot1Param ( + VOID + ); + +#endif /* RKATAGSLIB_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RkSdmmcPlatformLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RkSdmmcPlatformLib.h new file mode 100644 index 0000000..606e522 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RkSdmmcPlatformLib.h @@ -0,0 +1,33 @@ +/** @file + * + * RkSdmmcDxe platform helper library. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +typedef enum { + RkSdmmcCardPresenceUnsupported = 0, + RkSdmmcCardPresent, + RkSdmmcCardNotPresent +} RKSDMMC_CARD_PRESENCE_STATE; + +EFI_STATUS +EFIAPI +RkSdmmcSetClockRate ( + IN UINTN Frequency + ); + +VOID +EFIAPI +RkSdmmcSetIoMux ( + VOID + ); + +RKSDMMC_CARD_PRESENCE_STATE +EFIAPI +RkSdmmcGetCardPresenceState ( + VOID + ); diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipDisplayLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipDisplayLib.h new file mode 100644 index 0000000..9f9c875 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipDisplayLib.h @@ -0,0 +1,285 @@ +/** @file + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef __ROCKCHIP_DISPLAY_H__ +#define __ROCKCHIP_DISPLAY_H__ + +#include +#include +#include + +#define LIST_FOR_EACH_ENTRY(Pos, Head, Member) \ + for (Pos = BASE_CR((Head)->ForwardLink, typeof(*Pos), Member); \ + &Pos->Member != (Head); \ + Pos = BASE_CR(Pos->Member.ForwardLink, typeof(*Pos), Member)) + +#define __ROUND_MASK(x, y) ((__typeof__(x))((y)-1)) +#define ROUNDUP(x, y) ((((x)-1) | __ROUND_MASK(x, y))+1) +#define ROUNDDOWN(x, y) ((x) & ~__ROUND_MASK(x, y)) +#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) + +#define INLINE static inline + +#define EDID_SIZE 128 + +typedef enum { + ROCKCHIP_DISPLAY_FULLSCREEN, + ROCKCHIP_DISPLAY_CENTER, +} LOGO_DISPLAY_MODE; + +typedef enum { + ROCKCHIP_FMT_ARGB8888 = 0, + ROCKCHIP_FMT_RGB888, + ROCKCHIP_FMT_RGB565, + ROCKCHIP_FMT_YUV420SP = 4, + ROCKCHIP_FMT_YUV422SP, + ROCKCHIP_FMT_YUV444SP, +} DATA_FORMAT; + +#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0) +#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1) +#define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2) +#define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3) + +#define ROCKCHIP_DSC_PPS_SIZE_BYTE 88 + +/* + * display output interface supported by rockchip lcdc + */ +#define ROCKCHIP_OUT_MODE_P888 0 +#define ROCKCHIP_OUT_MODE_BT1120 0 +#define ROCKCHIP_OUT_MODE_P666 1 +#define ROCKCHIP_OUT_MODE_P565 2 +#define ROCKCHIP_OUT_MODE_BT656 5 +#define ROCKCHIP_OUT_MODE_S888 8 +#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 +#define ROCKCHIP_OUT_MODE_YUV420 14 +/* for use special outface */ +#define ROCKCHIP_OUT_MODE_AAAA 15 + +#define VOP_OUTPUT_IF_RGB BIT(0) +#define VOP_OUTPUT_IF_BT1120 BIT(1) +#define VOP_OUTPUT_IF_BT656 BIT(2) +#define VOP_OUTPUT_IF_LVDS0 BIT(3) +#define VOP_OUTPUT_IF_LVDS1 BIT(4) +#define VOP_OUTPUT_IF_MIPI0 BIT(5) +#define VOP_OUTPUT_IF_MIPI1 BIT(6) +#define VOP_OUTPUT_IF_eDP0 BIT(7) +#define VOP_OUTPUT_IF_eDP1 BIT(8) +#define VOP_OUTPUT_IF_DP0 BIT(9) +#define VOP_OUTPUT_IF_DP1 BIT(10) +#define VOP_OUTPUT_IF_HDMI0 BIT(11) +#define VOP_OUTPUT_IF_HDMI1 BIT(12) + +typedef struct { + UINT32 Mode; + UINT32 Offset; + UINT32 Width; + UINT32 Height; + UINT32 Bpp; + CHAR8 *Memory; + BOOLEAN YMirror; +} LOGO_INFO; + +typedef struct { + UINT32 Width; + UINT32 Height; +} VOP_RECT; + +struct rockchip_dsc_sink_cap { + /** + * @slice_width: the number of pixel columns that comprise the slice width + * @slice_height: the number of pixel rows that comprise the slice height + * @block_pred: Does block prediction + * @native_420: Does sink support DSC with 4:2:0 compression + * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc + * @version_major: DSC major version + * @version_minor: DSC minor version + * @target_bits_per_pixel_x16: bits num after compress and multiply 16 + */ + UINT16 slice_width; + UINT16 slice_height; + BOOLEAN block_pred; + BOOLEAN native_420; + UINT8 bpc_supported; + UINT8 version_major; + UINT8 version_minor; + UINT16 target_bits_per_pixel_x16; +}; + +typedef struct { + UINT32 LeftMargin; + UINT32 RightMargin; + UINT32 TopMargin; + UINT32 BottomMargin; +} OVER_SCAN; + +typedef struct { + /* Proposed mode values */ + UINT32 Clock; /* in kHz */ + UINT32 HDisplay; + UINT32 HSyncStart; + UINT32 HSyncEnd; + UINT32 HTotal; + UINT32 VDisplay; + UINT32 VSyncStart; + UINT32 VSyncEnd; + UINT32 VTotal; + UINT32 VRefresh; + UINT32 VScan; + UINT32 Flags; + UINT32 PictureAspectRatio; + UINT32 HSkew; + UINT32 Type; + /* Actual mode we give to hw */ + UINT32 CrtcClock; /* in KHz */ + UINT32 CrtcHDisplay; + UINT32 CrtcHBlankStart; + UINT32 CrtcHBblankEnd; + UINT32 CrtcHSyncStart; + UINT32 CrtcHSyncEnd; + UINT32 CrtcHTotal; + UINT32 CrtcHSkew; + UINT32 CrtcVDisplay; + UINT32 CrtcVBlankStart; + UINT32 CrtcVBlankEnd; + UINT32 CrtcVSyncStart; + UINT32 CrtcVSyncEnd; + UINT32 CrtcVTotal; + BOOLEAN Invalid; +} DRM_DISPLAY_MODE; + +typedef struct { + UINT16 Brightness; + UINT16 Contrast; + UINT16 Saturation; + UINT16 Hue; +} BASE_BCSH_INFO; + +typedef struct { + INT8 DispHeadFlag[6]; + /* struct base2_screen_info screen_info[4]; --- todo */ + BASE_BCSH_INFO BCSHInfo; + /* struct base_overscan overscan_info; --- todo */ + /* struct base2_gamma_lut_data gamma_lut_data; --- todo */ + /* struct base2_cubic_lut_data cubic_lut_data; --- todo */ + /* struct framebuffer_info framebuffer_info; --- todo */ + UINT32 Reserved[244]; + UINT32 CRC; +} BASE2_DISP_INFO; + +typedef struct { + VOID *Connector; + OVER_SCAN OverScan; + DRM_DISPLAY_MODE DisplayMode; + BASE2_DISP_INFO *DispInfo; /* disp_info from baseparameter 2.0 */ + UINT8 EDID[EDID_SIZE * 4]; + UINT32 BusFormat; + UINT32 OutputMode; + UINT32 Type; + UINT32 OutputInterface; + UINT32 OutputFlags; + UINT32 ColorSpace; + UINT32 BPC; + + /** + * @hold_mode: enabled when it's: + * (1) mcu hold mode + * (2) mipi dsi cmd mode + * (3) edp psr mode + */ + BOOLEAN hold_mode; +} CONNECTOR_STATE; + +typedef struct { + VOID *Crtc; + VOID *Private; + UINT32 CrtcID; + UINT32 Format; + UINT32 YMirror; + UINT32 RBSwap; + UINT32 XVirtual; + UINT32 SrcX; + UINT32 SrcY; + UINT32 SrcW; + UINT32 SrcH; + UINT32 CrtcX; + UINT32 CrtcY; + UINT32 CrtcW; + UINT32 CrtcH; + UINT32 Feature; + UINT32 DMAAddress; + BOOLEAN YUVOverlay; + VOP_RECT MaxOutput; + + UINT32 DclkCoreDiv; + UINT32 DclkOutDiv; + + UINT8 dsc_id; + UINT8 dsc_enable; + UINT8 dsc_slice_num; + UINT8 dsc_pixel_num; + UINT64 dsc_txp_clk_rate; + UINT64 dsc_pxl_clk_rate; + UINT64 dsc_cds_clk_rate; + struct drm_dsc_picture_parameter_set pps; + struct rockchip_dsc_sink_cap dsc_sink_cap; +} CRTC_STATE; + +typedef struct { + LIST_ENTRY ListHead; + CRTC_STATE CrtcState; + CONNECTOR_STATE ConnectorState; + + UINT32 ModeNumber; + INT32 VpsConfigModeID; + + VOID *MemoryBase; + UINT32 MemorySize; + + BOOLEAN IsInit; + BOOLEAN IsEnable; + + BOOLEAN IsForceOutput; + UINT32 ForceOutputFormat; +} DISPLAY_STATE; + +typedef struct { + UINT32 Resolution; + UINT32 Sync; + UINT32 BackPorch; + UINT32 FrontPorch; +} SCAN_TIMINGS; + +typedef struct { + UINT32 CrtcId; + UINT32 OscFreq; + SCAN_TIMINGS Horizontal; + SCAN_TIMINGS Vertical; + UINT32 HsyncActive; + UINT32 VsyncActive; + UINT32 DenActive; + UINT32 ClkActive; + UINT32 VpsConfigModeID; +} DISPLAY_MODE; + +EFIAPI +EFI_STATUS +DisplaySetCrtcInfo ( + OUT DRM_DISPLAY_MODE *Mode, + IN UINT32 AdjustFlags + ); + +UINT32 +EFIAPI +DrmModeVRefresh ( + DRM_DISPLAY_MODE *Mode + ); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h new file mode 100644 index 0000000..9b93e42 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/RockchipPlatformLib.h @@ -0,0 +1,155 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __PALTFORM_LIB_H__ +#define __PALTFORM_LIB_H__ + +#include + +VOID +EFIAPI +SdmmcIoMux ( + VOID + ); + +VOID +EFIAPI +SdhciEmmcIoMux ( + VOID + ); + +VOID +EFIAPI +EnableBacklight ( + IN BOOLEAN en + ); + +VOID +EFIAPI +EnablePWM ( + IN BOOLEAN en + ); + +VOID +EFIAPI +GmacIomux ( + IN UINT32 Id + ); + +VOID +EFIAPI +GmacIoPhyReset ( + IN UINT32 Id, + IN BOOLEAN Enable + ); + +VOID +EFIAPI +Rk806SpiIomux ( + VOID + ); + +VOID +EFIAPI +Rk806Configure ( + VOID + ); + +VOID +EFIAPI +SetCPULittleVoltage ( + IN UINT32 Microvolts + ); + +VOID +EFIAPI +NorFspiIomux ( + VOID + ); + +VOID +EFIAPI +NorFspiEnableClock ( + UINT32 *CruBase + ); + +VOID +EFIAPI +I2cIomux ( + UINT32 id + ); + +VOID +EFIAPI +UsbPortPowerEnable ( + VOID + ); + +VOID +EFIAPI +Usb2PhyResume ( + VOID + ); + +VOID +EFIAPI +PcieIoInit ( + UINT32 Segment + ); + +VOID +EFIAPI +PciePowerEn ( + UINT32 Segment, + BOOLEAN Enable + ); + +VOID +EFIAPI +PciePeReset ( + UINT32 Segment, + BOOLEAN Enable + ); + +VOID +EFIAPI +PwmFanIoSetup ( + VOID + ); + +VOID +EFIAPI +PwmFanSetSpeed ( + IN UINT32 Percentage + ); + +VOID +EFIAPI +PlatformInitLeds ( + VOID + ); + +VOID +EFIAPI +PlatformSetStatusLed ( + IN BOOLEAN Enable + ); + +VOID +EFIAPI +PlatformEarlyInit ( + VOID + ); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SdramLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SdramLib.h new file mode 100644 index 0000000..7faf26c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SdramLib.h @@ -0,0 +1,17 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef SDRAMLIB_H__ +#define SDRAMLIB_H__ + +UINT64 +SdramGetMemorySize ( + VOID + ); + +#endif /* SDRAMLIB_H__ */ \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Snor.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Snor.h new file mode 100644 index 0000000..930feab --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Snor.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_SFC_NOR_H_ +#define _HAL_SFC_NOR_H_ + +/***************************** Structure Definition **************************/ + +#define SPI_NOR_MAX_CMD_SIZE 8 +#define SNOR_SPEED_MAX 133000000 +#define SNOR_SPEED_DEFAULT 80000000 + +#define SNOR_PROTO_STR(a, b, c) (((a) << 8) | ((b) << 4) | (c)) + +#define SNOR_GET_PROTOCOL_ADDR_BITS(proto) (((proto) >> 4) & 0xf) +#define SNOR_GET_PROTOCOL_DATA_BITS(proto) ((proto) & 0xf) + +enum SPI_NOR_PROTOCOL { + SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), + SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2), + SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4), + SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8), + SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2), + SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4), + SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8), + SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2), + SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4), + SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8), +}; + +/* Flash opcodes. */ +#define SPINOR_OP_WREN 0x06 /**< Write enable */ +#define SPINOR_OP_RDSR 0x05 /**< Read status register */ +#define SPINOR_OP_WRSR 0x01 /**< Write status register 1 byte */ +#define SPINOR_OP_RDSR1 0x35 /**< Read status register 1 */ +#define SPINOR_OP_WRSR1 0x31 /**< Write status register 1 */ +#define SPINOR_OP_RDSR2 0x15 /**< Read status register 2 */ +#define SPINOR_OP_WRSR2 0x3e /**< Write status register 2 */ +#define SPINOR_OP_READ 0x03 /**< Read data bytes (low frequency) */ +#define SPINOR_OP_READ_FAST 0x0b /**< Read data bytes (high frequency) */ +#define SPINOR_OP_READ_1_1_2 0x3b /**< Read data bytes (Dual Output SPI) */ +#define SPINOR_OP_READ_1_2_2 0xbb /**< Read data bytes (Dual I/O SPI) */ +#define SPINOR_OP_READ_1_1_4 0x6b /**< Read data bytes (Quad Output SPI) */ +#define SPINOR_OP_READ_1_4_4 0xeb /**< Read data bytes (Quad I/O SPI) */ +#define SPINOR_OP_READ_EC 0xec /**< Read data bytes (Quad I/O SPI) 4 byte address */ +#define SPINOR_OP_PP 0x02 /**< Page program (up to 256 bytes) */ +#define SPINOR_OP_PP_1_1_4 0x32 /**< Quad page program */ +#define SPINOR_OP_PP_1_4_4 0x38 /**< Quad page program */ +#define SPINOR_OP_BE_4K 0x20 /**< Erase 4KiB block */ +#define SPINOR_OP_BE_4K_PMC 0xd7 /**< Erase 4KiB block on PMC chips */ +#define SPINOR_OP_BE_32K 0x52 /**< Erase 32KiB block */ +#define SPINOR_OP_CHIP_ERASE 0xc7 /**< Erase whole flash chip */ +#define SPINOR_OP_SE 0xd8 /**< Sector erase (usually 64KiB) */ +#define SPINOR_OP_RDID 0x9f /**< Read JEDEC ID */ +#define SPINOR_OP_RDSFDP 0x5a /**< Read SFDP */ +#define SPINOR_OP_RDCR 0x15 /**< Read configuration register */ +#define SPINOR_OP_WRCR 0x11 /**< Write configuration register */ +#define SPINOR_OP_RDFSR 0x70 /**< Read flag status register */ +#define SPINOR_OP_CLFSR 0x50 /**< Clear flag status register */ +#define SPINOR_OP_RDEAR 0xc8 /**< Read Extended Address Register */ +#define SPINOR_OP_WREAR 0xc5 /**< Write Extended Address Register */ +#define SPINOR_OP_READ_UUID 0x4b /**< Read SPI Nor UUID */ +#define SPINOR_OP_READ_SFDP 0x5A /**< Read SPI Nor SFDP */ + +struct SPI_NOR { + struct HAL_FSPI_HOST *spi; + const struct FLASH_INFO *info; + UINT32 pageSize; + UINT8 addrWidth; + UINT8 eraseOpcodeSec; + UINT8 eraseOpcodeBlk; + UINT8 readOpcode; + UINT8 readDummy; + UINT8 programOpcode; + + enum SPI_NOR_PROTOCOL readProto; + enum SPI_NOR_PROTOCOL writeProto; + UINT8 cmdBuf[SPI_NOR_MAX_CMD_SIZE]; + + UINT32 size; + UINT32 sectorSize; + UINT32 eraseSize; +}; + +typedef enum { + ERASE_SECTOR = 0, + ERASE_BLOCK64K, + ERASE_CHIP +} NOR_ERASE_TYPE; + +RETURN_STATUS HAL_SNOR_Init(struct SPI_NOR *nor); +RETURN_STATUS HAL_SNOR_DeInit(struct SPI_NOR *nor); +UINT32 HAL_SNOR_GetCapacity(struct SPI_NOR *nor); +RETURN_STATUS HAL_SNOR_ReadID(struct SPI_NOR *nor, UINT8 *data); +RETURN_STATUS HAL_SNOR_ReadData(struct SPI_NOR *nor, UINT32 from, void *buf, UINT32 len); +RETURN_STATUS HAL_SNOR_ProgData(struct SPI_NOR *nor, UINT32 to, void *buf, UINT32 len); +RETURN_STATUS HAL_SNOR_Read(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData); +RETURN_STATUS HAL_SNOR_Write(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData); +RETURN_STATUS HAL_SNOR_OverWrite(struct SPI_NOR *nor, UINT32 sec, UINT32 nSec, void *pData); +RETURN_STATUS HAL_SNOR_Erase(struct SPI_NOR *nor, UINT32 addr, NOR_ERASE_TYPE EraseType); +BOOLEAN HAL_SNOR_IsFlashSupported(UINT8 *flashId); +RETURN_STATUS HAL_SNOR_ReadUUID(struct SPI_NOR *nor, void *buf); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SpiLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SpiLib.h new file mode 100644 index 0000000..216d4db --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SpiLib.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef __RK_SPI_H +#define __RK_SPI_H + +#define HAL_SPI_MASTER_MAX_SCLK_OUT 50000000 /**< Max io clock in master mode */ +#define HAL_SPI_SLAVE_MAX_SCLK_OUT 20000000 /**< Max io in clock in slave mode */ + +#define CR0_DATA_FRAME_SIZE_4BIT (0x00 << SPI_CTRLR0_DFS_SHIFT) +#define CR0_DATA_FRAME_SIZE_8BIT (0x01 << SPI_CTRLR0_DFS_SHIFT) +#define CR0_DATA_FRAME_SIZE_16BIT (0x02 << SPI_CTRLR0_DFS_SHIFT) + +/* serial clock toggles in middle of first data bit */ +#define CR0_PHASE_1EDGE (0x00 << SPI_CTRLR0_SCPH_SHIFT) +/* serial clock toggles at start of first data bit */ +#define CR0_PHASE_2EDGE (0x01 << SPI_CTRLR0_SCPH_SHIFT) + +#define CR0_POLARITY_LOW (0x00 << SPI_CTRLR0_SCPOL_SHIFT) +#define CR0_POLARITY_HIGH (0x01 << SPI_CTRLR0_SCPOL_SHIFT) + +/* + * The period between ss_n active and + * sclk_out active is half sclk_out cycles + */ +#define CR0_SSD_HALF (0x00 << SPI_CTRLR0_SSD_SHIFT) +/* + * The period between ss_n active and + * sclk_out active is one sclk_out cycle + */ +#define CR0_SSD_ONE (0x01 << SPI_CTRLR0_SSD_SHIFT) + +#define CR0_EM_LITTLE (0x0 << SPI_CTRLR0_EM_SHIFT) +#define CR0_EM_BIG (0x1 << SPI_CTRLR0_EM_SHIFT) + +#define CR0_FIRSTBIT_MSB (0x0 << SPI_CTRLR0_FBM_SHIFT) +#define CR0_FIRSTBIT_LSB (0x1 << SPI_CTRLR0_FBM_SHIFT) + +#define CR0_BHT_16BIT (0x0 << SPI_CTRLR0_BHT_SHIFT) +#define CR0_BHT_8BIT (0x1 << SPI_CTRLR0_BHT_SHIFT) + +#define CR0_XFM_TR (0x00 << SPI_CTRLR0_XFM_SHIFT) +#define CR0_XFM_TO (0x01 << SPI_CTRLR0_XFM_SHIFT) +#define CR0_XFM_RO (0x02 << SPI_CTRLR0_XFM_SHIFT) + +#define CR0_OPM_MASTER (0x00 << SPI_CTRLR0_OPM_SHIFT) +#define CR0_OPM_SLAVE (0x01 << SPI_CTRLR0_OPM_SHIFT) + +#define CR0_CSM(nCycles) (((nCycles) << SPI_CTRLR0_CSM_SHIFT) & SPI_CTRLR0_CSM_MASK) +#define CR0_CSM_0CYCLE CR0_CSM(0) +#define CR0_CSM_1CYCLE CR0_CSM(1) +#define CR0_CSM_2CYCLES CR0_CSM(2) +#define CR0_CSM_3CYCLES CR0_CSM(3) + +/***************************** Structure Definition **************************/ + +/** @brief SPI Type definition */ +typedef enum { + SSI_MOTO_SPI = 0, + SSI_TI_SSP, + SSI_NS_MICROWIRE +} eSPI_SSIType; + +/** @brief SPI Transfer type definition */ +typedef enum { + SPI_POLL = 0, + SPI_IT, + SPI_DMA +} eSPI_TransferType; + +/** @brief SPI Configuration Structure definition */ +struct SPI_CONFIG { + UINT32 opMode; /**< Specifies the SPI operating mode, master or slave. */ + UINT32 xfmMode; /**< Specifies the SPI bidirectional mode state, tx only, rx only or trx mode. */ + UINT32 nBytes; /**< Specifies the SPI data size. */ + UINT32 clkPolarity; /**< Specifies the serial clock steady state. */ + UINT32 clkPhase; /**< Specifies the clock active edge for the bit capture. */ + UINT32 firstBit; /**< Specifies whether data transfers start from MSB or LSB bit. */ + UINT32 endianMode; /**< Specifies whether data transfers start from little or big endian. */ + UINT32 apbTransform; /**< Specifies apb transform type. */ + UINT32 ssd; /**< Specifies period between ss_n active and sclk_out. */ + UINT32 speed; /**< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. */ + UINT32 ssiType; /**< Specifies if the TI mode is enabled or not.*/ + UINT32 csm; /**< Specifies Motorola SPI Master SS_N high cycles for each frame data is transfer. */ +}; + +/* We have 2 DMA channels per SPI, one for RX and one for TX */ +struct HAL_SPI_DMA_INFO { + UINT8 channel; + UINT8 direction; + UINT32 addr; +}; + +struct HAL_SPI_DEV { + const UINT32 base; + const UINT32 clkId; + const UINT32 clkGateID; + const UINT32 pclkGateID; + const UINT8 irqNum; + const UINT8 isSlave; + const struct HAL_SPI_DMA_INFO txDma; + const struct HAL_SPI_DMA_INFO rxDma; +}; + +/** @brief SPI handle Structure definition */ +struct SPI_HANDLE { + struct SPI_REG *pReg; /**< Specifies SPI registers base address. */ + UINT32 maxFreq; /**< Specifies SPI clock frequency. */ + struct SPI_CONFIG config; /**< Specifies SPI communication parameters. */ + const UINT8 *pTxBuffer; /**< Specifies pointer to SPI Tx transfer Buffer. */ + const UINT8 *pTxBufferEnd; /**< Specifies pointer to SPI Tx End transfer Buffer. */ + UINT8 *pRxBuffer; /**< Specifies pointer to SPI Rx transfer Buffer. */ + UINT8 *pRxBufferEnd; /**< Specifies pointer to SPI Rx End transfer Buffer. */ + UINT32 len; /**< Specifies the transfer length . */ + eSPI_TransferType type; /**< Specifies the transfer type: POLL/IT/DMA. */ + UINT32 dmaBurstSize; /**< Specifies Dma Burst size */ +}; + + +RETURN_STATUS SPI_Init(struct SPI_HANDLE *pSPI, UINT32 base); +RETURN_STATUS SPI_DeInit(struct SPI_HANDLE *pSPI); +RETURN_STATUS SPI_FlushFifo(struct SPI_HANDLE *pSPI); +RETURN_STATUS SPI_SetCS(struct SPI_HANDLE *pSPI, UINT8 select, UINT8 enable); +RETURN_STATUS SPI_PioTransfer(struct SPI_HANDLE *pSPI); +RETURN_STATUS SPI_Stop(struct SPI_HANDLE *pSPI); +RETURN_STATUS SPI_Configure(struct SPI_HANDLE *pSPI, const UINT8 *pTxData, + UINT8 *pRxData, UINT32 Size); +UINT32 SPI_CalculateTimeout(struct SPI_HANDLE *pSPI); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SpiMem.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SpiMem.h new file mode 100644 index 0000000..67fa26f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/SpiMem.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _HAL_SPI_MEM_H_ +#define _HAL_SPI_MEM_H_ + +#define BIT(nr) (1UL << (nr)) +/** SPI Memory host mode */ +#define HAL_SPI_CPHA BIT(0) /**< clock phase */ +#define HAL_SPI_CPOL BIT(1) /**< clock polarity */ +#define HAL_SPI_MODE_0 (0 | 0) /**< (original MicroWire) */ +#define HAL_SPI_MODE_1 (0 | HAL_SPI_CPHA) +#define HAL_SPI_MODE_2 (HAL_SPI_CPOL | 0) +#define HAL_SPI_MODE_3 (HAL_SPI_CPOL | HAL_SPI_CPHA) +#define HAL_SPI_CS_HIGH BIT(2) /**< CS active high */ +#define HAL_SPI_LSB_FIRST BIT(3) /**< per-word bits-on-wire */ +#define HAL_SPI_3WIRE BIT(4) /**< SI/SO signals shared */ +#define HAL_SPI_LOOP BIT(5) /**< loopback mode */ +#define HAL_SPI_SLAVE BIT(6) /**< slave mode */ +#define HAL_SPI_PREAMBLE BIT(7) /**< Skip preamble bytes */ +#define HAL_SPI_TX_BYTE BIT(8) /**< transmit with 1 wire byte */ +#define HAL_SPI_TX_DUAL BIT(9) /**< transmit with 2 wires */ +#define HAL_SPI_TX_QUAD BIT(10) /**< transmit with 4 wires */ +#define HAL_SPI_RX_SLOW BIT(11) /**< receive with 1 wire slow */ +#define HAL_SPI_RX_DUAL BIT(12) /**< receive with 2 wires */ +#define HAL_SPI_RX_QUAD BIT(13) /**< receive with 4 wires */ +#define HAL_SPI_XIP BIT(14) /**< support spi flash xip mode */ + +/** SPI Memory host xfer flags */ +#define HAL_SPI_XFER_BEGIN BIT(0) /**< Assert CS before transfer */ +#define HAL_SPI_XFER_END BIT(1) /**< Deassert CS after transfer */ +#define HAL_SPI_XFER_ONCE (HAL_SPI_XFER_BEGIN | HAL_SPI_XFER_END) + +#define JEDEC_MFR(id) (((id) >> 16) & 0xff) + +#define HAL_SPI_MEM_OP_FORMAT(__cmd, __addr, __dummy, __data) \ + { \ + .cmd = __cmd, \ + .addr = __addr, \ + .dummy = __dummy, \ + .data = __data, \ + } + +#define HAL_SPI_MEM_OP_CMD(__opcode, __buswidth) \ + { \ + .buswidth = __buswidth, \ + .opcode = __opcode, \ + } + +#define HAL_SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ + { \ + .nbytes = __nbytes, \ + .val = __val, \ + .buswidth = __buswidth, \ + } + +#define HAL_SPI_MEM_OP_NO_ADDR \ + { \ + .nbytes = 0, \ + .val = 0, \ + .buswidth = 0, \ + } + +#define HAL_SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ + { \ + .a2dIdle = 0, \ + .nbytes = __nbytes, \ + .buswidth = __buswidth, \ + } + +#define HAL_SPI_MEM_OP_NO_DUMMY \ + { \ + .a2dIdle = 0, \ + .nbytes = 0, \ + .buswidth = 0, \ + } + +#define HAL_SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \ + { \ + .dir = HAL_SPI_MEM_DATA_IN, \ + .nbytes = __nbytes, \ + .buf.in = __buf, \ + .buswidth = __buswidth, \ + } + +#define HAL_SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \ + { \ + .dir = HAL_SPI_MEM_DATA_OUT, \ + .nbytes = __nbytes, \ + .buf.out = __buf, \ + .buswidth = __buswidth, \ + } + +#define HAL_SPI_MEM_OP_NO_DATA \ + { \ + .dir = HAL_SPI_MEM_DATA_IN, \ + .nbytes = 0, \ + .buf.out = NULL, \ + .buswidth = 0, \ + } + +/* Max len case: cmd(1) + addr(4) + dummy(4) */ +#define HAL_SPI_OP_LEN_MAX 0x10 + +/***************************** Structure Definition **************************/ + +enum SPI_MEM_DATA_DIR { + HAL_SPI_MEM_DATA_IN, + HAL_SPI_MEM_DATA_OUT, +}; + +struct HAL_SPI_MEM_OP { + struct { + uint8_t buswidth; + uint8_t opcode; + } cmd; + + struct { + uint8_t nbytes; + uint8_t buswidth; + uint32_t val; + } addr; + + struct { + uint8_t a2dIdle; + uint8_t nbytes; + uint8_t buswidth; + } dummy; + + struct { + uint8_t buswidth; + enum SPI_MEM_DATA_DIR dir; + unsigned int nbytes; + /**< buf.{in,out} must be DMA-able. */ + union { + void *in; + const void *out; + } buf; + } data; +}; + +#define HAL_SPI_MEM_OP(__cmd, __addr, __dummy, __data) \ + { \ + .cmd = __cmd, \ + .addr = __addr, \ + .dummy = __dummy, \ + .data = __data, \ + } + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Vop2Regs.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Vop2Regs.h new file mode 100644 index 0000000..dace873 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/Vop2Regs.h @@ -0,0 +1,701 @@ +/** @file + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef __VOP2_REGS_H__ +#define __VOP2_REGS_H__ + +/* System registers definition */ +#define RK3568_REG_CFG_DONE 0x000 +#define CFG_DONE_EN BIT(15) + +#define RK3568_VERSION_INFO 0x004 +#define EN_MASK 1 +#define ALL_MASK 0xFFFFFFFF + +#define RK3568_AUTO_GATING_CTRL 0x008 + +#define RK3568_SYS_AXI_LUT_CTRL 0x024 +#define LUT_DMA_EN_SHIFT 0 + +#define RK3568_DSP_IF_EN 0x028 +#define RGB_EN_SHIFT 0 +#define RK3588_DP0_EN_SHIFT 0 +#define RK3588_DP1_EN_SHIFT 1 +#define RK3588_RGB_EN_SHIFT 8 +#define HDMI0_EN_SHIFT 1 +#define EDP0_EN_SHIFT 3 +#define RK3588_EDP0_EN_SHIFT 2 +#define RK3588_HDMI0_EN_SHIFT 3 +#define MIPI0_EN_SHIFT 4 +#define RK3588_EDP1_EN_SHIFT 4 +#define RK3588_HDMI1_EN_SHIFT 5 +#define RK3588_MIPI0_EN_SHIFT 6 +#define MIPI1_EN_SHIFT 20 +#define RK3588_MIPI1_EN_SHIFT 7 +#define LVDS0_EN_SHIFT 5 +#define LVDS1_EN_SHIFT 24 +#define BT1120_EN_SHIFT 6 +#define BT656_EN_SHIFT 7 +#define IF_MUX_MASK 3 +#define RGB_MUX_SHIFT 8 +#define HDMI0_MUX_SHIFT 10 +#define RK3588_DP0_MUX_SHIFT 12 +#define RK3588_DP1_MUX_SHIFT 14 +#define EDP0_MUX_SHIFT 14 +#define RK3588_HDMI_EDP0_MUX_SHIFT 16 +#define RK3588_HDMI_EDP1_MUX_SHIFT 18 +#define MIPI0_MUX_SHIFT 16 +#define RK3588_MIPI0_MUX_SHIFT 20 +#define MIPI1_MUX_SHIFT 21 +#define LVDS0_MUX_SHIFT 18 +#define LVDS1_MUX_SHIFT 25 + +#define RK3568_DSP_IF_CTRL 0x02C +#define LVDS_DUAL_EN_SHIFT 0 +#define RK3588_BT656_UV_SWAP_SHIFT 0 +#define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 +#define RK3588_BT656_YC_SWAP_SHIFT 1 +#define LVDS_DUAL_SWAP_EN_SHIFT 2 +#define BT656_UV_SWAP 4 +#define RK3588_BT1120_UV_SWAP_SHIFT 4 +#define BT656_YC_SWAP 5 +#define RK3588_BT1120_YC_SWAP_SHIFT 5 +#define BT656_DCLK_POL 6 +#define RK3588_HDMI_DUAL_EN_SHIFT 8 +#define RK3588_EDP_DUAL_EN_SHIFT 8 +#define RK3588_DP_DUAL_EN_SHIFT 9 +#define RK3568_MIPI_DUAL_EN_SHIFT 10 +#define RK3588_MIPI_DSI0_MODE_SEL_SHIFT 11 +#define RK3588_MIPI_DSI1_MODE_SEL_SHIFT 12 + +#define RK3568_DSP_IF_POL 0x030 +#define IF_CTRL_REG_DONE_IMD_MASK 1 +#define IF_CTRL_REG_DONE_IMD_SHIFT 28 +#define IF_CRTL_MIPI_DCLK_POL_SHIT 19 +#define IF_CRTL_EDP_DCLK_POL_SHIT 15 +#define IF_CRTL_HDMI_DCLK_POL_SHIT 7 +#define IF_CRTL_HDMI_PIN_POL_MASK 0x7 +#define IF_CRTL_HDMI_PIN_POL_SHIT 4 + +#define RK3588_DP0_PIN_POL_SHIFT 8 +#define RK3588_DP1_PIN_POL_SHIFT 12 +#define RK3588_IF_PIN_POL_MASK 0x7 + +#define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 + +#define HDMI_EDP0_DCLK_DIV_SHIFT 16 +#define HDMI_EDP0_PIXCLK_DIV_SHIFT 18 +#define HDMI_EDP1_DCLK_DIV_SHIFT 20 +#define HDMI_EDP1_PIXCLK_DIV_SHIFT 22 +#define MIPI0_PIXCLK_DIV_SHIFT 24 +#define MIPI1_PIXCLK_DIV_SHIFT 26 + +#define RK3568_SYS_OTP_WIN_EN 0x50 +#define OTP_WIN_EN_SHIFT 0 +#define RK3568_SYS_LUT_PORT_SEL 0x58 +#define GAMMA_PORT_SEL_MASK 0x3 +#define GAMMA_PORT_SEL_SHIFT 0 +#define RK3568_MIPI_DUAL_EN_SHIFT 10 + +#define RK3568_SYS_PD_CTRL 0x034 +#define RK3568_VP0_LINE_FLAG 0x70 +#define RK3568_VP1_LINE_FLAG 0x74 +#define RK3568_VP2_LINE_FLAG 0x78 +#define RK3568_SYS0_INT_EN 0x80 +#define RK3568_SYS0_INT_CLR 0x84 +#define RK3568_SYS0_INT_STATUS 0x88 +#define RK3568_SYS1_INT_EN 0x90 +#define RK3568_SYS1_INT_CLR 0x94 +#define RK3568_SYS1_INT_STATUS 0x98 +#define RK3568_VP0_INT_EN 0xA0 +#define RK3568_VP0_INT_CLR 0xA4 +#define RK3568_VP0_INT_STATUS 0xA8 +#define RK3568_VP1_INT_EN 0xB0 +#define RK3568_VP1_INT_CLR 0xB4 +#define RK3568_VP1_INT_STATUS 0xB8 +#define RK3568_VP2_INT_EN 0xC0 +#define RK3568_VP2_INT_CLR 0xC4 +#define RK3568_VP2_INT_STATUS 0xC8 +#define RK3588_CLUSTER0_PD_EN_SHIFT 0 +#define RK3588_CLUSTER1_PD_EN_SHIFT 1 +#define RK3588_CLUSTER2_PD_EN_SHIFT 2 +#define RK3588_CLUSTER3_PD_EN_SHIFT 3 +#define RK3588_DSC_8K_PD_EN_SHIFT 5 +#define RK3588_DSC_4K_PD_EN_SHIFT 6 +#define RK3588_ESMART_PD_EN_SHIFT 7 + +#define RK3568_SYS_STATUS0 0x60 +#define RK3588_CLUSTER0_PD_STATUS_SHIFT 8 +#define RK3588_CLUSTER1_PD_STATUS_SHIFT 9 +#define RK3588_CLUSTER2_PD_STATUS_SHIFT 10 +#define RK3588_CLUSTER3_PD_STATUS_SHIFT 11 +#define RK3588_DSC_8K_PD_STATUS_SHIFT 13 +#define RK3588_DSC_4K_PD_STATUS_SHIFT 14 +#define RK3588_ESMART_PD_STATUS_SHIFT 15 + + +/* Overlay registers definition */ +#define RK3568_OVL_CTRL 0x600 +#define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 +#define RK3568_OVL_LAYER_SEL 0x604 +#define LAYER_SEL_MASK 0xF + +#define RK3568_OVL_PORT_SEL 0x608 +#define PORT_MUX_MASK 0xF +#define PORT_MUX_SHIFT 0 +#define LAYER_SEL_PORT_MASK 0x3 +#define LAYER_SEL_PORT_SHIFT 16 + +#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 +#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 +#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 +#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C +#define RK3568_MIX0_SRC_COLOR_CTRL 0x650 +#define RK3568_MIX0_DST_COLOR_CTRL 0x654 +#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 +#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C +#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 +#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 +#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 +#define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC +#define RK3568_VP0_BG_MIX_CTRL 0x6E0 +#define BG_MIX_CTRL_MASK 0xff +#define BG_MIX_CTRL_SHIFT 24 +#define RK3568_VP1_BG_MIX_CTRL 0x6E4 +#define RK3568_VP2_BG_MIX_CTRL 0x6E8 +#define RK3568_CLUSTER_DLY_NUM 0x6F0 +#define RK3568_SMART_DLY_NUM 0x6F8 + +/* Video Port registers definition */ +#define RK3568_VP0_DSP_CTRL 0xC00 +#define OUT_MODE_MASK 0xF +#define OUT_MODE_SHIFT 0 +#define DATA_SWAP_MASK 0x1F +#define DATA_SWAP_SHIFT 8 +#define DSP_BG_SWAP 0x1 +#define DSP_RB_SWAP 0x2 +#define DSP_RG_SWAP 0x4 +#define DSP_DELTA_SWAP 0x8 +#define CORE_DCLK_DIV_EN_SHIFT 4 +#define P2I_EN_SHIFT 5 +#define DSP_FILED_POL 6 +#define INTERLACE_EN_SHIFT 7 +#define POST_DSP_OUT_R2Y_SHIFT 15 +#define PRE_DITHER_DOWN_EN_SHIFT 16 +#define DITHER_DOWN_EN_SHIFT 17 +#define DSP_LUT_EN_SHIFT 28 + +#define STANDBY_EN_SHIFT 31 + +#define RK3568_VP0_MIPI_CTRL 0xC04 +#define DCLK_DIV2_SHIFT 4 +#define DCLK_DIV2_MASK 0x3 +#define MIPI_DUAL_EN_SHIFT 20 +#define MIPI_DUAL_SWAP_EN_SHIFT 21 +#define EDPI_TE_EN 28 +#define EDPI_WMS_HOLD_EN 30 +#define EDPI_WMS_FS 31 + +#define RK3568_VP0_COLOR_BAR_CTRL 0xC08 +#define RK3568_VP0_3D_LUT_CTRL 0xC10 +#define VP0_3D_LUT_EN_SHIFT 0 +#define VP0_3D_LUT_UPDATE_SHIFT 2 + +#define RK3588_VP0_CLK_CTRL 0xC0C +#define DCLK_CORE_DIV_SHIFT 0 +#define DCLK_OUT_DIV_SHIFT 2 + +#define RK3568_VP0_3D_LUT_MST 0xC20 + +#define RK3568_VP0_DSP_BG 0xC2C +#define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 +#define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 +#define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 +#define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C +#define RK3568_VP0_POST_SCL_CTRL 0xC40 +#define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 +#define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 +#define RK3568_VP0_DSP_HACT_ST_END 0xC4C +#define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 +#define RK3568_VP0_DSP_VACT_ST_END 0xC54 +#define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 +#define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C + +#define RK3568_VP0_BCSH_CTRL 0xC60 +#define BCSH_CTRL_Y2R_SHIFT 0 +#define BCSH_CTRL_Y2R_MASK 0x1 +#define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 +#define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 +#define BCSH_CTRL_R2Y_SHIFT 4 +#define BCSH_CTRL_R2Y_MASK 0x1 +#define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 +#define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 + +#define RK3568_VP0_BCSH_BCS 0xC64 +#define BCSH_BRIGHTNESS_SHIFT 0 +#define BCSH_BRIGHTNESS_MASK 0xFF +#define BCSH_CONTRAST_SHIFT 8 +#define BCSH_CONTRAST_MASK 0x1FF +#define BCSH_SATURATION_SHIFT 20 +#define BCSH_SATURATION_MASK 0x3FF +#define BCSH_OUT_MODE_SHIFT 30 +#define BCSH_OUT_MODE_MASK 0x3 + +#define RK3568_VP0_BCSH_H 0xC68 +#define BCSH_SIN_HUE_SHIFT 0 +#define BCSH_SIN_HUE_MASK 0x1FF +#define BCSH_COS_HUE_SHIFT 16 +#define BCSH_COS_HUE_MASK 0x1FF + +#define RK3568_VP0_BCSH_COLOR 0xC6C +#define BCSH_EN_SHIFT 31 +#define BCSH_EN_MASK 1 + +#define RK3568_VP1_DSP_CTRL 0xD00 +#define RK3568_VP1_MIPI_CTRL 0xD04 +#define RK3568_VP1_COLOR_BAR_CTRL 0xD08 +#define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 +#define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 +#define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 +#define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C +#define RK3568_VP1_POST_SCL_CTRL 0xD40 +#define RK3568_VP1_DSP_HACT_INFO 0xD34 +#define RK3568_VP1_DSP_VACT_INFO 0xD38 +#define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 +#define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 +#define RK3568_VP1_DSP_HACT_ST_END 0xD4C +#define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 +#define RK3568_VP1_DSP_VACT_ST_END 0xD54 +#define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 +#define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C + +#define RK3568_VP2_DSP_CTRL 0xE00 +#define RK3568_VP2_MIPI_CTRL 0xE04 +#define RK3568_VP2_COLOR_BAR_CTRL 0xE08 +#define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 +#define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 +#define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 +#define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C +#define RK3568_VP2_POST_SCL_CTRL 0xE40 +#define RK3568_VP2_DSP_HACT_INFO 0xE34 +#define RK3568_VP2_DSP_VACT_INFO 0xE38 +#define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 +#define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 +#define RK3568_VP2_DSP_HACT_ST_END 0xE4C +#define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 +#define RK3568_VP2_DSP_VACT_ST_END 0xE54 +#define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 +#define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C + +/* Cluster0 register definition */ +#define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 +#define CLUSTER_YUV2RGB_EN_SHIFT 8 +#define CLUSTER_RGB2YUV_EN_SHIFT 9 +#define CLUSTER_CSC_MODE_SHIFT 10 +#define CLUSTER_YRGB_XSCL_MODE_SHIFT 12 +#define CLUSTER_YRGB_YSCL_MODE_SHIFT 14 +#define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 +#define CLUSTER_YRGB_GT2_SHIFT 28 +#define CLUSTER_YRGB_GT4_SHIFT 29 +#define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 +#define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 +#define RK3568_CLUSTER0_WIN0_VIR 0x1018 +#define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 +#define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 +#define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 +#define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 +#define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 +#define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 +#define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C +#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 +#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 +#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 +#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C + +#define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 +#define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 +#define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 +#define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 +#define RK3568_CLUSTER0_WIN1_VIR 0x1098 +#define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 +#define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 +#define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 +#define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 +#define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 +#define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 +#define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC +#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 +#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 +#define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 +#define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC + +#define RK3568_CLUSTER0_CTRL 0x1100 +#define CLUSTER_EN_SHIFT 0 + +#define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 +#define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 +#define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 +#define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 +#define RK3568_CLUSTER1_WIN0_VIR 0x1218 +#define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 +#define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 +#define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 +#define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 +#define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 +#define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 +#define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C +#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 +#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 +#define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 +#define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C + +#define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 +#define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 +#define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 +#define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 +#define RK3568_CLUSTER1_WIN1_VIR 0x1298 +#define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 +#define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 +#define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 +#define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 +#define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 +#define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 +#define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC +#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 +#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 +#define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 +#define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC + +#define RK3568_CLUSTER1_CTRL 0x1300 + +/* Esmart register definition */ +#define RK3568_ESMART0_CTRL0 0x1800 +#define RGB2YUV_EN_SHIFT 1 +#define CSC_MODE_SHIFT 2 +#define CSC_MODE_MASK 0x3 + +#define RK3568_ESMART0_CTRL1 0x1804 +#define YMIRROR_EN_SHIFT 31 +#define RK3568_ESMART0_REGION0_CTRL 0x1810 +#define REGION0_RB_SWAP_SHIFT 14 +#define WIN_EN_SHIFT 0 +#define WIN_FORMAT_MASK 0x1f +#define WIN_FORMAT_SHIFT 1 + +#define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 +#define RK3568_ESMART0_REGION0_CBR_MST 0x1818 +#define RK3568_ESMART0_REGION0_VIR 0x181C +#define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 +#define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 +#define RK3568_ESMART0_REGION0_DSP_ST 0x1828 +#define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 +#define YRGB_XSCL_MODE_MASK 0x3 +#define YRGB_XSCL_MODE_SHIFT 0 +#define YRGB_XSCL_FILTER_MODE_MASK 0x3 +#define YRGB_XSCL_FILTER_MODE_SHIFT 2 +#define YRGB_YSCL_MODE_MASK 0x3 +#define YRGB_YSCL_MODE_SHIFT 4 +#define YRGB_YSCL_FILTER_MODE_MASK 0x3 +#define YRGB_YSCL_FILTER_MODE_SHIFT 6 + +#define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 +#define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 +#define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C +#define RK3568_ESMART0_REGION1_CTRL 0x1840 +#define YRGB_GT2_MASK 0x1 +#define YRGB_GT2_SHIFT 8 +#define YRGB_GT4_MASK 0x1 +#define YRGB_GT4_SHIFT 9 + +#define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 +#define RK3568_ESMART0_REGION1_CBR_MST 0x1848 +#define RK3568_ESMART0_REGION1_VIR 0x184C +#define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 +#define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 +#define RK3568_ESMART0_REGION1_DSP_ST 0x1858 +#define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 +#define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 +#define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 +#define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C +#define RK3568_ESMART0_REGION2_CTRL 0x1870 +#define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 +#define RK3568_ESMART0_REGION2_CBR_MST 0x1878 +#define RK3568_ESMART0_REGION2_VIR 0x187C +#define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 +#define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 +#define RK3568_ESMART0_REGION2_DSP_ST 0x1888 +#define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 +#define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 +#define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 +#define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C +#define RK3568_ESMART0_REGION3_CTRL 0x18A0 +#define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 +#define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 +#define RK3568_ESMART0_REGION3_VIR 0x18AC +#define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 +#define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 +#define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 +#define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 +#define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 +#define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 +#define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC + +#define RK3568_ESMART1_CTRL0 0x1A00 +#define RK3568_ESMART1_CTRL1 0x1A04 +#define RK3568_ESMART1_REGION0_CTRL 0x1A10 +#define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 +#define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 +#define RK3568_ESMART1_REGION0_VIR 0x1A1C +#define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 +#define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 +#define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 +#define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 +#define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 +#define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 +#define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C +#define RK3568_ESMART1_REGION1_CTRL 0x1A40 +#define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 +#define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 +#define RK3568_ESMART1_REGION1_VIR 0x1A4C +#define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 +#define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 +#define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 +#define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 +#define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 +#define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 +#define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C +#define RK3568_ESMART1_REGION2_CTRL 0x1A70 +#define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 +#define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 +#define RK3568_ESMART1_REGION2_VIR 0x1A7C +#define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 +#define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 +#define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 +#define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 +#define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 +#define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 +#define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C +#define RK3568_ESMART1_REGION3_CTRL 0x1AA0 +#define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 +#define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 +#define RK3568_ESMART1_REGION3_VIR 0x1AAC +#define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 +#define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 +#define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 +#define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 +#define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 +#define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 +#define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC + +#define RK3568_SMART0_CTRL0 0x1C00 +#define RK3568_SMART0_CTRL1 0x1C04 +#define RK3568_SMART0_REGION0_CTRL 0x1C10 +#define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 +#define RK3568_SMART0_REGION0_CBR_MST 0x1C18 +#define RK3568_SMART0_REGION0_VIR 0x1C1C +#define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 +#define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 +#define RK3568_SMART0_REGION0_DSP_ST 0x1C28 +#define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 +#define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 +#define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 +#define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C +#define RK3568_SMART0_REGION1_CTRL 0x1C40 +#define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 +#define RK3568_SMART0_REGION1_CBR_MST 0x1C48 +#define RK3568_SMART0_REGION1_VIR 0x1C4C +#define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 +#define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 +#define RK3568_SMART0_REGION1_DSP_ST 0x1C58 +#define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 +#define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 +#define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 +#define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C +#define RK3568_SMART0_REGION2_CTRL 0x1C70 +#define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 +#define RK3568_SMART0_REGION2_CBR_MST 0x1C78 +#define RK3568_SMART0_REGION2_VIR 0x1C7C +#define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 +#define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 +#define RK3568_SMART0_REGION2_DSP_ST 0x1C88 +#define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 +#define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 +#define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 +#define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C +#define RK3568_SMART0_REGION3_CTRL 0x1CA0 +#define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 +#define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 +#define RK3568_SMART0_REGION3_VIR 0x1CAC +#define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 +#define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 +#define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 +#define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 +#define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 +#define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 +#define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC + +#define RK3568_SMART1_CTRL0 0x1E00 +#define RK3568_SMART1_CTRL1 0x1E04 +#define RK3568_SMART1_REGION0_CTRL 0x1E10 +#define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 +#define RK3568_SMART1_REGION0_CBR_MST 0x1E18 +#define RK3568_SMART1_REGION0_VIR 0x1E1C +#define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 +#define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 +#define RK3568_SMART1_REGION0_DSP_ST 0x1E28 +#define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 +#define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 +#define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 +#define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C +#define RK3568_SMART1_REGION1_CTRL 0x1E40 +#define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 +#define RK3568_SMART1_REGION1_CBR_MST 0x1E48 +#define RK3568_SMART1_REGION1_VIR 0x1E4C +#define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 +#define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 +#define RK3568_SMART1_REGION1_DSP_ST 0x1E58 +#define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 +#define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 +#define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 +#define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C +#define RK3568_SMART1_REGION2_CTRL 0x1E70 +#define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 +#define RK3568_SMART1_REGION2_CBR_MST 0x1E78 +#define RK3568_SMART1_REGION2_VIR 0x1E7C +#define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 +#define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 +#define RK3568_SMART1_REGION2_DSP_ST 0x1E88 +#define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 +#define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 +#define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 +#define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C +#define RK3568_SMART1_REGION3_CTRL 0x1EA0 +#define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 +#define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 +#define RK3568_SMART1_REGION3_VIR 0x1EAC +#define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 +#define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 +#define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 +#define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 +#define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 +#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 +#define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC + +/* DSC 8K/4K register definition */ +#define RK3588_DSC_8K_PPS0_3 0x4000 +#define RK3588_DSC_8K_CTRL0 0x40A0 +#define DSC_EN_SHIFT 0 +#define DSC_RBIT_SHIFT 2 +#define DSC_RBYT_SHIFT 3 +#define DSC_FLAL_SHIFT 4 +#define DSC_MER_SHIFT 5 +#define DSC_EPB_SHIFT 6 +#define DSC_EPL_SHIFT 7 +#define DSC_NSLC_MASK 0x7 +#define DSC_NSLC_SHIFT 16 +#define DSC_SBO_SHIFT 28 +#define DSC_IFEP_SHIFT 29 +#define DSC_PPS_UPD_SHIFT 31 +#define DSC_CTRL0_DEF_CON ((1 << DSC_EN_SHIFT) | (1 << DSC_RBIT_SHIFT) | (0 << DSC_RBYT_SHIFT) | \ + (1 << DSC_FLAL_SHIFT) | (1 << DSC_MER_SHIFT) | (0 << DSC_EPB_SHIFT) | \ + (1 << DSC_EPL_SHIFT) | (1 << DSC_SBO_SHIFT)) + +#define RK3568_MAX_REG 0x1ED0 +#define RK3588_VOP2_REG_BASE 0xFDD90000 + +#define RK3568_SYS_CTRL_LINE_FLAG0 0x70 +#define LINE_FLAG_NUM_MASK 0x1FFF +#define RK3568_DSP_LINE_FLAG_NUM0_SHIFT 0 +#define RK3568_DSP_LINE_FLAG_NUM1_SHIFT 16 + +/* DSC CTRL registers definition */ +#define RK3588_DSC_8K_SYS_CTRL 0x200 +#define DSC_PORT_SEL_MASK 0x3 +#define DSC_PORT_SEL_SHIFT 0 +#define DSC_MAN_MODE_MASK 0x1 +#define DSC_MAN_MODE_SHIFT 2 +#define DSC_INTERFACE_MODE_MASK 0x3 +#define DSC_INTERFACE_MODE_SHIFT 4 +#define DSC_PIXEL_NUM_MASK 0x3 +#define DSC_PIXEL_NUM_SHIFT 6 +#define DSC_PXL_CLK_DIV_MASK 0x1 +#define DSC_PXL_CLK_DIV_SHIFT 8 +#define DSC_CDS_CLK_DIV_MASK 0x3 +#define DSC_CDS_CLK_DIV_SHIFT 12 +#define DSC_TXP_CLK_DIV_MASK 0x3 +#define DSC_TXP_CLK_DIV_SHIFT 14 +#define DSC_INIT_DLY_MODE_MASK 0x1 +#define DSC_INIT_DLY_MODE_SHIFT 16 +#define DSC_SCAN_EN_SHIFT 17 +#define DSC_HALT_EN_SHIFT 18 + +#define RK3588_DSC_8K_RST 0x204 +#define RST_DEASSERT_MASK 0x1 +#define RST_DEASSERT_SHIFT 0 + +#define RK3588_DSC_8K_CFG_DONE 0x208 +#define DSC_CFG_DONE_SHIFT 0 + +#define RK3588_DSC_8K_INIT_DLY 0x20C +#define DSC_INIT_DLY_NUM_MASK 0xffff +#define DSC_INIT_DLY_NUM_SHIFT 0 +#define SCAN_TIMING_PARA_IMD_EN_SHIFT 16 + +#define RK3588_DSC_8K_HTOTAL_HS_END 0x210 +#define DSC_HTOTAL_PW_MASK 0xffffffff +#define DSC_HTOTAL_PW_SHIFT 0 + +#define RK3588_DSC_8K_HACT_ST_END 0x214 +#define DSC_HACT_ST_END_MASK 0xffffffff +#define DSC_HACT_ST_END_SHIFT 0 + +#define RK3588_DSC_8K_VTOTAL_VS_END 0x218 +#define DSC_VTOTAL_PW_MASK 0xffffffff +#define DSC_VTOTAL_PW_SHIFT 0 + +#define RK3588_DSC_8K_VACT_ST_END 0x21C +#define DSC_VACT_ST_END_MASK 0xffffffff +#define DSC_VACT_ST_END_SHIFT 0 + +#define RK3588_DSC_8K_STATUS 0x220 + +#define RK3588_VOP_GRF_BASE 0xFD5A4000 +#define RK3588_GRF_VOP_CON2 0x0008 +#define RK3588_GRF_EDP0_ENABLE_SHIFT 0 +#define RK3588_GRF_HDMITX0_ENABLE_SHIFT 1 +#define RK3588_GRF_EDP1_ENABLE_SHIFT 3 +#define RK3588_GRF_HDMITX1_ENABLE_SHIFT 4 + +#define RK3588_VO0_GRF_BASE 0xFD5A6000 + +#define RK3588_VO1_GRF_BASE 0xFD5A8000 +#define RK3588_GRF_VO1_CON0 0x0000 +#define HDMI_SYNC_POL_MASK 0x3 +#define HDMI0_SYNC_POL_SHIFT 5 +#define HDMI1_SYNC_POL_SHIFT 7 + +#define RK3588_PMU_BISR_CON3 0x20C +#define RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT 9 +#define RK3588_PD_CLUSTER1_REPAIR_EN_SHIFT 10 +#define RK3588_PD_CLUSTER2_REPAIR_EN_SHIFT 11 +#define RK3588_PD_CLUSTER3_REPAIR_EN_SHIFT 12 +#define RK3588_PD_DSC_8K_REPAIR_EN_SHIFT 13 +#define RK3588_PD_DSC_4K_REPAIR_EN_SHIFT 14 +#define RK3588_PD_ESMART_REPAIR_EN_SHIFT 15 + +#define RK3588_PMU_BISR_STATUS5 0x294 +#define RK3588_PD_CLUSTER0_PWR_STAT_SHIFI 9 +#define RK3588_PD_CLUSTER1_PWR_STAT_SHIFI 10 +#define RK3588_PD_CLUSTER2_PWR_STAT_SHIFI 11 +#define RK3588_PD_CLUSTER3_PWR_STAT_SHIFI 12 +#define RK3588_PD_DSC_8K_PWR_STAT_SHIFI 13 +#define RK3588_PD_DSC_4K_PWR_STAT_SHIFI 14 +#define RK3588_PD_ESMART_PWR_STAT_SHIFI 15 + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_dp_helper.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_dp_helper.h new file mode 100644 index 0000000..e28b3cf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_dp_helper.h @@ -0,0 +1,1227 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef _DRM_DP_HELPER_H_ +#define _DRM_DP_HELPER_H_ + +/* + * Unless otherwise noted, all values are from the DP 1.1a spec. Note that + * DP and DPCD versions are independent. Differences from 1.0 are not noted, + * 1.0 devices basically don't exist in the wild. + * + * Abbreviations, in chronological order: + * + * eDP: Embedded DisplayPort version 1 + * DPI: DisplayPort Interoperability Guideline v1.1a + * 1.2: DisplayPort 1.2 + * MST: Multistream Transport - part of DP 1.2a + * + * 1.2 formally includes both eDP and DPI definitions. + */ + +/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */ +#define DP_MSA_MISC_SYNC_CLOCK (1 << 0) +#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8) +#define DP_MSA_MISC_STEREO_NO_3D (0 << 9) +#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9) +#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9) +/* bits per component for non-RAW */ +#define DP_MSA_MISC_6_BPC (0 << 5) +#define DP_MSA_MISC_8_BPC (1 << 5) +#define DP_MSA_MISC_10_BPC (2 << 5) +#define DP_MSA_MISC_12_BPC (3 << 5) +#define DP_MSA_MISC_16_BPC (4 << 5) +/* bits per component for RAW */ +#define DP_MSA_MISC_RAW_6_BPC (1 << 5) +#define DP_MSA_MISC_RAW_7_BPC (2 << 5) +#define DP_MSA_MISC_RAW_8_BPC (3 << 5) +#define DP_MSA_MISC_RAW_10_BPC (4 << 5) +#define DP_MSA_MISC_RAW_12_BPC (5 << 5) +#define DP_MSA_MISC_RAW_14_BPC (6 << 5) +#define DP_MSA_MISC_RAW_16_BPC (7 << 5) +/* pixel encoding/colorimetry format */ +#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \ + ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1)) +#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0) +#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0) +#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0) +#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1) +#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0) +#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0) +#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0) +#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1) +#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0) +#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1) +#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0) +#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1) +#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0) +#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1) +#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1) +#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0) +#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1) +#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14) + +#define DP_AUX_MAX_PAYLOAD_BYTES 16 + +#define DP_AUX_I2C_WRITE 0x0 +#define DP_AUX_I2C_READ 0x1 +#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 +#define DP_AUX_I2C_MOT 0x4 +#define DP_AUX_NATIVE_WRITE 0x8 +#define DP_AUX_NATIVE_READ 0x9 + +#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) +#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) +#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) +#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) + +#define DP_AUX_I2C_REPLY_ACK (0x0 << 2) +#define DP_AUX_I2C_REPLY_NACK (0x1 << 2) +#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) +#define DP_AUX_I2C_REPLY_MASK (0x3 << 2) + +/* AUX CH addresses */ +/* DPCD */ +#define DP_DPCD_REV 0x000 +# define DP_DPCD_REV_10 0x10 +# define DP_DPCD_REV_11 0x11 +# define DP_DPCD_REV_12 0x12 +# define DP_DPCD_REV_13 0x13 +# define DP_DPCD_REV_14 0x14 + +#define DP_MAX_LINK_RATE 0x001 + +#define DP_MAX_LANE_COUNT 0x002 +# define DP_MAX_LANE_COUNT_MASK 0x1f +# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ +# define DP_ENHANCED_FRAME_CAP (1 << 7) + +#define DP_MAX_DOWNSPREAD 0x003 +# define DP_MAX_DOWNSPREAD_0_5 (1 << 0) +# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) +# define DP_TPS4_SUPPORTED (1 << 7) + +#define DP_NORP 0x004 + +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +# define DP_DWN_STRM_PORT_PRESENT (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) +# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) +# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) +# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) +# define DP_FORMAT_CONVERSION (1 << 3) +# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 +# define DP_CAP_ANSI_8B10B (1 << 0) + +#define DP_DOWN_STREAM_PORT_COUNT 0x007 +# define DP_PORT_COUNT_MASK 0x0f +# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ +# define DP_OUI_SUPPORT (1 << 7) + +#define DP_RECEIVE_PORT_0_CAP_0 0x008 +# define DP_LOCAL_EDID_PRESENT (1 << 1) +# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) + +#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 + +#define DP_RECEIVE_PORT_1_CAP_0 0x00a +#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b + +#define DP_I2C_SPEED_CAP 0x00c /* DPI */ +# define DP_I2C_SPEED_1K 0x01 +# define DP_I2C_SPEED_5K 0x02 +# define DP_I2C_SPEED_10K 0x04 +# define DP_I2C_SPEED_100K 0x08 +# define DP_I2C_SPEED_400K 0x10 +# define DP_I2C_SPEED_1M 0x20 + +#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ +# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) +# define DP_FRAMING_CHANGE_CAP (1 << 1) +# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ + +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ +# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */ +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ + +#define DP_ADAPTER_CAP 0x00f /* 1.2 */ +# define DP_FORCE_LOAD_SENSE_CAP (1 << 0) +# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) + +#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ +# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ + +/* Multiple stream transport */ +#define DP_FAUX_CAP 0x020 /* 1.2 */ +# define DP_FAUX_CAP_1 (1 << 0) + +#define DP_MSTM_CAP 0x021 /* 1.2 */ +# define DP_MST_CAP (1 << 0) + +#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ + +/* AV_SYNC_DATA_BLOCK 1.2 */ +#define DP_AV_GRANULARITY 0x023 +# define DP_AG_FACTOR_MASK (0xf << 0) +# define DP_AG_FACTOR_3MS (0 << 0) +# define DP_AG_FACTOR_2MS (1 << 0) +# define DP_AG_FACTOR_1MS (2 << 0) +# define DP_AG_FACTOR_500US (3 << 0) +# define DP_AG_FACTOR_200US (4 << 0) +# define DP_AG_FACTOR_100US (5 << 0) +# define DP_AG_FACTOR_10US (6 << 0) +# define DP_AG_FACTOR_1US (7 << 0) +# define DP_VG_FACTOR_MASK (0xf << 4) +# define DP_VG_FACTOR_3MS (0 << 4) +# define DP_VG_FACTOR_2MS (1 << 4) +# define DP_VG_FACTOR_1MS (2 << 4) +# define DP_VG_FACTOR_500US (3 << 4) +# define DP_VG_FACTOR_200US (4 << 4) +# define DP_VG_FACTOR_100US (5 << 4) + +#define DP_AUD_DEC_LAT0 0x024 +#define DP_AUD_DEC_LAT1 0x025 + +#define DP_AUD_PP_LAT0 0x026 +#define DP_AUD_PP_LAT1 0x027 + +#define DP_VID_INTER_LAT 0x028 + +#define DP_VID_PROG_LAT 0x029 + +#define DP_REP_LAT 0x02a + +#define DP_AUD_DEL_INS0 0x02b +#define DP_AUD_DEL_INS1 0x02c +#define DP_AUD_DEL_INS2 0x02d +/* End of AV_SYNC_DATA_BLOCK */ + +#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ +# define DP_ALPM_CAP (1 << 0) + +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ +# define DP_AUX_FRAME_SYNC_CAP (1 << 0) + +#define DP_GUID 0x030 /* 1.2 */ + +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ +# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) + +#define DP_DSC_REV 0x061 +# define DP_DSC_MAJOR_MASK (0xf << 0) +# define DP_DSC_MINOR_MASK (0xf << 4) +# define DP_DSC_MAJOR_SHIFT 0 +# define DP_DSC_MINOR_SHIFT 4 + +#define DP_DSC_RC_BUF_BLK_SIZE 0x062 +# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 +# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 +# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 +# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 + +#define DP_DSC_RC_BUF_SIZE 0x063 + +#define DP_DSC_SLICE_CAP_1 0x064 +# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) +# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) +# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) +# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) +# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) +# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) +# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) + +#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 +# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) +# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 +# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 +# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 +# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 +# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 +# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 +# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 +# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 +# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 + +#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 +# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) + +#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ + +#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ + +#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 +# define DP_DSC_RGB (1 << 0) +# define DP_DSC_YCbCr444 (1 << 1) +# define DP_DSC_YCbCr422_Simple (1 << 2) +# define DP_DSC_YCbCr422_Native (1 << 3) +# define DP_DSC_YCbCr420_Native (1 << 4) + +#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A +# define DP_DSC_8_BPC (1 << 1) +# define DP_DSC_10_BPC (1 << 2) +# define DP_DSC_12_BPC (1 << 3) + +#define DP_DSC_PEAK_THROUGHPUT 0x06B +# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) +# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 +# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) +# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) +# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 +# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) + +#define DP_DSC_MAX_SLICE_WIDTH 0x06C + +#define DP_DSC_SLICE_CAP_2 0x06D +# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) +# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) +# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) + +#define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_BITS_PER_PIXEL_1_16 0x0 +# define DP_DSC_BITS_PER_PIXEL_1_8 0x1 +# define DP_DSC_BITS_PER_PIXEL_1_4 0x2 +# define DP_DSC_BITS_PER_PIXEL_1_2 0x3 +# define DP_DSC_BITS_PER_PIXEL_1 0x4 + +#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ +# define DP_PSR_IS_SUPPORTED 1 +# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ +# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ + +#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ +# define DP_PSR_NO_TRAIN_ON_EXIT 1 +# define DP_PSR_SETUP_TIME_330 (0 << 1) +# define DP_PSR_SETUP_TIME_275 (1 << 1) +# define DP_PSR_SETUP_TIME_220 (2 << 1) +# define DP_PSR_SETUP_TIME_165 (3 << 1) +# define DP_PSR_SETUP_TIME_110 (4 << 1) +# define DP_PSR_SETUP_TIME_55 (5 << 1) +# define DP_PSR_SETUP_TIME_0 (6 << 1) +# define DP_PSR_SETUP_TIME_MASK (7 << 1) +# define DP_PSR_SETUP_TIME_SHIFT 1 +# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ +# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ +/* + * 0x80-0x8f describe downstream port capabilities, but there are two layouts + * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, + * each port's descriptor is one byte wide. If it was set, each port's is + * four bytes wide, starting with the one byte from the base info. As of + * DP interop v1.1a only VGA defines additional detail. + */ + +/* offset 0 */ +#define DP_DOWNSTREAM_PORT_0 0x80 +# define DP_DS_PORT_TYPE_MASK (7 << 0) +# define DP_DS_PORT_TYPE_DP 0 +# define DP_DS_PORT_TYPE_VGA 1 +# define DP_DS_PORT_TYPE_DVI 2 +# define DP_DS_PORT_TYPE_HDMI 3 +# define DP_DS_PORT_TYPE_NON_EDID 4 +# define DP_DS_PORT_TYPE_DP_DUALMODE 5 +# define DP_DS_PORT_TYPE_WIRELESS 6 +# define DP_DS_PORT_HPD (1 << 3) +/* offset 1 for VGA is maximum megapixels per second / 8 */ +/* offset 2 */ +# define DP_DS_MAX_BPC_MASK (3 << 0) +# define DP_DS_8BPC 0 +# define DP_DS_10BPC 1 +# define DP_DS_12BPC 2 +# define DP_DS_16BPC 3 + +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY 0x090 /* 1.4 */ +# define DP_FEC_CAPABLE (1 << 0) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) +# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) + +/* link configuration */ +#define DP_LINK_BW_SET 0x100 +# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ +# define DP_LINK_BW_1_62 0x06 +# define DP_LINK_BW_2_7 0x0a +# define DP_LINK_BW_5_4 0x14 /* 1.2 */ +# define DP_LINK_BW_8_1 0x1e /* 1.4 */ + +#define DP_LANE_COUNT_SET 0x101 +# define DP_LANE_COUNT_MASK 0x0f +# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) + +#define DP_TRAINING_PATTERN_SET 0x102 +# define DP_TRAINING_PATTERN_DISABLE 0 +# define DP_TRAINING_PATTERN_1 1 +# define DP_TRAINING_PATTERN_2 2 +# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ +# define DP_TRAINING_PATTERN_4 7 /* 1.4 */ +# define DP_TRAINING_PATTERN_MASK 0x3 +# define DP_TRAINING_PATTERN_MASK_1_4 0xf + +/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ +# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) +# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) +# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) +# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) +# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) + +# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) +# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) + +# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) +# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) +# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) +# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) + +# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) + +# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) + +#define DP_DOWNSPREAD_CTRL 0x107 +# define DP_SPREAD_AMP_0_5 (1 << 4) +# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ + +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +# define DP_SET_ANSI_8B10B (1 << 0) + +#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ +/* bitmask as for DP_I2C_SPEED_CAP */ + +#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ +# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) +# define DP_FRAMING_CHANGE_ENABLE (1 << 1) +# define DP_PANEL_SELF_TEST_ENABLE (1 << 7) + +#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ +#define DP_LINK_QUAL_LANE1_SET 0x10c +#define DP_LINK_QUAL_LANE2_SET 0x10d +#define DP_LINK_QUAL_LANE3_SET 0x10e +# define DP_LINK_QUAL_PATTERN_DISABLE 0 +# define DP_LINK_QUAL_PATTERN_D10_2 1 +# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 +# define DP_LINK_QUAL_PATTERN_PRBS7 3 +# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 +# define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 +# define DP_LINK_QUAL_PATTERN_MASK 7 + +#define DP_TRAINING_LANE0_1_SET2 0x10f +#define DP_TRAINING_LANE2_3_SET2 0x110 +# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) +# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) +# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) +# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) + +#define DP_MSTM_CTRL 0x111 /* 1.2 */ +# define DP_MST_EN (1 << 0) +# define DP_UP_REQ_EN (1 << 1) +# define DP_UPSTREAM_IS_SRC (1 << 2) + +#define DP_AUDIO_DELAY0 0x112 /* 1.2 */ +#define DP_AUDIO_DELAY1 0x113 +#define DP_AUDIO_DELAY2 0x114 + +#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ +# define DP_LINK_RATE_SET_SHIFT 0 +# define DP_LINK_RATE_SET_MASK (7 << 0) + +#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ +# define DP_ALPM_ENABLE (1 << 0) +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) + +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ +# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) +# define DP_IRQ_HPD_ENABLE (1 << 1) + +#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ +# define DP_PWR_NOT_NEEDED (1 << 0) + +#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ +# define DP_FEC_READY (1 << 0) +# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) +# define DP_FEC_ERR_COUNT_DIS (0 << 1) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +# define DP_FEC_BIT_ERROR_COUNT (3 << 1) +# define DP_FEC_LANE_SELECT_MASK (3 << 4) +# define DP_FEC_LANE_0_SELECT (0 << 4) +# define DP_FEC_LANE_1_SELECT (1 << 4) +# define DP_FEC_LANE_2_SELECT (2 << 4) +# define DP_FEC_LANE_3_SELECT (3 << 4) + +#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ +# define DP_AUX_FRAME_SYNC_VALID (1 << 0) + +#define DP_DSC_ENABLE 0x160 /* DP 1.4 */ + +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ +# define DP_PSR_ENABLE (1 << 0) +# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) +# define DP_PSR_CRC_VERIFICATION (1 << 2) +# define DP_PSR_FRAME_CAPTURE (1 << 3) +# define DP_PSR_SELECTIVE_UPDATE (1 << 4) +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) +# define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ + +#define DP_ADAPTER_CTRL 0x1a0 +# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) + +#define DP_BRANCH_DEVICE_CTRL 0x1a1 +# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) + +#define DP_PAYLOAD_ALLOCATE_SET 0x1c0 +#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 +#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 + +#define DP_SINK_COUNT 0x200 +/* prior to 1.2 bit 7 was reserved mbz */ +# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) +# define DP_SINK_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) +# define DP_AUTOMATED_TEST_REQUEST (1 << 1) +# define DP_CP_IRQ (1 << 2) +# define DP_MCCS_IRQ (1 << 3) +# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ +# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ +# define DP_SINK_SPECIFIC_IRQ (1 << 6) + +#define DP_LANE0_1_STATUS 0x202 +#define DP_LANE2_3_STATUS 0x203 +# define DP_LANE_CR_DONE (1 << 0) +# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +# define DP_LANE_SYMBOL_LOCKED (1 << 2) + +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ + DP_LANE_CHANNEL_EQ_DONE | \ + DP_LANE_SYMBOL_LOCKED) + +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 + +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) + +#define DP_SINK_STATUS 0x205 + +#define DP_RECEIVE_PORT_0_STATUS (1 << 0) +#define DP_RECEIVE_PORT_1_STATUS (1 << 1) + +#define DP_ADJUST_REQUEST_LANE0_1 0x206 +#define DP_ADJUST_REQUEST_LANE2_3 0x207 +# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 +# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 +# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c +# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 +# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 +# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 +# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 +# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 + +#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c + +#define DP_TEST_REQUEST 0x218 +# define DP_TEST_LINK_TRAINING (1 << 0) +# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) +# define DP_TEST_LINK_EDID_READ (1 << 2) +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ + +#define DP_TEST_LINK_RATE 0x219 +# define DP_LINK_RATE_162 (0x6) +# define DP_LINK_RATE_27 (0xa) + +#define DP_TEST_LANE_COUNT 0x220 + +#define DP_TEST_PATTERN 0x221 +# define DP_NO_TEST_PATTERN 0x0 +# define DP_COLOR_RAMP 0x1 +# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 +# define DP_COLOR_SQUARE 0x3 + +#define DP_TEST_H_TOTAL_HI 0x222 +#define DP_TEST_H_TOTAL_LO 0x223 + +#define DP_TEST_V_TOTAL_HI 0x224 +#define DP_TEST_V_TOTAL_LO 0x225 + +#define DP_TEST_H_START_HI 0x226 +#define DP_TEST_H_START_LO 0x227 + +#define DP_TEST_V_START_HI 0x228 +#define DP_TEST_V_START_LO 0x229 + +#define DP_TEST_HSYNC_HI 0x22A +# define DP_TEST_HSYNC_POLARITY (1 << 7) +# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) +#define DP_TEST_HSYNC_WIDTH_LO 0x22B + +#define DP_TEST_VSYNC_HI 0x22C +# define DP_TEST_VSYNC_POLARITY (1 << 7) +# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) +#define DP_TEST_VSYNC_WIDTH_LO 0x22D + +#define DP_TEST_H_WIDTH_HI 0x22E +#define DP_TEST_H_WIDTH_LO 0x22F + +#define DP_TEST_V_HEIGHT_HI 0x230 +#define DP_TEST_V_HEIGHT_LO 0x231 + +#define DP_TEST_MISC0 0x232 +# define DP_TEST_SYNC_CLOCK (1 << 0) +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1) +# define DP_TEST_COLOR_FORMAT_SHIFT 1 +# define DP_COLOR_FORMAT_RGB (0 << 1) +# define DP_COLOR_FORMAT_YCbCr422 (1 << 1) +# define DP_COLOR_FORMAT_YCbCr444 (2 << 1) +# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) +# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) +# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) +# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) +# define DP_TEST_BIT_DEPTH_MASK (7 << 5) +# define DP_TEST_BIT_DEPTH_SHIFT 5 +# define DP_TEST_BIT_DEPTH_6 (0 << 5) +# define DP_TEST_BIT_DEPTH_8 (1 << 5) +# define DP_TEST_BIT_DEPTH_10 (2 << 5) +# define DP_TEST_BIT_DEPTH_12 (3 << 5) +# define DP_TEST_BIT_DEPTH_16 (4 << 5) + +#define DP_TEST_MISC1 0x233 +# define DP_TEST_REFRESH_DENOMINATOR (1 << 0) +# define DP_TEST_INTERLACED (1 << 1) + +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 + +#define DP_TEST_MISC0 0x232 + +#define DP_TEST_CRC_R_CR 0x240 +#define DP_TEST_CRC_G_Y 0x242 +#define DP_TEST_CRC_B_CB 0x244 + +#define DP_TEST_SINK_MISC 0x246 +# define DP_TEST_CRC_SUPPORTED (1 << 5) +# define DP_TEST_COUNT_MASK 0xf + +#define DP_TEST_PHY_PATTERN 0x248 +# define DP_TEST_PHY_PATTERN_NONE 0x0 +# define DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING 0x1 +# define DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT 0x2 +# define DP_TEST_PHY_PATTERN_PRBS7 0x3 +# define DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN 0x4 +# define DP_TEST_PHY_PATTERN_CP2520_PATTERN_1 0x5 +# define DP_TEST_PHY_PATTERN_CP2520_PATTERN_2 0x6 +# define DP_TEST_PHY_PATTERN_CP2520_PATTERN_3 0x7 +#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 +#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 +#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 +#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 +#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 +#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 +#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 +#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 +#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 +#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 + +#define DP_TEST_RESPONSE 0x260 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_TEST_EDID_CHECKSUM 0x261 + +#define DP_TEST_SINK 0x270 +# define DP_TEST_SINK_START (1 << 0) + +#define DP_FEC_STATUS 0x280 /* 1.4 */ +# define DP_FEC_DECODE_EN_DETECTED (1 << 0) +# define DP_FEC_DECODE_DIS_DETECTED (1 << 1) + +#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ + +#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ +# define DP_FEC_ERROR_COUNT_MASK 0x7F +# define DP_FEC_ERR_COUNT_VALID (1 << 7) + +#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ +# define DP_PAYLOAD_TABLE_UPDATED (1 << 0) +# define DP_PAYLOAD_ACT_HANDLED (1 << 1) + +#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ +/* up to ID_SLOT_63 at 0x2ff */ + +#define DP_SOURCE_OUI 0x300 +#define DP_SINK_OUI 0x400 +#define DP_BRANCH_OUI 0x500 +#define DP_BRANCH_ID 0x503 +#define DP_BRANCH_REVISION_START 0x509 +#define DP_BRANCH_HW_REV 0x509 +#define DP_BRANCH_SW_REV 0x50A + +#define DP_SET_POWER 0x600 +# define DP_SET_POWER_D0 0x1 +# define DP_SET_POWER_D3 0x2 +# define DP_SET_POWER_MASK 0x3 +# define DP_SET_POWER_D3_AUX_ON 0x5 + +#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ +# define DP_EDP_11 0x00 +# define DP_EDP_12 0x01 +# define DP_EDP_13 0x02 +# define DP_EDP_14 0x03 + +#define DP_EDP_GENERAL_CAP_1 0x701 +# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) +# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) +# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) +# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) +# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) +# define DP_EDP_FRC_ENABLE_CAP (1 << 5) +# define DP_EDP_COLOR_ENGINE_CAP (1 << 6) +# define DP_EDP_SET_POWER_CAP (1 << 7) + +#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 +# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) +# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) +# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) +# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) +# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) +# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) +# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) +# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) + +#define DP_EDP_GENERAL_CAP_2 0x703 +# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) + +#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ +# define DP_EDP_X_REGION_CAP_MASK (0xf << 0) +# define DP_EDP_X_REGION_CAP_SHIFT 0 +# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) +# define DP_EDP_Y_REGION_CAP_SHIFT 4 + +#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 +# define DP_EDP_BACKLIGHT_ENABLE (1 << 0) +# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) +# define DP_EDP_FRC_ENABLE (1 << 2) +# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) +# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) + +#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 +# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) +# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) +# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) +# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) +# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) +# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) +# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) +# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) +# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) +# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ + +#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 +#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 + +#define DP_EDP_PWMGEN_BIT_COUNT 0x724 +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 +# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) + +#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 + +#define DP_EDP_BACKLIGHT_FREQ_SET 0x728 +# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 + +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c + +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f + +#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 +#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 + +#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ +#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ + +#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ + +#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ +/* 0-5 sink count */ +# define DP_SINK_COUNT_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ +# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) +# define DP_LOCK_ACQUISITION_REQUEST (1 << 1) +# define DP_CEC_IRQ (1 << 2) + +#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ + +#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ +# define DP_PSR_LINK_CRC_ERROR (1 << 0) +# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) +# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ + +#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ +# define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ +# define DP_PSR_SINK_INACTIVE 0 +# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +# define DP_PSR_SINK_ACTIVE_RFB 2 +# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +# define DP_PSR_SINK_ACTIVE_RESYNC 4 +# define DP_PSR_SINK_INTERNAL_ERROR 7 +# define DP_PSR_SINK_STATE_MASK 0x07 + +#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ +# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) +# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 +# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) +# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 + +#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ +# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ +# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ +# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ +# define DP_SU_VALID (1 << 3) /* eDP 1.4 */ +# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ +# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ +# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ + +#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ +# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) + +#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ +#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ +#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ + +#define DP_DP13_DPCD_REV 0x2200 +#define DP_DP13_MAX_LINK_RATE 0x2201 + +#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ +# define DP_GTC_CAP (1 << 0) /* DP 1.3 */ +# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ +# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ +# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ +# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ +# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ +# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ +# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ + +/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ +#define DP_CEC_TUNNELING_CAPABILITY 0x3000 +# define DP_CEC_TUNNELING_CAPABLE (1 << 0) +# define DP_CEC_SNOOPING_CAPABLE (1 << 1) +# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) + +#define DP_CEC_TUNNELING_CONTROL 0x3001 +# define DP_CEC_TUNNELING_ENABLE (1 << 0) +# define DP_CEC_SNOOPING_ENABLE (1 << 1) + +#define DP_CEC_RX_MESSAGE_INFO 0x3002 +# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) +# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 +# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) +# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) +# define DP_CEC_RX_MESSAGE_ACKED (1 << 6) +# define DP_CEC_RX_MESSAGE_ENDED (1 << 7) + +#define DP_CEC_TX_MESSAGE_INFO 0x3003 +# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) +# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 +# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) +# define DP_CEC_TX_RETRY_COUNT_SHIFT 4 +# define DP_CEC_TX_MESSAGE_SEND (1 << 7) + +#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 +# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) +# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) +# define DP_CEC_TX_MESSAGE_SENT (1 << 4) +# define DP_CEC_TX_LINE_ERROR (1 << 5) +# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) +# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) + +#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ +# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) +# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) +# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) +# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) +# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) +# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) +# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) +# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) +#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ +# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) +# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) +# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) +# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) +# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) +# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) +# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) +# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) + +#define DP_CEC_RX_MESSAGE_BUFFER 0x3010 +#define DP_CEC_TX_MESSAGE_BUFFER 0x3020 +#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 + +#define DP_AUX_HDCP_BKSV 0x68000 +#define DP_AUX_HDCP_RI_PRIME 0x68005 +#define DP_AUX_HDCP_AKSV 0x68007 +#define DP_AUX_HDCP_AN 0x6800C +#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + (h) * 4) +#define DP_AUX_HDCP_BCAPS 0x68028 +# define DP_BCAPS_REPEATER_PRESENT BIT(1) +# define DP_BCAPS_HDCP_CAPABLE BIT(0) +#define DP_AUX_HDCP_BSTATUS 0x68029 +# define DP_BSTATUS_REAUTH_REQ BIT(3) +# define DP_BSTATUS_LINK_FAILURE BIT(2) +# define DP_BSTATUS_R0_PRIME_READY BIT(1) +# define DP_BSTATUS_READY BIT(0) +#define DP_AUX_HDCP_BINFO 0x6802A +#define DP_AUX_HDCP_KSV_FIFO 0x6802C +#define DP_AUX_HDCP_AINFO 0x6803B + +/* DP 1.2 Sideband message defines */ +/* peer device type - DP 1.2a Table 2-92 */ +#define DP_PEER_DEVICE_NONE 0x0 +#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 +#define DP_PEER_DEVICE_MST_BRANCHING 0x2 +#define DP_PEER_DEVICE_SST_SINK 0x3 +#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 + +/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ +#define DP_LINK_ADDRESS 0x01 +#define DP_CONNECTION_STATUS_NOTIFY 0x02 +#define DP_ENUM_PATH_RESOURCES 0x10 +#define DP_ALLOCATE_PAYLOAD 0x11 +#define DP_QUERY_PAYLOAD 0x12 +#define DP_RESOURCE_STATUS_NOTIFY 0x13 +#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 +#define DP_REMOTE_DPCD_READ 0x20 +#define DP_REMOTE_DPCD_WRITE 0x21 +#define DP_REMOTE_I2C_READ 0x22 +#define DP_REMOTE_I2C_WRITE 0x23 +#define DP_POWER_UP_PHY 0x24 +#define DP_POWER_DOWN_PHY 0x25 +#define DP_SINK_EVENT_NOTIFY 0x30 +#define DP_QUERY_STREAM_ENC_STATUS 0x38 + +/* DP 1.2 MST sideband nak reasons - table 2.84 */ +#define DP_NAK_WRITE_FAILURE 0x01 +#define DP_NAK_INVALID_READ 0x02 +#define DP_NAK_CRC_FAILURE 0x03 +#define DP_NAK_BAD_PARAM 0x04 +#define DP_NAK_DEFER 0x05 +#define DP_NAK_LINK_FAILURE 0x06 +#define DP_NAK_NO_RESOURCES 0x07 +#define DP_NAK_DPCD_FAIL 0x08 +#define DP_NAK_I2C_NAK 0x09 +#define DP_NAK_ALLOCATE_FAIL 0x0a + +#define MODE_I2C_START 1 +#define MODE_I2C_WRITE 2 +#define MODE_I2C_READ 4 +#define MODE_I2C_STOP 8 + +/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ +#define DP_MST_PHYSICAL_PORT_0 0 +#define DP_MST_LOGICAL_PORT_0 8 + +#define DP_LINK_STATUS_SIZE 6 +bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count); +bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count); +u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane); +u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane); + +#define DP_BRANCH_OUI_HEADER_SIZE 0xc +#define DP_RECEIVER_CAP_SIZE 0xf +#define EDP_PSR_RECEIVER_CAP_SIZE 2 +#define EDP_DISPLAY_CTL_CAP_SIZE 3 + +void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); + +u8 drm_dp_link_rate_to_bw_code(int link_rate); +int drm_dp_bw_code_to_link_rate(u8 link_bw); + +#define DP_SDP_AUDIO_TIMESTAMP 0x01 +#define DP_SDP_AUDIO_STREAM 0x02 +#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ +#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ +#define DP_SDP_ISRC 0x06 /* DP 1.2 */ +#define DP_SDP_VSC 0x07 /* DP 1.2 */ +#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ +#define DP_SDP_PPS 0x10 /* DP 1.4 */ +#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ +#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ +/* 0x80+ CEA-861 infoframe types */ + +#pragma pack(1) +struct dp_sdp_header { + u8 HB0; /* Secondary Data Packet ID */ + u8 HB1; /* Secondary Data Packet Type */ + u8 HB2; /* Secondary Data Packet Specific header, Byte 0 */ + u8 HB3; /* Secondary Data packet Specific header, Byte 1 */ +}; +#pragma pack() + +#define EDP_SDP_HEADER_REVISION_MASK 0x1F +#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F +#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F + +#pragma pack(1) +struct edp_vsc_psr { + struct dp_sdp_header sdp_header; + u8 DB0; /* Stereo Interface */ + u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ + u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ + u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ + u8 DB4; /* CRC value bits 7:0 of the G or Y component */ + u8 DB5; /* CRC value bits 15:8 of the G or Y component */ + u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ + u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ + u8 DB8_31[24]; /* Reserved */ +}; +#pragma pack() + +#define EDP_VSC_PSR_STATE_ACTIVE (1 << 0) +#define EDP_VSC_PSR_UPDATE_RFB (1 << 1) +#define EDP_VSC_PSR_CRC_VALUES_VALID (1 << 2) + +enum dp_pixelformat { + DP_PIXELFORMAT_RGB = 0, + DP_PIXELFORMAT_YUV444 = 0x1, + DP_PIXELFORMAT_YUV422 = 0x2, + DP_PIXELFORMAT_YUV420 = 0x3, + DP_PIXELFORMAT_Y_ONLY = 0x4, + DP_PIXELFORMAT_RAW = 0x5, + DP_PIXELFORMAT_RESERVED = 0x6, +}; + +enum dp_colorimetry { + DP_COLORIMETRY_DEFAULT = 0, + DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1, + DP_COLORIMETRY_BT709_YCC = 0x1, + DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2, + DP_COLORIMETRY_XVYCC_601 = 0x2, + DP_COLORIMETRY_OPRGB = 0x3, + DP_COLORIMETRY_XVYCC_709 = 0x3, + DP_COLORIMETRY_DCI_P3_RGB = 0x4, + DP_COLORIMETRY_SYCC_601 = 0x4, + DP_COLORIMETRY_RGB_CUSTOM = 0x5, + DP_COLORIMETRY_OPYCC_601 = 0x5, + DP_COLORIMETRY_BT2020_RGB = 0x6, + DP_COLORIMETRY_BT2020_CYCC = 0x6, + DP_COLORIMETRY_BT2020_YCC = 0x7, +}; + +enum dp_dynamic_range { + DP_DYNAMIC_RANGE_VESA = 0, + DP_DYNAMIC_RANGE_CTA = 1, +}; + +enum dp_content_type { + DP_CONTENT_TYPE_NOT_DEFINED = 0x00, + DP_CONTENT_TYPE_GRAPHICS = 0x01, + DP_CONTENT_TYPE_PHOTO = 0x02, + DP_CONTENT_TYPE_VIDEO = 0x03, + DP_CONTENT_TYPE_GAME = 0x04, +}; + +struct drm_dp_vsc_sdp { + unsigned char sdp_type; + unsigned char revision; + unsigned char length; + enum dp_pixelformat pixelformat; + enum dp_colorimetry colorimetry; + int bpc; + enum dp_dynamic_range dynamic_range; + enum dp_content_type content_type; +}; + +static inline int +drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); +} + +static inline u8 +drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; +} + +static inline bool +drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DPCD_REV] >= 0x11 && + (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); +} + +static inline bool +drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DPCD_REV] >= 0x12 && + dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; +} + +static inline bool +drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DPCD_REV] >= 0x14 && + dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; +} + +static inline u8 +drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : + DP_TRAINING_PATTERN_MASK; +} + +static inline bool +drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; +} + +static inline bool +drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; +} + +struct drm_dp_aux_msg { + unsigned int address; + u8 request; + u8 reply; + void *buffer; + size_t size; +}; + +struct drm_dp_aux { + const char *name; + ssize_t (*transfer)(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg); + unsigned int i2c_nack_count; + unsigned int i2c_defer_count; +}; + +ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size); +ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size); + +/** + * drm_dp_dpcd_readb() - read a single byte from the DPCD + * @aux: DisplayPort AUX channel + * @offset: address of the register to read + * @valuep: location where the value of the register will be stored + * + * Returns the number of bytes transferred (1) on success, or a negative + * error code on failure. + */ +static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, + unsigned int offset, u8 *valuep) +{ + return drm_dp_dpcd_read(aux, offset, valuep, 1); +} + +/** + * drm_dp_dpcd_writeb() - write a single byte to the DPCD + * @aux: DisplayPort AUX channel + * @offset: address of the register to write + * @value: value to write to the register + * + * Returns the number of bytes transferred (1) on success, or a negative + * error code on failure. + */ +static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, + unsigned int offset, u8 value) +{ + return drm_dp_dpcd_write(aux, offset, &value, 1); +} + +int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]); + +int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, + u8 status[DP_LINK_STATUS_SIZE]); + +#endif /* _DRM_DP_HELPER_H_ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_dsc.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_dsc.h new file mode 100644 index 0000000..3cb6eb9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_dsc.h @@ -0,0 +1,613 @@ +/* SPDX-License-Identifier: MIT + * Copyright (C) 2018 Intel Corp. + * + * Authors: + * Manasi Navare + */ + +#ifndef DRM_DSC_H_ +#define DRM_DSC_H_ + +#include + +/* VESA Display Stream Compression DSC 1.2 constants */ +#define DSC_NUM_BUF_RANGES 15 +#define DSC_MUX_WORD_SIZE_8_10_BPC 48 +#define DSC_MUX_WORD_SIZE_12_BPC 64 +#define DSC_RC_PIXELS_PER_GROUP 3 +#define DSC_SCALE_DECREMENT_INTERVAL_MAX 4095 +#define DSC_RANGE_BPG_OFFSET_MASK 0x3f + +/* DSC Rate Control Constants */ +#define DSC_RC_MODEL_SIZE_CONST 8192 +#define DSC_RC_EDGE_FACTOR_CONST 6 +#define DSC_RC_TGT_OFFSET_HI_CONST 3 +#define DSC_RC_TGT_OFFSET_LO_CONST 3 + +/* DSC PPS constants and macros */ +#define DSC_PPS_VERSION_MAJOR_SHIFT 4 +#define DSC_PPS_BPC_SHIFT 4 +#define DSC_PPS_MSB_SHIFT 8 +#define DSC_PPS_LSB_MASK (0xFF << 0) +#define DSC_PPS_BPP_HIGH_MASK (0x3 << 8) +#define DSC_PPS_VBR_EN_SHIFT 2 +#define DSC_PPS_SIMPLE422_SHIFT 3 +#define DSC_PPS_CONVERT_RGB_SHIFT 4 +#define DSC_PPS_BLOCK_PRED_EN_SHIFT 5 +#define DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK (0x3 << 8) +#define DSC_PPS_SCALE_DEC_INT_HIGH_MASK (0xF << 8) +#define DSC_PPS_RC_TGT_OFFSET_HI_SHIFT 4 +#define DSC_PPS_RC_RANGE_MINQP_SHIFT 11 +#define DSC_PPS_RC_RANGE_MAXQP_SHIFT 6 +#define DSC_PPS_NATIVE_420_SHIFT 1 +#define DSC_1_2_MAX_LINEBUF_DEPTH_BITS 16 +#define DSC_1_2_MAX_LINEBUF_DEPTH_VAL 0 +#define DSC_1_1_MAX_LINEBUF_DEPTH_BITS 13 + +/** + * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters + * + * This defines different rate control parameters used by the DSC engine + * to compress the frame. + */ +struct drm_dsc_rc_range_parameters { + /** + * @range_min_qp: Min Quantization Parameters allowed for this range + */ + u8 range_min_qp; + /** + * @range_max_qp: Max Quantization Parameters allowed for this range + */ + u8 range_max_qp; + /** + * @range_bpg_offset: + * Bits/group offset to apply to target for this group + */ + u8 range_bpg_offset; +}; + +/** + * struct drm_dsc_config - Parameters required to configure DSC + * + * Driver populates this structure with all the parameters required + * to configure the display stream compression on the source. + */ +struct drm_dsc_config { + /** + * @line_buf_depth: + * Bits per component for previous reconstructed line buffer + */ + u8 line_buf_depth; + /** + * @bits_per_component: Bits per component to code (8/10/12) + */ + u8 bits_per_component; + /** + * @convert_rgb: + * Flag to indicate if RGB - YCoCg conversion is needed + * True if RGB input, False if YCoCg input + */ + bool convert_rgb; + /** + * @slice_count: Number of slices per line used by the DSC encoder + */ + u8 slice_count; + /** + * @slice_width: Width of each slice in pixels + */ + u16 slice_width; + /** + * @slice_height: Slice height in pixels + */ + u16 slice_height; + /** + * @simple_422: True if simple 4_2_2 mode is enabled else False + */ + bool simple_422; + /** + * @pic_width: Width of the input display frame in pixels + */ + u16 pic_width; + /** + * @pic_height: Vertical height of the input display frame + */ + u16 pic_height; + /** + * @rc_tgt_offset_high: + * Offset to bits/group used by RC to determine QP adjustment + */ + u8 rc_tgt_offset_high; + /** + * @rc_tgt_offset_low: + * Offset to bits/group used by RC to determine QP adjustment + */ + u8 rc_tgt_offset_low; + /** + * @bits_per_pixel: + * Target bits per pixel with 4 fractional bits, bits_per_pixel << 4 + */ + u16 bits_per_pixel; + /** + * @rc_edge_factor: + * Factor to determine if an edge is present based on the bits produced + */ + u8 rc_edge_factor; + /** + * @rc_quant_incr_limit1: + * Slow down incrementing once the range reaches this value + */ + u8 rc_quant_incr_limit1; + /** + * @rc_quant_incr_limit0: + * Slow down incrementing once the range reaches this value + */ + u8 rc_quant_incr_limit0; + /** + * @initial_xmit_delay: + * Number of pixels to delay the initial transmission + */ + u16 initial_xmit_delay; + /** + * @initial_dec_delay: + * Initial decoder delay, number of pixel times that the decoder + * accumulates data in its rate buffer before starting to decode + * and output pixels. + */ + u16 initial_dec_delay; + /** + * @block_pred_enable: + * True if block prediction is used to code any groups within the + * picture. False if BP not used + */ + bool block_pred_enable; + /** + * @first_line_bpg_offset: + * Number of additional bits allocated for each group on the first + * line of slice. + */ + u8 first_line_bpg_offset; + /** + * @initial_offset: Value to use for RC model offset at slice start + */ + u16 initial_offset; + /** + * @rc_buf_thresh: Thresholds defining each of the buffer ranges + */ + u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; + /** + * @rc_range_params: + * Parameters for each of the RC ranges defined in + * &struct drm_dsc_rc_range_parameters + */ + struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; + /** + * @rc_model_size: Total size of RC model + */ + u16 rc_model_size; + /** + * @flatness_min_qp: Minimum QP where flatness information is sent + */ + u8 flatness_min_qp; + /** + * @flatness_max_qp: Maximum QP where flatness information is sent + */ + u8 flatness_max_qp; + /** + * @initial_scale_value: Initial value for the scale factor + */ + u8 initial_scale_value; + /** + * @scale_decrement_interval: + * Specifies number of group times between decrementing the scale factor + * at beginning of a slice. + */ + u16 scale_decrement_interval; + /** + * @scale_increment_interval: + * Number of group times between incrementing the scale factor value + * used at the beginning of a slice. + */ + u16 scale_increment_interval; + /** + * @nfl_bpg_offset: Non first line BPG offset to be used + */ + u16 nfl_bpg_offset; + /** + * @slice_bpg_offset: BPG offset used to enforce slice bit + */ + u16 slice_bpg_offset; + /** + * @final_offset: Final RC linear transformation offset value + */ + u16 final_offset; + /** + * @vbr_enable: True if VBR mode is enabled, false if disabled + */ + bool vbr_enable; + /** + * @mux_word_size: Mux word size (in bits) for SSM mode + */ + u8 mux_word_size; + /** + * @slice_chunk_size: + * The (max) size in bytes of the "chunks" that are used in slice + * multiplexing. + */ + u16 slice_chunk_size; + /** + * @rc_bits: Rate control buffer size in bits + */ + u16 rc_bits; + /** + * @dsc_version_minor: DSC minor version + */ + u8 dsc_version_minor; + /** + * @dsc_version_major: DSC major version + */ + u8 dsc_version_major; + /** + * @native_422: True if Native 4:2:2 supported, else false + */ + bool native_422; + /** + * @native_420: True if Native 4:2:0 supported else false. + */ + bool native_420; + /** + * @second_line_bpg_offset: + * Additional bits/grp for seconnd line of slice for native 4:2:0 + */ + u8 second_line_bpg_offset; + /** + * @nsl_bpg_offset: + * Num of bits deallocated for each grp that is not in second line of + * slice + */ + u16 nsl_bpg_offset; + /** + * @second_line_offset_adj: + * Offset adjustment for second line in Native 4:2:0 mode + */ + u16 second_line_offset_adj; +}; + +/** + * struct picture_parameter_set - Represents 128 bytes of Picture Parameter Set + * + * The VESA DSC standard defines picture parameter set (PPS) which display + * stream compression encoders must communicate to decoders. + * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in + * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. + * The PPS fields that span over more than a byte should be stored in Big Endian + * format. + */ +#pragma pack(1) +struct drm_dsc_picture_parameter_set { + /** + * @dsc_version: + * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC + * PPS0[7:4] - dsc_version_major: Contains major version of DSC + */ + u8 dsc_version; + /** + * @pps_identifier: + * PPS1[7:0] - Application specific identifier that can be + * used to differentiate between different PPS tables. + */ + u8 pps_identifier; + /** + * @pps_reserved: + * PPS2[7:0]- RESERVED Byte + */ + u8 pps_reserved; + /** + * @pps_3: + * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to + * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, + * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, + * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. + * PPS3[7:4] - bits_per_component: Bits per component for the original + * pixels of the encoded picture. + * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) + * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also + * allowed only when dsc_minor_version = 0x2) + */ + u8 pps_3; + /** + * @pps_4: + * PPS4[1:0] -These are the most significant 2 bits of + * compressed BPP bits_per_pixel[9:0] syntax element. + * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled + * PPS4[3] - simple_422: Indicates if decoder drops samples to + * reconstruct the 4:2:2 picture. + * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is + * active. + * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any + * groups in picture + * PPS4[7:6] - Reserved bits + */ + u8 pps_4; + /** + * @bits_per_pixel_low: + * PPS5[7:0] - This indicates the lower significant 8 bits of + * the compressed BPP bits_per_pixel[9:0] element. + */ + u8 bits_per_pixel_low; + /** + * @pic_height: + * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows + * within the raster. + */ + __be16 pic_height; + /** + * @pic_width: + * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within + * the raster. + */ + __be16 pic_width; + /** + * @slice_height: + * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. + */ + __be16 slice_height; + /** + * @slice_width: + * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. + */ + __be16 slice_width; + /** + * @chunk_size: + * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks + * that are used for slice multiplexing. + */ + __be16 chunk_size; + /** + * @initial_xmit_delay_high: + * PPS16[1:0] - Most Significant two bits of initial transmission delay. + * It specifies the number of pixel times that the encoder waits before + * transmitting data from its rate buffer. + * PPS16[7:2] - Reserved + */ + u8 initial_xmit_delay_high; + /** + * @initial_xmit_delay_low: + * PPS17[7:0] - Least significant 8 bits of initial transmission delay. + */ + u8 initial_xmit_delay_low; + /** + * @initial_dec_delay: + * + * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number + * of pixel times that the decoder accumulates data in its rate buffer + * before starting to decode and output pixels. + */ + __be16 initial_dec_delay; + /** + * @pps20_reserved: + * + * PPS20[7:0] - Reserved + */ + u8 pps20_reserved; + /** + * @initial_scale_value: + * PPS21[5:0] - Initial rcXformScale factor used at beginning + * of a slice. + * PPS21[7:6] - Reserved + */ + u8 initial_scale_value; + /** + * @scale_increment_interval: + * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing + * the rcXformScale factor at end of a slice. + */ + __be16 scale_increment_interval; + /** + * @scale_decrement_interval_high: + * PPS24[3:0] - Higher 4 bits indicating number of group times between + * decrementing the rcXformScale factor at beginning of a slice. + * PPS24[7:4] - Reserved + */ + u8 scale_decrement_interval_high; + /** + * @scale_decrement_interval_low: + * PPS25[7:0] - Lower 8 bits of scale decrement interval + */ + u8 scale_decrement_interval_low; + /** + * @pps26_reserved: + * PPS26[7:0] + */ + u8 pps26_reserved; + /** + * @first_line_bpg_offset: + * PPS27[4:0] - Number of additional bits that are allocated + * for each group on first line of a slice. + * PPS27[7:5] - Reserved + */ + u8 first_line_bpg_offset; + /** + * @nfl_bpg_offset: + * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits + * deallocated for each group for groups after the first line of slice. + */ + __be16 nfl_bpg_offset; + /** + * @slice_bpg_offset: + * PPS30, PPS31[7:0] - Number of bits that are deallocated for each + * group to enforce the slice constraint. + */ + __be16 slice_bpg_offset; + /** + * @initial_offset: + * PPS32,33[7:0] - Initial value for rcXformOffset + */ + __be16 initial_offset; + /** + * @final_offset: + * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset + */ + __be16 final_offset; + /** + * @flatness_min_qp: + * PPS36[4:0] - Minimum QP at which flatness is signaled and + * flatness QP adjustment is made. + * PPS36[7:5] - Reserved + */ + u8 flatness_min_qp; + /** + * @flatness_max_qp: + * PPS37[4:0] - Max QP at which flatness is signalled and + * the flatness adjustment is made. + * PPS37[7:5] - Reserved + */ + u8 flatness_max_qp; + /** + * @rc_model_size: + * PPS38,39[7:0] - Number of bits within RC Model. + */ + __be16 rc_model_size; + /** + * @rc_edge_factor: + * PPS40[3:0] - Ratio of current activity vs, previous + * activity to determine presence of edge. + * PPS40[7:4] - Reserved + */ + u8 rc_edge_factor; + /** + * @rc_quant_incr_limit0: + * PPS41[4:0] - QP threshold used in short term RC + * PPS41[7:5] - Reserved + */ + u8 rc_quant_incr_limit0; + /** + * @rc_quant_incr_limit1: + * PPS42[4:0] - QP threshold used in short term RC + * PPS42[7:5] - Reserved + */ + u8 rc_quant_incr_limit1; + /** + * @rc_tgt_offset: + * PPS43[3:0] - Lower end of the variability range around the target + * bits per group that is allowed by short term RC. + * PPS43[7:4]- Upper end of the variability range around the target + * bits per group that i allowed by short term rc. + */ + u8 rc_tgt_offset; + /** + * @rc_buf_thresh: + * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for + * the 15 ranges defined by 14 thresholds. + */ + u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; + /** + * @rc_range_parameters: + * PPS58[7:0] - PPS87[7:0] + * Parameters that correspond to each of the 15 ranges. + */ + __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; + /** + * @native_422_420: + * PPS88[0] - 0 = Native 4:2:2 not used + * 1 = Native 4:2:2 used + * PPS88[1] - 0 = Native 4:2:0 not use + * 1 = Native 4:2:0 used + * PPS88[7:2] - Reserved 6 bits + */ + u8 native_422_420; + /** + * @second_line_bpg_offset: + * PPS89[4:0] - Additional bits/group budget for the + * second line of a slice in Native 4:2:0 mode. + * Set to 0 if DSC minor version is 1 or native420 is 0. + * PPS89[7:5] - Reserved + */ + u8 second_line_bpg_offset; + /** + * @nsl_bpg_offset: + * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated + * for each group that is not in the second line of a slice. + */ + __be16 nsl_bpg_offset; + /** + * @second_line_offset_adj: + * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second + * line in Native 4:2:0 mode. + */ + __be16 second_line_offset_adj; + /** + * @pps_long_94_reserved: + * PPS 94, 95, 96, 97 - Reserved + */ + u32 pps_long_94_reserved; + /** + * @pps_long_98_reserved: + * PPS 98, 99, 100, 101 - Reserved + */ + u32 pps_long_98_reserved; + /** + * @pps_long_102_reserved: + * PPS 102, 103, 104, 105 - Reserved + */ + u32 pps_long_102_reserved; + /** + * @pps_long_106_reserved: + * PPS 106, 107, 108, 109 - reserved + */ + u32 pps_long_106_reserved; + /** + * @pps_long_110_reserved: + * PPS 110, 111, 112, 113 - reserved + */ + u32 pps_long_110_reserved; + /** + * @pps_long_114_reserved: + * PPS 114 - 117 - reserved + */ + u32 pps_long_114_reserved; + /** + * @pps_long_118_reserved: + * PPS 118 - 121 - reserved + */ + u32 pps_long_118_reserved; + /** + * @pps_long_122_reserved: + * PPS 122- 125 - reserved + */ + u32 pps_long_122_reserved; + /** + * @pps_short_126_reserved: + * PPS 126, 127 - reserved + */ + __be16 pps_short_126_reserved; +}; +#pragma pack() + +/** + * struct drm_dsc_pps_infoframe - DSC infoframe carrying the Picture Parameter + * Set Metadata + * + * This structure represents the DSC PPS infoframe required to send the Picture + * Parameter Set metadata required before enabling VESA Display Stream + * Compression. This is based on the DP Secondary Data Packet structure and + * comprises of SDP Header as defined &struct dp_sdp_header in drm_dp_helper.h + * and PPS payload defined in &struct drm_dsc_picture_parameter_set. + * + * @pps_header: Header for PPS as per DP SDP header format of type + * &struct dp_sdp_header + * @pps_payload: PPS payload fields as per DSC specification Table 4-1 + * as represented in &struct drm_dsc_picture_parameter_set + */ +#pragma pack(1) +struct drm_dsc_pps_infoframe { + struct dp_sdp_header pps_header; + struct drm_dsc_picture_parameter_set pps_payload; +}; +#pragma pack() + +void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, + const struct drm_dsc_config *dsc_cfg); +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); + +#endif /* _DRM_DSC_H_ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_mipi_dsi.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_mipi_dsi.h new file mode 100644 index 0000000..05f0749 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/drm_mipi_dsi.h @@ -0,0 +1,256 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * MIPI DSI Bus + * + * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd. + * Andrzej Hajda + */ + +#ifndef __DRM_MIPI_DSI_H__ +#define __DRM_MIPI_DSI_H__ + +#include +#include + +struct mipi_dsi_host; +struct mipi_dsi_device; + +/* request ACK from peripheral */ +#define MIPI_DSI_MSG_REQ_ACK BIT(0) +/* use Low Power Mode to transmit message */ +#define MIPI_DSI_MSG_USE_LPM BIT(1) + +/** + * struct mipi_dsi_msg - read/write DSI buffer + * @channel: virtual channel id + * @type: payload data type + * @flags: flags controlling this message transmission + * @tx_len: length of @tx_buf + * @tx_buf: data to be written + * @rx_len: length of @rx_buf + * @rx_buf: data to be read, or NULL + */ +struct mipi_dsi_msg { + u8 channel; + u8 type; + u16 flags; + + size_t tx_len; + const void *tx_buf; + + size_t rx_len; + void *rx_buf; +}; + +bool mipi_dsi_packet_format_is_short(u8 type); +bool mipi_dsi_packet_format_is_long(u8 type); + +/** + * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format + * @size: size (in bytes) of the packet + * @header: the four bytes that make up the header (Data ID, Word Count or + * Packet Data, and ECC) + * @payload_length: number of bytes in the payload + * @payload: a pointer to a buffer containing the payload, if any + */ +struct mipi_dsi_packet { + size_t size; + u8 header[4]; + size_t payload_length; + const u8 *payload; +}; + +int mipi_dsi_create_packet(struct mipi_dsi_packet *packet, + const struct mipi_dsi_msg *msg); + +/** + * struct mipi_dsi_host_ops - DSI bus operations + * @attach: attach DSI device to DSI host + * @detach: detach DSI device from DSI host + * @transfer: transmit a DSI packet + * + * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg + * structures. This structure contains information about the type of packet + * being transmitted as well as the transmit and receive buffers. When an + * error is encountered during transmission, this function will return a + * negative error code. On success it shall return the number of bytes + * transmitted for write packets or the number of bytes received for read + * packets. + * + * Note that typically DSI packet transmission is atomic, so the .transfer() + * function will seldomly return anything other than the number of bytes + * contained in the transmit buffer on success. + */ +struct mipi_dsi_host_ops { + int (*attach)(struct mipi_dsi_host *host, + struct mipi_dsi_device *dsi); + int (*detach)(struct mipi_dsi_host *host, + struct mipi_dsi_device *dsi); + ssize_t (*transfer)(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg); +}; + +/** + * struct mipi_dsi_host - DSI host device + * @dev: driver model device node for this DSI host + * @ops: DSI host operations + * @list: list management + */ +struct mipi_dsi_host { + struct udevice *dev; + const struct mipi_dsi_host_ops *ops; +}; + +/* DSI mode flags */ + +/* video mode */ +#define MIPI_DSI_MODE_VIDEO BIT(0) +/* video burst mode */ +#define MIPI_DSI_MODE_VIDEO_BURST BIT(1) +/* video pulse mode */ +#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) +/* enable auto vertical count mode */ +#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) +/* enable hsync-end packets in vsync-pulse and v-porch area */ +#define MIPI_DSI_MODE_VIDEO_HSE BIT(4) +/* disable hfront-porch area */ +#define MIPI_DSI_MODE_VIDEO_HFP BIT(5) +/* disable hback-porch area */ +#define MIPI_DSI_MODE_VIDEO_HBP BIT(6) +/* disable hsync-active area */ +#define MIPI_DSI_MODE_VIDEO_HSA BIT(7) +/* flush display FIFO on vsync pulse */ +#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) +/* disable EoT packets in HS mode */ +#define MIPI_DSI_MODE_EOT_PACKET BIT(9) +/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ +#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) +/* transmit data in low power */ +#define MIPI_DSI_MODE_LPM BIT(11) + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565, +}; + +#define DSI_DEV_NAME_SIZE 20 + +/** + * struct mipi_dsi_device - DSI peripheral device + * @host: DSI host for this peripheral + * @dev: driver model device node for this peripheral + * @name: DSI peripheral chip type + * @channel: virtual channel assigned to the peripheral + * @format: pixel format for video mode + * @lanes: number of active data lanes + * @mode_flags: DSI operation mode related flags + * @hs_rate: maximum lane frequency for high speed mode in hertz, this should + * be set to the real limits of the hardware, zero is only accepted for + * legacy drivers + * @lp_rate: maximum lane frequency for low power mode in hertz, this should + * be set to the real limits of the hardware, zero is only accepted for + * legacy drivers + */ +struct mipi_dsi_device { + struct mipi_dsi_host *host; + struct udevice *dev; + + char name[DSI_DEV_NAME_SIZE]; + unsigned int channel; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; + unsigned long hs_rate; + unsigned long lp_rate; +}; + +/** + * mipi_dsi_pixel_format_to_bpp - obtain the number of bits per pixel for any + * given pixel format defined by the MIPI DSI + * specification + * @fmt: MIPI DSI pixel format + * + * Returns: The number of bits per pixel of the given pixel format. + */ +static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt) +{ + switch (fmt) { + case MIPI_DSI_FMT_RGB888: + case MIPI_DSI_FMT_RGB666: + return 24; + + case MIPI_DSI_FMT_RGB666_PACKED: + return 18; + + case MIPI_DSI_FMT_RGB565: + return 16; + } + + return -EINVAL; +} + +int mipi_dsi_attach(struct mipi_dsi_device *dsi); +int mipi_dsi_detach(struct mipi_dsi_device *dsi); +int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi); +int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi); +int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi, + u16 value); + +ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable); +ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi, + const struct drm_dsc_picture_parameter_set *pps); + +ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload, + size_t size); +ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params, + size_t num_params, void *data, size_t size); + +/** + * enum mipi_dsi_dcs_tear_mode - Tearing Effect Output Line mode + * @MIPI_DSI_DCS_TEAR_MODE_VBLANK: the TE output line consists of V-Blanking + * information only + * @MIPI_DSI_DCS_TEAR_MODE_VHBLANK : the TE output line consists of both + * V-Blanking and H-Blanking information + */ +enum mipi_dsi_dcs_tear_mode { + MIPI_DSI_DCS_TEAR_MODE_VBLANK, + MIPI_DSI_DCS_TEAR_MODE_VHBLANK, +}; + +#define MIPI_DSI_DCS_POWER_MODE_DISPLAY BIT(2) +#define MIPI_DSI_DCS_POWER_MODE_NORMAL BIT(3) +#define MIPI_DSI_DCS_POWER_MODE_SLEEP BIT(4) +#define MIPI_DSI_DCS_POWER_MODE_PARTIAL BIT(5) +#define MIPI_DSI_DCS_POWER_MODE_IDLE BIT(6) + +ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi, + const void *data, size_t len); +ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd, + const void *data, size_t len); +ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data, + size_t len); +int mipi_dsi_dcs_nop(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_soft_reset(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode); +int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format); +int mipi_dsi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_set_display_off(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start, + u16 end); +int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start, + u16 end); +int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, + enum mipi_dsi_dcs_tear_mode mode); +int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format); +int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline); +int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi, + u16 brightness); +int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, + u16 *brightness); + +#endif /* __DRM_MIPI_DSI__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/errno.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/errno.h new file mode 100644 index 0000000..3767df3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/errno.h @@ -0,0 +1,168 @@ +#ifndef _LINUX_ERRNO_H +#define _LINUX_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ + +#define ENOSYS 38 /* Invalid system call number */ + +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ +#define ECANCELED 125 /* Operation Canceled */ +#define ENOKEY 126 /* Required key not available */ +#define EKEYEXPIRED 127 /* Key has expired */ +#define EKEYREVOKED 128 /* Key has been revoked */ +#define EKEYREJECTED 129 /* Key was rejected by service */ + +/* for robust mutexes */ +#define EOWNERDEAD 130 /* Owner died */ +#define ENOTRECOVERABLE 131 /* State not recoverable */ + +#define ERFKILL 132 /* Operation not possible due to RF-kill */ + +#define EHWPOISON 133 /* Memory page has hardware error */ + +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ +#define ERESTART_RESTARTBLOCK 516 /* restart by calling sys_restart_syscall */ +#define EPROBE_DEFER 517 /* Driver requests probe retry */ +#define EOPENSTALE 518 /* open found a stale dentry */ + +/* Defined for the NFSv3 protocol */ +#define EBADHANDLE 521 /* Illegal NFS file handle */ +#define ENOTSYNC 522 /* Update synchronization mismatch */ +#define EBADCOOKIE 523 /* Cookie is stale */ +#define ENOTSUPP 524 /* Operation is not supported */ +#define ETOOSMALL 525 /* Buffer or request is too small */ +#define ESERVERFAULT 526 /* An untranslatable error occurred */ +#define EBADTYPE 527 /* Type not supported by server */ +#define EJUKEBOX 528 /* Request initiated, but will not complete before timeout */ +#define EIOCBQUEUED 529 /* iocb queued, will get completion event */ +#define ERECALLCONFLICT 530 /* conflict with recalled state */ + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/mipi_display.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/mipi_display.h new file mode 100644 index 0000000..3542d1c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/mipi_display.h @@ -0,0 +1,143 @@ +/* + * Defines for Mobile Industry Processor Interface (MIPI(R)) + * Display Working Group standards: DSI, DCS, DBI, DPI + * + * Copyright (C) 2010 Guennadi Liakhovetski + * Copyright (C) 2006 Nokia Corporation + * Author: Imre Deak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef MIPI_DISPLAY_H +#define MIPI_DISPLAY_H + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COMPRESSION_MODE = 0x07, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a, + MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */ + MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */ + MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */ + MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */ + MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */ + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +/* MIPI DCS pixel formats */ +#define MIPI_DCS_PIXEL_FMT_24BIT 7 +#define MIPI_DCS_PIXEL_FMT_18BIT 6 +#define MIPI_DCS_PIXEL_FMT_16BIT 5 +#define MIPI_DCS_PIXEL_FMT_12BIT 3 +#define MIPI_DCS_PIXEL_FMT_8BIT 2 +#define MIPI_DCS_PIXEL_FMT_3BIT 1 + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/uboot-env.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/uboot-env.h new file mode 100644 index 0000000..47e2c24 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Library/uboot-env.h @@ -0,0 +1,222 @@ +#ifndef _UBOOT_ENV_H +#define _UBOOT_ENV_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define __maybe_unused + +typedef UINT8 u8; +typedef UINT16 u16; +typedef UINT32 u32; +typedef UINT64 u64; +typedef unsigned int uint; +typedef UINTN ulong; +typedef INTN ssize_t; +typedef UINTN size_t; +typedef BOOLEAN bool; +typedef UINT16 __be16; + +#define true TRUE +#define false FALSE + +#define udelay(x) MicroSecondDelay (x) +#define mdelay(x) MicroSecondDelay (x * 1000) + +#define dev_err(dev, args...) DEBUG ((DEBUG_ERROR, args)) +#define dev_info(dev, args...) DEBUG ((DEBUG_INFO, args)) +#define dev_dbg(dev, args...) DEBUG ((DEBUG_INFO, args)) +#define printf(args...) DEBUG ((DEBUG_INFO, args)) +#define debug(args...) DEBUG ((DEBUG_INFO, args)) +#define WARN(x, args...) DEBUG ((DEBUG_WARN, args)) + +#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) + +#define BIT(x) (1 << (x)) + +#define BITS_PER_LONG (sizeof(UINTN) * 8) +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +#define FIELD_PREP(_mask, _val) \ + ({ \ + ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ + }) + +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +#define fls(x) HighBitSet32(x) + +#define min(x,y) ({ \ + typeof(x) _x = (x); \ + typeof(y) _y = (y); \ + (void) (&_x == &_y); \ + _x < _y ? _x : _y; }) + +#define max(x,y) ({ \ + typeof(x) _x = (x); \ + typeof(y) _y = (y); \ + (void) (&_x == &_y); \ + _x > _y ? _x : _y; }) + +#define min_t(type, a, b) min(((type) a), ((type) b)) +#define max_t(type, a, b) max(((type) a), ((type) b)) + +#define do_div(n,base) ({ \ + uint32_t __base = (base); \ + uint32_t __rem; \ + __rem = ((uint64_t)(n)) % __base; \ + (n) = ((uint64_t)(n)) / __base; \ + __rem; \ + }) + +#define DIV_ROUND_CLOSEST(x, divisor) (((x) + ((divisor) / 2)) / (divisor)) + +#define writel(val, addr) MmioWrite32(addr, val) +#define readl(addr) MmioRead32(addr) + +// +// TODO: Actually check for timeout below... +// +#define readx_poll_timeout(op, addr, val, cond, timeout_us) \ +({ \ + for (;;) { \ + (val) = op(addr); \ + if (cond) \ + break; \ + } \ + (cond) ? 0 : -ETIMEDOUT; \ +}) + +#define readl_poll_timeout(addr, val, cond, timeout_us) \ + readx_poll_timeout(readl, addr, val, cond, timeout_us) + +#define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, \ + timeout_ms) \ +({ \ + int __ret; \ + for (;;) { \ + __ret = regmap_read((map), (addr), &(val)); \ + if (__ret) \ + break; \ + if (cond) \ + break; \ + if ((sleep_us)) \ + udelay((sleep_us)); \ + } \ + __ret ?: ((cond) ? 0 : -ETIMEDOUT); \ +}) + +static inline int regmap_write(UINTN map, uint offset, uint val) +{ + MmioWrite32 (map + offset, val); + return 0; +} + +static inline int regmap_read(UINTN map, uint offset, uint *valp) +{ + *valp = MmioRead32 (map + offset); + return 0; +} + +static inline int regmap_update_bits(UINTN map, uint offset, uint mask, uint val) +{ + uint reg; + int ret; + + ret = regmap_read(map, offset, ®); + if (ret) + return ret; + + reg &= ~mask; + + return regmap_write(map, offset, reg | (val & mask)); +} + +struct reset_ctl { + unsigned int offset; + unsigned int bit; +}; + +static inline void reset(const struct reset_ctl *ctl, bool en) +{ + u32 val; + val = (en << ctl->bit) | ((1 << ctl->bit) << 16); + regmap_write(CRU_BASE, ctl->offset, val); +} + +#define reset_assert(ctl) reset(ctl, true) +#define reset_deassert(ctl) reset(ctl, false) + +static inline u32 __get_unaligned_le32(const u8 *p) +{ + return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24; +} + +static inline u32 get_unaligned_le32(const void *p) +{ + return __get_unaligned_le32((const u8 *)p); +} + +static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) +{ + *remainder = dividend % divisor; + return dividend / divisor; +} + +static inline u64 div_u64(u64 dividend, u32 divisor) +{ + u32 remainder; + return div_u64_rem(dividend, divisor, &remainder); +} + +#define div64_ul(x, y) div_u64((x), (y)) + +#define abs(x) ({ \ + long ret; \ + if (sizeof(x) == sizeof(long)) { \ + long __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } else { \ + int __x = (x); \ + ret = (__x < 0) ? -__x : __x; \ + } \ + ret; \ + }) + +#define uswap_16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) + +#define cpu_to_be16(x) uswap_16(x) +#define be16_to_cpu(x) uswap_16(x) + +#define memcpy(dest, source, count) CopyMem(dest,source, (UINTN)(count)) +#define memset(dest, ch, count) SetMem(dest, (UINTN)(count),(UINT8)(ch)) +#define memchr(buf, ch, count) ScanMem8(buf, (UINTN)(count),(UINT8)ch) +#define memcmp(buf1, buf2, count) (int)(CompareMem(buf1, buf2, (UINTN)(count))) +#define memmove(dest, source, count) CopyMem(dest, source, (UINTN)(count)) +#define strlen(str) (size_t)(AsciiStrLen(str)) +#define strnlen(str, count) (size_t)(AsciiStrnLenS(str, count)) +#define strncpy(strDest, strSource, count) AsciiStrnCpyS(strDest, MAX_STRING_SIZE, strSource, (UINTN)count) +#define strcat(strDest, strSource) AsciiStrCatS(strDest, MAX_STRING_SIZE, strSource) +#define strcmp(string1, string2, count) (int)(AsciiStrCmp(string1, string2)) +#define strncmp(string1, string2, count) (int)(AsciiStrnCmp(string1, string2, (UINTN)(count))) + +#define malloc(sz) AllocatePool(sz) +#define calloc(num, sz) AllocateZeroPool((num) * (sz)); +#define free(buf) FreePool(buf) + +#endif // _UBOOT_ENV_H diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/DpPhy.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/DpPhy.h new file mode 100644 index 0000000..62bac0c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/DpPhy.h @@ -0,0 +1,64 @@ +/** @file +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef _DP_PHY_PROTOCOL_H_ +#define _DP_PHY_PROTOCOL_H_ + +#define DP_PHY_PROTOCOL_GUID \ + { 0xb4bcf881, 0xc8b3, 0x46d7, { 0xaf, 0xbe, 0x5a, 0x2d, 0x94, 0x9d, 0x93, 0xc3 } } + +typedef struct _DP_PHY_PROTOCOL DP_PHY_PROTOCOL; + +#define DP_PHY_MAX_LANES 4 + +typedef struct { + UINT32 LinkRate; + UINT32 LaneCount; + UINT32 LaneVoltageSwingLevels[DP_PHY_MAX_LANES]; + UINT32 LanePreEmphasisLevels[DP_PHY_MAX_LANES]; + BOOLEAN EnableSpreadSpectrum; + BOOLEAN SetLinkRateAndSpreadSpectrum; + BOOLEAN SetLaneCount; + BOOLEAN SetVoltageSwingAndPreEmphasisLevels; +} DP_PHY_CONFIGURATION; + +typedef struct { + UINT32 BusWidth; + UINT32 MaximumLinkRate; +} DP_PHY_CAPABILITIES; + +typedef +EFI_STATUS +(EFIAPI *DP_PHY_POWER_ON) ( + IN DP_PHY_PROTOCOL *This + ); + +typedef +EFI_STATUS +(EFIAPI *DP_PHY_POWER_OFF) ( + IN DP_PHY_PROTOCOL *This + ); + +typedef +EFI_STATUS +(EFIAPI *DP_PHY_CONFIGURE) ( + IN DP_PHY_PROTOCOL *This, + IN DP_PHY_CONFIGURATION *Config + ); + +struct _DP_PHY_PROTOCOL { + DP_PHY_POWER_ON PowerOn; + DP_PHY_POWER_OFF PowerOff; + DP_PHY_CONFIGURE Configure; + DP_PHY_CAPABILITIES Capabilities; + UINT32 Id; +}; + +extern EFI_GUID gDpPhyProtocolGuid; + +#endif // _DP_PHY_PROTOCOL_H_ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/I2c.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/I2c.h new file mode 100644 index 0000000..ebaad29 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/I2c.h @@ -0,0 +1,32 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Inc. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef _RK_I2C_H__ +#define _RK_I2C_H__ + +/* + * I2C_FLAG_NORESTART is not part of PI spec, it allows to continue + * transmission without repeated start operation. + */ +#define I2C_FLAG_NORESTART 0x00000002 + +/* + * Helper macros for maintaining multiple I2C buses + * and devices defined via EFI_I2C_DEVICE. + */ +#define I2C_DEVICE_ADDRESS(Index) ((Index) & MAX_UINT16) +#define I2C_DEVICE_BUS(Index) ((Index) >> 16) +#define I2C_DEVICE_INDEX(Bus, Address) (((Address) & MAX_UINT16) | (Bus) << 16) + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/I2cDemo.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/I2cDemo.h new file mode 100644 index 0000000..7515d49 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/I2cDemo.h @@ -0,0 +1,32 @@ +/******************************************************************************** +Copyright (C) 2016 Marvell International Ltd. + +SPDX-License-Identifier: BSD-2-Clause-Patent + +*******************************************************************************/ + +#ifndef __ROCKCHIP_I2CDEMO_H__ +#define __ROCKCHIP_I2CDEMO_H__ + +#define ROCKCHIP_I2CDEMO_PROTOCOL_GUID { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b }} + +typedef struct _ROCKCHIP_I2CDEMO_PROTOCOL ROCKCHIP_I2CDEMO_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *EFI_I2CDEMO_TRANSFER) ( + IN CONST ROCKCHIP_I2CDEMO_PROTOCOL *This, + IN UINT8 *RegAddress, + IN UINT16 RegAddressLength, + IN UINT8 *Buffer, + IN UINT16 Length +); + +struct _ROCKCHIP_I2CDEMO_PROTOCOL { + EFI_I2CDEMO_TRANSFER Read; + EFI_I2CDEMO_TRANSFER Write; + UINT32 Identifier; +}; + +extern EFI_GUID gRockchipI2cDemoProtocolGuid; +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/NorFlashProtocol.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/NorFlashProtocol.h new file mode 100644 index 0000000..7344e1b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/NorFlashProtocol.h @@ -0,0 +1,69 @@ +/** @file +* +* Copyright (c) 2022, Rockchip Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + + +#ifndef _UNI_NOR_FLASH_PROTOCOL_H_ +#define _UNI_NOR_FLASH_PROTOCOL_H_ + +#define UNI_NOR_FLASH_PROTOCOL_GUID \ + {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}} + +typedef struct _UNI_NOR_FLASH_PROTOCOL UNI_NOR_FLASH_PROTOCOL; + +typedef +UINT32 +(EFIAPI *UNI_FLASH_GET_SIZE_INTERFACE) ( + IN UNI_NOR_FLASH_PROTOCOL *This + ); + +typedef +EFI_STATUS +(EFIAPI *UNI_FLASH_ERASE_INTERFACE) ( + IN UNI_NOR_FLASH_PROTOCOL *This, + IN UINT32 Offset, + IN UINT32 Length + ); + +typedef +EFI_STATUS +(EFIAPI *UNI_FLASH_WRITE_INTERFACE) ( + IN UNI_NOR_FLASH_PROTOCOL *This, + IN UINT32 Offset, + IN UINT8 *Buffer, + UINT32 ulLength + ); + +typedef +EFI_STATUS +(EFIAPI *UNI_FLASH_READ_INTERFACE) ( + IN UNI_NOR_FLASH_PROTOCOL *This, + IN UINT32 Offset, + IN OUT UINT8 *Buffer, + IN UINT32 ulLen + ); + +typedef +EFI_STATUS +(EFIAPI *UNI_FLASH_UPDATE_INTERFACE) ( + IN UNI_NOR_FLASH_PROTOCOL *This, + IN UINT32 Offset, + IN UINT8 *Buffer, + UINT32 ulLength + ); + +struct _UNI_NOR_FLASH_PROTOCOL { + UNI_FLASH_GET_SIZE_INTERFACE GetSize; + UNI_FLASH_ERASE_INTERFACE Erase; + UNI_FLASH_WRITE_INTERFACE Write; + UNI_FLASH_READ_INTERFACE Read; + UNI_FLASH_UPDATE_INTERFACE Update; +}; + +extern EFI_GUID gUniNorFlashProtocolGuid; + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/OhciDeviceProtocol.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/OhciDeviceProtocol.h new file mode 100644 index 0000000..ba62bc7 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/OhciDeviceProtocol.h @@ -0,0 +1,23 @@ +/** @file + + Copyright (c) 2023, Mario Bălănică + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _OHCI_DEVICE_PROTOCOL_H_ +#define _OHCI_DEVICE_PROTOCOL_H_ + +#include + +#define OHCI_DEVICE_PROTOCOL_GUID \ + {0x54bce5e6, 0xbaae, 0x488a, {0x82, 0x67, 0xc0, 0x85, 0x7f, 0xb4, 0xe8, 0x05}} + +typedef struct { + UINT32 BaseAddress; +} OHCI_DEVICE_PROTOCOL; + +extern EFI_GUID gOhciDeviceProtocolGuid; + +#endif // _OHCI_DEVICE_PROTOCOL_H_ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/Pca9555.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/Pca9555.h new file mode 100644 index 0000000..141218c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/Pca9555.h @@ -0,0 +1,28 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * Copyright (c) 2023, Shimrra Shai + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __PCA9555_H__ +#define __PCA9555_H__ + +#include + +#include + +#define PCA95XX_PROTOCOL_GUID \ + { 0x7e91391b, 0xa23c, 0x4a51, { 0x9d, 0xf7, 0xf6, 0x74, 0xef, 0x1d, 0x51, 0x1b } } + +typedef struct _PCA95XX_PROTOCOL PCA95XX_PROTOCOL; + +struct _PCA95XX_PROTOCOL { + EMBEDDED_GPIO GpioProtocol; +}; + +extern EFI_GUID gPca95xxProtocolGuid; + +#endif // __PCA9555_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/Rk860xRegulator.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/Rk860xRegulator.h new file mode 100644 index 0000000..5894410 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/Rk860xRegulator.h @@ -0,0 +1,74 @@ +/** @file +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __RK860X_REGULATOR_H__ +#define __RK860X_REGULATOR_H__ + +#define RK860X_REGULATOR_PROTOCOL_GUID { 0xb9ef9018, 0x2096, 0x4bf5, { 0x94, 0xb2, 0x70, 0x32, 0xb9, 0xa9, 0xa4, 0x29 }} + +typedef struct _RK860X_REGULATOR_PROTOCOL RK860X_REGULATOR_PROTOCOL; + +typedef struct { + UINT32 Min; + UINT32 Max; +} VOLTAGE_RANGE; + +typedef +EFI_STATUS +(EFIAPI *EFI_RK860X_REGULATOR_GET_VOLTAGE) ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + OUT UINT32 *Voltage, + IN BOOLEAN Suspend +); + +typedef +EFI_STATUS +(EFIAPI *EFI_RK860X_REGULATOR_SET_VOLTAGE) ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN UINT32 Voltage, + IN BOOLEAN Suspend +); + +typedef +EFI_STATUS +(EFIAPI *EFI_RK860X_REGULATOR_GET_ENABLE) ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + OUT BOOLEAN *Enable, + IN BOOLEAN Suspend +); + +typedef +EFI_STATUS +(EFIAPI *EFI_RK860X_REGULATOR_SET_ENABLE) ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + IN BOOLEAN Enable, + IN BOOLEAN Suspend +); + +typedef +EFI_STATUS +(EFIAPI *EFI_RK860X_REGULATOR_GET_VOLTAGE_LIMIT) ( + IN CONST RK860X_REGULATOR_PROTOCOL *This, + OUT UINT32 *Voltage, + IN BOOLEAN PlatformPreferredLimit +); + +struct _RK860X_REGULATOR_PROTOCOL { + EFI_RK860X_REGULATOR_GET_VOLTAGE GetVoltage; + EFI_RK860X_REGULATOR_SET_VOLTAGE SetVoltage; + EFI_RK860X_REGULATOR_GET_ENABLE GetEnable; + EFI_RK860X_REGULATOR_SET_ENABLE SetEnable; + VOLTAGE_RANGE SupportedVoltageRange; + VOLTAGE_RANGE PreferredVoltageRange; + UINT8 Tag; + UINT32 Identifier; +}; + +extern EFI_GUID gRk860xRegulatorProtocolGuid; + +#endif // __RK860X_REGULATOR_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipConnectorProtocol.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipConnectorProtocol.h new file mode 100644 index 0000000..6c5bd5f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipConnectorProtocol.h @@ -0,0 +1,107 @@ +/** @file + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _ROCKCHIP_CONNECTOR_PROTOCOL_H_ +#define _ROCKCHIP_CONNECTOR_PROTOCOL_H_ + +#include + +#define RK_CONNECTOR_PROTOCOL_GUID \ + {0x50439CB6, 0x9B85, 0x11EC, {0x95, 0x73, 0xF4, 0x2A, 0x7D, 0xCB, 0x92, 0x5D}} + +typedef struct _ROCKCHIP_CONNECTOR_PROTOCOL ROCKCHIP_CONNECTOR_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_PREINIT) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_INIT) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_DEINIT) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_DETECT) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_GET_TIMING) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_GET_EDID) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_PREPARE) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_ENABLE) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_DISABLE) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CONNECTOR_UNPREPARE) ( + IN ROCKCHIP_CONNECTOR_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +struct _ROCKCHIP_CONNECTOR_PROTOCOL { + VOID *Private; + ROCKCHIP_CONNECTOR_PREINIT Preinit; + ROCKCHIP_CONNECTOR_INIT Init; + ROCKCHIP_CONNECTOR_DEINIT Deinit; + ROCKCHIP_CONNECTOR_DETECT Detect; + ROCKCHIP_CONNECTOR_GET_TIMING GetTiming; + ROCKCHIP_CONNECTOR_GET_EDID GetEdid; + ROCKCHIP_CONNECTOR_PREPARE Prepare; + ROCKCHIP_CONNECTOR_ENABLE Enable; + ROCKCHIP_CONNECTOR_DISABLE Disable; + ROCKCHIP_CONNECTOR_UNPREPARE Unprepare; +}; + +extern EFI_GUID gRockchipConnectorProtocolGuid; + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipCrtcProtocol.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipCrtcProtocol.h new file mode 100644 index 0000000..0ad4f34 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipCrtcProtocol.h @@ -0,0 +1,105 @@ +/** @file + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _ROCKCHIP_CRTC_PROTOCOL_H_ +#define _ROCKCHIP_CRTC_PROTOCOL_H_ + +#include + +#define ROCKCHIP_CRTC_PROTOCOL_GUID \ + {0xC128406A, 0x99D9, 0x11EC, {0x99, 0x27, 0xF4, 0x2A, 0x7D, 0xCB, 0x92, 0x5D}} + +typedef struct _ROCKCHIP_CRTC_PROTOCOL ROCKCHIP_CRTC_PROTOCOL; + +typedef struct { + BOOLEAN Enable; + UINT8 BgOvlDly; + UINT32 PlaneMask; + UINT32 PrimaryPlane; + INT32 OutputType; + INT32 CursorPlane; +} VPS_CONFIG; + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CRTC_PREINIT) ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CRTC_INIT) ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CRTC_DEINIT) ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CRTC_SET_PLANE) ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CRTC_PREPARE) ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CRTC_ENABLE) ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CRTC_DISABLE) ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_CRTC_UNPREPARE) ( + IN ROCKCHIP_CRTC_PROTOCOL *This, + IN OUT DISPLAY_STATE *DisplayState + ); + +struct _ROCKCHIP_CRTC_PROTOCOL { + VOID *Private; + ROCKCHIP_CRTC_PREINIT Preinit; + ROCKCHIP_CRTC_INIT Init; + ROCKCHIP_CRTC_DEINIT Deinit; + ROCKCHIP_CRTC_SET_PLANE SetPlane; + ROCKCHIP_CRTC_PREPARE Prepare; + ROCKCHIP_CRTC_ENABLE Enable; + ROCKCHIP_CRTC_DISABLE Disable; + ROCKCHIP_CRTC_UNPREPARE Unprepare; + DRM_DISPLAY_MODE ActiveMode; + VPS_CONFIG Vps[4]; + BOOLEAN HdmiHpd; + BOOLEAN Active; + BOOLEAN AssignPlane; +}; + +extern EFI_GUID gRockchipCrtcProtocolGuid; + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipDsiPanel.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipDsiPanel.h new file mode 100644 index 0000000..fe705d2 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipDsiPanel.h @@ -0,0 +1,50 @@ +/** @file +* +* Copyright (c) 2024, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef _ROCKCHIP_DSI_PANEL_PROTOCOL_H_ +#define _ROCKCHIP_DSI_PANEL_PROTOCOL_H_ + +#include +#include + +#define ROCKCHIP_DSI_PANEL_PROTOCOL_GUID \ + { 0xb4bcf881, 0xc8b3, 0x46d7, { 0xaf, 0xbe, 0x5a, 0x2d, 0x94, 0x9d, 0x93, 0xc3 } } + +typedef struct _ROCKCHIP_DSI_PANEL_PROTOCOL ROCKCHIP_DSI_PANEL_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *ROCKCHIP_DSI_PANEL_PREPARE)( + IN ROCKCHIP_DSI_PANEL_PROTOCOL *This + ); + +struct _ROCKCHIP_DSI_PANEL_PROTOCOL { + UINT32 DsiId; + UINT32 DsiLaneRate; + UINT32 DsiLanes; + UINT32 DsiFlags; + UINT32 DsiFormat; + BOOLEAN DscEnable; + BOOLEAN CPhyEnable; + BOOLEAN ScramblingEnable; + UINT32 SliceWidth; + UINT32 SliceHeight; + UINT32 VersionMajor; + UINT32 VersionMinor; + + UINT8 *InitSequence; + UINT32 InitSequenceLength; + + DISPLAY_MODE NativeMode; + + ROCKCHIP_DSI_PANEL_PREPARE Prepare; +}; + +extern EFI_GUID gRockchipDsiPanelProtocolGuid; + +#endif // _ROCKCHIP_DSI_PANEL_PROTOCOL_H_ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipI2cMasterProtocol.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipI2cMasterProtocol.h new file mode 100644 index 0000000..d530242 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Include/Protocol/RockchipI2cMasterProtocol.h @@ -0,0 +1,23 @@ +/** @file + + Copyright (c) 2023, Mario Bălănică + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _ROCKCHIP_I2C_MASTER_PROTOCOL_H_ +#define _ROCKCHIP_I2C_MASTER_PROTOCOL_H_ + +#include + +#define ROCKCHIP_I2C_MASTER_PROTOCOL_GUID \ + { 0x7b4af789, 0x43d2, 0x44a5, { 0xa0, 0xb3, 0x3f, 0xa5, 0xde, 0xd7, 0xa1, 0x27 } } + +typedef struct { + UINT8 Bus; +} ROCKCHIP_I2C_MASTER_PROTOCOL; + +extern EFI_GUID gRockchipI2cMasterProtocolGuid; + +#endif // _ROCKCHIP_I2C_MASTER_PROTOCOL_H_ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/BaseVariableLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/BaseVariableLib.c new file mode 100644 index 0000000..56ab462 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/BaseVariableLib.c @@ -0,0 +1,1460 @@ +/** @file + * + * Read-only non-volatile variable service library for early SEC phase. + * Based on FaultTolerantWritePei and VariablePei, without using any HOBs. + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
    + * Copyright (c) Microsoft Corporation.
    + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "Variable.h" + +STATIC FAULT_TOLERANT_WRITE_LAST_WRITE_DATA mFtwLastWriteData; +STATIC BOOLEAN mFtwLastWriteDataInitialized; + +// Also fits VARIABLE_HEADER +STATIC AUTHENTICATED_VARIABLE_HEADER mVariableHeaderFtw; +STATIC BOOLEAN mVariableHeaderFtwMerged; + +STATIC VARIABLE_INDEX_TABLE mVariableIndexTable; + +/** + Get the last Write Header pointer. + The last write header is the header whose 'complete' state hasn't been set. + After all, this header may be a EMPTY header entry for next Allocate. + + + @param FtwWorkSpaceHeader Pointer of the working block header + @param FtwWorkSpaceSize Size of the work space + @param FtwWriteHeader Pointer to retrieve the last write header + + @retval EFI_SUCCESS Get the last write record successfully + @retval EFI_ABORTED The FTW work space is damaged + +**/ +EFI_STATUS +FtwGetLastWriteHeader ( + IN EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER *FtwWorkSpaceHeader, + IN UINTN FtwWorkSpaceSize, + OUT EFI_FAULT_TOLERANT_WRITE_HEADER **FtwWriteHeader + ) +{ + UINTN Offset; + EFI_FAULT_TOLERANT_WRITE_HEADER *FtwHeader; + + *FtwWriteHeader = NULL; + FtwHeader = (EFI_FAULT_TOLERANT_WRITE_HEADER *)(FtwWorkSpaceHeader + 1); + Offset = sizeof (EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER); + + while (FtwHeader->Complete == FTW_VALID_STATE) { + Offset += FTW_WRITE_TOTAL_SIZE (FtwHeader->NumberOfWrites, FtwHeader->PrivateDataSize); + // + // If Offset exceed the FTW work space boudary, return error. + // + if (Offset >= FtwWorkSpaceSize) { + *FtwWriteHeader = FtwHeader; + return EFI_ABORTED; + } + + FtwHeader = (EFI_FAULT_TOLERANT_WRITE_HEADER *)((UINT8 *)FtwWorkSpaceHeader + Offset); + } + + // + // Last write header is found + // + *FtwWriteHeader = FtwHeader; + + return EFI_SUCCESS; +} + +/** + Get the last Write Record pointer. The last write Record is the Record + whose DestinationCompleted state hasn't been set. After all, this Record + may be a EMPTY record entry for next write. + + + @param FtwWriteHeader Pointer to the write record header + @param FtwWriteRecord Pointer to retrieve the last write record + + @retval EFI_SUCCESS Get the last write record successfully + @retval EFI_ABORTED The FTW work space is damaged + +**/ +EFI_STATUS +FtwGetLastWriteRecord ( + IN EFI_FAULT_TOLERANT_WRITE_HEADER *FtwWriteHeader, + OUT EFI_FAULT_TOLERANT_WRITE_RECORD **FtwWriteRecord + ) +{ + UINTN Index; + EFI_FAULT_TOLERANT_WRITE_RECORD *FtwRecord; + + *FtwWriteRecord = NULL; + FtwRecord = (EFI_FAULT_TOLERANT_WRITE_RECORD *)(FtwWriteHeader + 1); + + // + // Try to find the last write record "that has not completed" + // + for (Index = 0; Index < FtwWriteHeader->NumberOfWrites; Index += 1) { + if (FtwRecord->DestinationComplete != FTW_VALID_STATE) { + // + // The last write record is found + // + *FtwWriteRecord = FtwRecord; + return EFI_SUCCESS; + } + + FtwRecord++; + + if (FtwWriteHeader->PrivateDataSize != 0) { + FtwRecord = (EFI_FAULT_TOLERANT_WRITE_RECORD *)((UINTN)FtwRecord + (UINTN)FtwWriteHeader->PrivateDataSize); + } + } + + // + // if Index == NumberOfWrites, then + // the last record has been written successfully, + // but the Header->Complete Flag has not been set. + // also return the last record. + // + if (Index == FtwWriteHeader->NumberOfWrites) { + *FtwWriteRecord = (EFI_FAULT_TOLERANT_WRITE_RECORD *)((UINTN)FtwRecord - FTW_RECORD_SIZE (FtwWriteHeader->PrivateDataSize)); + return EFI_SUCCESS; + } + + return EFI_ABORTED; +} + +/** + Check to see if it is a valid work space. + + + @param WorkingHeader Pointer of working block header + @param WorkingLength Working block length + + @retval TRUE The work space is valid. + @retval FALSE The work space is invalid. + +**/ +BOOLEAN +IsValidWorkSpace ( + IN EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER *WorkingHeader, + IN UINTN WorkingLength + ) +{ + UINT8 Data; + + if (WorkingHeader == NULL) { + return FALSE; + } + + if ((WorkingHeader->WorkingBlockValid != FTW_VALID_STATE) || (WorkingHeader->WorkingBlockInvalid == FTW_VALID_STATE)) { + DEBUG ((DEBUG_ERROR, "FtwPei: Work block header valid bit check error\n")); + return FALSE; + } + + if (WorkingHeader->WriteQueueSize != (WorkingLength - sizeof (EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER))) { + DEBUG ((DEBUG_ERROR, "FtwPei: Work block header WriteQueueSize check error\n")); + return FALSE; + } + + // + // Check signature with gEdkiiWorkingBlockSignatureGuid + // + if (!CompareGuid (&gEdkiiWorkingBlockSignatureGuid, &WorkingHeader->Signature)) { + DEBUG ((DEBUG_ERROR, "FtwPei: Work block header signature check error, it should be gEdkiiWorkingBlockSignatureGuid\n")); + // + // To be compatible with old signature gEfiSystemNvDataFvGuid. + // + if (!CompareGuid (&gEfiSystemNvDataFvGuid, &WorkingHeader->Signature)) { + return FALSE; + } else { + Data = *(UINT8 *)(WorkingHeader + 1); + if (Data != 0xff) { + DEBUG ((DEBUG_ERROR, "FtwPei: Old format FTW structure can't be handled\n")); + ASSERT (FALSE); + return FALSE; + } + } + } + + return TRUE; +} + +/** + Main entry for Fault Tolerant Write PEIM. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Pointer to PEI Services table. + + @retval EFI_SUCCESS If the interface could be successfully installed + @retval Others Returned from PeiServicesInstallPpi() + +**/ +EFI_STATUS +EFIAPI +FaultTolerantWriteInitialize ( + VOID + ) +{ + EFI_STATUS Status; + EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER *FtwWorkingBlockHeader; + EFI_FAULT_TOLERANT_WRITE_HEADER *FtwLastWriteHeader; + EFI_FAULT_TOLERANT_WRITE_RECORD *FtwLastWriteRecord; + EFI_PHYSICAL_ADDRESS WorkSpaceAddress; + UINTN WorkSpaceLength; + EFI_PHYSICAL_ADDRESS SpareAreaAddress; + UINTN SpareAreaLength; + EFI_PHYSICAL_ADDRESS WorkSpaceInSpareArea; + + if (mFtwLastWriteDataInitialized) { + return EFI_SUCCESS; + } + + FtwWorkingBlockHeader = NULL; + FtwLastWriteHeader = NULL; + FtwLastWriteRecord = NULL; + + WorkSpaceAddress = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdFlashNvStorageFtwWorkingBase64); + if (WorkSpaceAddress == 0) { + WorkSpaceAddress = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashNvStorageFtwWorkingBase); + } + + WorkSpaceLength = (UINTN)PcdGet32 (PcdFlashNvStorageFtwWorkingSize); + + SpareAreaAddress = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdFlashNvStorageFtwSpareBase64); + if (SpareAreaAddress == 0) { + SpareAreaAddress = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashNvStorageFtwSpareBase); + } + + SpareAreaLength = (UINTN)PcdGet32 (PcdFlashNvStorageFtwSpareSize); + + // + // The address of FTW working base and spare base must not be 0. + // + ASSERT ((WorkSpaceAddress != 0) && (SpareAreaAddress != 0)); + + FtwWorkingBlockHeader = (EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER *)(UINTN)WorkSpaceAddress; + if (IsValidWorkSpace (FtwWorkingBlockHeader, WorkSpaceLength)) { + Status = FtwGetLastWriteHeader ( + FtwWorkingBlockHeader, + WorkSpaceLength, + &FtwLastWriteHeader + ); + if (!EFI_ERROR (Status)) { + Status = FtwGetLastWriteRecord ( + FtwLastWriteHeader, + &FtwLastWriteRecord + ); + } + + if (!EFI_ERROR (Status)) { + ASSERT (FtwLastWriteRecord != NULL); + if ((FtwLastWriteRecord->SpareComplete == FTW_VALID_STATE) && (FtwLastWriteRecord->DestinationComplete != FTW_VALID_STATE)) { + // + // If FTW last write was still in progress with SpareComplete set and DestinationComplete not set. + // It means the target buffer has been backed up in spare block, then target block has been erased, + // but the target buffer has not been writen in target block from spare block, we need to build + // FAULT_TOLERANT_WRITE_LAST_WRITE_DATA GUID hob to hold the FTW last write data. + // + mFtwLastWriteData.TargetAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)((INT64)SpareAreaAddress + FtwLastWriteRecord->RelativeOffset); + mFtwLastWriteData.SpareAddress = SpareAreaAddress; + mFtwLastWriteData.Length = SpareAreaLength; + DEBUG (( + DEBUG_INFO, + "FtwPei last write data: TargetAddress - 0x%x SpareAddress - 0x%x Length - 0x%x\n", + (UINTN)mFtwLastWriteData.TargetAddress, + (UINTN)mFtwLastWriteData.SpareAddress, + (UINTN)mFtwLastWriteData.Length + )); + } + } + } else { + FtwWorkingBlockHeader = NULL; + // + // If the working block workspace is not valid, try to find workspace in the spare block. + // + WorkSpaceInSpareArea = SpareAreaAddress + SpareAreaLength - WorkSpaceLength; + while (WorkSpaceInSpareArea >= SpareAreaAddress) { + if (CompareGuid (&gEdkiiWorkingBlockSignatureGuid, (EFI_GUID *)(UINTN)WorkSpaceInSpareArea)) { + // + // Found the workspace. + // + DEBUG ((DEBUG_INFO, "FtwPei: workspace in spare block is at 0x%x.\n", (UINTN)WorkSpaceInSpareArea)); + FtwWorkingBlockHeader = (EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER *)(UINTN)WorkSpaceInSpareArea; + break; + } + + WorkSpaceInSpareArea = WorkSpaceInSpareArea - sizeof (EFI_GUID); + } + + if ((FtwWorkingBlockHeader != NULL) && IsValidWorkSpace (FtwWorkingBlockHeader, WorkSpaceLength)) { + // + // It was workspace self reclaim, build FAULT_TOLERANT_WRITE_LAST_WRITE_DATA GUID hob for it. + // + mFtwLastWriteData.TargetAddress = WorkSpaceAddress - (WorkSpaceInSpareArea - SpareAreaAddress); + mFtwLastWriteData.SpareAddress = SpareAreaAddress; + mFtwLastWriteData.Length = SpareAreaLength; + DEBUG (( + DEBUG_INFO, + "FtwPei last write data: TargetAddress - 0x%x SpareAddress - 0x%x Length - 0x%x\n", + (UINTN)mFtwLastWriteData.TargetAddress, + (UINTN)mFtwLastWriteData.SpareAddress, + (UINTN)mFtwLastWriteData.Length + )); + } else { + // + // Both are invalid. + // + DEBUG ((DEBUG_ERROR, "FtwPei: Both working and spare block are invalid.\n")); + } + } + + mFtwLastWriteDataInitialized = TRUE; + + return EFI_SUCCESS; +} + +/** + + Gets the pointer to the first variable header in given variable store area. + + @param VarStoreHeader Pointer to the Variable Store Header. + + @return Pointer to the first variable header. + +**/ +VARIABLE_HEADER * +GetStartPointer ( + IN VARIABLE_STORE_HEADER *VarStoreHeader + ) +{ + // + // The start of variable store + // + return (VARIABLE_HEADER *)HEADER_ALIGN (VarStoreHeader + 1); +} + +/** + + Gets the pointer to the end of the variable storage area. + + This function gets pointer to the end of the variable storage + area, according to the input variable store header. + + @param VarStoreHeader Pointer to the Variable Store Header. + + @return Pointer to the end of the variable storage area. + +**/ +VARIABLE_HEADER * +GetEndPointer ( + IN VARIABLE_STORE_HEADER *VarStoreHeader + ) +{ + // + // The end of variable store + // + return (VARIABLE_HEADER *)HEADER_ALIGN ((UINTN)VarStoreHeader + VarStoreHeader->Size); +} + +/** + This code checks if variable header is valid or not. + + @param Variable Pointer to the Variable Header. + + @retval TRUE Variable header is valid. + @retval FALSE Variable header is not valid. + +**/ +BOOLEAN +IsValidVariableHeader ( + IN VARIABLE_HEADER *Variable + ) +{ + if ((Variable == NULL) || (Variable->StartId != VARIABLE_DATA)) { + return FALSE; + } + + return TRUE; +} + +/** + This code gets the size of variable header. + + @param AuthFlag Authenticated variable flag. + + @return Size of variable header in bytes in type UINTN. + +**/ +UINTN +GetVariableHeaderSize ( + IN BOOLEAN AuthFlag + ) +{ + UINTN Value; + + if (AuthFlag) { + Value = sizeof (AUTHENTICATED_VARIABLE_HEADER); + } else { + Value = sizeof (VARIABLE_HEADER); + } + + return Value; +} + +/** + This code gets the size of name of variable. + + @param Variable Pointer to the Variable Header. + @param AuthFlag Authenticated variable flag. + + @return Size of variable in bytes in type UINTN. + +**/ +UINTN +NameSizeOfVariable ( + IN VARIABLE_HEADER *Variable, + IN BOOLEAN AuthFlag + ) +{ + AUTHENTICATED_VARIABLE_HEADER *AuthVariable; + + AuthVariable = (AUTHENTICATED_VARIABLE_HEADER *)Variable; + if (AuthFlag) { + if ((AuthVariable->State == (UINT8)(-1)) || + (AuthVariable->DataSize == (UINT32)(-1)) || + (AuthVariable->NameSize == (UINT32)(-1)) || + (AuthVariable->Attributes == (UINT32)(-1))) + { + return 0; + } + + return (UINTN)AuthVariable->NameSize; + } else { + if ((Variable->State == (UINT8)(-1)) || + (Variable->DataSize == (UINT32)(-1)) || + (Variable->NameSize == (UINT32)(-1)) || + (Variable->Attributes == (UINT32)(-1))) + { + return 0; + } + + return (UINTN)Variable->NameSize; + } +} + +/** + This code gets the size of data of variable. + + @param Variable Pointer to the Variable Header. + @param AuthFlag Authenticated variable flag. + + @return Size of variable in bytes in type UINTN. + +**/ +UINTN +DataSizeOfVariable ( + IN VARIABLE_HEADER *Variable, + IN BOOLEAN AuthFlag + ) +{ + AUTHENTICATED_VARIABLE_HEADER *AuthVariable; + + AuthVariable = (AUTHENTICATED_VARIABLE_HEADER *)Variable; + if (AuthFlag) { + if ((AuthVariable->State == (UINT8)(-1)) || + (AuthVariable->DataSize == (UINT32)(-1)) || + (AuthVariable->NameSize == (UINT32)(-1)) || + (AuthVariable->Attributes == (UINT32)(-1))) + { + return 0; + } + + return (UINTN)AuthVariable->DataSize; + } else { + if ((Variable->State == (UINT8)(-1)) || + (Variable->DataSize == (UINT32)(-1)) || + (Variable->NameSize == (UINT32)(-1)) || + (Variable->Attributes == (UINT32)(-1))) + { + return 0; + } + + return (UINTN)Variable->DataSize; + } +} + +/** + This code gets the pointer to the variable name. + + @param Variable Pointer to the Variable Header. + @param AuthFlag Authenticated variable flag. + + @return A CHAR16* pointer to Variable Name. + +**/ +CHAR16 * +GetVariableNamePtr ( + IN VARIABLE_HEADER *Variable, + IN BOOLEAN AuthFlag + ) +{ + return (CHAR16 *)((UINTN)Variable + GetVariableHeaderSize (AuthFlag)); +} + +/** + This code gets the pointer to the variable guid. + + @param Variable Pointer to the Variable Header. + @param AuthFlag Authenticated variable flag. + + @return A EFI_GUID* pointer to Vendor Guid. + +**/ +EFI_GUID * +GetVendorGuidPtr ( + IN VARIABLE_HEADER *Variable, + IN BOOLEAN AuthFlag + ) +{ + AUTHENTICATED_VARIABLE_HEADER *AuthVariable; + + AuthVariable = (AUTHENTICATED_VARIABLE_HEADER *)Variable; + if (AuthFlag) { + return &AuthVariable->VendorGuid; + } else { + return &Variable->VendorGuid; + } +} + +/** + This code gets the pointer to the variable data. + + @param Variable Pointer to the Variable Header. + @param VariableHeader Pointer to the Variable Header that has consecutive content. + @param AuthFlag Authenticated variable flag. + + @return A UINT8* pointer to Variable Data. + +**/ +UINT8 * +GetVariableDataPtr ( + IN VARIABLE_HEADER *Variable, + IN VARIABLE_HEADER *VariableHeader, + IN BOOLEAN AuthFlag + ) +{ + UINTN Value; + + // + // Be careful about pad size for alignment + // + Value = (UINTN)GetVariableNamePtr (Variable, AuthFlag); + Value += NameSizeOfVariable (VariableHeader, AuthFlag); + Value += GET_PAD_SIZE (NameSizeOfVariable (VariableHeader, AuthFlag)); + + return (UINT8 *)Value; +} + +/** + This code gets the pointer to the next variable header. + + @param StoreInfo Pointer to variable store info structure. + @param Variable Pointer to the Variable Header. + @param VariableHeader Pointer to the Variable Header that has consecutive content. + + @return A VARIABLE_HEADER* pointer to next variable header. + +**/ +VARIABLE_HEADER * +GetNextVariablePtr ( + IN VARIABLE_STORE_INFO *StoreInfo, + IN VARIABLE_HEADER *Variable, + IN VARIABLE_HEADER *VariableHeader + ) +{ + EFI_PHYSICAL_ADDRESS TargetAddress; + EFI_PHYSICAL_ADDRESS SpareAddress; + UINTN Value; + + Value = (UINTN)GetVariableDataPtr (Variable, VariableHeader, StoreInfo->AuthFlag); + Value += DataSizeOfVariable (VariableHeader, StoreInfo->AuthFlag); + Value += GET_PAD_SIZE (DataSizeOfVariable (VariableHeader, StoreInfo->AuthFlag)); + // + // Be careful about pad size for alignment + // + Value = HEADER_ALIGN (Value); + + if (StoreInfo->FtwLastWriteData != NULL) { + TargetAddress = StoreInfo->FtwLastWriteData->TargetAddress; + SpareAddress = StoreInfo->FtwLastWriteData->SpareAddress; + if (((UINTN)Variable < (UINTN)TargetAddress) && (Value >= (UINTN)TargetAddress)) { + // + // Next variable is in spare block. + // + Value = (UINTN)SpareAddress + (Value - (UINTN)TargetAddress); + } + } + + return (VARIABLE_HEADER *)Value; +} + +/** + Get variable store status. + + @param VarStoreHeader Pointer to the Variable Store Header. + + @retval EfiRaw Variable store is raw + @retval EfiValid Variable store is valid + @retval EfiInvalid Variable store is invalid + +**/ +VARIABLE_STORE_STATUS +GetVariableStoreStatus ( + IN VARIABLE_STORE_HEADER *VarStoreHeader + ) +{ + if ((CompareGuid (&VarStoreHeader->Signature, &gEfiAuthenticatedVariableGuid) || + CompareGuid (&VarStoreHeader->Signature, &gEfiVariableGuid)) && + (VarStoreHeader->Format == VARIABLE_STORE_FORMATTED) && + (VarStoreHeader->State == VARIABLE_STORE_HEALTHY) + ) + { + return EfiValid; + } + + if ((((UINT32 *)(&VarStoreHeader->Signature))[0] == 0xffffffff) && + (((UINT32 *)(&VarStoreHeader->Signature))[1] == 0xffffffff) && + (((UINT32 *)(&VarStoreHeader->Signature))[2] == 0xffffffff) && + (((UINT32 *)(&VarStoreHeader->Signature))[3] == 0xffffffff) && + (VarStoreHeader->Size == 0xffffffff) && + (VarStoreHeader->Format == 0xff) && + (VarStoreHeader->State == 0xff) + ) + { + return EfiRaw; + } else { + return EfiInvalid; + } +} + +/** + Compare two variable names, one of them may be inconsecutive. + + @param StoreInfo Pointer to variable store info structure. + @param Name1 Pointer to one variable name. + @param Name2 Pointer to another variable name. + @param NameSize Variable name size. + + @retval TRUE Name1 and Name2 are identical. + @retval FALSE Name1 and Name2 are not identical. + +**/ +BOOLEAN +CompareVariableName ( + IN VARIABLE_STORE_INFO *StoreInfo, + IN CONST CHAR16 *Name1, + IN CONST CHAR16 *Name2, + IN UINTN NameSize + ) +{ + EFI_PHYSICAL_ADDRESS TargetAddress; + EFI_PHYSICAL_ADDRESS SpareAddress; + UINTN PartialNameSize; + + if (StoreInfo->FtwLastWriteData != NULL) { + TargetAddress = StoreInfo->FtwLastWriteData->TargetAddress; + SpareAddress = StoreInfo->FtwLastWriteData->SpareAddress; + if (((UINTN)Name1 < (UINTN)TargetAddress) && (((UINTN)Name1 + NameSize) > (UINTN)TargetAddress)) { + // + // Name1 is inconsecutive. + // + PartialNameSize = (UINTN)TargetAddress - (UINTN)Name1; + // + // Partial content is in NV storage. + // + if (CompareMem ((UINT8 *)Name1, (UINT8 *)Name2, PartialNameSize) == 0) { + // + // Another partial content is in spare block. + // + if (CompareMem ((UINT8 *)(UINTN)SpareAddress, (UINT8 *)Name2 + PartialNameSize, NameSize - PartialNameSize) == 0) { + return TRUE; + } + } + + return FALSE; + } else if (((UINTN)Name2 < (UINTN)TargetAddress) && (((UINTN)Name2 + NameSize) > (UINTN)TargetAddress)) { + // + // Name2 is inconsecutive. + // + PartialNameSize = (UINTN)TargetAddress - (UINTN)Name2; + // + // Partial content is in NV storage. + // + if (CompareMem ((UINT8 *)Name2, (UINT8 *)Name1, PartialNameSize) == 0) { + // + // Another partial content is in spare block. + // + if (CompareMem ((UINT8 *)(UINTN)SpareAddress, (UINT8 *)Name1 + PartialNameSize, NameSize - PartialNameSize) == 0) { + return TRUE; + } + } + + return FALSE; + } + } + + // + // Both Name1 and Name2 are consecutive. + // + if (CompareMem ((UINT8 *)Name1, (UINT8 *)Name2, NameSize) == 0) { + return TRUE; + } + + return FALSE; +} + +/** + This function compares a variable with variable entries in database. + + @param StoreInfo Pointer to variable store info structure. + @param Variable Pointer to the variable in our database + @param VariableHeader Pointer to the Variable Header that has consecutive content. + @param VariableName Name of the variable to compare to 'Variable' + @param VendorGuid GUID of the variable to compare to 'Variable' + @param PtrTrack Variable Track Pointer structure that contains Variable Information. + + @retval EFI_SUCCESS Found match variable + @retval EFI_NOT_FOUND Variable not found + +**/ +EFI_STATUS +CompareWithValidVariable ( + IN VARIABLE_STORE_INFO *StoreInfo, + IN VARIABLE_HEADER *Variable, + IN VARIABLE_HEADER *VariableHeader, + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VendorGuid, + OUT VARIABLE_POINTER_TRACK *PtrTrack + ) +{ + VOID *Point; + EFI_GUID *TempVendorGuid; + + TempVendorGuid = GetVendorGuidPtr (VariableHeader, StoreInfo->AuthFlag); + + if (VariableName[0] == 0) { + PtrTrack->CurrPtr = Variable; + return EFI_SUCCESS; + } else { + // + // Don't use CompareGuid function here for performance reasons. + // Instead we compare the GUID a UINT32 at a time and branch + // on the first failed comparison. + // + if ((((INT32 *)VendorGuid)[0] == ((INT32 *)TempVendorGuid)[0]) && + (((INT32 *)VendorGuid)[1] == ((INT32 *)TempVendorGuid)[1]) && + (((INT32 *)VendorGuid)[2] == ((INT32 *)TempVendorGuid)[2]) && + (((INT32 *)VendorGuid)[3] == ((INT32 *)TempVendorGuid)[3]) + ) + { + ASSERT (NameSizeOfVariable (VariableHeader, StoreInfo->AuthFlag) != 0); + Point = (VOID *)GetVariableNamePtr (Variable, StoreInfo->AuthFlag); + if (CompareVariableName (StoreInfo, VariableName, Point, NameSizeOfVariable (VariableHeader, StoreInfo->AuthFlag))) { + PtrTrack->CurrPtr = Variable; + return EFI_SUCCESS; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Return the variable store header and the store info based on the Index. + + @param Type The type of the variable store. + @param StoreInfo Return the store info. + + @return Pointer to the variable store header. +**/ +VARIABLE_STORE_HEADER * +GetVariableStore ( + IN VARIABLE_STORE_TYPE Type, + OUT VARIABLE_STORE_INFO *StoreInfo + ) +{ + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + VARIABLE_STORE_HEADER *VariableStoreHeader; + EFI_PHYSICAL_ADDRESS NvStorageBase; + UINT32 NvStorageSize; + FAULT_TOLERANT_WRITE_LAST_WRITE_DATA *FtwLastWriteData; + UINT32 BackUpOffset; + + StoreInfo->IndexTable = NULL; + StoreInfo->FtwLastWriteData = NULL; + StoreInfo->AuthFlag = FALSE; + VariableStoreHeader = NULL; + switch (Type) { + case VariableStoreTypeHob: + // + // Unsupported + // + break; + + case VariableStoreTypeNv: + if (!PcdGetBool (PcdEmuVariableNvModeEnable)) { + // + // Emulated non-volatile variable mode is not enabled. + // + + NvStorageSize = PcdGet32 (PcdFlashNvStorageVariableSize); + NvStorageBase = (EFI_PHYSICAL_ADDRESS)(PcdGet64 (PcdFlashNvStorageVariableBase64) != 0 ? + PcdGet64 (PcdFlashNvStorageVariableBase64) : + PcdGet32 (PcdFlashNvStorageVariableBase) + ); + ASSERT (NvStorageBase != 0); + + // + // First let FvHeader point to NV storage base. + // + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)NvStorageBase; + + // + // Check the FTW last write data hob. + // + BackUpOffset = 0; + FaultTolerantWriteInitialize (); + if (mFtwLastWriteDataInitialized) { + FtwLastWriteData = &mFtwLastWriteData; + if (FtwLastWriteData->TargetAddress == NvStorageBase) { + // + // Let FvHeader point to spare block. + // + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)FtwLastWriteData->SpareAddress; + DEBUG ((DEBUG_INFO, "PeiVariable: NV storage is backed up in spare block: 0x%x\n", (UINTN)FtwLastWriteData->SpareAddress)); + } else if ((FtwLastWriteData->TargetAddress > NvStorageBase) && (FtwLastWriteData->TargetAddress < (NvStorageBase + NvStorageSize))) { + StoreInfo->FtwLastWriteData = FtwLastWriteData; + // + // Flash NV storage from the offset is backed up in spare block. + // + BackUpOffset = (UINT32)(FtwLastWriteData->TargetAddress - NvStorageBase); + DEBUG ((DEBUG_INFO, "PeiVariable: High partial NV storage from offset: %x is backed up in spare block: 0x%x\n", BackUpOffset, (UINTN)FtwLastWriteData->SpareAddress)); + // + // At least one block data in flash NV storage is still valid, so still leave FvHeader point to NV storage base. + // + } + } + + // + // Check if the Firmware Volume is not corrupted + // + if ((FvHeader->Signature != EFI_FVH_SIGNATURE) || (!CompareGuid (&gEfiSystemNvDataFvGuid, &FvHeader->FileSystemGuid))) { + DEBUG ((DEBUG_ERROR, "Firmware Volume for Variable Store is corrupted\n")); + break; + } + + VariableStoreHeader = (VARIABLE_STORE_HEADER *)((UINT8 *)FvHeader + FvHeader->HeaderLength); + + StoreInfo->AuthFlag = (BOOLEAN)(CompareGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid)); + + StoreInfo->IndexTable = &mVariableIndexTable; + if (StoreInfo->IndexTable->StartPtr == NULL) { + // + // If it's the first time to access variable region in flash, create a guid hob to record + // VAR_ADDED type variable info. + // Note that as the resource of PEI phase is limited, only store the limited number of + // VAR_ADDED type variables to reduce access time. + // + StoreInfo->IndexTable->Length = 0; + StoreInfo->IndexTable->StartPtr = GetStartPointer (VariableStoreHeader); + StoreInfo->IndexTable->EndPtr = GetEndPointer (VariableStoreHeader); + StoreInfo->IndexTable->GoneThrough = 0; + } + } + + break; + + default: + ASSERT (FALSE); + break; + } + + StoreInfo->VariableStoreHeader = VariableStoreHeader; + return VariableStoreHeader; +} + +/** + Get variable header that has consecutive content. + + @param StoreInfo Pointer to variable store info structure. + @param Variable Pointer to the Variable Header. + @param VariableHeader Pointer to Pointer to the Variable Header that has consecutive content. + + @retval TRUE Variable header is valid. + @retval FALSE Variable header is not valid. + +**/ +BOOLEAN +GetVariableHeader ( + IN VARIABLE_STORE_INFO *StoreInfo, + IN VARIABLE_HEADER *Variable, + OUT VARIABLE_HEADER **VariableHeader + ) +{ + EFI_PHYSICAL_ADDRESS TargetAddress; + EFI_PHYSICAL_ADDRESS SpareAddress; + UINTN PartialHeaderSize; + + if (Variable == NULL) { + return FALSE; + } + + // + // First assume variable header pointed by Variable is consecutive. + // + *VariableHeader = Variable; + + if (StoreInfo->FtwLastWriteData != NULL) { + TargetAddress = StoreInfo->FtwLastWriteData->TargetAddress; + SpareAddress = StoreInfo->FtwLastWriteData->SpareAddress; + if (((UINTN)Variable > (UINTN)SpareAddress) && + (((UINTN)Variable - (UINTN)SpareAddress + (UINTN)TargetAddress) >= (UINTN)GetEndPointer (StoreInfo->VariableStoreHeader))) + { + // + // Reach the end of variable store. + // + return FALSE; + } + + if (((UINTN)Variable < (UINTN)TargetAddress) && (((UINTN)Variable + GetVariableHeaderSize (StoreInfo->AuthFlag)) > (UINTN)TargetAddress)) { + // + // Variable header pointed by Variable is inconsecutive, + // create a guid hob to combine the two partial variable header content together. + // + *VariableHeader = (VARIABLE_HEADER *)&mVariableHeaderFtw; + if (mVariableHeaderFtwMerged != TRUE) { + PartialHeaderSize = (UINTN)TargetAddress - (UINTN)Variable; + // + // Partial content is in NV storage. + // + CopyMem ((UINT8 *)*VariableHeader, (UINT8 *)Variable, PartialHeaderSize); + // + // Another partial content is in spare block. + // + CopyMem ((UINT8 *)*VariableHeader + PartialHeaderSize, (UINT8 *)(UINTN)SpareAddress, GetVariableHeaderSize (StoreInfo->AuthFlag) - PartialHeaderSize); + + mVariableHeaderFtwMerged = TRUE; + } + } + } else { + if (Variable >= GetEndPointer (StoreInfo->VariableStoreHeader)) { + // + // Reach the end of variable store. + // + return FALSE; + } + } + + return IsValidVariableHeader (*VariableHeader); +} + +/** + Get variable name or data to output buffer. + + @param StoreInfo Pointer to variable store info structure. + @param NameOrData Pointer to the variable name/data that may be inconsecutive. + @param Size Variable name/data size. + @param Buffer Pointer to output buffer to hold the variable name/data. + +**/ +VOID +GetVariableNameOrData ( + IN VARIABLE_STORE_INFO *StoreInfo, + IN UINT8 *NameOrData, + IN UINTN Size, + OUT UINT8 *Buffer + ) +{ + EFI_PHYSICAL_ADDRESS TargetAddress; + EFI_PHYSICAL_ADDRESS SpareAddress; + UINTN PartialSize; + + if (StoreInfo->FtwLastWriteData != NULL) { + TargetAddress = StoreInfo->FtwLastWriteData->TargetAddress; + SpareAddress = StoreInfo->FtwLastWriteData->SpareAddress; + if (((UINTN)NameOrData < (UINTN)TargetAddress) && (((UINTN)NameOrData + Size) > (UINTN)TargetAddress)) { + // + // Variable name/data is inconsecutive. + // + PartialSize = (UINTN)TargetAddress - (UINTN)NameOrData; + // + // Partial content is in NV storage. + // + CopyMem (Buffer, NameOrData, PartialSize); + // + // Another partial content is in spare block. + // + CopyMem (Buffer + PartialSize, (UINT8 *)(UINTN)SpareAddress, Size - PartialSize); + return; + } + } + + // + // Variable name/data is consecutive. + // + CopyMem (Buffer, NameOrData, Size); +} + +/** + Find the variable in the specified variable store. + + @param StoreInfo Pointer to the store info structure. + @param VariableName Name of the variable to be found + @param VendorGuid Vendor GUID to be found. + @param PtrTrack Variable Track Pointer structure that contains Variable Information. + + @retval EFI_SUCCESS Variable found successfully + @retval EFI_NOT_FOUND Variable not found + @retval EFI_INVALID_PARAMETER Invalid variable name + +**/ +EFI_STATUS +FindVariableEx ( + IN VARIABLE_STORE_INFO *StoreInfo, + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VendorGuid, + OUT VARIABLE_POINTER_TRACK *PtrTrack + ) +{ + VARIABLE_HEADER *Variable; + VARIABLE_HEADER *LastVariable; + VARIABLE_HEADER *MaxIndex; + UINTN Index; + UINTN Offset; + BOOLEAN StopRecord; + VARIABLE_HEADER *InDeletedVariable; + VARIABLE_STORE_HEADER *VariableStoreHeader; + VARIABLE_INDEX_TABLE *IndexTable; + VARIABLE_HEADER *VariableHeader; + + VariableStoreHeader = StoreInfo->VariableStoreHeader; + + if (VariableStoreHeader == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (GetVariableStoreStatus (VariableStoreHeader) != EfiValid) { + return EFI_UNSUPPORTED; + } + + if (~VariableStoreHeader->Size == 0) { + return EFI_NOT_FOUND; + } + + IndexTable = StoreInfo->IndexTable; + PtrTrack->StartPtr = GetStartPointer (VariableStoreHeader); + PtrTrack->EndPtr = GetEndPointer (VariableStoreHeader); + + InDeletedVariable = NULL; + + // + // No Variable Address equals zero, so 0 as initial value is safe. + // + MaxIndex = NULL; + VariableHeader = NULL; + + if (IndexTable != NULL) { + // + // traverse the variable index table to look for varible. + // The IndexTable->Index[Index] records the distance of two neighbouring VAR_ADDED type variables. + // + for (Offset = 0, Index = 0; Index < IndexTable->Length; Index++) { + ASSERT (Index < sizeof (IndexTable->Index) / sizeof (IndexTable->Index[0])); + Offset += IndexTable->Index[Index]; + MaxIndex = (VARIABLE_HEADER *)((UINT8 *)IndexTable->StartPtr + Offset); + GetVariableHeader (StoreInfo, MaxIndex, &VariableHeader); + if (CompareWithValidVariable (StoreInfo, MaxIndex, VariableHeader, VariableName, VendorGuid, PtrTrack) == EFI_SUCCESS) { + if (VariableHeader->State == (VAR_IN_DELETED_TRANSITION & VAR_ADDED)) { + InDeletedVariable = PtrTrack->CurrPtr; + } else { + return EFI_SUCCESS; + } + } + } + + if (IndexTable->GoneThrough != 0) { + // + // If the table has all the existing variables indexed, return. + // + PtrTrack->CurrPtr = InDeletedVariable; + return (PtrTrack->CurrPtr == NULL) ? EFI_NOT_FOUND : EFI_SUCCESS; + } + } + + if (MaxIndex != NULL) { + // + // HOB exists but the variable cannot be found in HOB + // If not found in HOB, then let's start from the MaxIndex we've found. + // + Variable = GetNextVariablePtr (StoreInfo, MaxIndex, VariableHeader); + LastVariable = MaxIndex; + } else { + // + // Start Pointers for the variable. + // Actual Data Pointer where data can be written. + // + Variable = PtrTrack->StartPtr; + LastVariable = PtrTrack->StartPtr; + } + + // + // Find the variable by walk through variable store + // + StopRecord = FALSE; + while (GetVariableHeader (StoreInfo, Variable, &VariableHeader)) { + if ((VariableHeader->State == VAR_ADDED) || (VariableHeader->State == (VAR_IN_DELETED_TRANSITION & VAR_ADDED))) { + // + // Record Variable in VariableIndex HOB + // + if ((IndexTable != NULL) && !StopRecord) { + Offset = (UINTN)Variable - (UINTN)LastVariable; + if ((Offset > 0x0FFFF) || (IndexTable->Length >= sizeof (IndexTable->Index) / sizeof (IndexTable->Index[0]))) { + // + // Stop to record if the distance of two neighbouring VAR_ADDED variable is larger than the allowable scope(UINT16), + // or the record buffer is full. + // + StopRecord = TRUE; + } else { + IndexTable->Index[IndexTable->Length++] = (UINT16)Offset; + LastVariable = Variable; + } + } + + if (CompareWithValidVariable (StoreInfo, Variable, VariableHeader, VariableName, VendorGuid, PtrTrack) == EFI_SUCCESS) { + if (VariableHeader->State == (VAR_IN_DELETED_TRANSITION & VAR_ADDED)) { + InDeletedVariable = PtrTrack->CurrPtr; + } else { + return EFI_SUCCESS; + } + } + } + + Variable = GetNextVariablePtr (StoreInfo, Variable, VariableHeader); + } + + // + // If gone through the VariableStore, that means we never find in Firmware any more. + // + if ((IndexTable != NULL) && !StopRecord) { + IndexTable->GoneThrough = 1; + } + + PtrTrack->CurrPtr = InDeletedVariable; + + return (PtrTrack->CurrPtr == NULL) ? EFI_NOT_FOUND : EFI_SUCCESS; +} + +/** + Find the variable in HOB and Non-Volatile variable storages. + + @param VariableName Name of the variable to be found + @param VendorGuid Vendor GUID to be found. + @param PtrTrack Variable Track Pointer structure that contains Variable Information. + @param StoreInfo Return the store info. + + @retval EFI_SUCCESS Variable found successfully + @retval EFI_NOT_FOUND Variable not found + @retval EFI_INVALID_PARAMETER Invalid variable name +**/ +EFI_STATUS +FindVariable ( + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VendorGuid, + OUT VARIABLE_POINTER_TRACK *PtrTrack, + OUT VARIABLE_STORE_INFO *StoreInfo + ) +{ + EFI_STATUS Status; + VARIABLE_STORE_TYPE Type; + + if ((VariableName[0] != 0) && (VendorGuid == NULL)) { + return EFI_INVALID_PARAMETER; + } + + for (Type = (VARIABLE_STORE_TYPE)0; Type < VariableStoreTypeMax; Type++) { + GetVariableStore (Type, StoreInfo); + Status = FindVariableEx ( + StoreInfo, + VariableName, + VendorGuid, + PtrTrack + ); + if (!EFI_ERROR (Status)) { + return Status; + } + } + + return EFI_NOT_FOUND; +} + +/** + This service retrieves a variable's value using its name and GUID. + + Read the specified variable from the UEFI variable store. If the Data + buffer is too small to hold the contents of the variable, the error + EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the required buffer + size to obtain the data. + + @param VariableName A pointer to a null-terminated string that is the variable's name. + @param VariableGuid A pointer to an EFI_GUID that is the variable's GUID. The combination of + VariableGuid and VariableName must be unique. + @param Attributes If non-NULL, on return, points to the variable's attributes. + @param DataSize On entry, points to the size in bytes of the Data buffer. + On return, points to the size of the data returned in Data. + @param Data Points to the buffer which will hold the returned variable value. + May be NULL with a zero DataSize in order to determine the size of the buffer needed. + + @retval EFI_SUCCESS The variable was read successfully. + @retval EFI_NOT_FOUND The variable was be found. + @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the resulting data. + DataSize is updated with the size required for + the specified variable. + @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL. + @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error. + +**/ +EFI_STATUS +EFIAPI +BaseGetVariable ( + IN CONST CHAR16 *VariableName, + IN CONST EFI_GUID *VariableGuid, + OUT UINT32 *Attributes, + IN OUT UINTN *DataSize, + OUT VOID *Data OPTIONAL + ) +{ + VARIABLE_POINTER_TRACK Variable; + UINTN VarDataSize; + EFI_STATUS Status; + VARIABLE_STORE_INFO StoreInfo; + VARIABLE_HEADER *VariableHeader; + + if ((VariableName == NULL) || (VariableGuid == NULL) || (DataSize == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if (VariableName[0] == 0) { + return EFI_NOT_FOUND; + } + + VariableHeader = NULL; + + // + // Find existing variable + // + Status = FindVariable (VariableName, VariableGuid, &Variable, &StoreInfo); + if (EFI_ERROR (Status)) { + return Status; + } + + GetVariableHeader (&StoreInfo, Variable.CurrPtr, &VariableHeader); + + // + // Get data size + // + VarDataSize = DataSizeOfVariable (VariableHeader, StoreInfo.AuthFlag); + if (*DataSize >= VarDataSize) { + if (Data == NULL) { + return EFI_INVALID_PARAMETER; + } + + GetVariableNameOrData (&StoreInfo, GetVariableDataPtr (Variable.CurrPtr, VariableHeader, StoreInfo.AuthFlag), VarDataSize, Data); + Status = EFI_SUCCESS; + } else { + Status = EFI_BUFFER_TOO_SMALL; + } + + if (Attributes != NULL) { + *Attributes = VariableHeader->Attributes; + } + + *DataSize = VarDataSize; + + return Status; +} + +/** + Return the next variable name and GUID. + + This function is called multiple times to retrieve the VariableName + and VariableGuid of all variables currently available in the system. + On each call, the previous results are passed into the interface, + and, on return, the interface returns the data for the next + interface. When the entire variable list has been returned, + EFI_NOT_FOUND is returned. + + @param VariableNameSize On entry, points to the size of the buffer pointed to by VariableName. + On return, the size of the variable name buffer. + @param VariableName On entry, a pointer to a null-terminated string that is the variable's name. + On return, points to the next variable's null-terminated name string. + @param VariableGuid On entry, a pointer to an EFI_GUID that is the variable's GUID. + On return, a pointer to the next variable's GUID. + + @retval EFI_SUCCESS The variable was read successfully. + @retval EFI_NOT_FOUND The variable could not be found. + @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the resulting + data. VariableNameSize is updated with the size + required for the specified variable. + @retval EFI_INVALID_PARAMETER VariableName, VariableGuid or + VariableNameSize is NULL. + @retval EFI_DEVICE_ERROR The variable could not be retrieved because of a device error. + +**/ +EFI_STATUS +EFIAPI +BaseGetNextVariableName ( + IN OUT UINTN *VariableNameSize, + IN OUT CHAR16 *VariableName, + IN OUT EFI_GUID *VariableGuid + ) +{ + VARIABLE_STORE_TYPE Type; + VARIABLE_POINTER_TRACK Variable; + VARIABLE_POINTER_TRACK VariableInHob; + VARIABLE_POINTER_TRACK VariablePtrTrack; + UINTN VarNameSize; + EFI_STATUS Status; + VARIABLE_STORE_HEADER *VariableStoreHeader[VariableStoreTypeMax]; + VARIABLE_HEADER *VariableHeader; + VARIABLE_STORE_INFO StoreInfo; + VARIABLE_STORE_INFO StoreInfoForNv; + VARIABLE_STORE_INFO StoreInfoForHob; + + if ((VariableName == NULL) || (VariableGuid == NULL) || (VariableNameSize == NULL)) { + return EFI_INVALID_PARAMETER; + } + + VariableHeader = NULL; + + Status = FindVariable (VariableName, VariableGuid, &Variable, &StoreInfo); + if ((Variable.CurrPtr == NULL) || (Status != EFI_SUCCESS)) { + return Status; + } + + if (VariableName[0] != 0) { + // + // If variable name is not NULL, get next variable + // + GetVariableHeader (&StoreInfo, Variable.CurrPtr, &VariableHeader); + Variable.CurrPtr = GetNextVariablePtr (&StoreInfo, Variable.CurrPtr, VariableHeader); + } + + VariableStoreHeader[VariableStoreTypeHob] = GetVariableStore (VariableStoreTypeHob, &StoreInfoForHob); + VariableStoreHeader[VariableStoreTypeNv] = GetVariableStore (VariableStoreTypeNv, &StoreInfoForNv); + + while (TRUE) { + // + // Switch from HOB to Non-Volatile. + // + while (!GetVariableHeader (&StoreInfo, Variable.CurrPtr, &VariableHeader)) { + // + // Find current storage index + // + for (Type = (VARIABLE_STORE_TYPE)0; Type < VariableStoreTypeMax; Type++) { + if ((VariableStoreHeader[Type] != NULL) && (Variable.StartPtr == GetStartPointer (VariableStoreHeader[Type]))) { + break; + } + } + + ASSERT (Type < VariableStoreTypeMax); + // + // Switch to next storage + // + for (Type++; Type < VariableStoreTypeMax; Type++) { + if (VariableStoreHeader[Type] != NULL) { + break; + } + } + + // + // Capture the case that + // 1. current storage is the last one, or + // 2. no further storage + // + if (Type == VariableStoreTypeMax) { + return EFI_NOT_FOUND; + } + + Variable.StartPtr = GetStartPointer (VariableStoreHeader[Type]); + Variable.EndPtr = GetEndPointer (VariableStoreHeader[Type]); + Variable.CurrPtr = Variable.StartPtr; + GetVariableStore (Type, &StoreInfo); + } + + if ((VariableHeader->State == VAR_ADDED) || (VariableHeader->State == (VAR_IN_DELETED_TRANSITION & VAR_ADDED))) { + if (VariableHeader->State == (VAR_IN_DELETED_TRANSITION & VAR_ADDED)) { + // + // If it is a IN_DELETED_TRANSITION variable, + // and there is also a same ADDED one at the same time, + // don't return it. + // + Status = FindVariableEx ( + &StoreInfo, + GetVariableNamePtr (Variable.CurrPtr, StoreInfo.AuthFlag), + GetVendorGuidPtr (VariableHeader, StoreInfo.AuthFlag), + &VariablePtrTrack + ); + if (!EFI_ERROR (Status) && (VariablePtrTrack.CurrPtr != Variable.CurrPtr)) { + Variable.CurrPtr = GetNextVariablePtr (&StoreInfo, Variable.CurrPtr, VariableHeader); + continue; + } + } + + // + // Don't return NV variable when HOB overrides it + // + if ((VariableStoreHeader[VariableStoreTypeHob] != NULL) && (VariableStoreHeader[VariableStoreTypeNv] != NULL) && + (Variable.StartPtr == GetStartPointer (VariableStoreHeader[VariableStoreTypeNv])) + ) + { + Status = FindVariableEx ( + &StoreInfoForHob, + GetVariableNamePtr (Variable.CurrPtr, StoreInfo.AuthFlag), + GetVendorGuidPtr (VariableHeader, StoreInfo.AuthFlag), + &VariableInHob + ); + if (!EFI_ERROR (Status)) { + Variable.CurrPtr = GetNextVariablePtr (&StoreInfo, Variable.CurrPtr, VariableHeader); + continue; + } + } + + VarNameSize = NameSizeOfVariable (VariableHeader, StoreInfo.AuthFlag); + ASSERT (VarNameSize != 0); + + if (VarNameSize <= *VariableNameSize) { + GetVariableNameOrData (&StoreInfo, (UINT8 *)GetVariableNamePtr (Variable.CurrPtr, StoreInfo.AuthFlag), VarNameSize, (UINT8 *)VariableName); + + CopyMem (VariableGuid, GetVendorGuidPtr (VariableHeader, StoreInfo.AuthFlag), sizeof (EFI_GUID)); + + Status = EFI_SUCCESS; + } else { + Status = EFI_BUFFER_TOO_SMALL; + } + + *VariableNameSize = VarNameSize; + // + // Variable is found + // + return Status; + } else { + Variable.CurrPtr = GetNextVariablePtr (&StoreInfo, Variable.CurrPtr, VariableHeader); + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/BaseVariableLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/BaseVariableLib.inf new file mode 100644 index 0000000..f27a0fc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/BaseVariableLib.inf @@ -0,0 +1,51 @@ +#/** @file +# +# Read-only non-volatile variable service library for early SEC phase. +# Based on FaultTolerantWritePei and VariablePei, without using any HOBs or PPIs. +# +# Copyright (c) 2024, Mario Bălănică +# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
    +# Copyright (c) Microsoft Corporation.
    +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = BaseVariableLib + FILE_GUID = 0a9a1145-e20f-4d69-be68-eb13b3c3e4a3 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = BaseVariableLib + +[Sources] + BaseVariableLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + PcdLib + +[Guids] + gEdkiiWorkingBlockSignatureGuid ## SOMETIMES_CONSUMES ## GUID + gEfiAuthenticatedVariableGuid ## SOMETIMES_CONSUMES ## GUID + gEfiVariableGuid ## SOMETIMES_CONSUMES ## GUID + gEfiSystemNvDataFvGuid ## SOMETIMES_CONSUMES ## GUID + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ## SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable ## SOMETIMES_CONSUMES diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/Variable.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/Variable.h new file mode 100644 index 0000000..0d725ba --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/BaseVariableLib/Variable.h @@ -0,0 +1,45 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
    + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef _BASE_VARIABLE_H_ +#define _BASE_VARIABLE_H_ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +typedef enum { + VariableStoreTypeHob, + VariableStoreTypeNv, + VariableStoreTypeMax +} VARIABLE_STORE_TYPE; + +typedef struct { + VARIABLE_STORE_HEADER *VariableStoreHeader; + VARIABLE_INDEX_TABLE *IndexTable; + // + // If it is not NULL, it means there may be an inconsecutive variable whose + // partial content is still in NV storage, but another partial content is backed up + // in spare block. + // + FAULT_TOLERANT_WRITE_LAST_WRITE_DATA *FtwLastWriteData; + BOOLEAN AuthFlag; +} VARIABLE_STORE_INFO; + +#endif // _BASE_VARIABLE_H_ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/CruLib/CruLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/CruLib/CruLib.c new file mode 100644 index 0000000..4dcd6da --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/CruLib/CruLib.c @@ -0,0 +1,1048 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "Include/Library/CruLib.h" +#include +#include +#include +#include + +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +/** @defgroup CRU_How_To_Use How To Use + * @{ + + The CRU driver can be used as follows: + + - Invoke cru functions to set clk rate, enable or disable clk, reset clk in each device. + - The gate and soft reset id is include register offset and shift information: + + con_offset: id /16 + shift: id %16 + + - The mux and div id is include register offset, shift, mask information: + + [15:0]: con + [23:16]: shift + [31:24]: width + + - CRU driver is just responsible for passing simple command data, And + the usecount is the user's responsibility. Protection the usecount at the driver layer. + - More details refer to APIs' descriptions as below. + + @} */ + +/** @defgroup CRU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +#define PWRDOWN_SHIT 13 +#define PWRDOWN_MASK 1 << PWRDOWN_SHIT +#define PLL_POSTDIV1_SHIFT 12 +#define PLL_POSTDIV1_MASK 0x7 << PLL_POSTDIV1_SHIFT +#define PLL_FBDIV_SHIFT 0 +#define PLL_FBDIV_MASK 0xfff << PLL_FBDIV_SHIFT +#define PLL_POSTDIV2_SHIFT 6 +#define PLL_POSTDIV2_MASK 0x7 << PLL_POSTDIV2_SHIFT +#define PLL_REFDIV_SHIFT 0 +#define PLL_REFDIV_MASK 0x3f << PLL_REFDIV_SHIFT +#define PLL_DSMPD_SHIFT 12 +#define PLL_DSMPD_MASK 1 << PLL_DSMPD_SHIFT +#define PLL_FRAC_SHIFT 0 +#define PLL_FRAC_MASK 0xffffff << PLL_FRAC_SHIFT + +#define PLLCON0_M_SHIFT 0 +#define PLLCON0_M_MASK 0x3ff << PLLCON0_M_SHIFT +#define PLLCON1_P_SHIFT 0 +#define PLLCON1_P_MASK 0x3f << PLLCON1_P_SHIFT +#define PLLCON1_S_SHIFT 6 +#define PLLCON1_S_MASK 0x7 << PLLCON1_S_SHIFT +#define PLLCON2_K_SHIFT 0 +#define PLLCON2_K_MASK 0xffff << PLLCON2_K_SHIFT +#define PLLCON1_PWRDOWN BIT(13) +#define PLLCON6_LOCK_STATUS BIT(15) + +#define MIN_FOUTVCO_FREQ (800 * MHZ) +#define MAX_FOUTVCO_FREQ (2000 * MHZ) +#define MIN_FOUT_FREQ (24 * MHZ) +#define MAX_FOUT_FREQ (1600 * MHZ) + +#define RK3588_VCO_MIN_HZ (2250UL * MHZ) +#define RK3588_VCO_MAX_HZ (4500UL * MHZ) +#define RK3588_FOUT_MIN_HZ (37UL * MHZ) +#define RK3588_FOUT_MAX_HZ (4500UL * MHZ) + +#define EXPONENT_OF_FRAC_PLL 24 +#define RK_PLL_MODE_SLOW 0 +#define RK_PLL_MODE_NORMAL 1 +#define RK_PLL_MODE_DEEP 2 +#define PLL_GET_PLLMODE(val, shift, mask) (((uint32_t)(val) & mask) >> shift) + +#define PLL_GET_FBDIV(x) (((uint32_t)(x) & (PLL_FBDIV_MASK)) >> PLL_FBDIV_SHIFT) +#define PLL_GET_REFDIV(x) \ + (((uint32_t)(x) & (PLL_REFDIV_MASK)) >> PLL_REFDIV_SHIFT) +#define PLL_GET_POSTDIV1(x) \ + (((uint32_t)(x) & (PLL_POSTDIV1_MASK)) >> PLL_POSTDIV1_SHIFT) +#define PLL_GET_POSTDIV2(x) \ + (((uint32_t)(x) & (PLL_POSTDIV2_MASK)) >> PLL_POSTDIV2_SHIFT) +#define PLL_GET_DSMPD(x) (((uint32_t)(x) & (PLL_DSMPD_MASK)) >> PLL_DSMPD_SHIFT) +#define PLL_GET_FRAC(x) (((uint32_t)(x) & (PLL_FRAC_MASK)) >> PLL_FRAC_SHIFT) + +#define CRU_PLL_ROUND_UP_TO_KHZ(x) (HAL_DIV_ROUND_UP((x), KHZ) * KHZ) + +/********************* Private Structure Definition **************************/ +static struct PLL_CONFIG g_rockchipAutoTable; + +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ + +/** Calculate the greatest common divisor */ +static uint32_t CRU_Gcd(uint32_t m, uint32_t n) +{ + int t; + + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } + m -= n; + } + + return n; +} + +/** + * @brief Rockchip pll clk set postdiv. + * @param foutHz: output freq + * @param *postDiv1: pll postDiv1 + * @param *postDiv2: pll postDiv2 + * @param *foutVco: pll vco + * @return HAL_Status. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = fractional PLL non-divided output frequency + * FOUTPOSTDIV = fractional PLL divided output frequency + * (output of second post divider) + */ +static HAL_Status CRU_PllSetPostDiv(uint32_t foutHz, uint32_t *postDiv1, + uint32_t *postDiv2, uint32_t *foutVco) +{ + uint32_t freq; + + if (foutHz < MIN_FOUTVCO_FREQ) { + for (*postDiv1 = 1; *postDiv1 <= 7; (*postDiv1)++) { + for (*postDiv2 = 1; *postDiv2 <= 7; (*postDiv2)++) { + freq = foutHz * (*postDiv1) * (*postDiv2); + if (freq >= MIN_FOUTVCO_FREQ && freq <= MAX_FOUTVCO_FREQ) { + *foutVco = freq; + + return HAL_OK; + } + } + } + + return HAL_ERROR; + } else { + *postDiv1 = 1; + *postDiv2 = 1; + + return HAL_OK; + } +} + +/** + * @brief Get pll parameter by auto. + * @param finHz: pll intput freq + * @param foutHz: pll output freq + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = fractional PLL non-divided output frequency + * FOUTPOSTDIV = fractional PLL divided output frequency + * (output of second post divider) + * FREF = fractional PLL input reference frequency, (the OSC_HZ 24MHz input) + * REFDIV = fractional PLL input reference clock divider + * FBDIV = Integer value programmed into feedback divide + */ +static const struct PLL_CONFIG *CRU_PllSetByAuto(uint32_t finHz, + uint32_t foutHz) +{ + struct PLL_CONFIG *rateTable = &g_rockchipAutoTable; + uint32_t foutVco = foutHz; + uint64_t fin64, frac64; + uint32_t postDiv1, postDiv2; + uint32_t clkGcd = 0; + HAL_Status error; + + if (finHz == 0 || foutHz == 0 || foutHz == finHz) { + return NULL; + } + + error = CRU_PllSetPostDiv(foutHz, &postDiv1, &postDiv2, &foutVco); + if (error) { + return NULL; + } + rateTable->postDiv1 = postDiv1; + rateTable->postDiv2 = postDiv2; + rateTable->dsmpd = 1; + + if (finHz / MHZ * MHZ == finHz && foutHz / MHZ * MHZ == foutHz) { + finHz /= MHZ; + foutVco /= MHZ; + clkGcd = CRU_Gcd(finHz, foutVco); + rateTable->refDiv = finHz / clkGcd; + rateTable->fbDiv = foutVco / clkGcd; + + rateTable->frac = 0; + } else if (finHz / MHZ * MHZ != finHz) { + clkGcd = foutHz / finHz; + rateTable->fbDiv = clkGcd; + rateTable->refDiv = 1; + rateTable->postDiv1 = 1; + rateTable->postDiv2 = 1; + + fin64 = foutHz * rateTable->refDiv; + fin64 = HAL_DivU64(fin64 << EXPONENT_OF_FRAC_PLL, finHz); + frac64 = rateTable->fbDiv; + frac64 = rateTable->fbDiv << EXPONENT_OF_FRAC_PLL; + frac64 = fin64 - frac64; + rateTable->frac = frac64; + if (rateTable->frac > 0) { + rateTable->dsmpd = 0; + } + } else { + clkGcd = CRU_Gcd(finHz / MHZ, foutVco / MHZ); + rateTable->refDiv = finHz / MHZ / clkGcd; + rateTable->fbDiv = foutVco / MHZ / clkGcd; + rateTable->frac = 0; + + frac64 = (foutVco % MHZ); + fin64 = finHz; + frac64 = frac64 * rateTable->refDiv; + frac64 = HAL_DivU64(frac64 << EXPONENT_OF_FRAC_PLL, fin64); + rateTable->frac = frac64; + if (rateTable->frac > 0) { + rateTable->dsmpd = 0; + } + } + + return rateTable; +} + +/** + * @brief Get pll parameter by rateTable. + * @param *pSetup: struct PLL_SETUP struct, Contains PLL register parameters + * @param rate: pll target rate. + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Look up the rateTable to get the PLL config parameter + */ +static const struct PLL_CONFIG *CRU_PllGetSettings(struct PLL_SETUP *pSetup, + uint32_t rate) +{ + const struct PLL_CONFIG *rateTable = pSetup->rateTable; + + if (rateTable == NULL) { + return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate); + } + + while (rateTable->rate) { + if (rateTable->rate == rate) { + break; + } + rateTable++; + } + if (rateTable->rate != rate) { + return CRU_PllSetByAuto(PLL_INPUT_OSC_RATE, rate); + } else { + return rateTable; + } +} + +static const struct PLL_CONFIG *CRU_PllV1SetByAuto(uint32_t fin_hz, + uint32_t fout_hz) +{ + struct PLL_CONFIG *rate_table = &g_rockchipAutoTable; + uint32_t p, m, s; + uint64_t fvco, fref, fout, ffrac; + + if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz) + return NULL; + + if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ) + return NULL; + + for (s = 0; s <= 6; s++) { + fvco = fout_hz << s; + if (fvco < RK3588_VCO_MIN_HZ || + fvco > RK3588_VCO_MAX_HZ) + continue; + for (p = 1; p <= 4; p++) { + for (m = 64; m <= 1023; m++) { + if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) { + rate_table->p = p; + rate_table->m = m; + rate_table->s = s; + fref = fin_hz / p; + ffrac = fvco - (m * fref); + fout = ffrac * 65536; + rate_table->k = fout / fref; + return rate_table; + } + } + } + } + + DEBUG((DEBUG_ERROR, "%a: CANNOT FIND Fout by auto,fout = %lu\n", __func__, fout_hz)); + return NULL; +} + +/** + * @brief Get pll parameter by rateTable. (RK3588) + * @param *pSetup: struct PLL_SETUP struct, Contains PLL register parameters + * @param rate: pll target rate. + * @return struct PLL_CONFIG. + * How to calculate the PLL: + * Look up the rateTable to get the PLL config parameter + */ +static const struct PLL_CONFIG *CRU_PllV1GetSettings(struct PLL_SETUP *pSetup, + uint32_t rate) +{ + const struct PLL_CONFIG *rateTable = pSetup->rateTable; + + if (rateTable == NULL) { + return CRU_PllV1SetByAuto(PLL_INPUT_OSC_RATE, rate); + } + + while (rateTable->rate) { + if (rateTable->rate == rate) { + break; + } + rateTable++; + } + if (rateTable->rate != rate) { + return CRU_PllV1SetByAuto(PLL_INPUT_OSC_RATE, rate); + } else { + return rateTable; + } +} + +/** @} */ +/********************* Public Function Definition ****************************/ + +/** @defgroup CRU_Exported_Functions_Group5 Other Functions + * @attention these APIs allow direct use in the HAL layer. + * @{ + */ + +/** + * @brief Get pll freq. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return pll rate. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + * If DSMPD = 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / REFDIV) * (FBDIV + FRAC / (2^24)) + * FOUTPOSTDIV = FOUTVCO / (POSTDIV1*POSTDIV2) + * FOUT = FOUTVCO / POSTDIV1 / POSTDIV2 + */ +uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup) +{ + uint32_t refDiv, fbDiv, postdDv1, postDiv2, frac, dsmpd; + uint32_t mode = 0, rate = PLL_INPUT_OSC_RATE; + + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + postdDv1 = PLL_GET_POSTDIV1(READ_REG(*(pSetup->conOffset0))); + fbDiv = PLL_GET_FBDIV(READ_REG(*(pSetup->conOffset0))); + postDiv2 = PLL_GET_POSTDIV2(READ_REG(*(pSetup->conOffset1))); + refDiv = PLL_GET_REFDIV(READ_REG(*(pSetup->conOffset1))); + dsmpd = PLL_GET_DSMPD(READ_REG(*(pSetup->conOffset1))); + frac = PLL_GET_FRAC(READ_REG(*(pSetup->conOffset2))); + rate = (rate / refDiv) * fbDiv; + if (dsmpd == 0) { + uint64_t fracRate = PLL_INPUT_OSC_RATE; + + fracRate *= frac; + fracRate = fracRate >> EXPONENT_OF_FRAC_PLL; + fracRate = fracRate / refDiv; + rate += fracRate; + } + rate = rate / (postdDv1 * postDiv2); + rate = CRU_PLL_ROUND_UP_TO_KHZ(rate); + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/** + * @brief Set pll freq. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @param rate: pll set rate + * @return HAL_Status. + * How to calculate the PLL: + * Force PLL into slow mode + * Pll Power down + * Pll Config fbDiv, refDiv, postdDv1, postDiv2, dsmpd, frac + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 2400; + + if (rate == HAL_CRU_GetPllFreq(pSetup)) { + return HAL_OK; + } else if (rate < MIN_FOUT_FREQ) { + return HAL_INVAL; + } else if (rate > MAX_FOUT_FREQ) { + return HAL_INVAL; + } + + pConfig = CRU_PllGetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_POSTDIV2_MASK, pConfig->postDiv2 << PLL_POSTDIV2_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_REFDIV_MASK, pConfig->refDiv << PLL_REFDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_POSTDIV1_MASK, pConfig->postDiv1 << PLL_POSTDIV1_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLL_FBDIV_MASK, pConfig->fbDiv << PLL_FBDIV_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLL_DSMPD_MASK, pConfig->dsmpd << PLL_DSMPD_SHIFT); + + if (pConfig->frac) { + WRITE_REG(*(pSetup->conOffset2), (READ_REG(*(pSetup->conOffset2)) & 0xff000000) | pConfig->frac); + } + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (pSetup->stat0) { + if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) { + break; + } + } else { + if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) { + break; + } + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +/** + * @brief Get pll v1 freq(RK3588). + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return pll rate. + * How to calculate the PLL: + * Formulas also embedded within the fractional PLL Verilog model: + * If K = 0 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / P * M + * FOUT = FOUTVCO / 2^S + * If K > 0 (DSM is enabled, "fractional mode") + * FOUTVCO = (FREF / P) * (M + K / 65536) + * FOUT = FOUTVCO / 2^S + */ +uint32_t HAL_CRU_GetPllV1Freq(struct PLL_SETUP *pSetup) +{ + uint32_t m, p, s, k; + uint64_t rate = PLL_INPUT_OSC_RATE; + uint32_t mode = 0; + + if (pSetup->modeMask) + mode = PLL_GET_PLLMODE(READ_REG(*(pSetup->modeOffset)), pSetup->modeShift, + pSetup->modeMask); + else + mode = RK_PLL_MODE_NORMAL; + + switch (mode) { + case RK_PLL_MODE_SLOW: + rate = PLL_INPUT_OSC_RATE; + break; + case RK_PLL_MODE_NORMAL: + m = (READ_REG(*(pSetup->conOffset0)) & PLLCON0_M_MASK) >> PLLCON0_M_SHIFT; + p = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_P_MASK) >> PLLCON1_P_SHIFT; + s = (READ_REG(*(pSetup->conOffset1)) & PLLCON1_S_MASK) >> PLLCON1_S_SHIFT; + k = (READ_REG(*(pSetup->conOffset2)) & PLLCON2_K_MASK) >> PLLCON2_K_SHIFT; + + rate *= m; + rate = rate / p; + if (k) { + /* fractional mode */ + uint64_t frac = PLL_INPUT_OSC_RATE / p; + + frac *= k; + frac = frac / 65536; + rate += frac; + } + rate = rate >> s; + + break; + case RK_PLL_MODE_DEEP: + default: + rate = 32768; + break; + } + + return rate; +} + +/** + * @brief Set pll v1 freq(RK3588). + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @param rate: pll set rate + * @return HAL_Status. + * How to calculate the PLL: + * Force PLL into slow mode + * Pll Power down + * Pll Config M, P, S, K + * Pll Power up + * Waiting for pll lock + * Force PLL into normal mode + */ +HAL_Status HAL_CRU_SetPllV1Freq(struct PLL_SETUP *pSetup, uint32_t rate) +{ + const struct PLL_CONFIG *pConfig; + int delay = 24000000; + + if (rate == HAL_CRU_GetPllV1Freq(pSetup)) { + return HAL_OK; + } else if (rate < RK3588_FOUT_MIN_HZ) { + return HAL_INVAL; + } else if (rate > RK3588_FOUT_MAX_HZ) { + return HAL_INVAL; + } + + pConfig = CRU_PllV1GetSettings(pSetup, rate); + if (!pConfig) { + return HAL_ERROR; + } + + /* Force PLL into slow mode to ensure output stable clock */ + if (pSetup->modeMask) + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_SLOW << pSetup->modeShift); + + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); + + /* Pll Config */ + WRITE_REG_MASK_WE(*(pSetup->conOffset0), PLLCON0_M_MASK, pConfig->m << PLLCON0_M_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_P_MASK, pConfig->p << PLLCON1_P_SHIFT); + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PLLCON1_S_MASK, pConfig->s << PLLCON1_S_SHIFT); + if (pConfig->k) + WRITE_REG_MASK_WE(*(pSetup->conOffset2), PLLCON2_K_MASK, pConfig->k << PLLCON2_K_SHIFT); + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (READ_REG(*(pSetup->conOffset6)) & (1 << pSetup->lockShift)) { + break; + } + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + /* Force PLL into normal mode */ + if (pSetup->modeMask) + WRITE_REG_MASK_WE(*(pSetup->modeOffset), pSetup->modeMask, RK_PLL_MODE_NORMAL << pSetup->modeShift); + + return HAL_OK; +} + +/** + * @brief Set pll power up. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup) +{ + int delay = 2400; + + /* Pll Power up */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 0 << PWRDOWN_SHIT); + + /* Waiting for pll lock */ + while (delay > 0) { + if (pSetup->stat0) { + if (READ_REG(*(pSetup->stat0)) & (1 << pSetup->lockShift)) { + break; + } + } else { + if (READ_REG(*(pSetup->conOffset1)) & (1 << pSetup->lockShift)) { + break; + } + } + HAL_CPUDelayUs(1000); + delay--; + } + if (delay == 0) { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Set pll power down. + * @param *pSetup: struct PLL_SETUP struct,Contains PLL register parameters + * @return HAL_Status. + */ +HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup) +{ + /* Pll Power down */ + WRITE_REG_MASK_WE(*(pSetup->conOffset1), PWRDOWN_MASK, 1 << PWRDOWN_SHIT); + + return HAL_OK; +} + +/** + * @brief IP Clock is Enabled API + * @param clk: clk gate id + * @return HAL_Check + */ +HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clockId) +{ + CRU_CLOCK *clk; + uint32_t index, shift, address; + HAL_Check ret; + + clk = HAL_CRU_ClkGetById(clockId); + if (clk == NULL) { + ASSERT (FALSE); + return HAL_FALSE; + } else if ((clk->flags & CLOCK_SUPPORT_GATE) == 0) { + return HAL_TRUE; + } + + index = CLK_GATE_GET_REG_OFFSET(clk->gate); + shift = CLK_GATE_GET_BITS_SHIFT(clk->gate); + address = CRU_CON_REG_ADDRESS(clk->regBase, clk->gateOffset, index); + + ret = (HAL_Check)(!((MmioRead32(address) & (1 << shift)) >> shift)); + + return ret; +} + +/** + * @brief IP Clock Enable API + * @param clk: clk gate id + * @return NONE + */ +HAL_Status HAL_CRU_ClkEnable(uint32_t clockId) +{ + CRU_CLOCK *clk; + uint32_t index, shift, address; + + clk = HAL_CRU_ClkGetById(clockId); + if (clk == NULL || (clk->flags & CLOCK_SUPPORT_GATE) == 0) { + ASSERT (FALSE); + return HAL_ERROR; + } + + index = CLK_GATE_GET_REG_OFFSET(clk->gate); + shift = CLK_GATE_GET_BITS_SHIFT(clk->gate); + address = CRU_CON_REG_ADDRESS(clk->regBase, clk->gateOffset, index); + + MmioWrite32(address, VAL_MASK_WE(1U << shift, 0U << shift)); + + return HAL_OK; +} + +/** + * @brief IP Clock Disabled API + * @param clk: clk gate id + * @return NONE + */ +HAL_Status HAL_CRU_ClkDisable(uint32_t clockId) +{ + CRU_CLOCK *clk; + uint32_t index, shift, address; + + clk = HAL_CRU_ClkGetById(clockId); + if (clk == NULL || (clk->flags & CLOCK_SUPPORT_GATE) == 0) { + ASSERT (FALSE); + return HAL_ERROR; + } + + index = CLK_GATE_GET_REG_OFFSET(clk->gate); + shift = CLK_GATE_GET_BITS_SHIFT(clk->gate); + address = CRU_CON_REG_ADDRESS(clk->regBase, clk->gateOffset, index); + + MmioWrite32(address, VAL_MASK_WE(1U << shift, 1U << shift)); + + return HAL_OK; +} + +/** + * @brief IP Clock set div API + * @param clockId: div id(Contains div offset, shift, mask information) + * @param divValue: div value + * @return NONE + */ +HAL_Status HAL_CRU_ClkSetDiv(uint32_t clockId, uint32_t divValue) +{ + CRU_CLOCK *clk; + uint32_t shift, mask, index, address; + + clk = HAL_CRU_ClkGetById(clockId); + if (clk == NULL || (clk->flags & CLOCK_SUPPORT_DIV) == 0) { + ASSERT (FALSE); + return HAL_ERROR; + } + + index = CLK_DIV_GET_REG_OFFSET(clk->div); + shift = CLK_DIV_GET_BITS_SHIFT(clk->div); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(clk->div); + address = CRU_CON_REG_ADDRESS(clk->regBase, clk->divOffset, index); + + if (divValue > mask) { + divValue = mask; + } + + MmioWrite32(address, VAL_MASK_WE(mask, (divValue - 1U) << shift)); + + return HAL_OK; +} + +/** + * @brief IP Clock get div API + * @param clockId: div id(Contains div offset, shift, mask information) + * @return div value + */ +uint32_t HAL_CRU_ClkGetDiv(uint32_t clockId) +{ + CRU_CLOCK *clk; + uint32_t shift, mask, index, divValue, address; + + clk = HAL_CRU_ClkGetById(clockId); + if (clk == NULL || (clk->flags & CLOCK_SUPPORT_DIV) == 0) { + ASSERT (clk != NULL); + return 1; + } + + index = CLK_DIV_GET_REG_OFFSET(clk->div); + shift = CLK_DIV_GET_BITS_SHIFT(clk->div); + HAL_ASSERT(shift < 16); + mask = CLK_DIV_GET_MASK(clk->div); + address = CRU_CON_REG_ADDRESS(clk->regBase, clk->divOffset, index); + + divValue = ((MmioRead32(address) & mask) >> shift) + 1; + + return divValue; +} + +/** + * @brief IP Clock set mux API + * @param clockId: mux id(Contains mux offset, shift, mask information) + * @param muxValue: mux value + * @return NONE + */ +HAL_SECTION_SRAM_CODE +HAL_Status HAL_CRU_ClkSetMux(uint32_t clockId, uint32_t muxValue) +{ + CRU_CLOCK *clk; + uint32_t shift, mask, index, address; + + clk = HAL_CRU_ClkGetById(clockId); + if (clk == NULL || (clk->flags & CLOCK_SUPPORT_MUX) == 0) { + ASSERT (FALSE); + return HAL_ERROR; + } + + index = CLK_MUX_GET_REG_OFFSET(clk->mux); + shift = CLK_MUX_GET_BITS_SHIFT(clk->mux); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(clk->mux); + address = CRU_CON_REG_ADDRESS(clk->regBase, clk->muxOffset, index); + + MmioWrite32(address, VAL_MASK_WE(mask, muxValue << shift)); + + return HAL_OK; +} + +/** + * @brief IP Clock get mux API + * @param clockId: mux id(Contains mux offset, shift, mask information) + * @return mux value + */ +HAL_SECTION_SRAM_CODE +uint32_t HAL_CRU_ClkGetMux(uint32_t clockId) +{ + CRU_CLOCK *clk; + uint32_t shift, mask, index, muxValue, address; + + clk = HAL_CRU_ClkGetById(clockId); + if (clk == NULL || (clk->flags & CLOCK_SUPPORT_MUX) == 0) { + ASSERT (FALSE); + return 0; + } + + index = CLK_MUX_GET_REG_OFFSET(clk->mux); + shift = CLK_MUX_GET_BITS_SHIFT(clk->mux); + HAL_ASSERT(shift < 16); + mask = CLK_MUX_GET_MASK(clk->mux); + address = CRU_CON_REG_ADDRESS(clk->regBase, clk->muxOffset, index); + + muxValue = ((MmioRead32(address) & mask) >> shift); + + return muxValue; +} + +/** + * @brief Get frac div config. + * @param rateOut: clk out rate. + * @param rate: clk src rate. + * @param numerator: the returned numerator. + * @param denominator: the returned denominator. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate, + uint32_t *numerator, + uint32_t *denominator) +{ + uint32_t gcdVal; + + gcdVal = CRU_Gcd(rate, rateOut); + if (!gcdVal) { + return HAL_ERROR; + } + + *numerator = rateOut / gcdVal; + *denominator = rate / gcdVal; + + if (*numerator < 4) { + *numerator *= 4; + *denominator *= 4; + } + if (*numerator > 0xffff || *denominator > 0xffff) { + return HAL_INVAL; + } + + return HAL_OK; +} + +/** + * @brief Get Np5 best div. + * @param clockId: clk id. + * @param rate: clk rate. + * @param pRate: clk parent rate + * @param bestdiv: the returned bestdiv. + * @return HAL_Status. + */ +HAL_Status HAL_CRU_ClkNp5BestDiv(uint32_t clockId, uint32_t rate, uint32_t pRate, uint32_t *bestdiv) +{ + CRU_CLOCK *clk; + uint32_t maxDiv; + uint32_t i; + + clk = HAL_CRU_ClkGetById(clockId); + if (clk == NULL) { + return HAL_ERROR; + } + + maxDiv = CLK_DIV_GET_MASK(clk->div); + + for (i = 0; i < maxDiv; i++) { + if (((pRate * 2) == (rate * (i * 2 + 3)))) { + *bestdiv = i; + + return HAL_OK; + } + } + + return HAL_ERROR; +} + +/** + * @brief vop dclk enable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +__WEAK HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId) +{ + HAL_CRU_ClkEnable(gateId); + + return HAL_OK; +} + +/** + * @brief vop dclk disable. + * @param gateId: gate id + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +__WEAK HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId) +{ + HAL_CRU_ClkDisable(gateId); + + return HAL_OK; +} + +/** + * @brief assert CRU global software reset. + * @param type: global software reset type. + * @return HAL_INVAL if the SoC does not support. + */ +HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type) +{ +#ifdef CRU_GLB_SRST_FST_VALUE_OFFSET + if (type == GLB_SRST_FST) { + CRU->GLB_SRST_FST_VALUE = GLB_SRST_FST; + } +#endif +#ifdef CRU_GLB_SRST_SND_VALUE_OFFSET + if (type == GLB_SRST_SND) { + CRU->GLB_SRST_SND_VALUE = GLB_SRST_SND; + } +#endif + + return HAL_INVAL; +} + +/** + * @brief IP Clock is reset API + * @param clk: clk reset id + * @return HAL_Check + */ +HAL_Check HAL_CRU_RstIsAsserted(uint32_t resetId) +{ + CRU_RESET *rst; + uint32_t index, shift, address; + HAL_Check ret; + + rst = HAL_CRU_RstGetById(resetId); + if (rst == NULL) { + ASSERT (FALSE); + return HAL_FALSE; + } + + index = CLK_RESET_GET_REG_OFFSET(rst->srst); + shift = CLK_RESET_GET_BITS_SHIFT(rst->srst); + HAL_ASSERT(shift < 16); + address = CRU_CON_REG_ADDRESS(rst->regBase, rst->srstOffset, index); + + ret = (HAL_Check)((MmioRead32(address) & (1 << shift)) >> shift); + + return ret; +} + +/** + * @brief IP Clock Reset Assert API + * @param clk: clk reset id + * @return NONE + */ +HAL_Status HAL_CRU_RstAssert(uint32_t resetId) +{ + CRU_RESET *rst; + uint32_t index, shift, address; + + rst = HAL_CRU_RstGetById(resetId); + if (rst == NULL) { + ASSERT (FALSE); + return HAL_ERROR; + } + + index = CLK_RESET_GET_REG_OFFSET(rst->srst); + shift = CLK_RESET_GET_BITS_SHIFT(rst->srst); + HAL_ASSERT(shift < 16); + address = CRU_CON_REG_ADDRESS(rst->regBase, rst->srstOffset, index); + + MmioWrite32(address, VAL_MASK_WE(1U << shift, 1U << shift)); + + return HAL_OK; +} + +/** + * @brief IP Clock Reset Deassert API + * @param clk: clk reset id + * @return NONE + */ +HAL_Status HAL_CRU_RstDeassert(uint32_t resetId) +{ + CRU_RESET *rst; + uint32_t index, shift, address; + + rst = HAL_CRU_RstGetById(resetId); + if (rst == NULL) { + ASSERT (FALSE); + return HAL_ERROR; + } + + index = CLK_RESET_GET_REG_OFFSET(rst->srst); + shift = CLK_RESET_GET_BITS_SHIFT(rst->srst); + HAL_ASSERT(shift < 16); + address = CRU_CON_REG_ADDRESS(rst->regBase, rst->srstOffset, index); + + MmioWrite32(address, VAL_MASK_WE(1U << shift, 0U << shift)); + + return HAL_OK; +} + +/** @} */ + +/** @} */ + +/** @} */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/CruLib/CruLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/CruLib/CruLib.inf new file mode 100644 index 0000000..2c07344 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/CruLib/CruLib.inf @@ -0,0 +1,39 @@ +#/** @file +# +# Copyright (c) 2017, Rockchip Inc. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CruLib + FILE_GUID = e4457c4c-2cca-11ec-95b4-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = CruLib + +[Sources.common] + CruLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + DebugLib + IoLib + RockchipPlatformLib + +[BuildOptions] + +[Pcd] + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.c new file mode 100644 index 0000000..cd58702 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.c @@ -0,0 +1,1311 @@ +/** @file + Rockchip eDP Driver. + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +# define DP_MAX_LINK_RATE 0x001 +# define DP_MAX_LANE_COUNT 0x002 + +#define DP_LANE0_1_STATUS 0x202 +#define DP_LANE2_3_STATUS 0x203 +# define DP_LANE_CR_DONE (1 << 0) +# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +# define DP_LANE_SYMBOL_LOCKED (1 << 2) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +#define DP_LINK_BW_SET 0x100 +# define DP_LINK_BW_1_62 0x06 +# define DP_LINK_BW_2_7 0x0a +# define DP_LINK_BW_5_4 0x14 /* 1.2 */ +# define DP_LINK_BW_8_1 0x1e /* 1.4 */ + +#define DP_ADJUST_REQUEST_LANE0_1 0x206 +#define DP_ADJUST_REQUEST_LANE2_3 0x207 + +#define DP_DOWNSPREAD_CTRL 0x107 +# define DP_SPREAD_AMP_0_5 (1 << 4) +#define DP_MAX_DOWNSPREAD 0x003 +# define DP_MAX_DOWNSPREAD_0_5 (1 << 0) + +#define DP_SET_ANSI_8B10B (1 << 0) + +#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) + +#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) + +#define DP_TRAINING_PATTERN_SET 0x102 +# define DP_TRAINING_PATTERN_DISABLE 0 +# define DP_TRAINING_PATTERN_1 1 +# define DP_TRAINING_PATTERN_2 2 +# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ +# define DP_TRAINING_PATTERN_4 7 /* 1.4 */ +# define DP_TRAINING_PATTERN_MASK 0x3 +# define DP_TRAINING_PATTERN_MASK_1_4 0xf +# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) + +#define DP_LINK_SCRAMBLING_DISABLE (1 << 5) + +#define DP_LANE_COUNT_SET 0x101 +# define DP_LANE_COUNT_MASK 0x0f +# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) + +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | DP_LANE_CHANNEL_EQ_DONE | DP_LANE_SYMBOL_LOCKED) +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 + +#define EIO 5 /* I/O error */ +#define ENODEV 19 /* No such device */ + +/* DRM-DP-HELPER */ +STATIC +VOID +DrmDpLinkTrainClockRecoveryDelay ( + CONST UINT8 Dpcd[DP_RECEIVER_CAP_SIZE] + ) +{ + INT32 RdInterval = Dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_TRAINING_AUX_RD_MASK; + + if (RdInterval > 4) + DEBUG ((DEBUG_WARN, "AUX interval %d, out of range (max 4)\n", RdInterval)); + + if (RdInterval == 0 || Dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) + NanoSecondDelay(100000); + else + MicroSecondDelay (RdInterval * 4); +} + +STATIC +VOID +DrmDpLinkTrainChannelEqDelay ( + CONST UINT8 Dpcd[DP_RECEIVER_CAP_SIZE] + ) +{ + INT32 RdInterval = Dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_TRAINING_AUX_RD_MASK; + + if (RdInterval > 4) + DEBUG ((DEBUG_WARN, "AUX interval %d, out of range (max 4)\n", RdInterval)); + + if (RdInterval == 0) + NanoSecondDelay(400000); + else + MicroSecondDelay (RdInterval * 4); +} + +STATIC +INT32 +DrmDpBwCodeToLinkRate ( + UINT8 LinkBw + ) +{ + switch(LinkBw) { + default: + DEBUG ((DEBUG_WARN, "Unknown DP link BW code %x, using 162000\n", LinkBw)); + case DP_LINK_BW_1_62: + return 162000; + case DP_LINK_BW_2_7: + return 270000; + case DP_LINK_BW_5_4: + return 540000; + case DP_LINK_BW_8_1: + return 810000; + } +} + +VOID +AnalogixDpEnableScramble ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ) +{ + UINT8 Data; + + if (Enable) { + AnalogixDpEnableScrambling(Dp); + + AnalogixDpReadByteFromDpcd(Dp, DP_TRAINING_PATTERN_SET, + &Data); + AnalogixDpWriteByteToDpcd(Dp, + DP_TRAINING_PATTERN_SET, + (UINT8)(Data & ~DP_LINK_SCRAMBLING_DISABLE)); + } else { + AnalogixDpDisableScrambling(Dp); + + AnalogixDpReadByteFromDpcd(Dp, DP_TRAINING_PATTERN_SET, + &Data); + AnalogixDpWriteByteToDpcd(Dp, + DP_TRAINING_PATTERN_SET, + (UINT8)(Data | DP_LINK_SCRAMBLING_DISABLE)); + } +} + +BOOLEAN +AnalogixDpGetPllLockStatus ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + UINTN i; + + for(i = 0; i < 20; i++) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_DEBUG_CTL); + MicroSecondDelay (20); + } + + if (Reg & PLL_LOCK) { + return PLL_LOCKED; + } else { + DEBUG ((DEBUG_WARN, "Pll unlocked \n")); + return PLL_UNLOCKED; + } +} + +VOID +AnalogixDpEnableRxToEnhancedMode ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ) +{ + UINT8 Data; + + AnalogixDpReadByteFromDpcd(Dp, DP_LANE_COUNT_SET, &Data); + + if (Enable) + AnalogixDpWriteByteToDpcd(Dp, DP_LANE_COUNT_SET, + DP_LANE_COUNT_ENHANCED_FRAME_EN | DPCD_LANE_COUNT_SET(Data)); + else + AnalogixDpWriteByteToDpcd(Dp, DP_LANE_COUNT_SET, + DPCD_LANE_COUNT_SET(Data)); +} + +VOID +AnalogixDpEnableEnhancedMode ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ) +{ + UINT32 Reg; + + if (Enable) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_4); + Reg |= ENHANCED; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_4,Reg); + } else { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_4); + Reg &= ~ENHANCED; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_4,Reg); + } +} + +VOID +AnalogixDpInitVideo ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_STA_1, Reg); + + Reg = 0x0; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_1, Reg); + + Reg = CHA_CRI(4) | CHA_CTRL; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_2, Reg); + + Reg = 0x0; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_3, Reg); + + Reg = VID_HRES_TH(2) | VID_VRES_TH(0); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_8, Reg); +} + +VOID +AnalogixDpResetMacro ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_PHY_TEST); + Reg |= MACRO_RST; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PHY_TEST, Reg); + + /* 10 us is the minimum reset time. */ + NanoSecondDelay (20000); + + Reg &= ~MACRO_RST; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PHY_TEST, Reg); +} + +STATIC +VOID +AnalogixDpGetMaxRxBandwidth ( + OUT struct AnalogixDpDevice *Dp, + IN UINT8 *Bandwidth + ) +{ + UINT8 Data; + /* + * For DP rev.1.1, Maximum link rate of Main Link Lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link Lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps + */ + AnalogixDpReadByteFromDpcd(Dp, DP_MAX_LINK_RATE, &Data); + *Bandwidth = Data; +} + +STATIC +VOID +AnalogixDpGetMaxRxLaneCount ( + OUT struct AnalogixDpDevice *Dp, + IN UINT8 *LaneCount + ) +{ + UINT8 Data; + + /* + * For DP rev.1.1, Maximum number of Main Link Lanes + * 0x01 = 1 Lane, 0x02 = 2 Lanes, 0x04 = 4 Lanes + */ + AnalogixDpReadByteFromDpcd(Dp, DP_MAX_LANE_COUNT, &Data); + *LaneCount = DPCD_MAX_LANE_COUNT(Data); +} + +UINTN +AnalogixDpInitTraining ( + OUT struct AnalogixDpDevice *Dp, + enum LinkLaneCountType MaxLane, + INT32 MaxRate + ) +{ + UINT8 Dpcd; + + /* + * MACRO_RST must be applied after the PLL_LOCCK to avoid + * the DP inter pair skew issue for at least 10us + * */ + AnalogixDpResetMacro(Dp); + + /* Initailze by reading RX's DPCD */ + AnalogixDpGetMaxRxBandwidth(Dp, &Dp->LinkTrain.LinkRate); + AnalogixDpGetMaxRxLaneCount(Dp, &Dp->LinkTrain.LaneCount); + + if ((Dp->LinkTrain.LinkRate != DP_LINK_BW_1_62) && + (Dp->LinkTrain.LinkRate != DP_LINK_BW_2_7) && + (Dp->LinkTrain.LinkRate != DP_LINK_BW_5_4) ) { + DEBUG ((DEBUG_WARN, "faiied to get Rx Max Link Rate 0x%2x \n", + Dp->LinkTrain.LinkRate)); + return -ENODEV; + } + + if (Dp->LinkTrain.LaneCount == 0) { + DEBUG ((DEBUG_WARN, "faiied to get Rx Max Lane count\n")); + return -ENODEV; + } + + /* Setup TX Lane count & rate */ + if (Dp->LinkTrain.LaneCount > MaxLane) + Dp->LinkTrain.LaneCount = MaxLane; + if (Dp->LinkTrain.LinkRate > MaxRate) + Dp->LinkTrain.LinkRate = MaxRate; + + AnalogixDpReadByteFromDpcd(Dp, DP_MAX_DOWNSPREAD, &Dpcd); + Dp->LinkTrain.SSC = !!(Dpcd & DP_MAX_DOWNSPREAD_0_5); + + /* All DP analog module power up */ + AnalogixDpSetAnalogPowerDown(Dp, POWER_ALL, 0); + + return 0; +} + +BOOLEAN +AnalogixDpSscSupportes ( + OUT struct AnalogixDpDevice *Dp + ) +{ + // Todo + return Dp->LinkTrain.SSC; +} + +UINTN +AnalogixDpSetLinkBandwidth ( + OUT struct AnalogixDpDevice *Dp, + UINT32 BwType + ) +{ + UINTN i; + UINT32 Reg; + OUT struct PhyConfigureOptsDp OPTS_DP; + OUT struct RockchipHdptxPhy Hdptx; + Dp->Id = Hdptx.Id = PcdGet32(PcdEdpId); + + OPTS_DP.LANES = Dp->LinkTrain.LaneCount; + OPTS_DP.LINKRATE = DrmDpBwCodeToLinkRate(Dp->LinkTrain.LinkRate) / 100; + OPTS_DP.SSC = AnalogixDpSscSupportes(Dp); + OPTS_DP.SETLANES = FALSE; + OPTS_DP.SETRATE = TRUE; + OPTS_DP.SETVOLTAGES = FALSE; + + RockchipHdptxPhyConfigure(&Hdptx, &OPTS_DP); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_LINK_BW_SET, BwType); + + Reg = AnalogixDpGetPllLockStatus(Dp); + for (i = 0; i < 20; i++) { + if (Reg != PLL_LOCKED) + MicroSecondDelay (10); + else + break; + } + + return 0; +} + +UINTN +AnalogixDpSetLaneCount ( + OUT struct AnalogixDpDevice *Dp, + UINT32 Count + ) +{ + UINTN Reg ; + OUT struct PhyConfigureOptsDp OPTS_DP; + OUT struct RockchipHdptxPhy Hdptx; + Dp->Id = Hdptx.Id = PcdGet32(PcdEdpId); + + Reg = Count; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_LANE_COUNT_SET, Reg); + + OPTS_DP.LANES = Dp->LinkTrain.LaneCount; + OPTS_DP.LINKRATE = DrmDpBwCodeToLinkRate(Dp->LinkTrain.LinkRate) / 100; + OPTS_DP.SSC = AnalogixDpSscSupportes(Dp); + OPTS_DP.SETLANES = TRUE; + OPTS_DP.SETRATE = FALSE; + OPTS_DP.SETVOLTAGES = FALSE; + RockchipHdptxPhyConfigure(&Hdptx, &OPTS_DP); + + return 0 ; +} + +STATIC +INT32 +AnalogixDpLinkStart ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT8 Buf[4]; + INT32 Lane, LaneCount, Retval; + + LaneCount = Dp->LinkTrain.LaneCount; + Dp->LinkTrain.LtState = CLOCK_RECOVERY; + Dp->LinkTrain.EqLoop = 0; + + for (Lane = 0; Lane < LaneCount; Lane++) + Dp->LinkTrain.CrLoop[Lane] = 0; + + /* Set link rate and count as you want to establish*/ + AnalogixDpSetLinkBandwidth(Dp, Dp->LinkTrain.LinkRate); + AnalogixDpSetLaneCount(Dp, Dp->LinkTrain.LaneCount); + + /* Setup RX configuration */ + Buf[0] = Dp->LinkTrain.LinkRate; + Buf[1] = Dp->LinkTrain.LaneCount; + Retval = AnalogixDpWriteBytesToDpcd(Dp, DP_LINK_BW_SET, 2, Buf); + if (Retval) + return Retval; + + /* Spread AMP if required, Enable 8b/10b coding */ + Buf[0] = AnalogixDpSscSupportes(Dp) ? DP_SPREAD_AMP_0_5 : 0; + Buf[1] = DP_SET_ANSI_8B10B; + Retval = AnalogixDpWriteBytesToDpcd(Dp, DP_DOWNSPREAD_CTRL, + 2, Buf); + if (Retval < 0) + return Retval; + + /* Set TX voltage-swing and pre-emphasis to minimum */ + for (Lane = 0; Lane < LaneCount; Lane++) + Dp->LinkTrain.TrainingLane[Lane] = + DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | + DP_TRAIN_PRE_EMPH_LEVEL_0; + AnalogixDpSetLaneLinkTraining(Dp); + + /* Set training pattern 1 */ + AnalogixDpSetTrainingPattern(Dp, TRAINING_PTN1); + + /* Set RX training pattern */ + Retval = AnalogixDpWriteByteToDpcd(Dp, + DP_TRAINING_PATTERN_SET, + DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); + if (Retval) + return Retval; + + for (Lane = 0; Lane < LaneCount; Lane++) + Buf[Lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | + DP_TRAIN_VOLTAGE_SWING_LEVEL_0; + + Retval = AnalogixDpWriteBytesToDpcd(Dp, DP_TRAINING_LANE0_SET, + LaneCount, Buf); + + return Retval; +} + +STATIC +UINT8 +AnalogixDpGetAdjustRequestVoltage ( + UINT8 AdjustRequest[2], + UINTN Lane) +{ + UINTN Shift = (Lane & 1) * 4; + UINT8 LinkValue = AdjustRequest[Lane >> 1]; + + return (LinkValue >> Shift) & 0x3; +} + +STATIC +UINT8 +AnalogixDpGetAdjustRequestPreEmphasis ( + UINT8 AdjustRequest[2], + UINTN Lane + ) +{ + UINTN shift = (Lane & 1) * 4; + UINT8 link_value = AdjustRequest[Lane >> 1]; + + return ((link_value >> shift) & 0xc) >> 2; +} + +STATIC +VOID +AnalogixDpTrainingPatternDis ( + OUT struct AnalogixDpDevice *Dp + ) +{ + AnalogixDpSetTrainingPattern(Dp, DP_NONE); + + AnalogixDpWriteByteToDpcd(Dp, DP_TRAINING_PATTERN_SET, + DP_TRAINING_PATTERN_DISABLE); +} + +STATIC +INT32 +AnalogixDpIsEnhancedModeAvailable ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT8 Data; + INT32 Retval; + + AnalogixDpReadByteFromDpcd(Dp, DP_MAX_LANE_COUNT, &Data); + Retval = DPCD_ENHANCED_FRAME_CAP(Data); + + return Retval; +} + +STATIC +VOID +AnalogixDpSetEnhancedMode ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT8 Data; + + Data = AnalogixDpIsEnhancedModeAvailable(Dp); + AnalogixDpEnableRxToEnhancedMode(Dp, Data); + AnalogixDpEnableEnhancedMode(Dp, Data); +} + +STATIC +VOID +AnalogixDpReduceLinkRate ( + OUT struct AnalogixDpDevice *Dp + ) +{ + AnalogixDpTrainingPatternDis(Dp); + AnalogixDpSetEnhancedMode(Dp); + Dp->LinkTrain.LtState = FAILED; +} + +STATIC +VOID +AnalogixDpGetAdjustTrainingLane ( + OUT struct AnalogixDpDevice *Dp, + UINT8 AdjustRequest[2]) +{ + UINTN Lane , LaneCount; + UINT8 VoltageSwing, PreEmphasis, TrainingLane; + LaneCount = Dp->LinkTrain.LaneCount; + + for (Lane = 0; Lane < LaneCount; Lane++) { + VoltageSwing = AnalogixDpGetAdjustRequestVoltage( + AdjustRequest, Lane + ); + PreEmphasis = AnalogixDpGetAdjustRequestPreEmphasis( + AdjustRequest, Lane + ); + TrainingLane = DPCD_VOLTAGE_SWING_SET(VoltageSwing) | + DPCD_PRE_EMPHASIS_SET(PreEmphasis); + if (VoltageSwing == VOLTAGE_LEVEL_3) + TrainingLane |= DP_TRAIN_MAX_SWING_REACHED; + if (PreEmphasis == PRE_EMPHASIS_LEVEL_3) + TrainingLane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; + + Dp->LinkTrain.TrainingLane[Lane] = TrainingLane; + } +} + +VOID +AnalogixDpSetLaneLinkTraining ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT8 Lane; + OUT struct PhyConfigureOptsDp OPTS_DP; + OUT struct RockchipHdptxPhy Hdptx; + Dp->Id = Hdptx.Id = PcdGet32(PcdEdpId); + + for (Lane = 0; Lane < Dp->LinkTrain.LaneCount; Lane++) { + UINT8 TrainingLane = Dp->LinkTrain.TrainingLane[Lane]; + UINT8 VS, PE; + + AnalogixDpRegWrite(Dp, + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * Lane, + Dp->LinkTrain.TrainingLane[Lane]); + + VS = (TrainingLane & DP_TRAIN_VOLTAGE_SWING_MASK) >> + DP_TRAIN_VOLTAGE_SWING_SHIFT; + PE = (TrainingLane & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT; + OPTS_DP.VOLTAGE[Lane] = VS; + OPTS_DP.PRE[Lane] = PE; + } + + OPTS_DP.LANES = Dp->LinkTrain.LaneCount; + OPTS_DP.LINKRATE = DrmDpBwCodeToLinkRate(Dp->LinkTrain.LinkRate) / 100; + OPTS_DP.SETLANES = FALSE; + OPTS_DP.SETRATE = FALSE; + OPTS_DP.SETVOLTAGES = TRUE; + RockchipHdptxPhyConfigure(&Hdptx, &OPTS_DP); +} + +STATIC +UINT8 +AnalogixDpGetLaneStatus ( + UINT8 LinkStatus[2], + INT32 Lane + ) +{ + INT32 Shift = (Lane & 1) * 4; + UINT8 LinkValue = LinkStatus[Lane >> 1]; + + return (LinkValue >> Shift) & 0xf; +} + +STATIC +INT32 +AnalogixDpClockRecoveryOk ( + UINT8 LinkStatus[2], + INT32 LaneCount + ) +{ + INT32 Lane; + UINT8 LaneStatus; + + for (Lane = 0; Lane < LaneCount; Lane++) { + LaneStatus = AnalogixDpGetLaneStatus(LinkStatus, Lane); + if ((LaneStatus & DP_LANE_CR_DONE) == 0) + return -EINVAL; + } + return 0; +} + +BOOLEAN +AnalogixDpTps3Supported ( + OUT struct AnalogixDpDevice *Dp + ) +{ + BOOLEAN SourceTps3Supported, SinkTps3Supported; + UINT8 Dpcd = 0; + + SourceTps3Supported = + Dp->VideoInfo.MaxLinkRate == DP_LINK_BW_5_4; + + AnalogixDpReadByteFromDpcd(Dp, DP_MAX_LANE_COUNT, &Dpcd); + SinkTps3Supported = Dpcd & DP_TPS3_SUPPORTED; + + return SourceTps3Supported && SinkTps3Supported; +} + +STATIC +INT32 +AnalogixDpProcessClockRecovery ( + OUT struct AnalogixDpDevice *Dp + ) +{ + INT32 Lane, LaneCount, Retval; + UINT8 VoltageSwing, PreEmphasis, TrainingLane; + UINT8 LinkStatus[2], AdjustRequest[2]; + UINT8 TrainingPattern = TRAINING_PTN2; + + DrmDpLinkTrainClockRecoveryDelay(Dp->Dpcd); + + LaneCount = Dp->LinkTrain.LaneCount; + + Retval = AnalogixDpReadBytesFromDpcd(Dp, + DP_LANE0_1_STATUS, 2, LinkStatus); + if (Retval) + return Retval; + + if (AnalogixDpClockRecoveryOk(LinkStatus, LaneCount) == 0) { + if (AnalogixDpTps3Supported(Dp)) + TrainingPattern = TRAINING_PTN3; + + /* set training pattern for EQ*/ + AnalogixDpSetTrainingPattern(Dp, TrainingPattern); + + Retval = AnalogixDpWriteByteToDpcd(Dp, + DP_TRAINING_PATTERN_SET, + (TrainingPattern == TRAINING_PTN3 ? + DP_TRAINING_PATTERN_3 : DP_TRAINING_PATTERN_2)); + if (Retval) + return Retval; + + DEBUG ((DEBUG_WARN, "Link Training Clock Recovery success\n")); + Dp->LinkTrain.LtState = EQUALIZER_TRAINING; + + return 0; + } else { + Retval = AnalogixDpReadBytesFromDpcd(Dp, + DP_ADJUST_REQUEST_LANE0_1, 2, AdjustRequest); + if (Retval) + return Retval; + + for (Lane = 0; Lane < LaneCount; Lane++) { + TrainingLane = AnalogixDpGetLaneLinkTraining( + Dp, Lane); + VoltageSwing = AnalogixDpGetAdjustRequestVoltage( + AdjustRequest, Lane); + PreEmphasis = AnalogixDpGetAdjustRequestPreEmphasis( + AdjustRequest, Lane); + + if (DPCD_VOLTAGE_SWING_GET(TrainingLane) == + VoltageSwing && + DPCD_PRE_EMPHASIS_GET(TrainingLane) == + PreEmphasis) + Dp->LinkTrain.CrLoop[Lane]++; + + if (Dp->LinkTrain.CrLoop[Lane] == MAX_CR_LOOP || + VoltageSwing == VOLTAGE_LEVEL_3 || + PreEmphasis == PRE_EMPHASIS_LEVEL_3) { + DEBUG ((DEBUG_ERROR, "CR Max reached (%d,%d)\n", + Dp->LinkTrain.CrLoop[Lane], + VoltageSwing, PreEmphasis)); + AnalogixDpReduceLinkRate(Dp); + return -EIO; + } + } + } + + AnalogixDpGetAdjustTrainingLane(Dp, AdjustRequest); + AnalogixDpSetLaneLinkTraining(Dp); + + Retval = AnalogixDpWriteBytesToDpcd(Dp, + DP_TRAINING_LANE0_SET, LaneCount, + Dp->LinkTrain.TrainingLane); + if (Retval) + return Retval; + + return Retval; +} + +STATIC +INT32 +AnalogixDpChannelEqOk ( + UINT8 LinkStatus[2], + UINT8 LinkAlign, + INT32 LaneCount + ) +{ + INT32 Lane; + UINT8 LaneStatus; + + if ((LinkAlign & DP_INTERLANE_ALIGN_DONE) == 0) + return -EINVAL; + + for (Lane = 0; Lane < LaneCount; Lane++) { + LaneStatus = AnalogixDpGetLaneStatus(LinkStatus, Lane); + LaneStatus &= DP_CHANNEL_EQ_BITS; + if (LaneStatus != DP_CHANNEL_EQ_BITS) + return -EINVAL; + } + + return 0; +} + +STATIC +INT32 +AnalogixDpProcessEqualizerTraining ( + OUT struct AnalogixDpDevice *Dp + ) +{ + INT32 LaneCount, Retval; + UINT32 Reg; + UINT8 LinkAlign; + UINT8 LinkStatus[2], AdjustRequest[2]; + + DrmDpLinkTrainChannelEqDelay(Dp->Dpcd); + + LaneCount = Dp->LinkTrain.LaneCount; + + Retval = AnalogixDpReadBytesFromDpcd(Dp, + DP_LANE0_1_STATUS, 2, LinkStatus); + if (Retval) + return Retval; + + if (AnalogixDpClockRecoveryOk(LinkStatus, LaneCount)) { + DEBUG ((DEBUG_WARN, "AnalogixDpReduceLinkRate \n")); + AnalogixDpReduceLinkRate(Dp); + //Todo + //return -EIO; + } + + Retval = AnalogixDpReadBytesFromDpcd(Dp, + DP_ADJUST_REQUEST_LANE0_1, 2, AdjustRequest); + if (Retval) + return Retval; + + Retval = AnalogixDpReadByteFromDpcd(Dp, + DP_LANE_ALIGN_STATUS_UPDATED, &LinkAlign); + if (Retval) + return Retval; + + /* Training pattern set to normal */ + AnalogixDpTrainingPatternDis(Dp); + if (!AnalogixDpChannelEqOk(LinkStatus, LinkAlign, LaneCount)) { + + DEBUG ((DEBUG_WARN, "Link Training success\n")); + + AnalogixDpGetLinkBandwidth(Dp, &Reg); + Dp->LinkTrain.LinkRate = Reg; + AnalogixDpGetLaneCount(Dp, &Reg); + Dp->LinkTrain.LaneCount = Reg; + + DEBUG ((DEBUG_WARN, "Final link rate = 0x%.2x, Lane count = 0x%.2x\n", + Dp->LinkTrain.LinkRate, Dp->LinkTrain.LaneCount)); + + /* Set enhanced mode if available */ + AnalogixDpSetEnhancedMode(Dp); + Dp->LinkTrain.LtState = FINISHED; + + return 0; + } + + /* not all locked */ + Dp->LinkTrain.EqLoop++; + if (Dp->LinkTrain.EqLoop > MAX_EQ_LOOP) { + DEBUG ((DEBUG_WARN, "EQ Max loop\n")); + AnalogixDpReduceLinkRate(Dp); + return -EIO; + } + + Retval = AnalogixDpReadBytesFromDpcd(Dp, + DP_ADJUST_REQUEST_LANE0_1, 2, AdjustRequest); + if (Retval) + return Retval; + + AnalogixDpGetAdjustTrainingLane(Dp, AdjustRequest); + AnalogixDpSetLaneLinkTraining(Dp); + + Retval = AnalogixDpWriteBytesToDpcd(Dp, DP_TRAINING_LANE0_SET, + LaneCount, Dp->LinkTrain.TrainingLane); + + return Retval; +} + +STATIC +INT32 +AnalogixDpSwLinkTraining ( + OUT struct AnalogixDpDevice *Dp + ) +{ + INT32 Retval = 0, TrainingFinished = 0; + + Dp->LinkTrain.LtState = START; + + while (!Retval && !TrainingFinished) { + switch (Dp->LinkTrain.LtState) { + case START: + Retval = AnalogixDpLinkStart(Dp); + if (Retval) + DEBUG ((DEBUG_WARN, "LT link start failed!\n")); + break; + case CLOCK_RECOVERY: + Retval = AnalogixDpProcessClockRecovery(Dp); + if (Retval) + DEBUG ((DEBUG_WARN, "LT CR failed!\n")); + case EQUALIZER_TRAINING: + Retval = AnalogixDpProcessEqualizerTraining(Dp); + if (Retval) + DEBUG ((DEBUG_WARN, "LT EQ failed!\n")); + case FINISHED: + TrainingFinished = 1; + break; + case FAILED: + return -EIO; + } + } + + return Retval; +} + +INT32 +AnalogixDpSetLinkTrain ( + OUT struct AnalogixDpDevice *Dp, + UINT32 Count, + UINT32 BwType + ) +{ + INT32 i, Ret; + + for (i = 0; i < 5; i++) { + Ret = AnalogixDpInitTraining(Dp, Count, BwType); + if (Ret < 0) { + DEBUG ((DEBUG_WARN, "faiied to init training\n")); + return Ret; + } + + Ret = AnalogixDpSwLinkTraining(Dp); + if (!Ret) + break; + } + + return Ret; +} + +VOID +AnalogixDpConfigVideoSlaveMode ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_FUNC_EN_1); + Reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); + Reg |= MASTER_VID_FUNC_EN_N; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_FUNC_EN_1, Reg); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_10); + Reg &= ~INTERACE_SCAN_CFG; + Reg |= (Dp->VideoInfo.Interlaced << 2); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_10, Reg); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_10); + Reg &= ~VSYNC_POLARITY_CFG; + Reg |= (Dp->VideoInfo.VSyncPolarity << 1); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_10, Reg); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_10); + Reg &= ~HSYNC_POLARITY_CFG; + Reg |= (Dp->VideoInfo.HSyncPolarity << 0); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_10, Reg); + + Reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SOC_GENERAL_CTL, Reg); +} + +VOID +AnalogixDpSetVideoColorFormat ( + OUT struct AnalogixDpDevice *Dp + ) +{ + //Todo + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_2, 0x10); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_3, 0x00); +} + +VOID +AnalogixDpSetVideoCrMn ( + OUT struct AnalogixDpDevice *Dp, + enum ClockRecoveryMValueType Type, + UINT32 MValue, + UINT32 NValue + ) +{ + UINT32 Reg; + + if (Type == REGISTER_M) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_4); + Reg |= FIX_M_VID; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_4, Reg); + Reg = MValue & 0xff; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_M_VID_0, Reg); + Reg = (MValue >> 8) & 0xff; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_M_VID_1, Reg); + Reg = (MValue >> 16) & 0xff; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_M_VID_2, Reg); + + Reg = NValue & 0xff; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_N_VID_0, Reg); + Reg = (NValue >> 8) & 0xff; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_N_VID_1, Reg); + Reg = (NValue >> 16) & 0xff; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_N_VID_2, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_4); + Reg &= ~FIX_M_VID; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_4, Reg); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_N_VID_0, 0x00); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_N_VID_1, 0x80); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_N_VID_2, 0x00); + } +} + +VOID +AnalogixDpSetVideoTimingMode ( + OUT struct AnalogixDpDevice *Dp, + UINT32 Type + ) +{ + UINT32 Reg; + + if (Type == VIDEO_TIMING_FROM_CAPTURE) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_10); + Reg &= ~FORMAT_SEL; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_10, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_10); + Reg |= FORMAT_SEL; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_10, Reg); + } +} + +STATIC +INT32 +AnalogixDpConfigVideo ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg ,Ret; + UINT32 TimeoutLoop, DoneCount; + + AnalogixDpConfigVideoSlaveMode(Dp); + AnalogixDpSetVideoColorFormat(Dp); + + Reg = AnalogixDpGetPllLockStatus(Dp); + if (Reg != PLL_LOCKED ) { + DEBUG ((DEBUG_WARN, "PLL is not locked yet. \n")); + Ret = AnalogixDpRegRead(Dp, ANALOGIX_DP_DEBUG_CTL); + DEBUG ((DEBUG_WARN, "PLL Dp debug ctl ret 0x%.8x\n", Ret)); + } + + for (;;) { + TimeoutLoop++; + if (AnalogixDpIsSlaveVideoStreamClockOn(Dp) == 0) + break; + if (TimeoutLoop > DP_TIMEOUT_LOOP_COUNT) { + DEBUG ((DEBUG_WARN, "Timeout of video streamclk ok\n")); + return -ETIMEDOUT; + } + + NanoSecondDelay(2000); + } + + /* Set to use the Register calculated M/N video */ + AnalogixDpSetVideoCrMn(Dp, CALCULATED_M, 0, 0); + + /* For video bist Video timing must be generated register */ + AnalogixDpSetVideoTimingMode(Dp, VIDEO_TIMING_FROM_CAPTURE); + + /* Disable video mute */ + AnalogixDpEnableVideoMute(Dp, 0); + + /* Configure video slave mode */ + AnalogixDpEnableVideoMaster(Dp, 0); + + /* Enable video input */ + AnalogixDpStartVideo(Dp); + + TimeoutLoop = 0; + + for (;;) { + TimeoutLoop++; + if (AnalogixDpIsVideoStreamOn(Dp) == 0) { + DoneCount++; + if (DoneCount > 10) + break; + } else if (DoneCount) + DoneCount = 0; + + if (TimeoutLoop > DP_TIMEOUT_LOOP_COUNT) { + DEBUG ((DEBUG_ERROR, "Timeout of video streamclk ok\n")); + return -ETIMEDOUT; + } + + NanoSecondDelay(1001000); + } + + return 0; +} + +EFI_STATUS +AnalogixDpConnectorPreInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + struct RockchipHdptxPhy Hdptx; + struct AnalogixDpDevice *Dp; + Dp = AllocateZeroPool(sizeof (*Dp)); + + ConnectorState->Type = DRM_MODE_CONNECTOR_eDP; + ConnectorState->OutputInterface = VOP_OUTPUT_IF_eDP1; + Dp->Id = Hdptx.Id = PcdGet32(PcdEdpId); + + if (Dp->Id) + ConnectorState->OutputInterface = VOP_OUTPUT_IF_eDP1; + else + ConnectorState->OutputInterface = VOP_OUTPUT_IF_eDP0; + + if (ConnectorState->OutputInterface == VOP_OUTPUT_IF_eDP0) { + MmioWrite32(0xFD5A8000, 0xFFFF0001); + } else { + MmioWrite32(0xFD5A8004, 0xFFFF0001); + } + + RockchipHdptxPhyInit(&Hdptx); + MicroSecondDelay (10); + EnableBacklight(TRUE); + EnablePWM(TRUE); + AnalogixDpReset(Dp); + AnalogixDpSwreset(Dp); + AnalogixDpInitAnalogParam(Dp); + AnalogixDpInitInterrupt(Dp); + /* SW defined function Normal operation */ + AnalogixDpEnableSwFunction(Dp); + AnalogixDpConfigInterrupt(Dp); + AnalogixDpInitAnalogFunc(Dp); + AnalogixDpInitHpd(Dp); + AnalogixDpInitAux(Dp); + + return 0; +}; + +STATIC +INT32 +AnalogixDpLinkPowerUp ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT8 Value; + INTN Ret; + + if (Dp->Dpcd[DP_DPCD_REV] < 0x11) + return 0; + + Ret = AnalogixDpReadByteFromDpcd(Dp, DP_SET_POWER, &Value); + if (Ret < 0) + return Ret; + + Value &= ~DP_SET_POWER_MASK; + Value |= DP_SET_POWER_D0; + + Ret = AnalogixDpWriteByteToDpcd(Dp, DP_SET_POWER, Value); + if (Ret < 0) + return Ret; + + MicroSecondDelay (1); + return 0; +}; + +EFI_STATUS +AnalogixDpConnectorInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + + ConnectorState->OutputMode = ROCKCHIP_OUT_MODE_AAAA; + ConnectorState->ColorSpace = V4L2_COLORSPACE_DEFAULT; + + return 0; +}; + +EFI_STATUS +AnalogixDpConnectorGetEdid ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + //Todo + return 0; +}; + +EFI_STATUS +AnalogixDpConnectorEnable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + struct AnalogixDpDevice *Dp; + Dp = AllocatePool(sizeof (*Dp)); + struct VideoInfo *Video = &Dp->VideoInfo; + UINTN Ret; + + switch (ConnectorState->BPC) { + case 12: + Video->ColorDepth = COLOR_12; + break; + case 10: + Video->ColorDepth = COLOR_10; + break; + case 6: + Video->ColorDepth = COLOR_6; + break; + case 8: + Video->ColorDepth = COLOR_8; + break; + default: + Video->ColorDepth = COLOR_8; + break; + } + + Dp->VideoInfo.MaxLinkRate = DP_LINK_BW_5_4; + Dp->VideoInfo.MaxLaneCount = LANE_COUNT4; + Dp->LinkTrain.SSC = TRUE; + Dp->Id = PcdGet32(PcdEdpId); + + Ret = AnalogixDpReadBytesFromDpcd(Dp, DP_DPCD_REV, + DP_RECEIVER_CAP_SIZE, Dp->Dpcd); + if (Ret) { + DEBUG ((DEBUG_WARN, "Falied to read dpcd cap \n")); + return Ret; + } + + Ret = AnalogixDpLinkPowerUp(Dp); + if (Ret) { + DEBUG ((DEBUG_WARN, "Falied to link power up \n")); + return Ret; + } + + Ret = AnalogixDpSetLinkTrain(Dp, Dp->VideoInfo.MaxLaneCount, + Dp->VideoInfo.MaxLinkRate); + if (Ret) { + DEBUG ((DEBUG_WARN, "Unable to do link train !!! \n")); + return Ret; + } + + AnalogixDpEnableScramble(Dp, 1); + AnalogixDpEnableRxToEnhancedMode(Dp, 1); + AnalogixDpEnableEnhancedMode(Dp, 1); + + AnalogixDpInitVideo(Dp); + AnalogixDpSetVideoFormat(Dp, &ConnectorState->DisplayMode); + AnalogixDpConfigVideo(Dp); + +#if REG_DUMP + DumpDpRegisters(Dp); + DumpHdptxPhyRegisters(Dp); +#endif + FreePool(Dp); + return 0; +}; + +EFI_STATUS +AnalogixDpConnectorDisable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + //Todo + return 0; +}; + +EFI_STATUS +AnalogixDpConnectorDetect ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + //Todo + return 0; +}; + +ROCKCHIP_CONNECTOR_PROTOCOL mDp = { + NULL, + AnalogixDpConnectorPreInit, + AnalogixDpConnectorInit, + NULL, + AnalogixDpConnectorDetect, + NULL, + AnalogixDpConnectorGetEdid, + NULL, + AnalogixDpConnectorEnable, + AnalogixDpConnectorDisable, + NULL +}; + +EFI_STATUS +EFIAPI +AnalogixDpInitDp ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + Handle = NULL; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gRockchipConnectorProtocolGuid, + &mDp, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf new file mode 100644 index 0000000..a1be628 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf @@ -0,0 +1,63 @@ +#/** @file +# +# Component description file for analogix dp module +# +# Copyright (c) 2017, Rockchip Inc. All rights reserved.
    +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AnalogixDpLib + FILE_GUID = 10142bcc-7b5c-11ec-b45f-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = AnalogixDpInitDp + +[Sources.common] + AnalogixDpLib.c + AnalogixDpReg.c + PhyRockchipSamsungHdptx.c + +[LibraryClasses] + TimerLib + DebugLib + IoLib + BaseLib + BaseMemoryLib + RockchipDisplayLib + MemoryAllocationLib + PWMLib + RockchipPlatformLib + UefiLib + UefiDriverEntryPoint + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[BuildOptions] + +[Pcd] + gRockchipTokenSpaceGuid.PcdLcdPixelFormat + gRockchipTokenSpaceGuid.PcdEdpId + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution + +[Protocols] + gRockchipConnectorProtocolGuid + +[Depex] + TRUE + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpReg.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpReg.c new file mode 100644 index 0000000..92c6341 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/AnalogixDpReg.c @@ -0,0 +1,1233 @@ +/** @file + Rockchip eDP Driver. + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#define COMMON_INT_MASK_1 0 +#define COMMON_INT_MASK_2 0 +#define COMMON_INT_MASK_3 0 +#define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) +#define INT_STA_MASK INT_HPD + +VOID +AnalogixDpRegWrite ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 Offset, + IN UINT32 Value + ) +{ + UINT32 BASE; + + if (!Dp->Id) + BASE = ANALOGIX_DP0_REG_BASE; + else + BASE = ANALOGIX_DP1_REG_BASE; + + MmioWrite32(BASE + Offset, Value); +} + +UINT32 +AnalogixDpRegRead ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 Offset + ) +{ + UINT32 Reg; + UINT32 BASE; + + if (!Dp->Id) + BASE = ANALOGIX_DP0_REG_BASE; + else + BASE = ANALOGIX_DP1_REG_BASE; + + Reg = MmioRead32(BASE + Offset); + return Reg; +} + +VOID +AnalogixDpStopVideo ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_1); + Reg &= ~VIDEO_EN; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_1, Reg); +} + +VOID +AnalogixDpSetLaneMap ( + OUT struct AnalogixDpDevice *Dp + ) +{ + //Todo + AnalogixDpRegWrite(Dp, ANALOGIX_DP_LANE_MAP, 0xE4); +} + + +VOID +AnalogixDpEnableVideoMute ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_1); + if (Enable) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_1); + Reg |= HDCP_VIDEO_MUTE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_1,Reg); + } else { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_1); + Reg &= ~HDCP_VIDEO_MUTE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_1,Reg); + } +} + +VOID +AnalogixDpLaneSwap ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ) +{ + //Todo + UINT32 Reg; + + if (Enable) + Reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | + LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; + else + Reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | + LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_LANE_MAP, Reg); +} + +VOID +AnalogixDpReset ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + AnalogixDpStopVideo(Dp); + AnalogixDpEnableVideoMute(Dp, 0); + + Reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | + AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | + HDCP_FUNC_EN_N | SW_FUNC_EN_N; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_FUNC_EN_1, Reg); + + Reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | + SERDES_FIFO_FUNC_EN_N | + LS_CLK_DOMAIN_FUNC_EN_N; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_FUNC_EN_2, Reg); + + NanoSecondDelay (30000); + + AnalogixDpSetLaneMap(Dp); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_1, 0x0); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_2, 0x40); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_3, 0x0); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_4, 0x0); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_HDCP_CTL, 0x0); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x5e); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0x1a); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PHY_TEST, 0x0); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101); +} + +VOID +AnalogixDpSwreset ( + OUT struct AnalogixDpDevice *Dp + ) +{ + /* SW_RESET */ + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TX_SW_RESET,RESET_DP_TX); +} + +VOID +AnalogixDpInitAnalogParam ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = TX_TERMINAL_CTRL_50_OHM; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_ANALOG_CTL_1, Reg); + + Reg = SEL_24M | TX_DVDD_BIT_1_0625V; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_ANALOG_CTL_2, Reg); + + Reg = REF_CLK_24M; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PLL_REG_1, Reg); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PLL_REG_2, 0x99); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PLL_REG_3, 0x40); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PLL_REG_4, 0x58); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PLL_REG_5, 0x22); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BIAS, 0x44); + + Reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_ANALOG_CTL_3, Reg); + + Reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | + TX_CUR1_2X | TX_CUR_16_MA; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PLL_FILTER_CTL_1, Reg); + + Reg = CH3_AMP_400_MV | CH2_AMP_400_MV | + CH1_AMP_400_MV | CH0_AMP_400_MV; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TX_AMP_TUNING_CTL, Reg); + + MicroSecondDelay (10); +} + +VOID +AnalogixDpInitInterrupt ( + OUT struct AnalogixDpDevice *Dp + ) +{ + /* Set interrupt pin assertion polarity as high */ + AnalogixDpRegWrite(Dp, ANALOGIX_DP_INT_CTL,INT_POL1 | INT_POL0); + + /* Clear pending Regisers */ + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_INT_STA_MASK, 0x63); + + /* 0:mask,1: unmask */ + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_INT_STA_MASK, 0x00); +} + +VOID +AnalogixDpEnableSwFunction ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_FUNC_EN_1); + Reg &= ~SW_FUNC_EN_N; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_FUNC_EN_1, Reg); +} + +VOID +AnalogixDpConfigInterrupt ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + /* 0: mask, 1: unmask */ + Reg = COMMON_INT_MASK_1; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_MASK_1, Reg); + Reg = COMMON_INT_MASK_2; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_MASK_2, Reg); + + Reg = COMMON_INT_MASK_3; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_MASK_3, Reg); + + Reg = COMMON_INT_MASK_4; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_MASK_4, Reg); + Reg = INT_STA_MASK; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_INT_STA_MASK, Reg); + +} + +VOID +AnalogixDpSetAnalogPowerDown ( + OUT struct AnalogixDpDevice *Dp, + enum AnalogPowerBlock Block, + BOOLEAN Enable + ) +{ + UINT32 Reg; + UINT32 PhyPdAddr = ANALOGIX_DP_PD; + //Todo + switch (Block) { + case AUX_BLOCK: + if (Enable) { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg |= AUX_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg &= ~AUX_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } + break; + case CH0_BLOCK: + if (Enable) { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg |= CH0_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg &= ~CH0_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } + break; + case CH1_BLOCK: + if (Enable) { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg |= CH1_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg &= ~CH1_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } + break; + case CH2_BLOCK: + if (Enable) { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg |= CH2_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg &= ~CH2_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } + break; + case CH3_BLOCK: + if (Enable) { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg |= CH3_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg &= ~CH3_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } + break; + case ANALOG_TOTAL: + if (Enable) { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg |= DP_PHY_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, PhyPdAddr); + Reg &= ~DP_PHY_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } + break; + case POWER_ALL: + if (Enable) { + Reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | + CH1_PD | CH0_PD; + AnalogixDpRegWrite(Dp, PhyPdAddr, Reg); + } else { + AnalogixDpRegWrite(Dp, PhyPdAddr, 0x00); + } + break; + default: + break; + } +} + +VOID +AnalogixDpSetPllPowerDown ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ) +{ + UINT32 Reg; + + if (Enable) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_PLL_CTL); + Reg |= DP_PLL_PD; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PLL_CTL,Reg); + } else { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_PLL_CTL); + Reg &= ~DP_PLL_PD; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_PLL_CTL,Reg); + } +} + +VOID +AnalogixDpInitAnalogFunc ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + AnalogixDpSetAnalogPowerDown(Dp, POWER_ALL, 0); + + Reg = PLL_LOCK_CHG; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_STA_1, Reg); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_DEBUG_CTL); + Reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_DEBUG_CTL, Reg); + + /* Power up PLL */ + AnalogixDpSetPllPowerDown(Dp, 0); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_FUNC_EN_2); + Reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N + | AUX_FUNC_EN_N); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_FUNC_EN_2, Reg); +} + +VOID +AnalogixDpClearHotplugInterrupts ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + //TODO + Reg = HOTPLUG_CHG | HPD_LOST | PLUG; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_COMMON_INT_STA_4, Reg); + + Reg = INT_HPD; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_INT_STA, Reg); +} + +VOID +AnalogixDpInitHpd ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + AnalogixDpClearHotplugInterrupts(Dp); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_3); + Reg &= ~(F_HPD | HPD_CTRL); + + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_3, Reg); +} + +VOID +AnalogixDpResetAux ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + /* Disable AUX channel module */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_FUNC_EN_2); + Reg |= AUX_FUNC_EN_N; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_FUNC_EN_2, Reg); +} + +VOID +AnalogixDpInitAux ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + /* Clear inerrupts related to AUX channel */ + Reg = RPLY_RECEIV | AUX_ERR; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_INT_STA, Reg); + + AnalogixDpResetAux(Dp); + + Reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | + AUX_HW_RETRY_COUNT_SEL(3) | + AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_HW_RETRY_CTL, Reg); + + /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ + Reg = DEFER_CTRL_EN | DEFER_COUNT(1); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_DEFER_CTL, Reg); + + /* Enable AUX channel module */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_FUNC_EN_2); + Reg &= ~AUX_FUNC_EN_N; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_FUNC_EN_2, Reg); +} + +INT32 +AnalogixDpWriteByteToDpcd ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 RegAddr, + IN UINT8 Data + ) +{ + UINT32 Reg; + UINTN i; + UINTN Retval; + + for (i = 0; i < 3; i++) { + /* Clear AUX CH data buffer */ + Reg = BUF_CLR; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUFFER_DATA_CTL, Reg); + + /* Select DPCD device address */ + Reg = AUX_ADDR_7_0(RegAddr); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_7_0, Reg); + Reg = AUX_ADDR_15_8(RegAddr); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_15_8, Reg); + Reg = AUX_ADDR_19_16(RegAddr); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_19_16, Reg); + + /* write Data buffer */ + Reg = (UINT32)Data; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUF_DATA_0, Reg); + + /* + * Set DisplayPort transaction and write 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + Reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_1, Reg); + + Retval = AnalogixDpStartAuxTransaction(Dp); + if (Retval == 0) + break; + } + + return Retval; +} + +INT32 +AnalogixDpWriteBytesToDpcd ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 RegAddr, + IN UINT32 Count, + IN UINT8 Data[] + ) +{ + UINT32 Reg; + UINT32 StartOffset; + UINT32 CurDataCount, CurDataIdx; + INT32 Retval = 0; + INT32 i; + + /* Clear AUX CH data buffer */ + Reg = BUF_CLR; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUFFER_DATA_CTL, Reg); + + StartOffset = 0; + while (StartOffset < Count) { + /* Buffer size of AUX CH is 16 * 4bytes */ + if ((Count - StartOffset) > 16) + CurDataCount = 16; + else + CurDataCount = Count - StartOffset; + + for (i = 0; i < 3; i++) { + /* Select DPCD device address */ + Reg = AUX_ADDR_7_0(RegAddr + StartOffset); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_7_0, Reg); + Reg = AUX_ADDR_15_8(RegAddr + StartOffset); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_15_8, Reg); + Reg = AUX_ADDR_19_16(RegAddr + StartOffset); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_19_16, Reg); + + for (CurDataIdx = 0; CurDataIdx < CurDataCount; + CurDataIdx++) { + Reg = Data[StartOffset + CurDataIdx]; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUF_DATA_0 + + 4 * CurDataIdx, Reg); + } + + /* + * Set DisplayPort transaction and write + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + Reg = AUX_LENGTH(CurDataCount) | + AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_1, Reg); + + /* Start AUX transaction */ + Retval = AnalogixDpStartAuxTransaction(Dp); + if (Retval == 0) + break; + } + StartOffset += CurDataCount; + } + return Retval; +} + +INT32 +AnalogixDpReadByteFromDpcd ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 RegAddr, + IN UINT8 *Data + ) +{ + UINT32 Reg; + INT32 i; + INT32 Retval; + + for (i = 0; i < 3; i++) { + /* Clear AUX CH data buffer */ + Reg = BUF_CLR; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUFFER_DATA_CTL, Reg); + + /* Select DPCD device address */ + Reg = AUX_ADDR_7_0(RegAddr); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_7_0, Reg); + Reg = AUX_ADDR_15_8(RegAddr); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_15_8, Reg); + Reg = AUX_ADDR_19_16(RegAddr); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_19_16, Reg); + + /* + * Set DisplayPort transaction and read 1 byte + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + Reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_1, Reg); + + /* Start AUX transaction */ + Retval = AnalogixDpStartAuxTransaction(Dp); + if (Retval == 0) + break; + } + + /* Read data buffer */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_BUF_DATA_0); + *Data = (UINT8)(Reg & 0xff); + + return Retval; +} + +INT32 +AnalogixDpStartAuxTransaction ( + OUT struct AnalogixDpDevice *Dp + ) +{ + INT32 Reg; + INT32 Retval = 0; + INT32 TimeOutLoop =0; + + /* Enable AUX CH operation */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_AUX_CH_CTL_2); + Reg |= AUX_EN; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_2, Reg); + + /* Is AUX CH command reply received? */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_INT_STA); + + while (!(Reg & RPLY_RECEIV)) { + TimeOutLoop++; + if (DP_TIMEOUT_LOOP_COUNT < TimeOutLoop) { + DEBUG ((DEBUG_WARN, "AUX CH command reply failed!\n")); + return -ETIMEDOUT; + } + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_INT_STA); + NanoSecondDelay (11000); + } + + /* Clear interrupt source for AUX CH command reply */ + AnalogixDpRegWrite(Dp, ANALOGIX_DP_INT_STA, Reg); + + /* Clear interrupt source for AUX CH access error */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_INT_STA); + if (Reg & AUX_ERR) { + AnalogixDpRegWrite(Dp, ANALOGIX_DP_INT_STA,AUX_ERR); + return -EREMOTEIO; + } + + /* Check AUX CH error access status */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_AUX_CH_STA); + if ((Reg & AUX_STATUS_MASK) != 0) { + DEBUG ((DEBUG_ERROR,"AUX CH error happens: %d \n", + Reg & AUX_STATUS_MASK)); + return -EREMOTEIO; + } + + return Retval; +} + +INT32 +AnalogixDpReadBytesFromDpcd ( + OUT struct AnalogixDpDevice *Dp, + IN UINT32 RegAddr, + IN UINT32 Count, + IN UINT8 Data[] + ) +{ + UINT32 Reg; + UINT32 StartOffset; + UINT32 CurDataCount, CurDataIdx; + INT32 i; + INT32 Retval = 0; + + /* Clear AUX CH data buffer*/ + Reg = BUF_CLR; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUFFER_DATA_CTL, Reg); + + StartOffset = 0; + while (StartOffset < Count) { + /* Buffer size of AUX CH is 16 * 4 bytes */ + if ((Count - StartOffset) > 16) + CurDataCount = 16; + else + CurDataCount = Count - StartOffset; + + /* AUX CH Request Transaction process */ + for (i = 0; i < 3; i++) { + /* Select DPCD device address */ + Reg = AUX_ADDR_7_0(RegAddr + StartOffset); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_7_0, Reg); + Reg = AUX_ADDR_15_8(RegAddr + StartOffset); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_15_8, Reg); + Reg = AUX_ADDR_19_16(RegAddr + StartOffset); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_19_16, Reg); + + /* + * Set DisplayPort transaction and read + * If bit 3 is 1,DisplayPort transaction + * If bit 3 is 0,I2C transaction + */ + Reg = AUX_LENGTH(CurDataCount) | + AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_1, Reg); + + /* Start AUX transaction */ + Retval = AnalogixDpStartAuxTransaction(Dp); + if (Retval == 0) + break; + } + + for (CurDataIdx = 0; CurDataIdx < CurDataCount; + CurDataIdx++) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_BUF_DATA_0 + + 4 * CurDataIdx); + Data[StartOffset + CurDataIdx] = + (UINT8)Reg; + } + + StartOffset += CurDataCount; + } + + return Retval; +} + +INTN +AnalogixDpSelectI2cDevice ( + OUT struct AnalogixDpDevice *Dp, + UINTN DeviceAddr, + UINTN RegAddr + ) +{ + UINT32 Reg; + INTN Retval; + + // Todo + /* Set EDID device address */ + Reg = DeviceAddr; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_7_0, Reg); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_15_8, 0x0); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_ADDR_19_16, 0x0); + + /* Set offset from base address of EDID device */ + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUF_DATA_0, RegAddr); + + /* + * Set I2C transaction and write address + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + Reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | + AUX_TX_COMM_WRITE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_1, Reg); + + /* Start AUX transaction */ + Retval = AnalogixDpStartAuxTransaction(Dp); + if (Retval < 0) + return Retval; + + return 0; +} + +INTN +AnalogixDpReadByteFromI2c ( + struct AnalogixDpDevice *Dp, + UINTN DeviceAddr, + UINTN RegAddr, + UINTN *DATA + ) +{ + UINT32 Reg; + INTN i; + INTN Retval; + + // Todo + for (i = 0; i < 3; i++) { + /* Clear AUX CH data buffer */ + Reg = BUF_CLR; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUFFER_DATA_CTL, Reg); + + /* Select EDID device */ + Retval = AnalogixDpSelectI2cDevice(Dp, DeviceAddr, + RegAddr); + if (Retval != 0) + continue; + + /* + * Set I2C transaction and read data + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + Reg = AUX_TX_COMM_I2C_TRANSACTION | + AUX_TX_COMM_READ; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_1, Reg); + + /* Start AUX transaction */ + Retval = AnalogixDpStartAuxTransaction(Dp); + if (Retval == 0) + break; + } + + /* Read data */ + if (Retval == 0) + *DATA = AnalogixDpRegRead(Dp, ANALOGIX_DP_BUF_DATA_0); + + return Retval; +} + +INTN +AnalogixDpReadBytesFromI2c ( + OUT struct AnalogixDpDevice *Dp, + UINTN DeviceAddr, + UINTN RegAddr, + UINTN Count, + UINT8 Edid[]) +{ + UINT32 Reg; + UINTN i, j; + UINTN CurDataIdx; + UINTN Defer = 0; + INT32 Retval = 0; + + // Todo + for (i = 0; i < Count; i += 16) { + for (j = 0; j < 3; j++) { + /* Clear AUX CH data buffer */ + Reg = BUF_CLR; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_BUFFER_DATA_CTL, Reg); + + /* Set normal AUX CH command */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_AUX_CH_CTL_2); + Reg &= ~ADDR_ONLY; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_2, Reg); + + /* + * If Rx sends defer, Tx sends only reads + * request without sending address + */ + if (!Defer) + Retval = AnalogixDpSelectI2cDevice(Dp, + DeviceAddr, RegAddr + i); + else + Defer = 0; + + if (Retval == 0) { + /* + * Set I2C transaction and write data + * If bit 3 is 1, DisplayPort transaction. + * If Bit 3 is 0, I2C transaction. + */ + Reg = AUX_LENGTH(16) | + AUX_TX_COMM_I2C_TRANSACTION | + AUX_TX_COMM_READ; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_AUX_CH_CTL_1, + Reg); + + /* Start AUX transaction */ + Retval = AnalogixDpStartAuxTransaction(Dp); + if (Retval == 0) + break; + } + /* Check if Rx sends defer */ + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_AUX_RX_COMM); + if (Reg == AUX_RX_COMM_AUX_DEFER || + Reg == AUX_RX_COMM_I2C_DEFER) + Defer = 1; + } + + for (CurDataIdx = 0; CurDataIdx < 16; CurDataIdx++) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_BUF_DATA_0 + + 4 * CurDataIdx); + Edid[i + CurDataIdx] = (UINT8)Reg; + } + } + + return Retval; +} + +VOID +AnalogixDpSetTrainingPattern ( + OUT struct AnalogixDpDevice *Dp, + OUT enum PatternSet Pattern + ) +{ + UINT32 Reg; + + switch (Pattern) { + case PRBS7: + Reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TRAINING_PTN_SET, Reg); + break; + case D10_2: + Reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TRAINING_PTN_SET, Reg); + break; + case TRAINING_PTN1: + Reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TRAINING_PTN_SET, Reg); + break; + case TRAINING_PTN2: + Reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TRAINING_PTN_SET, Reg); + break; + case TRAINING_PTN3: + Reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN3; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TRAINING_PTN_SET, Reg); + break; + case DP_NONE: + Reg = SCRAMBLING_ENABLE | + LINK_QUAL_PATTERN_SET_DISABLE | + SW_TRAINING_PATTERN_SET_NORMAL; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TRAINING_PTN_SET, Reg); + default: + break; + } +} + +UINT32 +AnalogixDpGetLaneLinkTraining ( + OUT struct AnalogixDpDevice *Dp, + IN UINT8 Lane + ) +{ + return AnalogixDpRegRead(Dp, + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * Lane); +} + +VOID +AnalogixDpGetLinkBandwidth ( + OUT struct AnalogixDpDevice *Dp, + UINT32 *BwType) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_LINK_BW_SET); + *BwType = Reg; +} + +VOID +AnalogixDpGetLaneCount ( + OUT struct AnalogixDpDevice *Dp, + UINT32 *Count + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_LANE_COUNT_SET); + *Count = Reg; +} + +INT32 +AnalogixDpIsSlaveVideoStreamClockOn ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_1); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_1, Reg); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_1); + + if (!(Reg & DET_STA)) + return -EINVAL; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_2); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_2, Reg); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_2); + + if (Reg & CHA_STA) + return -EINVAL; + + return 0; +} + +VOID +AnalogixDpEnableVideoMaster ( + OUT struct AnalogixDpDevice *Dp, + BOOLEAN Enable + ) +{ + UINT32 Reg; + + if (Enable) { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SOC_GENERAL_CTL); + Reg &= ~VIDEO_MODE_MASK; + Reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SOC_GENERAL_CTL, Reg); + } else { + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SOC_GENERAL_CTL); + Reg &= ~VIDEO_MODE_MASK; + Reg |= VIDEO_MODE_SLAVE_MODE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SOC_GENERAL_CTL, Reg); + } +} + +VOID +AnalogixDpStartVideo ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_VIDEO_CTL_1); + Reg |= VIDEO_EN; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_VIDEO_CTL_1, Reg); +} + +INTN +AnalogixDpIsVideoStreamOn ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_3); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_SYS_CTL_3, Reg); + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_SYS_CTL_3); + if (!(Reg & STRM_VALID)) + return -EINVAL; + + return 0; +} + +VOID +AnalogixDpEnableScrambling ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_TRAINING_PTN_SET); + Reg &= ~SCRAMBLING_DISABLE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TRAINING_PTN_SET, Reg); +} + +VOID +AnalogixDpDisableScrambling ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 Reg; + + Reg = AnalogixDpRegRead(Dp, ANALOGIX_DP_TRAINING_PTN_SET); + Reg |= ~SCRAMBLING_DISABLE; + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TRAINING_PTN_SET, Reg); +} + +VOID +AnalogixDpSetVideoFormat ( + OUT struct AnalogixDpDevice *Dp, + OUT CONST DRM_DISPLAY_MODE *Mode + ) +{ + UINT32 Hsw, Hfp, Hbp, Vsw, Vfp, Vbp; + + Dp->VideoInfo.Interlaced = !!(Mode->Flags & DRM_MODE_FLAG_INTERLACE); + Dp->VideoInfo.VSyncPolarity = TRUE; + Dp->VideoInfo.HSyncPolarity = TRUE; + + Hsw = Mode->HSyncEnd - Mode->HSyncStart; + Hfp = Mode->HSyncStart - Mode->HDisplay; + Hbp = Mode->HTotal - Mode->HSyncEnd; + Vsw = Mode->VSyncEnd - Mode->VSyncStart; + Vfp = Mode->VSyncStart - Mode->VDisplay; + Vbp = Mode->VTotal - Mode->VSyncEnd; + + /* Set Video Format Parameters */ + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TOTAL_LINE_CFG_L, + TOTAL_LINE_CFG_L(Mode->VTotal)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TOTAL_LINE_CFG_H, + TOTAL_LINE_CFG_H(Mode->VTotal >> 8)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_ACTIVE_LINE_CFG_L, + ACTIVE_LINE_CFG_L(Mode->VDisplay)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_ACTIVE_LINE_CFG_H, + ACTIVE_LINE_CFG_H(Mode->VDisplay >> 8)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_V_F_PORCH_CFG, + V_F_PORCH_CFG(Vfp)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_V_SYNC_WIDTH_CFG, + V_SYNC_WIDTH_CFG(Vsw)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_V_B_PORCH_CFG, + V_B_PORCH_CFG(Vbp)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_L, + TOTAL_PIXEL_CFG_L(Mode->HTotal)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_TOTAL_PIXEL_CFG_H, + TOTAL_PIXEL_CFG_H(Mode->HTotal >> 8)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_L, + ACTIVE_PIXEL_CFG_L(Mode->HDisplay)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_ACTIVE_PIXEL_CFG_H, + ACTIVE_PIXEL_CFG_H(Mode->HDisplay >> 8)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_H_F_PORCH_CFG_L, + H_F_PORCH_CFG_L(Hfp)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_H_F_PORCH_CFG_H, + H_F_PORCH_CFG_H(Hfp >> 8)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_H_SYNC_CFG_L, + H_SYNC_CFG_L(Hsw)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_H_SYNC_CFG_H, + H_SYNC_CFG_H(Hsw >> 8)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_H_B_PORCH_CFG_L, + H_B_PORCH_CFG_L(Hbp)); + AnalogixDpRegWrite(Dp, ANALOGIX_DP_H_B_PORCH_CFG_H, + H_B_PORCH_CFG_H(Hbp >> 8)); +} + +VOID +DumpHdptxPhyRegisters ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINT32 i, Ret; + UINT32 Shift, BASE; + + if (!Dp->Id) + Shift = BASE = EDP0TX_PHY_BASE; + else + Shift = BASE = EDP1TX_PHY_BASE; + + DEBUG ((DEBUG_WARN, "\nHDPTX_PHY_BASE\n%.8x ", BASE)); + for (i = 0; i < 168; i++) { + Ret = MmioRead32(Shift); + Shift = Shift + 0x04; + DEBUG ((DEBUG_WARN, "%.8x ", Ret)); + if((i+1) % 4 == 0) { + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + } + } + + Shift = BASE+0x400; + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + for (i = 0; i < 40; i++) { + Ret = MmioRead32(Shift); + Shift = Shift + 0x04; + DEBUG ((DEBUG_WARN, "%.8x ", Ret)); + if( (i+1) % 4 == 0) { + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + } + } + + Shift = BASE + 0x800; + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + for (i = 0; i < 40; i++) { + Ret = MmioRead32(Shift); + Shift = Shift + 0x04; + DEBUG ((DEBUG_WARN, "%.8x ", Ret)); + if((i+1) % 4 == 0) { + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + } + } + + Shift = BASE + 0x0C00; + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + for (i = 0; i < 40; i++) { + Ret = MmioRead32(Shift); + Shift = Shift + 0x04; + DEBUG ((DEBUG_WARN, "%.8x ", Ret)); + if((i+1) % 4 == 0) { + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + } + } + + Shift = BASE + 0x1000; + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + for ( i = 0; i < 40; i++) { + Ret = MmioRead32(Shift); + Shift = Shift + 0x04; + DEBUG ((DEBUG_WARN, "%.8x ", Ret)); + if( (i+1) % 4 == 0) { + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + } + } + + Shift = BASE + 0x1400; + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + for (i = 0; i < 40; i++) { + Ret = MmioRead32(Shift); + Shift = Shift + 0x04; + DEBUG ((DEBUG_WARN, "%.8x ", Ret)); + if( (i+1) % 4 == 0) { + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + } + } + + Shift = BASE + 0x1800; + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + for (i = 0; i < 40; i++) { + Ret = MmioRead32(Shift); + Shift = Shift + 0x04; + DEBUG ((DEBUG_WARN, "%.8x ", Ret)); + if((i+1) % 4 == 0) { + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + } + } +} + +VOID +DumpDpRegisters ( + OUT struct AnalogixDpDevice *Dp + ) +{ + UINTN i; + UINT32 Ret; + UINT32 Shift; + + if (!Dp->Id) + Shift = ANALOGIX_DP0_REG_BASE; + else + Shift = ANALOGIX_DP1_REG_BASE; + + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + for (i = 0; i < 800; i++) { + Ret = MmioRead32(Shift); + Shift = Shift + 0x04; + DEBUG ((DEBUG_WARN, "%.8x ", Ret)); + if( (i+1) % 4 == 0) + DEBUG ((DEBUG_WARN, "\n%.8x ", Shift)); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.c new file mode 100644 index 0000000..fd90c81 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.c @@ -0,0 +1,1706 @@ +/** @file + * + * Synopsys DesignWare DisplayPort 1.4 TX controller driver + * + * This was ported from U-Boot downstream. It currently lacks: + * - EDID and HPD. + * + * After all features are merged in and tested, the code should ideally + * be refactored to meet EDK II conventions. + * + * U-Boot file: drivers/video/drm/dw-dp.c + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code can be relicensed as BSD-2-Clause-Patent if permission + * is granted by the original authors. + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define DPTX_VERSION_NUMBER 0x0000 +#define DPTX_VERSION_TYPE 0x0004 +#define DPTX_ID 0x0008 + +#define DPTX_CONFIG_REG1 0x0100 +#define DPTX_CONFIG_REG2 0x0104 +#define DPTX_CONFIG_REG3 0x0108 + +#define DPTX_CCTL 0x0200 +#define FORCE_HPD BIT(4) +#define DEFAULT_FAST_LINK_TRAIN_EN BIT(2) +#define ENHANCE_FRAMING_EN BIT(1) +#define SCRAMBLE_DIS BIT(0) +#define DPTX_SOFT_RESET_CTRL 0x0204 +#define VIDEO_RESET BIT(5) +#define AUX_RESET BIT(4) +#define AUDIO_SAMPLER_RESET BIT(3) +#define PHY_SOFT_RESET BIT(1) +#define CONTROLLER_RESET BIT(0) + +#define DPTX_VSAMPLE_CTRL 0x0300 +#define PIXEL_MODE_SELECT GENMASK(22, 21) +#define VIDEO_MAPPING GENMASK(20, 16) +#define VIDEO_STREAM_ENABLE BIT(5) +#define DPTX_VSAMPLE_STUFF_CTRL1 0x0304 +#define DPTX_VSAMPLE_STUFF_CTRL2 0x0308 +#define DPTX_VINPUT_POLARITY_CTRL 0x030c +#define DE_IN_POLARITY BIT(2) +#define HSYNC_IN_POLARITY BIT(1) +#define VSYNC_IN_POLARITY BIT(0) +#define DPTX_VIDEO_CONFIG1 0x0310 +#define HACTIVE GENMASK(31, 16) +#define HBLANK GENMASK(15, 2) +#define I_P BIT(1) +#define R_V_BLANK_IN_OSC BIT(0) +#define DPTX_VIDEO_CONFIG2 0x0314 +#define VBLANK GENMASK(31, 16) +#define VACTIVE GENMASK(15, 0) +#define DPTX_VIDEO_CONFIG3 0x0318 +#define H_SYNC_WIDTH GENMASK(31, 16) +#define H_FRONT_PORCH GENMASK(15, 0) +#define DPTX_VIDEO_CONFIG4 0x031c +#define V_SYNC_WIDTH GENMASK(31, 16) +#define V_FRONT_PORCH GENMASK(15, 0) +#define DPTX_VIDEO_CONFIG5 0x0320 +#define INIT_THRESHOLD_HI GENMASK(22, 21) +#define AVERAGE_BYTES_PER_TU_FRAC GENMASK(19, 16) +#define INIT_THRESHOLD GENMASK(13, 7) +#define AVERAGE_BYTES_PER_TU GENMASK(6, 0) +#define DPTX_VIDEO_MSA1 0x0324 +#define VSTART GENMASK(31, 16) +#define HSTART GENMASK(15, 0) +#define DPTX_VIDEO_MSA2 0x0328 +#define MISC0 GENMASK(31, 24) +#define DPTX_VIDEO_MSA3 0x032c +#define MISC1 GENMASK(31, 24) +#define DPTX_VIDEO_HBLANK_INTERVAL 0x0330 +#define HBLANK_INTERVAL_EN BIT(16) +#define HBLANK_INTERVAL GENMASK(15, 0) + +#define DPTX_AUD_CONFIG1 0x0400 +#define AUDIO_TIMESTAMP_VERSION_NUM GENMASK(29, 24) +#define AUDIO_PACKET_ID GENMASK(23, 16) +#define AUDIO_MUTE BIT(15) +#define NUM_CHANNELS GENMASK(14, 12) +#define HBR_MODE_ENABLE BIT(10) +#define AUDIO_DATA_WIDTH GENMASK(9, 5) +#define AUDIO_DATA_IN_EN GENMASK(4, 1) +#define AUDIO_INF_SELECT BIT(0) + +#define DPTX_SDP_VERTICAL_CTRL 0x0500 +#define EN_VERTICAL_SDP BIT(2) +#define EN_AUDIO_STREAM_SDP BIT(1) +#define EN_AUDIO_TIMESTAMP_SDP BIT(0) +#define DPTX_SDP_HORIZONTAL_CTRL 0x0504 +#define EN_HORIZONTAL_SDP BIT(2) +#define DPTX_SDP_STATUS_REGISTER 0x0508 +#define DPTX_SDP_MANUAL_CTRL 0x050c +#define DPTX_SDP_STATUS_EN 0x0510 + +#define DPTX_SDP_REGISTER_BANK 0x0600 +#define SDP_REGS GENMASK(31, 0) + +#define DPTX_PHYIF_CTRL 0x0a00 +#define PHY_WIDTH BIT(25) +#define PHY_POWERDOWN GENMASK(20, 17) +#define PHY_BUSY GENMASK(15, 12) +#define SSC_DIS BIT(16) +#define XMIT_ENABLE GENMASK(11, 8) +#define PHY_LANES GENMASK(7, 6) +#define PHY_RATE GENMASK(5, 4) +#define TPS_SEL GENMASK(3, 0) +#define DPTX_PHY_TX_EQ 0x0a04 +#define DPTX_CUSTOMPAT0 0x0a08 +#define DPTX_CUSTOMPAT1 0x0a0c +#define DPTX_CUSTOMPAT2 0x0a10 +#define DPTX_HBR2_COMPLIANCE_SCRAMBLER_RESET 0x0a14 +#define DPTX_PHYIF_PWRDOWN_CTRL 0x0a18 + +#define DPTX_AUX_CMD 0x0b00 +#define AUX_CMD_TYPE GENMASK(31, 28) +#define AUX_ADDR GENMASK(27, 8) +#define I2C_ADDR_ONLY BIT(4) +#define AUX_LEN_REQ GENMASK(3, 0) +#define DPTX_AUX_STATUS 0x0b04 +#define AUX_TIMEOUT BIT(17) +#define AUX_BYTES_READ GENMASK(23, 19) +#define AUX_STATUS GENMASK(7, 4) +#define DPTX_AUX_DATA0 0x0b08 +#define DPTX_AUX_DATA1 0x0b0c +#define DPTX_AUX_DATA2 0x0b10 +#define DPTX_AUX_DATA3 0x0b14 + +#define DPTX_GENERAL_INTERRUPT 0x0d00 +#define VIDEO_FIFO_OVERFLOW_STREAM0 BIT(6) +#define AUDIO_FIFO_OVERFLOW_STREAM0 BIT(5) +#define SDP_EVENT_STREAM0 BIT(4) +#define AUX_CMD_INVALID BIT(3) +#define AUX_REPLY_EVENT BIT(1) +#define HPD_EVENT BIT(0) +#define DPTX_GENERAL_INTERRUPT_ENABLE 0x0d04 +#define AUX_REPLY_EVENT_EN BIT(1) +#define HPD_EVENT_EN BIT(0) +#define DPTX_HPD_STATUS 0x0d08 +#define HPD_STATE GENMASK(11, 9) +#define HPD_STATUS BIT(8) +#define HPD_HOT_UNPLUG BIT(2) +#define HPD_HOT_PLUG BIT(1) +#define HPD_IRQ BIT(0) +#define DPTX_HPD_INTERRUPT_ENABLE 0x0d0c +#define HPD_UNPLUG_ERR_EN BIT(3) +#define HPD_UNPLUG_EN BIT(2) +#define HPD_PLUG_EN BIT(1) +#define HPD_IRQ_EN BIT(0) + +#define DPTX_MAX_REGISTER DPTX_HPD_INTERRUPT_ENABLE + +#define SDP_REG_BANK_SIZE 16 + +#define DRM_COLOR_FORMAT_RGB444 BIT(0) +#define DRM_COLOR_FORMAT_YCRCB444 BIT(1) +#define DRM_COLOR_FORMAT_YCRCB422 BIT(2) +#define DRM_COLOR_FORMAT_YCRCB420 BIT(3) + +struct drm_dp_link_caps { + bool enhanced_framing; + bool tps3_supported; + bool tps4_supported; + bool channel_coding; + bool ssc; +}; + +struct drm_dp_link_train_set { + unsigned int voltage_swing[4]; + unsigned int pre_emphasis[4]; +}; + +struct drm_dp_link_train { + struct drm_dp_link_train_set request; + struct drm_dp_link_train_set adjust; + bool clock_recovered; + bool channel_equalized; +}; + +struct dw_dp_link { + u8 dpcd[DP_RECEIVER_CAP_SIZE]; + unsigned char revision; + unsigned int rate; + unsigned int lanes; + struct drm_dp_link_caps caps; + struct drm_dp_link_train train; + u8 sink_count; + u8 vsc_sdp_extension_for_colorimetry_supported; +}; + +struct dw_dp_video { + DRM_DISPLAY_MODE mode; + u32 bus_format; + u8 video_mapping; + u8 pixel_mode; + u8 color_format; + u8 bpc; + u8 bpp; +}; + +struct dw_dp_sdp { + struct dp_sdp_header header; + u8 db[32]; + unsigned long flags; +}; + +struct dw_dp { + UINT32 Signature; + ROCKCHIP_CONNECTOR_PROTOCOL connector; + UINTN regmap; + DP_PHY_PROTOCOL *phy; + struct reset_ctl reset; + int id; + + //struct gpio_desc hpd_gpio; + struct drm_dp_aux aux; + struct dw_dp_link link; + struct dw_dp_video video; + + bool force_hpd; + bool force_output; + u32 max_link_rate; +}; + +#define DW_DP_SIGNATURE SIGNATURE_32 ('D', 'W', 'D', 'P') + +#define DW_DP_FROM_CONNECTOR_PROTOCOL(a) CR (a, struct dw_dp, connector, DW_DP_SIGNATURE) +#define DW_DP_FROM_DRM_DP_AUX(a) CR (a, struct dw_dp, aux, DW_DP_SIGNATURE) + +enum { + SOURCE_STATE_IDLE, + SOURCE_STATE_UNPLUG, + SOURCE_STATE_HPD_TIMEOUT = 4, + SOURCE_STATE_PLUG = 7 +}; + +enum { + DPTX_VM_RGB_6BIT, + DPTX_VM_RGB_8BIT, + DPTX_VM_RGB_10BIT, + DPTX_VM_RGB_12BIT, + DPTX_VM_RGB_16BIT, + DPTX_VM_YCBCR444_8BIT, + DPTX_VM_YCBCR444_10BIT, + DPTX_VM_YCBCR444_12BIT, + DPTX_VM_YCBCR444_16BIT, + DPTX_VM_YCBCR422_8BIT, + DPTX_VM_YCBCR422_10BIT, + DPTX_VM_YCBCR422_12BIT, + DPTX_VM_YCBCR422_16BIT, + DPTX_VM_YCBCR420_8BIT, + DPTX_VM_YCBCR420_10BIT, + DPTX_VM_YCBCR420_12BIT, + DPTX_VM_YCBCR420_16BIT, +}; + +enum { + DPTX_MP_SINGLE_PIXEL, + DPTX_MP_DUAL_PIXEL, + DPTX_MP_QUAD_PIXEL, +}; + +enum { + DPTX_SDP_VERTICAL_INTERVAL = BIT(0), + DPTX_SDP_HORIZONTAL_INTERVAL = BIT(1), +}; + +enum { + DPTX_PHY_PATTERN_NONE, + DPTX_PHY_PATTERN_TPS_1, + DPTX_PHY_PATTERN_TPS_2, + DPTX_PHY_PATTERN_TPS_3, + DPTX_PHY_PATTERN_TPS_4, + DPTX_PHY_PATTERN_SERM, + DPTX_PHY_PATTERN_PBRS7, + DPTX_PHY_PATTERN_CUSTOM_80BIT, + DPTX_PHY_PATTERN_CP2520_1, + DPTX_PHY_PATTERN_CP2520_2, +}; + +enum { + DPTX_PHYRATE_RBR, + DPTX_PHYRATE_HBR, + DPTX_PHYRATE_HBR2, + DPTX_PHYRATE_HBR3, +}; + +struct dw_dp_output_format { + u32 bus_format; + u32 color_format; + u8 video_mapping; + u8 bpc; + u8 bpp; +}; + +static const struct dw_dp_output_format possible_output_fmts[] = { + { MEDIA_BUS_FMT_RGB101010_1X30, DRM_COLOR_FORMAT_RGB444, + DPTX_VM_RGB_10BIT, 10, 30 }, + { MEDIA_BUS_FMT_RGB888_1X24, DRM_COLOR_FORMAT_RGB444, + DPTX_VM_RGB_8BIT, 8, 24 }, + { MEDIA_BUS_FMT_YUV10_1X30, DRM_COLOR_FORMAT_YCRCB444, + DPTX_VM_YCBCR444_10BIT, 10, 30 }, + { MEDIA_BUS_FMT_YUV8_1X24, DRM_COLOR_FORMAT_YCRCB444, + DPTX_VM_YCBCR444_8BIT, 8, 24}, + { MEDIA_BUS_FMT_YUYV10_1X20, DRM_COLOR_FORMAT_YCRCB422, + DPTX_VM_YCBCR422_10BIT, 10, 20 }, + { MEDIA_BUS_FMT_YUYV8_1X16, DRM_COLOR_FORMAT_YCRCB422, + DPTX_VM_YCBCR422_8BIT, 8, 16 }, + { MEDIA_BUS_FMT_UYYVYY10_0_5X30, DRM_COLOR_FORMAT_YCRCB420, + DPTX_VM_YCBCR420_10BIT, 10, 15 }, + { MEDIA_BUS_FMT_UYYVYY8_0_5X24, DRM_COLOR_FORMAT_YCRCB420, + DPTX_VM_YCBCR420_8BIT, 8, 12 }, + { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, DRM_COLOR_FORMAT_RGB444, + DPTX_VM_RGB_6BIT, 6, 18 }, +}; + +static int dw_dp_aux_write_data(struct dw_dp *dp, const u8 *buffer, size_t size) +{ + size_t i, j; + + for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { + size_t num = min_t(size_t, size - i * 4, 4); + u32 value = 0; + + for (j = 0; j < num; j++) + value |= buffer[i * 4 + j] << (j * 8); + + regmap_write(dp->regmap, DPTX_AUX_DATA0 + i * 4, value); + } + + return size; +} + +static int dw_dp_aux_read_data(struct dw_dp *dp, u8 *buffer, size_t size) +{ + size_t i, j; + + for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { + size_t num = min_t(size_t, size - i * 4, 4); + u32 value; + + regmap_read(dp->regmap, DPTX_AUX_DATA0 + i * 4, &value); + + for (j = 0; j < num; j++) + buffer[i * 4 + j] = value >> (j * 8); + } + + return size; +} + +static ssize_t dw_dp_aux_transfer(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg) +{ + u32 status, value; + ssize_t ret = 0; + int timeout = 0; + struct dw_dp *dp = DW_DP_FROM_DRM_DP_AUX (aux); + + switch (msg->request & ~DP_AUX_I2C_MOT) { + case DP_AUX_NATIVE_WRITE: + case DP_AUX_I2C_WRITE: + case DP_AUX_I2C_WRITE_STATUS_UPDATE: + ret = dw_dp_aux_write_data(dp, msg->buffer, msg->size); + if (ret < 0) + return ret; + break; + case DP_AUX_NATIVE_READ: + case DP_AUX_I2C_READ: + break; + default: + return -EINVAL; + } + + if (msg->size > 0) + value = FIELD_PREP(AUX_LEN_REQ, msg->size - 1); + else + value = FIELD_PREP(I2C_ADDR_ONLY, 1); + + value |= FIELD_PREP(AUX_CMD_TYPE, msg->request); + value |= FIELD_PREP(AUX_ADDR, msg->address); + regmap_write(dp->regmap, DPTX_AUX_CMD, value); + + timeout = regmap_read_poll_timeout(dp->regmap, DPTX_GENERAL_INTERRUPT, + status, status & AUX_REPLY_EVENT, + 200, 10); + + if (timeout) { + printf("timeout waiting for AUX reply\n"); + return -ETIMEDOUT; + } + regmap_write(dp->regmap, DPTX_GENERAL_INTERRUPT, AUX_REPLY_EVENT); + + regmap_read(dp->regmap, DPTX_AUX_STATUS, &value); + if (value & AUX_TIMEOUT) { + printf("aux timeout\n"); + return -ETIMEDOUT; + } + + msg->reply = FIELD_GET(AUX_STATUS, value); + + if (msg->size > 0 && msg->reply == DP_AUX_NATIVE_REPLY_ACK) { + if (msg->request & DP_AUX_I2C_READ) { + size_t count = FIELD_GET(AUX_BYTES_READ, value) - 1; + + if (count != msg->size) { + printf("aux fail to read %lu bytes\n", count); + return -EBUSY; + } + + ret = dw_dp_aux_read_data(dp, msg->buffer, count); + if (ret < 0) + return ret; + } + } + + return ret; +} + +static bool dw_dp_bandwidth_ok(struct dw_dp *dp, + const DRM_DISPLAY_MODE *mode, u32 bpp, + unsigned int lanes, unsigned int rate) +{ + u32 max_bw, req_bw; + + req_bw = mode->Clock * bpp / 8; + max_bw = lanes * rate; + if (req_bw > max_bw) + return false; + + return true; +} + +static void dw_dp_hpd_init(struct dw_dp *dp) +{ + /* Enable all HPD interrupts */ + regmap_update_bits(dp->regmap, DPTX_HPD_INTERRUPT_ENABLE, + HPD_UNPLUG_EN | HPD_PLUG_EN | HPD_IRQ_EN, + FIELD_PREP(HPD_UNPLUG_EN, 1) | + FIELD_PREP(HPD_PLUG_EN, 1) | + FIELD_PREP(HPD_IRQ_EN, 1)); + + /* Enable all top-level interrupts */ + regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, + HPD_EVENT_EN, FIELD_PREP(HPD_EVENT_EN, 1)); +} + +static void dw_dp_aux_init(struct dw_dp *dp) +{ + regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, + FIELD_PREP(AUX_RESET, 1)); + udelay(10); + regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, AUX_RESET, + FIELD_PREP(AUX_RESET, 0)); + + regmap_update_bits(dp->regmap, DPTX_GENERAL_INTERRUPT_ENABLE, + AUX_REPLY_EVENT_EN, + FIELD_PREP(AUX_REPLY_EVENT_EN, 1)); +} + +static void dw_dp_init(struct dw_dp *dp) +{ + regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, + FIELD_PREP(CONTROLLER_RESET, 1)); + udelay(10); + regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, CONTROLLER_RESET, + FIELD_PREP(CONTROLLER_RESET, 0)); + + regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, + FIELD_PREP(PHY_SOFT_RESET, 1)); + udelay(10); + regmap_update_bits(dp->regmap, DPTX_SOFT_RESET_CTRL, PHY_SOFT_RESET, + FIELD_PREP(PHY_SOFT_RESET, 0)); + + regmap_update_bits(dp->regmap, DPTX_CCTL, DEFAULT_FAST_LINK_TRAIN_EN, + FIELD_PREP(DEFAULT_FAST_LINK_TRAIN_EN, 0)); + + dw_dp_hpd_init(dp); + dw_dp_aux_init(dp); +} + +static void dw_dp_phy_set_pattern(struct dw_dp *dp, u32 pattern) +{ + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, TPS_SEL, + FIELD_PREP(TPS_SEL, pattern)); +} + +static void dw_dp_phy_xmit_enable(struct dw_dp *dp, u32 lanes) +{ + u32 xmit_enable; + + switch (lanes) { + case 4: + case 2: + case 1: + xmit_enable = GENMASK(lanes - 1, 0); + break; + case 0: + default: + xmit_enable = 0; + break; + } + + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, XMIT_ENABLE, + FIELD_PREP(XMIT_ENABLE, xmit_enable)); +} + +static int dw_dp_link_power_up(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + u8 value; + int ret; + + if (link->revision < 0x11) + return 0; + + ret = drm_dp_dpcd_readb(&dp->aux, DP_SET_POWER, &value); + if (ret < 0) + return ret; + + value &= ~DP_SET_POWER_MASK; + value |= DP_SET_POWER_D0; + + ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, value); + if (ret < 0) + return ret; + + udelay(1000); + return 0; +} + +static int dw_dp_link_probe(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + u8 dpcd; + int ret; + + ret = drm_dp_read_dpcd_caps(&dp->aux, link->dpcd); + if (ret < 0) + return ret; + + ret = drm_dp_dpcd_readb(&dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, + &dpcd); + if (ret < 0) + return ret; + + link->vsc_sdp_extension_for_colorimetry_supported = + !!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); + + link->revision = link->dpcd[DP_DPCD_REV]; + link->rate = min_t(u32, min(dp->max_link_rate, dp->phy->Capabilities.MaximumLinkRate * 100), + drm_dp_max_link_rate(link->dpcd)); + link->lanes = min_t(u8, dp->phy->Capabilities.BusWidth, + drm_dp_max_lane_count(link->dpcd)); + + link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(link->dpcd); + link->caps.tps3_supported = drm_dp_tps3_supported(link->dpcd); + link->caps.tps4_supported = drm_dp_tps4_supported(link->dpcd); + link->caps.channel_coding = drm_dp_channel_coding_supported(link->dpcd); + link->caps.ssc = !!(link->dpcd[DP_MAX_DOWNSPREAD] & + DP_MAX_DOWNSPREAD_0_5); + + return 0; +} + +static int dw_dp_link_train_update_vs_emph(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + struct drm_dp_link_train_set *request = &link->train.request; + DP_PHY_CONFIGURATION phy_cfg; + unsigned int lanes = link->lanes, *vs, *pe; + u8 buf[4]; + int i, ret; + + vs = request->voltage_swing; + pe = request->pre_emphasis; + + for (i = 0; i < lanes; i++) { + phy_cfg.LaneVoltageSwingLevels[i] = vs[i]; + phy_cfg.LanePreEmphasisLevels[i] = pe[i]; + } + phy_cfg.LaneCount = lanes; + phy_cfg.LinkRate = link->rate / 100; + phy_cfg.SetLaneCount = false; + phy_cfg.SetLinkRateAndSpreadSpectrum = false; + phy_cfg.SetVoltageSwingAndPreEmphasisLevels = true; + ret = dp->phy->Configure(dp->phy, &phy_cfg); + if (ret) + return ret; + + for (i = 0; i < lanes; i++) + buf[i] = (vs[i] << DP_TRAIN_VOLTAGE_SWING_SHIFT) | + (pe[i] << DP_TRAIN_PRE_EMPHASIS_SHIFT); + ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes); + if (ret < 0) + return ret; + + return 0; +} + +static int dw_dp_link_configure(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + DP_PHY_CONFIGURATION phy_cfg; + u8 buf[2]; + int ret, phy_rate; + + /* Move PHY to P3 */ + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, + FIELD_PREP(PHY_POWERDOWN, 0x3)); + + phy_cfg.LaneCount = link->lanes; + phy_cfg.LinkRate = link->rate / 100; + phy_cfg.EnableSpreadSpectrum = link->caps.ssc; + phy_cfg.SetLaneCount = true; + phy_cfg.SetLinkRateAndSpreadSpectrum = true; + phy_cfg.SetVoltageSwingAndPreEmphasisLevels = false; + ret = dp->phy->Configure(dp->phy, &phy_cfg); + if (ret) + return ret; + + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, + FIELD_PREP(PHY_LANES, link->lanes / 2)); + + switch (link->rate) { + case 810000: + phy_rate = DPTX_PHYRATE_HBR3; + break; + case 540000: + phy_rate = DPTX_PHYRATE_HBR2; + break; + case 270000: + phy_rate = DPTX_PHYRATE_HBR; + break; + case 162000: + default: + phy_rate = DPTX_PHYRATE_RBR; + break; + } + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, + FIELD_PREP(PHY_RATE, phy_rate)); + + /* Move PHY to P0 */ + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, + FIELD_PREP(PHY_POWERDOWN, 0x0)); + + dw_dp_phy_xmit_enable(dp, link->lanes); + + buf[0] = drm_dp_link_rate_to_bw_code(link->rate); + buf[1] = link->lanes; + + if (link->caps.enhanced_framing) { + buf[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; + regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, + FIELD_PREP(ENHANCE_FRAMING_EN, 1)); + } else { + regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, + FIELD_PREP(ENHANCE_FRAMING_EN, 0)); + } + + ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); + if (ret < 0) + return ret; + + buf[0] = link->caps.ssc ? DP_SPREAD_AMP_0_5 : 0; + buf[1] = link->caps.channel_coding ? DP_SET_ANSI_8B10B : 0; + + ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, + sizeof(buf)); + if (ret < 0) + return ret; + + return 0; +} + +static void dw_dp_link_train_init(struct drm_dp_link_train *train) +{ + struct drm_dp_link_train_set *request = &train->request; + struct drm_dp_link_train_set *adjust = &train->adjust; + unsigned int i; + + for (i = 0; i < 4; i++) { + request->voltage_swing[i] = 0; + adjust->voltage_swing[i] = 0; + + request->pre_emphasis[i] = 0; + adjust->pre_emphasis[i] = 0; + } + + train->clock_recovered = false; + train->channel_equalized = false; +} + +static int dw_dp_link_train_set_pattern(struct dw_dp *dp, u32 pattern) +{ + u8 buf = 0; + int ret; + + if (pattern && pattern != DP_TRAINING_PATTERN_4) { + buf |= DP_LINK_SCRAMBLING_DISABLE; + + regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, + FIELD_PREP(SCRAMBLE_DIS, 1)); + } else { + regmap_update_bits(dp->regmap, DPTX_CCTL, SCRAMBLE_DIS, + FIELD_PREP(SCRAMBLE_DIS, 0)); + } + + switch (pattern) { + case DP_TRAINING_PATTERN_DISABLE: + dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); + break; + case DP_TRAINING_PATTERN_1: + dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_1); + break; + case DP_TRAINING_PATTERN_2: + dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_2); + break; + case DP_TRAINING_PATTERN_3: + dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_3); + break; + case DP_TRAINING_PATTERN_4: + dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_TPS_4); + break; + default: + return -EINVAL; + } + + ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, + buf | pattern); + if (ret < 0) + return ret; + + return 0; +} + +static void dw_dp_link_get_adjustments(struct dw_dp_link *link, + u8 status[DP_LINK_STATUS_SIZE]) +{ + struct drm_dp_link_train_set *adjust = &link->train.adjust; + unsigned int i; + + for (i = 0; i < link->lanes; i++) { + adjust->voltage_swing[i] = + drm_dp_get_adjust_request_voltage(status, i) >> + DP_TRAIN_VOLTAGE_SWING_SHIFT; + + adjust->pre_emphasis[i] = + drm_dp_get_adjust_request_pre_emphasis(status, i) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT; + } +} + +static void dw_dp_link_train_adjust(struct drm_dp_link_train *train) +{ + struct drm_dp_link_train_set *request = &train->request; + struct drm_dp_link_train_set *adjust = &train->adjust; + unsigned int i; + + for (i = 0; i < 4; i++) + if (request->voltage_swing[i] != adjust->voltage_swing[i]) + request->voltage_swing[i] = adjust->voltage_swing[i]; + + for (i = 0; i < 4; i++) + if (request->pre_emphasis[i] != adjust->pre_emphasis[i]) + request->pre_emphasis[i] = adjust->pre_emphasis[i]; +} + +static int dw_dp_link_clock_recovery(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + u8 status[DP_LINK_STATUS_SIZE]; + unsigned int tries = 0; + int ret; + + ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1); + if (ret) + return ret; + + for (;;) { + ret = dw_dp_link_train_update_vs_emph(dp); + if (ret) + return ret; + + drm_dp_link_train_clock_recovery_delay(link->dpcd); + + ret = drm_dp_dpcd_read_link_status(&dp->aux, status); + if (ret < 0) { + dev_err(dp->dev, "failed to read link status: %d\n", + ret); + return ret; + } + + if (drm_dp_clock_recovery_ok(status, link->lanes)) { + link->train.clock_recovered = true; + break; + } + + dw_dp_link_get_adjustments(link, status); + + if (link->train.request.voltage_swing[0] == + link->train.adjust.voltage_swing[0]) + tries++; + else + tries = 0; + + if (tries == 5) + break; + + dw_dp_link_train_adjust(&link->train); + } + + return 0; +} + +static int dw_dp_link_channel_equalization(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + u8 status[DP_LINK_STATUS_SIZE], pattern; + unsigned int tries; + int ret; + + if (link->caps.tps4_supported) + pattern = DP_TRAINING_PATTERN_4; + else if (link->caps.tps3_supported) + pattern = DP_TRAINING_PATTERN_3; + else + pattern = DP_TRAINING_PATTERN_2; + ret = dw_dp_link_train_set_pattern(dp, pattern); + if (ret) + return ret; + + for (tries = 1; tries < 5; tries++) { + ret = dw_dp_link_train_update_vs_emph(dp); + if (ret) + return ret; + + drm_dp_link_train_channel_eq_delay(link->dpcd); + + ret = drm_dp_dpcd_read_link_status(&dp->aux, status); + if (ret < 0) + return ret; + + if (!drm_dp_clock_recovery_ok(status, link->lanes)) { + dev_err(dp->dev, + "clock recovery lost while eq\n"); + link->train.clock_recovered = false; + break; + } + + if (drm_dp_channel_eq_ok(status, link->lanes)) { + link->train.channel_equalized = true; + break; + } + + dw_dp_link_get_adjustments(link, status); + dw_dp_link_train_adjust(&link->train); + } + + return 0; +} + +static int dw_dp_link_downgrade(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + struct dw_dp_video *video = &dp->video; + + switch (link->rate) { + case 162000: + return -EINVAL; + case 270000: + link->rate = 162000; + break; + case 540000: + link->rate = 270000; + break; + case 810000: + link->rate = 540000; + break; + } + + if (!dw_dp_bandwidth_ok(dp, &video->mode, video->bpp, link->lanes, + link->rate)) + return -E2BIG; + + return 0; +} + +static int dw_dp_link_train(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + int ret; + +retry: + dw_dp_link_train_init(&link->train); + + printf("training link: %u lane%s at %u MHz\n", + link->lanes, (link->lanes > 1) ? "s" : "", link->rate / 100); + + ret = dw_dp_link_configure(dp); + if (ret < 0) { + dev_err(dp->dev, "failed to configure DP link: %d\n", ret); + return ret; + } + + ret = dw_dp_link_clock_recovery(dp); + if (ret < 0) { + dev_err(dp->dev, "clock recovery failed: %d\n", ret); + goto out; + } + + if (!link->train.clock_recovered) { + dev_err(dp->dev, "clock recovery failed, downgrading link\n"); + + ret = dw_dp_link_downgrade(dp); + if (ret < 0) + goto out; + else + goto retry; + } + + printf("clock recovery succeeded\n"); + + ret = dw_dp_link_channel_equalization(dp); + if (ret < 0) { + dev_err(dp->dev, "channel equalization failed: %d\n", ret); + goto out; + } + + if (!link->train.channel_equalized) { + dev_err(dp->dev, + "channel equalization failed, downgrading link\n"); + + ret = dw_dp_link_downgrade(dp); + if (ret < 0) + goto out; + else + goto retry; + } + + printf("channel equalization succeeded\n"); + +out: + dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_DISABLE); + return ret; +} + +static int dw_dp_link_enable(struct dw_dp *dp) +{ + int ret; + + ret = dw_dp_link_power_up(dp); + if (ret < 0) + return ret; + + ret = dw_dp_link_train(dp); + if (ret < 0) { + dev_err(dp->dev, "link training failed: %d\n", ret); + return ret; + } + + return 0; +} + +static int dw_dp_set_phy_default_config(struct dw_dp *dp) +{ + struct dw_dp_link *link = &dp->link; + DP_PHY_CONFIGURATION phy_cfg; + int ret, i, phy_rate; + + link->vsc_sdp_extension_for_colorimetry_supported = false; + link->rate = 270000; + link->lanes = dp->phy->Capabilities.BusWidth; + + link->caps.enhanced_framing = true; + link->caps.channel_coding = true; + link->caps.ssc = true; + + /* Move PHY to P3 */ + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, + FIELD_PREP(PHY_POWERDOWN, 0x3)); + + for (i = 0; i < link->lanes; i++) { + phy_cfg.LaneVoltageSwingLevels[i] = 3; + phy_cfg.LanePreEmphasisLevels[i] = 0; + } + phy_cfg.LaneCount = link->lanes; + phy_cfg.LinkRate = link->rate / 100; + phy_cfg.EnableSpreadSpectrum = link->caps.ssc; + phy_cfg.SetLaneCount = true; + phy_cfg.SetLinkRateAndSpreadSpectrum = true; + phy_cfg.SetVoltageSwingAndPreEmphasisLevels = true; + ret = dp->phy->Configure(dp->phy, &phy_cfg); + if (ret) + return ret; + + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, + FIELD_PREP(PHY_LANES, link->lanes / 2)); + + switch (link->rate) { + case 810000: + phy_rate = DPTX_PHYRATE_HBR3; + break; + case 540000: + phy_rate = DPTX_PHYRATE_HBR2; + break; + case 270000: + phy_rate = DPTX_PHYRATE_HBR; + break; + case 162000: + default: + phy_rate = DPTX_PHYRATE_RBR; + break; + } + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_RATE, + FIELD_PREP(PHY_RATE, phy_rate)); + + /* Move PHY to P0 */ + regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_POWERDOWN, + FIELD_PREP(PHY_POWERDOWN, 0x0)); + + dw_dp_phy_xmit_enable(dp, link->lanes); + + regmap_update_bits(dp->regmap, DPTX_CCTL, ENHANCE_FRAMING_EN, + FIELD_PREP(ENHANCE_FRAMING_EN, 1)); + + dw_dp_phy_set_pattern(dp, DPTX_PHY_PATTERN_NONE); + return 0; +} + +static int dw_dp_send_sdp(struct dw_dp *dp, struct dw_dp_sdp *sdp) +{ + const u8 *payload = sdp->db; + u32 reg; + int i, nr = 0; + + reg = DPTX_SDP_REGISTER_BANK + nr * 9 * 4; + + /* SDP header */ + regmap_write(dp->regmap, reg, get_unaligned_le32(&sdp->header)); + + /* SDP data payload */ + for (i = 1; i < 9; i++, payload += 4) + regmap_write(dp->regmap, reg + i * 4, + FIELD_PREP(SDP_REGS, get_unaligned_le32(payload))); + + if (sdp->flags & DPTX_SDP_VERTICAL_INTERVAL) + regmap_update_bits(dp->regmap, DPTX_SDP_VERTICAL_CTRL, + EN_VERTICAL_SDP << nr, + EN_VERTICAL_SDP << nr); + + if (sdp->flags & DPTX_SDP_HORIZONTAL_INTERVAL) + regmap_update_bits(dp->regmap, DPTX_SDP_HORIZONTAL_CTRL, + EN_HORIZONTAL_SDP << nr, + EN_HORIZONTAL_SDP << nr); + + return 0; +} + +static void dw_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, + struct dw_dp_sdp *sdp) +{ + sdp->header.HB0 = 0; + sdp->header.HB1 = DP_SDP_VSC; + sdp->header.HB2 = vsc->revision; + sdp->header.HB3 = vsc->length; + + sdp->db[16] = (vsc->pixelformat & 0xf) << 4; + sdp->db[16] |= vsc->colorimetry & 0xf; + + switch (vsc->bpc) { + case 8: + sdp->db[17] = 0x1; + break; + case 10: + sdp->db[17] = 0x2; + break; + case 12: + sdp->db[17] = 0x3; + break; + case 16: + sdp->db[17] = 0x4; + break; + case 6: + default: + break; + } + + if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) + sdp->db[17] |= 0x80; + + sdp->db[18] = vsc->content_type & 0x7; + + sdp->flags |= DPTX_SDP_VERTICAL_INTERVAL; +} + +static int dw_dp_send_vsc_sdp(struct dw_dp *dp) +{ + struct dw_dp_video *video = &dp->video; + struct drm_dp_vsc_sdp vsc = {}; + struct dw_dp_sdp sdp = {}; + + vsc.revision = 0x5; + vsc.length = 0x13; + + switch (video->color_format) { + case DRM_COLOR_FORMAT_YCRCB444: + vsc.pixelformat = DP_PIXELFORMAT_YUV444; + break; + case DRM_COLOR_FORMAT_YCRCB420: + vsc.pixelformat = DP_PIXELFORMAT_YUV420; + break; + case DRM_COLOR_FORMAT_YCRCB422: + vsc.pixelformat = DP_PIXELFORMAT_YUV422; + break; + case DRM_COLOR_FORMAT_RGB444: + default: + vsc.pixelformat = DP_PIXELFORMAT_RGB; + break; + } + + if (video->color_format == DRM_COLOR_FORMAT_RGB444) + vsc.colorimetry = DP_COLORIMETRY_DEFAULT; + else + vsc.colorimetry = DP_COLORIMETRY_BT709_YCC; + + vsc.bpc = video->bpc; + vsc.dynamic_range = DP_DYNAMIC_RANGE_CTA; + vsc.content_type = DP_CONTENT_TYPE_NOT_DEFINED; + + dw_dp_vsc_sdp_pack(&vsc, &sdp); + + return dw_dp_send_sdp(dp, &sdp); +} + +static int dw_dp_video_set_pixel_mode(struct dw_dp *dp, u8 pixel_mode) +{ + switch (pixel_mode) { + case DPTX_MP_SINGLE_PIXEL: + case DPTX_MP_DUAL_PIXEL: + case DPTX_MP_QUAD_PIXEL: + break; + default: + return -EINVAL; + } + + regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, PIXEL_MODE_SELECT, + FIELD_PREP(PIXEL_MODE_SELECT, pixel_mode)); + + return 0; +} + +static int dw_dp_video_set_msa(struct dw_dp *dp, u8 color_format, u8 bpc, + u16 vstart, u16 hstart) +{ + struct dw_dp_link *link = &dp->link; + u16 misc = 0; + + if (link->vsc_sdp_extension_for_colorimetry_supported) + misc |= DP_MSA_MISC_COLOR_VSC_SDP; + + switch (color_format) { + case DRM_COLOR_FORMAT_RGB444: + misc |= DP_MSA_MISC_COLOR_RGB; + break; + case DRM_COLOR_FORMAT_YCRCB444: + misc |= DP_MSA_MISC_COLOR_YCBCR_444_BT709; + break; + case DRM_COLOR_FORMAT_YCRCB422: + misc |= DP_MSA_MISC_COLOR_YCBCR_422_BT709; + break; + case DRM_COLOR_FORMAT_YCRCB420: + break; + default: + return -EINVAL; + } + + switch (bpc) { + case 6: + misc |= DP_MSA_MISC_6_BPC; + break; + case 8: + misc |= DP_MSA_MISC_8_BPC; + break; + case 10: + misc |= DP_MSA_MISC_10_BPC; + break; + case 12: + misc |= DP_MSA_MISC_12_BPC; + break; + case 16: + misc |= DP_MSA_MISC_16_BPC; + break; + default: + return -EINVAL; + } + + regmap_write(dp->regmap, DPTX_VIDEO_MSA1, + FIELD_PREP(VSTART, vstart) | FIELD_PREP(HSTART, hstart)); + regmap_write(dp->regmap, DPTX_VIDEO_MSA2, FIELD_PREP(MISC0, misc)); + regmap_write(dp->regmap, DPTX_VIDEO_MSA3, FIELD_PREP(MISC1, misc >> 8)); + + return 0; +} + +static int dw_dp_video_enable(struct dw_dp *dp) +{ + struct dw_dp_video *video = &dp->video; + struct dw_dp_link *link = &dp->link; + DRM_DISPLAY_MODE *mode = &video->mode; + u8 color_format = video->color_format; + u8 bpc = video->bpc; + u8 pixel_mode = video->pixel_mode; + u8 bpp = video->bpp, init_threshold, vic; + u32 hactive, hblank, h_sync_width, h_front_porch; + u32 vactive, vblank, v_sync_width, v_front_porch; + u32 vstart = mode->VTotal - mode->VSyncStart; + u32 hstart = mode->HTotal - mode->HSyncStart; + u32 peak_stream_bandwidth, link_bandwidth; + u32 average_bytes_per_tu, average_bytes_per_tu_frac; + u32 ts, hblank_interval; + u32 value; + int ret; + + ret = dw_dp_video_set_pixel_mode(dp, pixel_mode); + if (ret) + return ret; + + ret = dw_dp_video_set_msa(dp, color_format, bpc, vstart, hstart); + if (ret) + return ret; + + regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_MAPPING, + FIELD_PREP(VIDEO_MAPPING, video->video_mapping)); + + /* Configure DPTX_VINPUT_POLARITY_CTRL register */ + value = 0; + if (mode->Flags & DRM_MODE_FLAG_PHSYNC) + value |= FIELD_PREP(HSYNC_IN_POLARITY, 1); + if (mode->Flags & DRM_MODE_FLAG_PVSYNC) + value |= FIELD_PREP(VSYNC_IN_POLARITY, 1); + regmap_write(dp->regmap, DPTX_VINPUT_POLARITY_CTRL, value); + + /* Configure DPTX_VIDEO_CONFIG1 register */ + hactive = mode->HDisplay; + hblank = mode->HTotal - mode->HDisplay; + value = FIELD_PREP(HACTIVE, hactive) | FIELD_PREP(HBLANK, hblank); + if (mode->Flags & DRM_MODE_FLAG_INTERLACE) + value |= FIELD_PREP(I_P, 1); +#if 0 + vic = drm_match_cea_mode(mode); + if (vic == 5 || vic == 6 || vic == 7 || + vic == 10 || vic == 11 || vic == 20 || + vic == 21 || vic == 22 || vic == 39 || + vic == 25 || vic == 26 || vic == 40 || + vic == 44 || vic == 45 || vic == 46 || + vic == 50 || vic == 51 || vic == 54 || + vic == 55 || vic == 58 || vic == 59) + value |= R_V_BLANK_IN_OSC; +#endif + regmap_write(dp->regmap, DPTX_VIDEO_CONFIG1, value); + + /* Configure DPTX_VIDEO_CONFIG2 register */ + vblank = mode->VTotal - mode->VDisplay; + vactive = mode->VDisplay; + regmap_write(dp->regmap, DPTX_VIDEO_CONFIG2, + FIELD_PREP(VBLANK, vblank) | FIELD_PREP(VACTIVE, vactive)); + + /* Configure DPTX_VIDEO_CONFIG3 register */ + h_sync_width = mode->HSyncEnd - mode->HSyncStart; + h_front_porch = mode->HSyncStart - mode->HDisplay; + regmap_write(dp->regmap, DPTX_VIDEO_CONFIG3, + FIELD_PREP(H_SYNC_WIDTH, h_sync_width) | + FIELD_PREP(H_FRONT_PORCH, h_front_porch)); + + /* Configure DPTX_VIDEO_CONFIG4 register */ + v_sync_width = mode->VSyncEnd - mode->VSyncStart; + v_front_porch = mode->VSyncStart - mode->VDisplay; + regmap_write(dp->regmap, DPTX_VIDEO_CONFIG4, + FIELD_PREP(V_SYNC_WIDTH, v_sync_width) | + FIELD_PREP(V_FRONT_PORCH, v_front_porch)); + + /* Configure DPTX_VIDEO_CONFIG5 register */ + peak_stream_bandwidth = mode->Clock * bpp / 8; + link_bandwidth = (link->rate / 1000) * link->lanes; + ts = peak_stream_bandwidth * 64 / link_bandwidth; + average_bytes_per_tu = ts / 1000; + average_bytes_per_tu_frac = ts / 100 - average_bytes_per_tu * 10; + if (pixel_mode == DPTX_MP_SINGLE_PIXEL) { + if (average_bytes_per_tu < 6) + init_threshold = 32; + else if (hblank <= 80 && + color_format != DRM_COLOR_FORMAT_YCRCB420) + init_threshold = 12; + else if (hblank <= 40 && + color_format == DRM_COLOR_FORMAT_YCRCB420) + init_threshold = 3; + else + init_threshold = 16; + } else { + u32 t1 = 0, t2 = 0, t3 = 0; + + switch (bpc) { + case 6: + t1 = (4 * 1000 / 9) * link->lanes; + break; + case 8: + if (color_format == DRM_COLOR_FORMAT_YCRCB422) { + t1 = (1000 / 2) * link->lanes; + } else { + if (pixel_mode == DPTX_MP_DUAL_PIXEL) + t1 = (1000 / 3) * link->lanes; + else + t1 = (3000 / 16) * link->lanes; + } + break; + case 10: + if (color_format == DRM_COLOR_FORMAT_YCRCB422) + t1 = (2000 / 5) * link->lanes; + else + t1 = (4000 / 15) * link->lanes; + break; + case 12: + if (color_format == DRM_COLOR_FORMAT_YCRCB422) { + if (pixel_mode == DPTX_MP_DUAL_PIXEL) + t1 = (1000 / 6) * link->lanes; + else + t1 = (1000 / 3) * link->lanes; + } else { + t1 = (2000 / 9) * link->lanes; + } + break; + case 16: + if (color_format != DRM_COLOR_FORMAT_YCRCB422 && + pixel_mode == DPTX_MP_DUAL_PIXEL) + t1 = (1000 / 6) * link->lanes; + else + t1 = (1000 / 4) * link->lanes; + break; + default: + return -EINVAL; + } + + if (color_format == DRM_COLOR_FORMAT_YCRCB420) + t2 = (link->rate / 4) * 1000 / (mode->Clock / 2); + else + t2 = (link->rate / 4) * 1000 / mode->Clock; + + if (average_bytes_per_tu_frac) + t3 = average_bytes_per_tu + 1; + else + t3 = average_bytes_per_tu; + init_threshold = t1 * t2 * t3 / (1000 * 1000); + if (init_threshold <= 16 || average_bytes_per_tu < 10) + init_threshold = 40; + } + + regmap_write(dp->regmap, DPTX_VIDEO_CONFIG5, + FIELD_PREP(INIT_THRESHOLD_HI, init_threshold >> 6) | + FIELD_PREP(AVERAGE_BYTES_PER_TU_FRAC, + average_bytes_per_tu_frac) | + FIELD_PREP(INIT_THRESHOLD, init_threshold) | + FIELD_PREP(AVERAGE_BYTES_PER_TU, average_bytes_per_tu)); + + /* Configure DPTX_VIDEO_HBLANK_INTERVAL register */ + hblank_interval = hblank * (link->rate / 4) / mode->Clock; + regmap_write(dp->regmap, DPTX_VIDEO_HBLANK_INTERVAL, + FIELD_PREP(HBLANK_INTERVAL_EN, 1) | + FIELD_PREP(HBLANK_INTERVAL, hblank_interval)); + + /* Video stream enable */ + regmap_update_bits(dp->regmap, DPTX_VSAMPLE_CTRL, VIDEO_STREAM_ENABLE, + FIELD_PREP(VIDEO_STREAM_ENABLE, 1)); + + if (link->vsc_sdp_extension_for_colorimetry_supported) + dw_dp_send_vsc_sdp(dp); + + return 0; +} + +static int dw_dp_connector_init(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE *state) +{ + CONNECTOR_STATE *conn_state = &state->ConnectorState; + struct dw_dp *dp = DW_DP_FROM_CONNECTOR_PROTOCOL (conn); + int ret; + + conn_state->OutputInterface |= dp->id ? VOP_OUTPUT_IF_DP1 : VOP_OUTPUT_IF_DP0; + conn_state->OutputMode = ROCKCHIP_OUT_MODE_AAAA; + conn_state->ColorSpace = V4L2_COLORSPACE_DEFAULT; + + reset_assert(&dp->reset); + udelay(20); + reset_deassert(&dp->reset); + + dw_dp_init(dp); + dp->phy->PowerOn (dp->phy); + + return ret; +} + +static int dw_dp_connector_get_edid(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE *state) +{ + return 0; +} + +static int dw_dp_get_output_fmts_index(u32 bus_format) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(possible_output_fmts); i++) { + const struct dw_dp_output_format *fmt = &possible_output_fmts[i]; + + if (fmt->bus_format == bus_format) + break; + } + + if (i == ARRAY_SIZE(possible_output_fmts)) + return 1; + + return i; +} + +static int dw_dp_connector_prepare(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE *state) +{ + CONNECTOR_STATE *conn_state = &state->ConnectorState; + struct dw_dp *dp = DW_DP_FROM_CONNECTOR_PROTOCOL (conn); + struct dw_dp_video *video = &dp->video; + int bus_fmt; + + bus_fmt = dw_dp_get_output_fmts_index(conn_state->BusFormat); + video->video_mapping = possible_output_fmts[bus_fmt].video_mapping; + video->color_format = possible_output_fmts[bus_fmt].color_format; + video->bus_format = possible_output_fmts[bus_fmt].bus_format; + video->bpc = possible_output_fmts[bus_fmt].bpc; + video->bpp = possible_output_fmts[bus_fmt].bpp; + + return 0; +} + +static int dw_dp_connector_enable(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE *state) +{ + CONNECTOR_STATE *conn_state = &state->ConnectorState; + DRM_DISPLAY_MODE *mode = &conn_state->DisplayMode; + struct dw_dp *dp = DW_DP_FROM_CONNECTOR_PROTOCOL (conn); + struct dw_dp_video *video = &dp->video; + int ret; + + memcpy(&video->mode, mode, sizeof(video->mode)); + video->pixel_mode = DPTX_MP_QUAD_PIXEL; + + if (dp->force_output) { + ret = dw_dp_set_phy_default_config(dp); + if (ret < 0) + printf("failed to set phy_default config: %d\n", ret); + } else { + ret = dw_dp_link_enable(dp); + if (ret < 0) { + printf("failed to enable link: %d\n", ret); + return ret; + } + } + + ret = dw_dp_video_enable(dp); + if (ret < 0) { + printf("failed to enable video: %d\n", ret); + return ret; + } + + return 0; +} + +static int dw_dp_connector_disable(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE *state) +{ + /* TODO */ + + return 0; +} + +static int dw_dp_connector_detect(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE *state) +{ + return 0; +} + +static int dw_dp_ddc_init(struct dw_dp *dp) +{ + dp->aux.name = "dw-dp"; + dp->aux.transfer = dw_dp_aux_transfer; + + return 0; +} + +EFI_STATUS +DwDpConnectorPreInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + + ConnectorState->Type = DRM_MODE_CONNECTOR_DisplayPort; + + return 0; +}; + +EFI_STATUS +DwDpConnectorInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + ret = dw_dp_connector_init(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +DwDpConnectorDetect ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + ret = dw_dp_connector_detect(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +DwDpConnectorGetEdid ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + ret = dw_dp_connector_get_edid(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +DwDpConnectorEnable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + /* this should be called by the GOP driver instead */ + dw_dp_connector_prepare (This, DisplayState); + + ret = dw_dp_connector_enable(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +DwDpConnectorDisable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + ret = dw_dp_connector_disable(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +ROCKCHIP_CONNECTOR_PROTOCOL mDpConnectorOps = { + NULL, + DwDpConnectorPreInit, + DwDpConnectorInit, + NULL, + DwDpConnectorDetect, + NULL, + DwDpConnectorGetEdid, + NULL, + DwDpConnectorEnable, + DwDpConnectorDisable, + NULL +}; + +static struct dw_dp mRk3588Dp[] = { + { + .regmap = 0xfde50000, + .reset = { 0xAE0, 8 }, + .id = 0, + }, + { + .regmap = 0xfde60000, + .reset = { 0xAE0, 9 }, + .id = 1, + }, +}; + +STATIC VOID *mDpPhyEventRegistration; + +STATIC +VOID +DpPhyRegistrationEventHandler ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_HANDLE Handle; + UINTN BufferSize; + EFI_STATUS Status; + DP_PHY_PROTOCOL *DpPhy; + struct dw_dp *DwDp; + UINTN Index; + + while (TRUE) { + BufferSize = sizeof (EFI_HANDLE); + Status = gBS->LocateHandle (ByRegisterNotify, + NULL, + mDpPhyEventRegistration, + &BufferSize, + &Handle); + if (EFI_ERROR (Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG ((DEBUG_WARN, "%a: Failed to locate gDpPhyProtocolGuid. Status=%r\n", + __FUNCTION__, Status)); + } + break; + } + + Status = gBS->HandleProtocol (Handle, &gDpPhyProtocolGuid, (VOID **) &DpPhy); + ASSERT_EFI_ERROR (Status); + + for (Index = 0; Index < ARRAY_SIZE (mRk3588Dp); Index++) { + DwDp = &mRk3588Dp[Index]; + if (DwDp->id == DpPhy->Id) { + DwDp->Signature = DW_DP_SIGNATURE; + DwDp->phy = DpPhy; + DwDp->force_output = TRUE; + CopyMem (&DwDp->connector, &mDpConnectorOps, sizeof (ROCKCHIP_CONNECTOR_PROTOCOL)); + dw_dp_ddc_init (DwDp); + + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gRockchipConnectorProtocolGuid, + &DwDp->connector, + NULL + ); + break; + } + } + + ASSERT_EFI_ERROR (Status); + break; + } +} + +EFI_STATUS +EFIAPI +DwDpInitDp ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EfiCreateProtocolNotifyEvent (&gDpPhyProtocolGuid, + TPL_CALLBACK, + DpPhyRegistrationEventHandler, + NULL, + &mDpPhyEventRegistration); + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.inf new file mode 100644 index 0000000..11e3dcf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwDpLib.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Synopsys DesignWare DisplayPort 1.4 TX controller driver +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DwDpLib + FILE_GUID = e495b4c8-4793-429b-a5c5-5e5fd60bf63b + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = DwDpInitDp + +[Sources.common] + DwDpLib.c + drm_dp_helper.c + +[LibraryClasses] + UefiDriverEntryPoint + UefiLib + UefiBootServicesTableLib + TimerLib + DebugLib + IoLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + RockchipDisplayLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[BuildOptions] + +[Pcd] + +[Protocols] + gRockchipConnectorProtocolGuid ## PRODUCES + gDpPhyProtocolGuid ## CONSUMES + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.c new file mode 100644 index 0000000..ee26379 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.c @@ -0,0 +1,768 @@ +/** @file + Rockchip HDMI Driver. + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) + +#define RK3588_GRF_SOC_CON2 0x0308 +#define RK3588_HDMI1_HPD_INT_MSK BIT(15) +#define RK3588_HDMI1_HPD_INT_CLR BIT(14) +#define RK3588_HDMI0_HPD_INT_MSK BIT(13) +#define RK3588_HDMI0_HPD_INT_CLR BIT(12) +#define RK3588_GRF_SOC_CON7 0x031c +#define RK3588_SET_HPD_PATH_MASK (0x3 << 12) +#define RK3588_GRF_SOC_STATUS1 0x0384 +#define RK3588_HDMI0_LOW_MORETHAN100MS BIT(20) +#define RK3588_HDMI0_HPD_PORT_LEVEL BIT(19) +#define RK3588_HDMI0_IHPD_PORT BIT(18) +#define RK3588_HDMI0_OHPD_INT BIT(17) +#define RK3588_HDMI0_LEVEL_INT BIT(16) +#define RK3588_HDMI0_INTR_CHANGE_CNT (0x7 << 13) +#define RK3588_HDMI1_LOW_MORETHAN100MS BIT(28) +#define RK3588_HDMI1_HPD_PORT_LEVEL BIT(27) +#define RK3588_HDMI1_IHPD_PORT BIT(26) +#define RK3588_HDMI1_OHPD_INT BIT(25) +#define RK3588_HDMI1_LEVEL_INT BIT(24) +#define RK3588_HDMI1_INTR_CHANGE_CNT (0x7 << 21) + +#define RK3588_GRF_VO1_CON3 0x000c +#define RK3588_COLOR_FORMAT_MASK 0xf +#define RK3588_YUV444 0x2 +#define RK3588_YUV420 0x3 +#define RK3588_COMPRESSED_DATA 0xb +#define RK3588_COLOR_DEPTH_MASK (0xf << 4) +#define RK3588_8BPC 0 +#define RK3588_10BPC (0x6 << 4) +#define RK3588_CECIN_MASK BIT(8) +#define RK3588_SCLIN_MASK BIT(9) +#define RK3588_SDAIN_MASK BIT(10) +#define RK3588_MODE_MASK BIT(11) +#define RK3588_COMPRESS_MODE_MASK BIT(12) +#define RK3588_I2S_SEL_MASK BIT(13) +#define RK3588_SPDIF_SEL_MASK BIT(14) +#define RK3588_GRF_VO1_CON4 0x0010 +#define RK3588_HDMI21_MASK BIT(0) +#define RK3588_GRF_VO1_CON9 0x0024 +#define RK3588_HDMI0_GRANT_SEL BIT(10) +#define RK3588_HDMI0_GRANT_SW BIT(11) +#define RK3588_HDMI1_GRANT_SEL BIT(12) +#define RK3588_HDMI1_GRANT_SW BIT(13) +#define RK3588_GRF_VO1_CON6 0x0018 +#define RK3588_GRF_VO1_CON7 0x001c + +#define PPS_TABLE_LEN 8 + +#define COLOR_DEPTH_10BIT BIT(31) +#define HDMI_FRL_MODE BIT(30) +#define HDMI_EARC_MODE BIT(29) +#define DATA_RATE_MASK 0xFFFFFFF + +#define HDMI20_MAX_RATE 600000 +#define HDMI_8K60_RATE 2376000 + +#define DDC_CI_ADDR 0x37 +#define DDC_SEGMENT_ADDR 0x30 + +#define HDMI_EDID_LEN 512 +#define HDMI_EDID_BLOCK_LEN 128 + +#define DDC_ADDR 0x50 + +VOID +DwHdmiQpRegWrite ( + OUT struct DwHdmiQpDevice *Hdmi, + IN UINT32 Value, + IN UINT32 Offset + ) +{ + UINT32 BASE; + + if (!Hdmi->Id) + BASE = HDMI0_BASE; + else + BASE = HDMI1_BASE; + + MmioWrite32(BASE + Offset, Value); +}; + +UINT32 +DwHdmiQpRegRead ( + OUT struct DwHdmiQpDevice *Hdmi, + IN UINT32 Offset + ) +{ + UINT32 Value; + UINT32 BASE; + + if (!Hdmi->Id) + BASE = HDMI0_BASE; + else + BASE = HDMI1_BASE; + + Value = MmioRead32(BASE + Offset); + return Value; +}; + +VOID +DwHdmiQpRegMod ( + OUT struct DwHdmiQpDevice *Hdmi, + IN UINT32 Value, + IN UINT32 Mask, + IN UINT32 Offset + ) +{ + UINT32 Val; + UINT32 BASE; + + if (!Hdmi->Id) + BASE = HDMI0_BASE; + else + BASE = HDMI1_BASE; + + Val = MmioRead32(BASE + Offset); + Val &= ~Mask; + Val |= Value; + + MmioWrite32(BASE + Offset, Val); +}; + +VOID +DwHdmiQpSetIomux( + OUT struct DwHdmiQpDevice *Hdmi + ) +{ + UINT32 Val; + + if (!Hdmi->Id) { + Val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + MmioWrite32(0xFD5A8000 + RK3588_GRF_VO1_CON3, Val); + + Val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + MmioWrite32(0xFD58C000 + RK3588_GRF_SOC_CON7, Val); + + Val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL, + RK3588_HDMI0_GRANT_SEL); + MmioWrite32(0xFD5A8000 + RK3588_GRF_VO1_CON9, Val); + } else { + Val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) | + HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) | + HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) | + HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK); + MmioWrite32(0xFD5A8000 + RK3588_GRF_VO1_CON6, Val); + + Val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK, + RK3588_SET_HPD_PATH_MASK); + MmioWrite32(0xFD58C000 + RK3588_GRF_SOC_CON7, Val); + + Val = HIWORD_UPDATE(RK3588_HDMI1_GRANT_SEL, + RK3588_HDMI1_GRANT_SEL); + MmioWrite32(0xFD5A8000 + RK3588_GRF_VO1_CON9, Val); + } +}; + +STATIC +BOOLEAN +DwHdmiI2cPollForIrq( + OUT struct DwHdmiQpDevice *Hdmi +) +{ + struct DwHdmiQpI2c *I2c = &Hdmi->I2c; + UINT32 Stat; + + Stat = DwHdmiQpRegRead(Hdmi, MAINUNIT_1_INT_STATUS); + I2c->Stat = Stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | + I2CM_NACK_RCVD_IRQ); + Hdmi->ScdcIntr = Stat& (SCDC_UPD_FLAGS_RD_IRQ | + SCDC_UPD_FLAGS_CHG_IRQ | + SCDC_UPD_FLAGS_CLR_IRQ | + SCDC_RR_REPLY_STOP_IRQ | + SCDC_NACK_RCVD_IRQ); + + Hdmi->FltIntr = Stat & (FLT_EXIT_TO_LTSP_IRQ | + FLT_EXIT_TO_LTS4_IRQ | + FLT_EXIT_TO_LTSL_IRQ); + + DEBUG((DEBUG_VERBOSE, "i2c main unit irq:%02x\n", Stat)); + if (I2c->Stat) { + DwHdmiQpRegWrite(Hdmi, I2c->Stat, MAINUNIT_1_INT_CLEAR); + I2c->Cmp = TRUE; + } + + if (Hdmi->FltIntr) { + DEBUG((DEBUG_VERBOSE, "i2c flt irq:%02x\n", Hdmi->FltIntr)); + DwHdmiQpRegWrite(Hdmi, Hdmi->FltIntr, MAINUNIT_1_INT_CLEAR); + Hdmi->FltCmp = TRUE; + } + + if (Hdmi->ScdcIntr) { + UINT8 val; + + DEBUG((DEBUG_VERBOSE, "i2c scdc irq:%02x\n", Hdmi->ScdcIntr)); + DwHdmiQpRegWrite(Hdmi, Hdmi->ScdcIntr, MAINUNIT_1_INT_CLEAR); + val = DwHdmiQpRegRead(Hdmi, SCDC_STATUS0); + + /* frl start */ + if (val & BIT(4)) { + DwHdmiQpRegMod(Hdmi, 0, SCDC_UPD_FLAGS_POLL_EN | + SCDC_UPD_FLAGS_AUTO_CLR, SCDC_CONFIG0); + DwHdmiQpRegMod(Hdmi, 0, SCDC_UPD_FLAGS_RD_IRQ, + MAINUNIT_1_INT_MASK_N); + DEBUG((DEBUG_VERBOSE, "frl start\n")); + } + } + + if (Stat) + return TRUE; + + return FALSE; +} + +STATIC +EFI_STATUS +DwHdmiI2cRead( + IN struct DwHdmiQpDevice *Hdmi, + UINT8 *Buf, + UINTN Length +) +{ + EFI_STATUS Status = EFI_SUCCESS; + struct DwHdmiQpI2c *I2c = &Hdmi->I2c; + + if (!I2c->IsRegAddr) { + DEBUG((DEBUG_INFO, "Set read register address to 0\n")); + I2c->SlaveReg = 0x0; + I2c->IsRegAddr = TRUE; + } + + while (Length--) { + I2c->Cmp = FALSE; + DwHdmiQpRegMod(Hdmi, I2c->SlaveReg++ << 12, I2CM_ADDR, I2CM_INTERFACE_CONTROL0); + if (I2c->IsSegment) + DwHdmiQpRegMod(Hdmi, I2CM_EXT_READ, I2CM_WR_MASK, + I2CM_INTERFACE_CONTROL0); + else + DwHdmiQpRegMod(Hdmi, I2CM_FM_READ, I2CM_WR_MASK, + I2CM_INTERFACE_CONTROL0); + + // Wait for transfer done here + int timeout = 10 * 1000; + int interval = 100; + BOOLEAN ret; + while (timeout) { + ret = DwHdmiI2cPollForIrq(Hdmi); + if (I2c->Cmp) + break; + + timeout -= interval; + MicroSecondDelay(interval); + } + + if (!timeout && !ret) { + DEBUG((DEBUG_ERROR, "HDMI I2C read time out!\n")); + DwHdmiQpRegWrite(Hdmi, 0x01, I2CM_CONTROL0); + Status = EFI_TIMEOUT; + goto exit; + } + + if (I2c->Stat & I2CM_NACK_RCVD_IRQ) { + DEBUG((DEBUG_ERROR, "HDMI I2C read error\n")); + DwHdmiQpRegWrite(Hdmi, 0x01, I2CM_CONTROL0); + Status = EFI_DEVICE_ERROR; + goto exit; + } + + MicroSecondDelay(500); + + *Buf = DwHdmiQpRegRead(Hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; + Buf++; + DEBUG((DEBUG_VERBOSE, "i2c read succeed I2c->Stat = %02x 0x%02x RegAddr=%02x\n", I2c->Stat, + DwHdmiQpRegRead(Hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff, + I2c->SlaveReg-1)); + + DwHdmiQpRegMod(Hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); + } + I2c->IsSegment = FALSE; + +exit: + return Status; +} + +STATIC +EFI_STATUS +DwHdmiI2cWrite( + IN struct DwHdmiQpDevice *Hdmi, + UINT8 *Buf, + UINTN Length +) +{ + EFI_STATUS Status = EFI_SUCCESS; + struct DwHdmiQpI2c *I2c = &Hdmi->I2c; + + if (!I2c->IsRegAddr) { + I2c->SlaveReg = Buf[0]; + Length--; + Buf++; + I2c->IsRegAddr = TRUE; + } + + while (Length--) { + I2c->Cmp = FALSE; + DwHdmiQpRegWrite(Hdmi, *Buf, I2CM_INTERFACE_WRDATA_0_3); + Buf++; + DwHdmiQpRegMod(Hdmi, I2c->SlaveReg++ << 12, I2CM_ADDR, I2CM_INTERFACE_CONTROL0); + DwHdmiQpRegMod(Hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, + I2CM_INTERFACE_CONTROL0); + + // Wait for transfer done here + int timeout = 10 * 1000; + int interval = 100; + BOOLEAN ret; + while (timeout) { + ret = DwHdmiI2cPollForIrq(Hdmi); + if (I2c->Cmp) + break; + + timeout -= interval; + MicroSecondDelay(interval); + } + + if (!timeout && !ret) { + DEBUG((DEBUG_ERROR, "HDMI I2C write time out!\n")); + DwHdmiQpRegWrite(Hdmi, 0x01, I2CM_CONTROL0); + Status = EFI_TIMEOUT; + goto exit; + } + + /* Check for error condition on the bus */ + if (I2c->Stat & I2CM_NACK_RCVD_IRQ) { + DEBUG((DEBUG_ERROR, "HDMI I2C write nack!\n")); + DwHdmiQpRegWrite(Hdmi, 0x01, I2CM_CONTROL0); + Status = EFI_DEVICE_ERROR; + goto exit; + } + + DwHdmiQpRegMod(Hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); + } + + DEBUG((DEBUG_VERBOSE, "HDMI I2C write done! I2c->Stat = %02x\n", I2c->Stat)); + +exit: + return Status; +} + +STATIC +EFI_STATUS +DwHdmiQpI2cXfer( + IN struct DwHdmiQpDevice *Hdmi, + IN struct i2c_msg *Msgs, + IN INTN Num +) +{ + EFI_STATUS Status = EFI_SUCCESS; + struct DwHdmiQpI2c *I2c = &Hdmi->I2c; + UINT8 Addr = Msgs[0].addr; + + if (Addr == DDC_CI_ADDR) + /* + * The internal I2C controller does not support the multi-byte + * read and write operations needed for DDC/CI. + * TOFIX: Blacklist the DDC/CI address until we filter out + * unsupported I2C operations. + */ + return EFI_UNSUPPORTED; + + DEBUG((DEBUG_VERBOSE, "HDMI I2C xfer: Num: %d, Addr: %02x\n", + Num, Addr)); + + for (int i = 0; i < Num; i++) { + if (Msgs[i].len == 0) { + DEBUG((DEBUG_ERROR, "Unsupported transfer %d/%d, no data\n", + i + 1, Num)); + return EFI_UNSUPPORTED; + } + } + + /* Unmute DONE and ERROR interrupts */ + DwHdmiQpRegMod(Hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, + I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, + MAINUNIT_1_INT_MASK_N); + + if (Addr == DDC_SEGMENT_ADDR && Msgs[0].len == 1) + Addr = DDC_ADDR; + + DwHdmiQpRegMod(Hdmi, Addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); + + /* Set slave device register address on transfer */ + I2c->IsRegAddr = FALSE; + + /* Set segment pointer for I2C extended read mode operation */ + I2c->IsSegment = FALSE; + + for (int i = 0; i < Num; i++) { + DEBUG((DEBUG_VERBOSE, "xfer: num: %d/%d, len: %d, flags: %x\n", + i + 1, Num, Msgs[i].len, Msgs[i].flags)); + + if (Msgs[i].addr == DDC_SEGMENT_ADDR && Msgs[i].len == 1) { + I2c->IsSegment = TRUE; + DwHdmiQpRegMod(Hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, + I2CM_INTERFACE_CONTROL1); + DwHdmiQpRegMod(Hdmi, *Msgs[i].buf << 7, I2CM_SEG_PTR, + I2CM_INTERFACE_CONTROL1); + } else { + if (Msgs[i].flags & I2C_M_RD) + Status = DwHdmiI2cRead(Hdmi, Msgs[i].buf, Msgs[i].len); + else + Status = DwHdmiI2cWrite(Hdmi, Msgs[i].buf, Msgs[i].len); + } + + if (Status) + break; + } + + if (Status) + return Status; + + /* Mute DONE and ERROR interrupts */ + DwHdmiQpRegMod(Hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, + MAINUNIT_1_INT_MASK_N); + + return Status; +} + +STATIC +VOID +DwHdmiI2cInit( + OUT struct DwHdmiQpDevice *Hdmi +) +{ + UINT32 BaseAddr; + if (Hdmi->Id) + BaseAddr = HDMI1_BASE; + else + BaseAddr = HDMI0_BASE; + + /* Software reset */ + DwHdmiQpRegWrite(Hdmi, 0x01, I2CM_CONTROL0); + + DwHdmiQpRegMod(Hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); + + /* Clear DONE and ERROR interrupts */ + DwHdmiQpRegWrite(Hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, + MAINUNIT_1_INT_CLEAR); +} + +STATIC +VOID +DumpEdid(IN struct DwHdmiQpDevice *Hdmi) +{ + DEBUG((DEBUG_INIT, "DwHdmiQpLib.c: Dumping EDID: \n")); + UINT8 EDID[EDID_SIZE]; + UINT8 BaseAddr = 0x0; + struct i2c_msg msgs[] = { + { + .addr = DDC_ADDR, + .flags = 0, + .len = 1, + .buf = &BaseAddr, + }, { + .addr = DDC_ADDR, + .flags = I2C_M_RD, + .len = EDID_SIZE, + .buf = EDID, + } + }; + if(DwHdmiQpI2cXfer(Hdmi, msgs, 2)) { + return; + } + for (int i = 0; i < EDID_SIZE; i++) { + DEBUG((DEBUG_INIT, "%02x ", EDID[i])); + if (!((i + 1) % 8)) + DEBUG((DEBUG_INIT, "\n")); + } +} + +VOID +DwHdmiQpI2cSetIomux( + OUT struct DwHdmiQpDevice *Hdmi + ) +{ + if (!Hdmi->Id) { + switch (Hdmi->I2c.PinMux) { + case 0: + GpioPinSetFunction(4, GPIO_PIN_PB7, 0x5); + GpioPinSetFunction(4, GPIO_PIN_PC0, 0x5); + break; + case 1: + GpioPinSetFunction(0, GPIO_PIN_PD5, 0xb); + GpioPinSetFunction(0, GPIO_PIN_PD4, 0xb); + break; + case 2: + GpioPinSetFunction(3, GPIO_PIN_PC7, 0x5); + GpioPinSetFunction(3, GPIO_PIN_PD0, 0x5); + break; + default: + break; + } + } else { + switch (Hdmi->I2c.PinMux) { + case 0: + GpioPinSetFunction(2, GPIO_PIN_PB4, 0x4); + GpioPinSetFunction(2, GPIO_PIN_PB5, 0x4); + break; + case 1: + GpioPinSetFunction(3, GPIO_PIN_PC5, 0x5); + GpioPinSetFunction(3, GPIO_PIN_PC6, 0x5); + break; + case 2: + GpioPinSetFunction(1, GPIO_PIN_PA3, 0x5); + GpioPinSetFunction(1, GPIO_PIN_PA4, 0x5); + break; + default: + break; + } + } +}; + +EFI_STATUS +DwHdmiQpConnectorPreInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + struct RockchipHdptxPhyHdmi Hdptx; + struct DwHdmiQpDevice *Hdmi; + Hdmi = AllocateZeroPool(sizeof (*Hdmi)); + + DEBUG ((DEBUG_INIT, "DwHdmiQpConnectorPreInit")); + ConnectorState->Type = DRM_MODE_CONNECTOR_HDMIA; + Hdmi->Id = Hdptx.Id = PcdGet32(PcdHdmiId); + Hdmi->I2c.PinMux = PcdGet32(PcdHdmiDDCI2CPinMux); + + if (Hdmi->Id) + ConnectorState->OutputInterface = VOP_OUTPUT_IF_HDMI1; + else + ConnectorState->OutputInterface = VOP_OUTPUT_IF_HDMI0; + + DwHdmiQpSetIomux(Hdmi); + DwHdmiQpI2cSetIomux(Hdmi); + DwHdmiI2cInit(Hdmi); + + HdptxRopllCmnConfig(&Hdptx); + DEBUG ((DEBUG_INFO, "%a hdmi pre init success\n", __func__)); + return 0; +}; + +EFI_STATUS +DwHdmiQpConnectorInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + + DEBUG ((DEBUG_INIT, "DwHdmiQpConnectorInit")); + ConnectorState->OutputMode = ROCKCHIP_OUT_MODE_AAAA; + ConnectorState->ColorSpace = V4L2_COLORSPACE_DEFAULT; + + return 0; +}; + +EFI_STATUS +DwHdmiQpConnectorGetEdid ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + //Todo + return 0; +}; + +VOID +Rk3588SetColorFormat( + OUT struct DwHdmiQpDevice *Hdmi, + IN UINT64 BusFormat, + IN UINT32 Depth + ) +{ + UINT32 Val = 0; + + switch (BusFormat) { + case MEDIA_BUS_FMT_RGB888_1X24: + case MEDIA_BUS_FMT_RGB101010_1X30: + Val = HIWORD_UPDATE(0, RK3588_COLOR_FORMAT_MASK); + break; + case MEDIA_BUS_FMT_UYYVYY8_0_5X24: + case MEDIA_BUS_FMT_UYYVYY10_0_5X30: + Val = HIWORD_UPDATE(RK3588_YUV420, RK3588_COLOR_FORMAT_MASK); + break; + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_YUV10_1X30: + Val = HIWORD_UPDATE(RK3588_YUV444, RK3588_COLOR_FORMAT_MASK); + break; + default: + DEBUG ((DEBUG_INFO, "%a can't set correct color format\n", __func__)); + return; + } + + if (Depth == 8) + Val |= HIWORD_UPDATE(RK3588_8BPC, RK3588_COLOR_DEPTH_MASK); + else + Val |= HIWORD_UPDATE(RK3588_10BPC, RK3588_COLOR_DEPTH_MASK); + + if (!Hdmi->Id) + MmioWrite32(0xFD5A8000 + RK3588_GRF_VO1_CON3, Val); + else + MmioWrite32(0xFD5A8000 + RK3588_GRF_VO1_CON6, Val); +} + +VOID +HdmiConfigAvi( + OUT struct DwHdmiQpDevice *Hdmi + ) +{ + /* 1080p60 */ + DwHdmiQpRegWrite(Hdmi, 0x000d0200, PKT_AVI_CONTENTS0); + DwHdmiQpRegWrite(Hdmi, 0x00281027, PKT_AVI_CONTENTS1); + DwHdmiQpRegWrite(Hdmi, 0x00000010, PKT_AVI_CONTENTS2); + DwHdmiQpRegWrite(Hdmi, 0x00000000, PKT_AVI_CONTENTS3); + DwHdmiQpRegWrite(Hdmi, 0x00000000, PKT_AVI_CONTENTS4); + DwHdmiQpRegWrite(Hdmi, 0x00000000, PKT_AVI_CONTENTS5); + DwHdmiQpRegWrite(Hdmi, 0x00000000, PKT_AVI_CONTENTS6); + DwHdmiQpRegWrite(Hdmi, 0x00000000, PKT_AVI_CONTENTS7); +}; + +VOID +DwHdmiQpSetup( + OUT struct DwHdmiQpDevice *Hdmi, + OUT DISPLAY_STATE *DisplayState + ) +{ + struct RockchipHdptxPhyHdmi Hdptx; + CONNECTOR_STATE *ConnectorState = &DisplayState->ConnectorState; + UINT32 Val = 0; + + ConnectorState->Type = DRM_MODE_CONNECTOR_HDMIA; + Hdptx.Id = PcdGet32(PcdHdmiId); + + Val = DwHdmiQpRegRead(Hdmi, 0xb0); + DEBUG ((DEBUG_INIT, "%a Hdptx.Id :%d\n", __func__, Hdptx.Id)); + DEBUG ((DEBUG_INIT, "%a 0xb0:%d\n", __func__, Val)); + Rk3588SetColorFormat(Hdmi, MEDIA_BUS_FMT_RGB888_1X24, 8); + HdmiConfigAvi(Hdmi); + + DwHdmiQpRegMod(Hdmi, 0, OPMODE_DVI, LINK_CONFIG0); + DwHdmiQpRegMod(Hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); + DwHdmiQpRegMod(Hdmi, KEEPOUT_REKEY_ALWAYS, KEEPOUT_REKEY_CFG, FRAME_COMPOSER_CONFIG9); + DwHdmiQpRegWrite(Hdmi, 0, FLT_CONFIG0); + + DumpEdid(Hdmi); + + //enable phy output + HdptxRopllTmdsModeConfig(&Hdptx); + MicroSecondDelay(50); + DwHdmiQpRegWrite(Hdmi, 2, PKTSCHED_PKT_CONTROL0); + DwHdmiQpRegMod(Hdmi, PKTSCHED_GCP_TX_EN, PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN); +}; + +EFI_STATUS +DwHdmiQpConnectorEnable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + struct DwHdmiQpDevice *Hdmi; + Hdmi = AllocatePool(sizeof (*Hdmi)); + DEBUG ((DEBUG_INIT, "DwHdmiQpConnectorEnable\n")); + Hdmi->Id = PcdGet32(PcdHdmiId); + + DwHdmiQpSetup(Hdmi, DisplayState); + + return 0; +}; + +EFI_STATUS +DwHdmiQpConnectorDisable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + //Todo + return 0; +}; + +EFI_STATUS +DwHdmiQpConnectorDetect ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + //Todo + return 0; +}; + +ROCKCHIP_CONNECTOR_PROTOCOL mHdmi = { + NULL, + DwHdmiQpConnectorPreInit, + DwHdmiQpConnectorInit, + NULL, + DwHdmiQpConnectorDetect, + NULL, + DwHdmiQpConnectorGetEdid, + NULL, + DwHdmiQpConnectorEnable, + DwHdmiQpConnectorDisable, + NULL +}; + +EFI_STATUS +EFIAPI +DwHdmiQpInitHdmi ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + DEBUG ((DEBUG_INIT, "hdmi init start\n")); + Handle = NULL; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gRockchipConnectorProtocolGuid, + &mHdmi, + NULL + ); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INIT, "hdmi init success\n")); + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf new file mode 100644 index 0000000..c737a08 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf @@ -0,0 +1,63 @@ +#/** @file +# +# Component description file for dw-hdmi-qp module +# +# Copyright (c) 2017, Rockchip Inc. All rights reserved.
    +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DwHdmiQpLib + FILE_GUID = e4000dd0-b732-11ed-887a-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = DwHdmiQpInitHdmi + +[Sources.common] + DwHdmiQpLib.c + PhyRockchipSamsungHdptxHdmi.c + +[LibraryClasses] + TimerLib + DebugLib + IoLib + BaseLib + BaseMemoryLib + RockchipDisplayLib + MemoryAllocationLib + PWMLib + RockchipPlatformLib + UefiLib + UefiDriverEntryPoint + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[BuildOptions] + +[Pcd] + gRockchipTokenSpaceGuid.PcdLcdPixelFormat + gRockchipTokenSpaceGuid.PcdHdmiId + gRockchipTokenSpaceGuid.PcdHdmiDDCI2CPinMux + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution + +[Protocols] + gRockchipConnectorProtocolGuid + +[Depex] + TRUE + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.c new file mode 100644 index 0000000..e8c90a0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.c @@ -0,0 +1,1623 @@ +/** @file + * + * Synopsys DesignWare MIPI DSI2 controller driver + * + * This was ported from U-Boot downstream. + * + * After all features are merged in and tested, the code should ideally + * be refactored to meet EDK II conventions. + * + * U-Boot file: drivers/video/drm/dw_mipi_dsi2.c + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + * Copyright (c) 2023-2024, Mario Bălănică + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code can be relicensed as BSD-2-Clause-Patent if permission + * is granted by the original authors. + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "rockchip_phy.h" + +#define UPDATE(v, h, l) (((v) << (l)) & GENMASK((h), (l))) + +#define DSI2_PWR_UP 0x000c +#define RESET 0 +#define POWER_UP BIT(0) +#define CMD_TX_MODE(x) UPDATE(x, 24, 24) +#define DSI2_SOFT_RESET 0x0010 +#define SYS_RSTN BIT(2) +#define PHY_RSTN BIT(1) +#define IPI_RSTN BIT(0) +#define INT_ST_MAIN 0x0014 +#define DSI2_MODE_CTRL 0x0018 +#define DSI2_MODE_STATUS 0x001c +#define DSI2_CORE_STATUS 0x0020 +#define PRI_RD_DATA_AVAIL BIT(26) +#define PRI_FIFOS_NOT_EMPTY BIT(25) +#define PRI_BUSY BIT(24) +#define CRI_RD_DATA_AVAIL BIT(18) +#define CRT_FIFOS_NOT_EMPTY BIT(17) +#define CRI_BUSY BIT(16) +#define IPI_FIFOS_NOT_EMPTY BIT(9) +#define IPI_BUSY BIT(8) +#define CORE_FIFOS_NOT_EMPTY BIT(1) +#define CORE_BUSY BIT(0) +#define MANUAL_MODE_CFG 0x0024 +#define MANUAL_MODE_EN BIT(0) +#define DSI2_TIMEOUT_HSTX_CFG 0x0048 +#define TO_HSTX(x) UPDATE(x, 15, 0) +#define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c +#define TO_HSTXRDY(x) UPDATE(x, 15, 0) +#define DSI2_TIMEOUT_LPRX_CFG 0x0050 +#define TO_LPRXRDY(x) UPDATE(x, 15, 0) +#define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 +#define TO_LPTXRDY(x) UPDATE(x, 15, 0) +#define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 +#define TO_LPTXTRIG(x) UPDATE(x, 15, 0) +#define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c +#define TO_LPTXULPS(x) UPDATE(x, 15, 0) +#define DSI2_TIMEOUT_BTA_CFG 0x60 +#define TO_BTA(x) UPDATE(x, 15, 0) + +#define DSI2_PHY_MODE_CFG 0x0100 +#define PPI_WIDTH(x) UPDATE(x, 9, 8) +#define PHY_LANES(x) UPDATE(x - 1, 5, 4) +#define PHY_TYPE(x) UPDATE(x, 0, 0) +#define DSI2_PHY_CLK_CFG 0X0104 +#define PHY_LPTX_CLK_DIV(x) UPDATE(x, 12, 8) +#define NON_CONTINUOUS_CLK BIT(0) +#define DSI2_PHY_LP2HS_MAN_CFG 0x010c +#define PHY_LP2HS_TIME(x) UPDATE(x, 28, 0) +#define DSI2_PHY_HS2LP_MAN_CFG 0x0114 +#define PHY_HS2LP_TIME(x) UPDATE(x, 28, 0) +#define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c +#define PHY_MAX_RD_TIME(x) UPDATE(x, 26, 0) +#define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 +#define PHY_ESC_CMD_TIME(x) UPDATE(x, 28, 0) +#define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c +#define PHY_ESC_BYTE_TIME(x) UPDATE(x, 28, 0) + +#define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 +#define PHY_IPI_RATIO(x) UPDATE(x, 21, 0) +#define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C +#define PHY_SYS_RATIO(x) UPDATE(x, 16, 0) + +#define DSI2_DSI_GENERAL_CFG 0x0200 +#define BTA_EN BIT(1) +#define EOTP_TX_EN BIT(0) +#define DSI2_DSI_VCID_CFG 0x0204 +#define TX_VCID(x) UPDATE(x, 1, 0) +#define DSI2_DSI_SCRAMBLING_CFG 0x0208 +#define SCRAMBLING_SEED(x) UPDATE(x, 31, 16) +#define SCRAMBLING_EN BIT(0) +#define DSI2_DSI_VID_TX_CFG 0x020c +#define LPDT_DISPLAY_CMD_EN BIT(20) +#define BLK_VFP_HS_EN BIT(14) +#define BLK_VBP_HS_EN BIT(13) +#define BLK_VSA_HS_EN BIT(12) +#define BLK_HFP_HS_EN BIT(6) +#define BLK_HBP_HS_EN BIT(5) +#define BLK_HSA_HS_EN BIT(4) +#define VID_MODE_TYPE(x) UPDATE(x, 1, 0) +#define DSI2_CRI_TX_HDR 0x02c0 +#define CMD_TX_MODE(x) UPDATE(x, 24, 24) +#define DSI2_CRI_TX_PLD 0x02c4 +#define DSI2_CRI_RX_HDR 0x02c8 +#define DSI2_CRI_RX_PLD 0x02cc + +#define DSI2_IPI_COLOR_MAN_CFG 0x0300 +#define IPI_DEPTH(x) UPDATE(x, 7, 4) +#define IPI_DEPTH_5_6_5_BITS 0x02 +#define IPI_DEPTH_6_BITS 0x03 +#define IPI_DEPTH_8_BITS 0x05 +#define IPI_DEPTH_10_BITS 0x06 +#define IPI_FORMAT(x) UPDATE(x, 3, 0) +#define IPI_FORMAT_RGB 0x0 +#define IPI_FORMAT_DSC 0x0b +#define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 +#define VID_HSA_TIME(x) UPDATE(x, 29, 0) +#define DSI2_IPI_VID_HBP_MAN_CFG 0x030c +#define VID_HBP_TIME(x) UPDATE(x, 29, 0) +#define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 +#define VID_HACT_TIME(x) UPDATE(x, 29, 0) +#define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c +#define VID_HLINE_TIME(x) UPDATE(x, 29, 0) +#define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 +#define VID_VSA_LINES(x) UPDATE(x, 9, 0) +#define DSI2_IPI_VID_VBP_MAN_CFG 0X032C +#define VID_VBP_LINES(x) UPDATE(x, 9, 0) +#define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 +#define VID_VACT_LINES(x) UPDATE(x, 13, 0) +#define DSI2_IPI_VID_VFP_MAN_CFG 0X033C +#define VID_VFP_LINES(x) UPDATE(x, 9, 0) +#define DSI2_IPI_PIX_PKT_CFG 0x0344 +#define MAX_PIX_PKT(x) UPDATE(x, 15, 0) + +#define DSI2_INT_ST_PHY 0x0400 +#define DSI2_INT_MASK_PHY 0x0404 +#define DSI2_INT_ST_TO 0x0410 +#define DSI2_INT_MASK_TO 0x0414 +#define DSI2_INT_ST_ACK 0x0420 +#define DSI2_INT_MASK_ACK 0x0424 +#define DSI2_INT_ST_IPI 0x0430 +#define DSI2_INT_MASK_IPI 0x0434 +#define DSI2_INT_ST_FIFO 0x0440 +#define DSI2_INT_MASK_FIFO 0x0444 +#define DSI2_INT_ST_PRI 0x0450 +#define DSI2_INT_MASK_PRI 0x0454 +#define DSI2_INT_ST_CRI 0x0460 +#define DSI2_INT_MASK_CRI 0x0464 +#define DSI2_INT_FORCE_CRI 0x0468 +#define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI + +#define CMD_PKT_STATUS_TIMEOUT_US 1000 +#define MODE_STATUS_TIMEOUT_US 20000 +#define SYS_CLK 351000000LL +#define PSEC_PER_SEC 1000000000000LL +#define USEC_PER_SEC 1000000L +#define MSEC_PER_SEC 1000L + +#define GRF_REG_FIELD(reg, lsb, msb) (((reg) << 16) | ((lsb) << 8) | (msb)) + +enum vid_mode_type { + VID_MODE_TYPE_NON_BURST_SYNC_PULSES, + VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, + VID_MODE_TYPE_BURST, +}; + +enum mode_ctrl { + IDLE_MODE, + AUTOCALC_MODE, + COMMAND_MODE, + VIDEO_MODE, + DATA_STREAM_MODE, + VIDE_TEST_MODE, + DATA_STREAM_TEST_MODE, +}; + +enum grf_reg_fields { + TXREQCLKHS_EN, + GATING_EN, + IPI_SHUTDN, + IPI_COLORM, + IPI_COLOR_DEPTH, + IPI_FORMAT, + MAX_FIELDS, +}; + +enum phy_type { + DPHY, + CPHY, +}; + +enum ppi_width { + PPI_WIDTH_8_BITS, + PPI_WIDTH_16_BITS, + PPI_WIDTH_32_BITS, +}; + +#pragma pack(1) +struct rockchip_cmd_header { + u8 data_type; + u8 delay_ms; + u8 payload_length; +}; +#pragma pack() + +struct rockchip_cmd_desc { + struct rockchip_cmd_header header; + const u8 *payload; +}; + +struct rockchip_panel_cmds { + struct rockchip_cmd_desc *cmds; + int cmd_cnt; +}; + +struct dw_mipi_dsi2_plat_data { + const u32 *dsi0_grf_reg_fields; + const u32 *dsi1_grf_reg_fields; + unsigned long long dphy_max_bit_rate_per_lane; + unsigned long long cphy_max_symbol_rate_per_lane; +}; + +struct mipi_dcphy { + /* Non-SNPS PHY */ + struct rockchip_phy *phy; + + u16 input_div; + u16 feedback_div; +}; + +/** + * struct mipi_dphy_configure - MIPI D-PHY configuration set + * + * This structure is used to represent the configuration state of a + * MIPI D-PHY phy. + */ +struct mipi_dphy_configure { + unsigned int clk_miss; + unsigned int clk_post; + unsigned int clk_pre; + unsigned int clk_prepare; + unsigned int clk_settle; + unsigned int clk_term_en; + unsigned int clk_trail; + unsigned int clk_zero; + unsigned int d_term_en; + unsigned int eot; + unsigned int hs_exit; + unsigned int hs_prepare; + unsigned int hs_settle; + unsigned int hs_skip; + unsigned int hs_trail; + unsigned int hs_zero; + unsigned int init; + unsigned int lpx; + unsigned int ta_get; + unsigned int ta_go; + unsigned int ta_sure; + unsigned int wakeup; + unsigned long hs_clk_rate; + unsigned long lp_clk_rate; + unsigned char lanes; +}; + +struct dw_mipi_dsi2 { + UINT32 Signature; + ROCKCHIP_CONNECTOR_PROTOCOL connector; + UINTN base; + UINTN grf; + int id; + struct dw_mipi_dsi2 *master; + struct dw_mipi_dsi2 *slave; + bool prepared; + + bool auto_calc_mode; + bool c_option; + bool dsc_enable; + bool scrambling_en; + unsigned int slice_width; + unsigned int slice_height; + u32 version_major; + u32 version_minor; + + unsigned int lane_hs_rate; /* Kbps/Ksps per lane */ + u32 channel; + u32 lanes; + u32 format; + u32 mode_flags; + u64 mipi_pixel_rate; + struct mipi_dcphy dcphy; + DRM_DISPLAY_MODE mode; + bool data_swap; + + struct mipi_dsi_host host; + struct mipi_dsi_device *device; + struct mipi_dphy_configure mipi_dphy_cfg; + const struct dw_mipi_dsi2_plat_data *pdata; + struct drm_dsc_picture_parameter_set *pps; + + ROCKCHIP_DSI_PANEL_PROTOCOL *RockchipDsiPanel; +}; + +#define DW_MIPI_DSI2_SIGNATURE SIGNATURE_32 ('D', 'W', 'd', '2') + +#define DW_MIPI_DSI2_FROM_CONNECTOR_PROTOCOL(a) \ + CR (a, struct dw_mipi_dsi2, connector, DW_MIPI_DSI2_SIGNATURE) + +#define DW_MIPI_DSI2_FROM_MIPI_DSI_HOST(a) \ + CR (a, struct dw_mipi_dsi2, host, DW_MIPI_DSI2_SIGNATURE) + +static int rockchip_panel_parse_cmds(const u8 *data, int length, + struct rockchip_panel_cmds *pcmds) +{ + int len; + const u8 *buf; + const struct rockchip_cmd_header *header; + int i, cnt = 0; + + /* scan commands */ + cnt = 0; + buf = data; + len = length; + while (len > sizeof(*header)) { + header = (const struct rockchip_cmd_header *)buf; + buf += sizeof(*header) + header->payload_length; + len -= sizeof(*header) + header->payload_length; + cnt++; + } + + pcmds->cmds = calloc(cnt, sizeof(struct rockchip_cmd_desc)); + if (!pcmds->cmds) + return -ENOMEM; + + pcmds->cmd_cnt = cnt; + + buf = data; + len = length; + for (i = 0; i < cnt; i++) { + struct rockchip_cmd_desc *desc = &pcmds->cmds[i]; + + header = (const struct rockchip_cmd_header *)buf; + length -= sizeof(*header); + buf += sizeof(*header); + desc->header.data_type = header->data_type; + desc->header.delay_ms = header->delay_ms; + desc->header.payload_length = header->payload_length; + desc->payload = buf; + buf += header->payload_length; + length -= header->payload_length; + } + + return 0; +} + +static int rockchip_panel_send_dsi_cmds(struct mipi_dsi_device *dsi, + struct rockchip_panel_cmds *cmds) +{ + int i, ret; + struct drm_dsc_picture_parameter_set *pps = NULL; + + if (!cmds) + return -EINVAL; + + for (i = 0; i < cmds->cmd_cnt; i++) { + struct rockchip_cmd_desc *desc = &cmds->cmds[i]; + const struct rockchip_cmd_header *header = &desc->header; + + switch (header->data_type) { + case MIPI_DSI_COMPRESSION_MODE: + ret = mipi_dsi_compression_mode(dsi, desc->payload[0]); + break; + case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: + case MIPI_DSI_GENERIC_LONG_WRITE: + ret = mipi_dsi_generic_write(dsi, desc->payload, + header->payload_length); + break; + case MIPI_DSI_DCS_SHORT_WRITE: + case MIPI_DSI_DCS_SHORT_WRITE_PARAM: + case MIPI_DSI_DCS_LONG_WRITE: + ret = mipi_dsi_dcs_write_buffer(dsi, desc->payload, + header->payload_length); + break; + case MIPI_DSI_PICTURE_PARAMETER_SET: + pps = AllocateZeroPool(sizeof(*pps)); + if (!pps) + return -ENOMEM; + + memcpy(pps, desc->payload, header->payload_length); + ret = mipi_dsi_picture_parameter_set(dsi, pps); + free(pps); + break; + default: + printf("unsupport command data type: %d\n", + header->data_type); + return -EINVAL; + } + + if (ret < 0) { + printf("failed to write cmd%d: %d\n", i, ret); + return ret; + } + + if (header->delay_ms) + mdelay(header->delay_ms); + } + + return 0; +} + +static int rockchip_panel_init(struct dw_mipi_dsi2 *dsi2) +{ + ROCKCHIP_DSI_PANEL_PROTOCOL *Panel = dsi2->RockchipDsiPanel; + const void *data; + int len = 0; + int ret; + struct rockchip_panel_cmds *on_cmds; + + Panel->Prepare(Panel); + + data = Panel->InitSequence; + len = Panel->InitSequenceLength; + + if (data) { + on_cmds = calloc(1, sizeof(*on_cmds)); + if (!on_cmds) + return -ENOMEM; + + ret = rockchip_panel_parse_cmds(data, len, on_cmds); + if (ret) { + printf("failed to parse panel init sequence\n"); + goto free_on_cmds; + } + + ret = rockchip_panel_send_dsi_cmds(dsi2->device, on_cmds); + if (ret) + printf("failed to send on cmds: %d\n", ret); + } + + return 0; + +free_on_cmds: + free(on_cmds); + return ret; +} + +static inline void dsi_write(struct dw_mipi_dsi2 *dsi2, u32 reg, u32 val) +{ + writel(val, dsi2->base + reg); +} + +static inline u32 dsi_read(struct dw_mipi_dsi2 *dsi2, u32 reg) +{ + return readl(dsi2->base + reg); +} + +static inline void dsi_update_bits(struct dw_mipi_dsi2 *dsi2, + u32 reg, u32 mask, u32 val) +{ + u32 orig, tmp; + + orig = dsi_read(dsi2, reg); + tmp = orig & ~mask; + tmp |= val & mask; + dsi_write(dsi2, reg, tmp); +} + +static void grf_field_write(struct dw_mipi_dsi2 *dsi2, enum grf_reg_fields index, + unsigned int val) +{ + const u32 field = dsi2->id ? dsi2->pdata->dsi1_grf_reg_fields[index] : + dsi2->pdata->dsi0_grf_reg_fields[index]; + u16 reg; + u8 msb, lsb; + + if (!field) + return; + + reg = (field >> 16) & 0xffff; + lsb = (field >> 8) & 0xff; + msb = (field >> 0) & 0xff; + + regmap_write(dsi2->grf, reg, GENMASK(msb, lsb) << 16 | val << lsb); +} + +static unsigned long dw_mipi_dsi2_get_lane_rate(struct dw_mipi_dsi2 *dsi2) +{ + const DRM_DISPLAY_MODE *mode = &dsi2->mode; + ROCKCHIP_DSI_PANEL_PROTOCOL *Panel = dsi2->RockchipDsiPanel; + u64 max_lane_rate, lane_rate; + unsigned int value; + int bpp, lanes; + u64 tmp; + + max_lane_rate = (dsi2->c_option) ? + dsi2->pdata->cphy_max_symbol_rate_per_lane : + dsi2->pdata->dphy_max_bit_rate_per_lane; + + /* + * optional override of the desired bandwidth + * High-Speed mode: Differential and terminated: 80Mbps ~ 4500 Mbps + */ + value = Panel->DsiLaneRate; + if (value >= 80000 && value <= 4500000) + return value * MSEC_PER_SEC; + else if (value >= 80 && value <= 4500) + return value * USEC_PER_SEC; + + bpp = mipi_dsi_pixel_format_to_bpp(dsi2->format); + if (bpp < 0) + bpp = 24; + + lanes = dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes; + tmp = (u64)mode->CrtcClock * 1000 * bpp; + do_div(tmp, lanes); + + if (dsi2->c_option) + tmp = DIV_ROUND_CLOSEST(tmp * 100, 228); + + /* set BW a little larger only in video burst mode in + * consideration of the protocol overhead and HS mode + * switching to BLLP mode, take 1 / 0.9, since Mbps must + * big than bandwidth of RGB + */ + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + tmp *= 10; + do_div(tmp, 9); + } + + if (tmp > max_lane_rate) + lane_rate = max_lane_rate; + else + lane_rate = tmp; + + return lane_rate; +} + +static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) +{ + u32 sts, mask; + int ret; + + mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; + ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, + sts, !(sts & mask), + CMD_PKT_STATUS_TIMEOUT_US); + if (ret < 0) { + printf("command interface is busy: 0x%x\n", sts); + return ret; + } + + return 0; +} + +static int dw_mipi_dsi2_read_from_fifo(struct dw_mipi_dsi2 *dsi2, + const struct mipi_dsi_msg *msg) +{ + u8 *payload = msg->rx_buf; + u8 data_type; + u16 wc; + int i, j, ret, len = msg->rx_len; + unsigned int vrefresh = DrmModeVRefresh(&dsi2->mode); + u32 val; + + ret = readl_poll_timeout(dsi2->base + DSI2_CORE_STATUS, + val, val & CRI_RD_DATA_AVAIL, + DIV_ROUND_UP(1000000, vrefresh)); + if (ret) { + printf("CRI has no available read data\n"); + return ret; + } + + val = dsi_read(dsi2, DSI2_CRI_RX_HDR); + data_type = val & 0x3f; + + if (mipi_dsi_packet_format_is_short(data_type)) { + for (i = 0; i < len && i < 2; i++) + payload[i] = (val >> (8 * (i + 1))) & 0xff; + + return 0; + } + + wc = (val >> 8) & 0xffff; + /* Receive payload */ + for (i = 0; i < len && i < wc; i += 4) { + val = dsi_read(dsi2, DSI2_CRI_RX_PLD); + for (j = 0; j < 4 && j + i < len && j + i < wc; j++) + payload[i + j] = val >> (8 * j); + } + + return 0; +} + +static ssize_t dw_mipi_dsi2_transfer(struct dw_mipi_dsi2 *dsi2, + const struct mipi_dsi_msg *msg) +{ + struct mipi_dsi_packet packet; + int ret; + int val; + u32 mode; + + dsi_update_bits(dsi2, DSI2_DSI_VID_TX_CFG, LPDT_DISPLAY_CMD_EN, + msg->flags & MIPI_DSI_MSG_USE_LPM ? + LPDT_DISPLAY_CMD_EN : 0); + + /* create a packet to the DSI protocol */ + ret = mipi_dsi_create_packet(&packet, msg); + if (ret) { + printf("failed to create packet: %d\n", ret); + return ret; + } + + /* check cri interface is not busy */ + ret = cri_fifos_wait_avail(dsi2); + if (ret) + return ret; + + /* Send payload */ + while (DIV_ROUND_UP(packet.payload_length, 4)) { + if (packet.payload_length < 4) { + /* send residu payload */ + val = 0; + memcpy(&val, packet.payload, packet.payload_length); + dsi_write(dsi2, DSI2_CRI_TX_PLD, val); + packet.payload_length = 0; + } else { + val = get_unaligned_le32(packet.payload); + dsi_write(dsi2, DSI2_CRI_TX_PLD, val); + packet.payload += 4; + packet.payload_length -= 4; + } + } + + /* Send packet header */ + mode = CMD_TX_MODE(msg->flags & MIPI_DSI_MSG_USE_LPM ? 1 : 0); + val = get_unaligned_le32(packet.header); + dsi_write(dsi2, DSI2_CRI_TX_HDR, mode | val); + + ret = cri_fifos_wait_avail(dsi2); + if (ret) + return ret; + + if (msg->rx_len) { + ret = dw_mipi_dsi2_read_from_fifo(dsi2, msg); + if (ret < 0) + return ret; + } + + if (dsi2->slave) { + ret = dw_mipi_dsi2_transfer(dsi2->slave, msg); + if (ret < 0) + return ret; + } + + return msg->rx_len ? msg->rx_len : msg->tx_len; +} + +static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) +{ + u32 val, color_depth; + + switch (dsi2->format) { + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + color_depth = IPI_DEPTH_6_BITS; + break; + case MIPI_DSI_FMT_RGB565: + color_depth = IPI_DEPTH_5_6_5_BITS; + break; + case MIPI_DSI_FMT_RGB888: + default: + color_depth = IPI_DEPTH_8_BITS; + break; + } + + val = IPI_DEPTH(color_depth) | + IPI_FORMAT(dsi2->dsc_enable ? IPI_FORMAT_DSC : IPI_FORMAT_RGB); + dsi_write(dsi2, DSI2_IPI_COLOR_MAN_CFG, val); + grf_field_write(dsi2, IPI_COLOR_DEPTH, color_depth); + + if (dsi2->dsc_enable) + grf_field_write(dsi2, IPI_FORMAT, IPI_FORMAT_DSC); +} + +static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) +{ + DRM_DISPLAY_MODE *mode = &dsi2->mode; + u32 hline, hsa, hbp, hact; + u64 hline_time, hsa_time, hbp_time, hact_time, tmp; + u64 pixel_clk, phy_hs_clk; + u32 vact, vsa, vfp, vbp; + u16 val; + + if (dsi2->slave || dsi2->master) + val = mode->HDisplay / 2; + else + val = mode->HDisplay; + + dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); + + dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); + + if (dsi2->auto_calc_mode) + return; + + /* + * if the controller is intended to operate in data stream mode, + * no more steps are required. + */ + if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) + return; + + vact = mode->VDisplay; + vsa = mode->VSyncEnd - mode->VSyncStart; + vfp = mode->VSyncStart - mode->VDisplay; + vbp = mode->VTotal - mode->VSyncEnd; + hact = mode->HDisplay; + hsa = mode->HSyncEnd - mode->HSyncStart; + hbp = mode->HTotal - mode->HSyncEnd; + hline = mode->HTotal; + + pixel_clk = mode->CrtcClock * MSEC_PER_SEC; + + if (dsi2->c_option) + phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); + else + phy_hs_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); + + tmp = hsa * phy_hs_clk; + hsa_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); + dsi_write(dsi2, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); + + tmp = hbp * phy_hs_clk; + hbp_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); + dsi_write(dsi2, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); + + tmp = hact * phy_hs_clk; + hact_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); + dsi_write(dsi2, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); + + tmp = hline * phy_hs_clk; + hline_time = DIV_ROUND_CLOSEST(tmp << 16, pixel_clk); + dsi_write(dsi2, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); + + dsi_write(dsi2, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); + dsi_write(dsi2, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); + dsi_write(dsi2, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vact)); + dsi_write(dsi2, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); +} + +static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) +{ + u32 val = 0, mode; + int ret; + + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) + val |= BLK_HFP_HS_EN; + + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) + val |= BLK_HBP_HS_EN; + + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) + val |= BLK_HSA_HS_EN; + + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + val |= VID_MODE_TYPE_BURST; + else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; + else + val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; + + dsi_write(dsi2, DSI2_DSI_VID_TX_CFG, val); + + dsi_write(dsi2, DSI2_MODE_CTRL, VIDEO_MODE); + ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, + mode, mode & VIDEO_MODE, + MODE_STATUS_TIMEOUT_US); + if (ret < 0) + printf("failed to enter video mode\n"); +} + +static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) +{ + u32 mode; + int ret; + + dsi_write(dsi2, DSI2_MODE_CTRL, DATA_STREAM_MODE); + ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, + mode, mode & DATA_STREAM_MODE, + MODE_STATUS_TIMEOUT_US); + if (ret < 0) + printf("failed to enter data stream mode\n"); +} + +static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) +{ + u32 mode; + int ret; + + dsi_write(dsi2, DSI2_MODE_CTRL, COMMAND_MODE); + ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, + mode, mode & COMMAND_MODE, + MODE_STATUS_TIMEOUT_US); + if (ret < 0) + printf("failed to enter cmd mode\n"); +} + +static void dw_mipi_dsi2_enable(struct dw_mipi_dsi2 *dsi2) +{ + u32 mode; + int ret; + + dw_mipi_dsi2_ipi_set(dsi2); + + if (dsi2->auto_calc_mode) { + dsi_write(dsi2, DSI2_MODE_CTRL, AUTOCALC_MODE); + ret = readl_poll_timeout(dsi2->base + DSI2_MODE_STATUS, + mode, mode == IDLE_MODE, + MODE_STATUS_TIMEOUT_US); + if (ret < 0) + printf("auto calculation training failed\n"); + } + + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) + dw_mipi_dsi2_set_vid_mode(dsi2); + else + dw_mipi_dsi2_set_data_stream_mode(dsi2); + + if (dsi2->slave) + dw_mipi_dsi2_enable(dsi2->slave); +} + +static void dw_mipi_dsi2_disable(struct dw_mipi_dsi2 *dsi2) +{ + dsi_write(dsi2, DSI2_IPI_PIX_PKT_CFG, 0); + dw_mipi_dsi2_set_cmd_mode(dsi2); + + if (dsi2->slave) + dw_mipi_dsi2_disable(dsi2->slave); +} + +static void dw_mipi_dsi2_post_disable(struct dw_mipi_dsi2 *dsi2) +{ + if (!dsi2->prepared) + return; + + dsi_write(dsi2, DSI2_PWR_UP, RESET); + + if (dsi2->dcphy.phy) + rockchip_phy_power_off(dsi2->dcphy.phy); + + dsi2->prepared = false; + + if (dsi2->slave) + dw_mipi_dsi2_post_disable(dsi2->slave); +} + +static int dw_mipi_dsi2_connector_pre_init(ROCKCHIP_CONNECTOR_PROTOCOL *conn, + DISPLAY_STATE *state) +{ + CONNECTOR_STATE *conn_state = &state->ConnectorState; + struct dw_mipi_dsi2 *dsi2 = DW_MIPI_DSI2_FROM_CONNECTOR_PROTOCOL(conn); + struct mipi_dsi_host *host = &dsi2->host; + struct mipi_dsi_device *device; + + conn_state->Type = DRM_MODE_CONNECTOR_DSI; + + device = dsi2->device; + if (!device) + return -ENODEV; + + device->host = host; + mipi_dsi_attach(device); + + return 0; +} + +static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2) +{ + struct udevice *dev = dsi2->device->dev; + ROCKCHIP_DSI_PANEL_PROTOCOL *Panel = dsi2->RockchipDsiPanel; + struct rockchip_cmd_header *header; + struct drm_dsc_picture_parameter_set *pps = NULL; + u8 *dsc_packed_pps; + const void *data; + int len; + + dsi2->c_option = Panel->CPhyEnable; + dsi2->scrambling_en = Panel->ScramblingEnable; + dsi2->dsc_enable = Panel->DscEnable; + + if (dsi2->slave) { + dsi2->slave->c_option = dsi2->c_option; + dsi2->slave->scrambling_en = dsi2->scrambling_en; + dsi2->slave->dsc_enable = dsi2->dsc_enable; + } + + if (!dsi2->dsc_enable) + return 0; + + dsi2->slice_width = Panel->SliceWidth; + dsi2->slice_height = Panel->SliceHeight; + dsi2->version_major = Panel->VersionMajor; + dsi2->version_minor = Panel->VersionMinor; + + data = Panel->InitSequence; + len = Panel->InitSequenceLength; + + if (!data) + return -EINVAL; + + while (len > sizeof(*header)) { + header = (struct rockchip_cmd_header *)data; + data += sizeof(*header); + len -= sizeof(*header); + + if (header->payload_length > len) + return -EINVAL; + + if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) { + dsc_packed_pps = calloc(1, header->payload_length); + if (!dsc_packed_pps) + return -ENOMEM; + + memcpy(dsc_packed_pps, data, header->payload_length); + pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps; + break; + } + + data += header->payload_length; + len -= header->payload_length; + } + + if (!pps) { + printf("not found dsc pps definition\n"); + return -EINVAL; + } + + dsi2->pps = pps; + + if (dsi2->slave) { + u16 pic_width = be16_to_cpu(pps->pic_width) / 2; + + dsi2->pps->pic_width = cpu_to_be16(pic_width); + printf("dsc pic_width change from %d to %d\n", pic_width * 2, pic_width); + } + + return 0; +} + +static int dw_mipi_dsi2_connector_init(ROCKCHIP_CONNECTOR_PROTOCOL *conn, DISPLAY_STATE *state) +{ + CONNECTOR_STATE *conn_state = &state->ConnectorState; + CRTC_STATE *cstate = &state->CrtcState; + struct dw_mipi_dsi2 *dsi2 = DW_MIPI_DSI2_FROM_CONNECTOR_PROTOCOL(conn); + struct rockchip_phy *phy = NULL; + struct udevice *phy_dev; + struct udevice *dev; + int ret; + + conn_state->OutputMode = ROCKCHIP_OUT_MODE_P888; + conn_state->ColorSpace = V4L2_COLORSPACE_DEFAULT; + conn_state->OutputInterface |= + dsi2->id ? VOP_OUTPUT_IF_MIPI1 : VOP_OUTPUT_IF_MIPI0; + + if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) { + conn_state->OutputFlags |= ROCKCHIP_OUTPUT_MIPI_DS_MODE; + conn_state->hold_mode = true; + } + +#if 0 + if (dsi2->lanes > 4) { + ret = uclass_get_device_by_name(UCLASS_DISPLAY, + "dsi@fde30000", + &dev); + if (ret) + return ret; + + dsi2->slave = dev_get_priv(dev); + if (!dsi2->slave) + return -ENODEV; + + dsi2->slave->master = dsi2; + dsi2->lanes /= 2; + + dsi2->slave->auto_calc_mode = dsi2->auto_calc_mode; + dsi2->slave->lanes = dsi2->lanes; + dsi2->slave->format = dsi2->format; + dsi2->slave->mode_flags = dsi2->mode_flags; + dsi2->slave->channel = dsi2->channel; + conn_state->OutputFlags |= + ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE; + if (dsi2->data_swap) + conn_state->OutputFlags |= ROCKCHIP_OUTPUT_DATA_SWAP; + + conn_state->OutputInterface |= VOP_OUTPUT_IF_MIPI1; + + ret = uclass_get_device_by_phandle(UCLASS_PHY, dev, + "phys", &phy_dev); + if (ret) + return -ENODEV; + + phy = (struct rockchip_phy *)dev_get_driver_data(phy_dev); + if (!phy) + return -ENODEV; + + dsi2->slave->dcphy.phy = phy; + if (phy->funcs && phy->funcs->init) + return phy->funcs->init(phy); + } +#endif + + dw_mipi_dsi2_get_dsc_params_from_sink(dsi2); + + if (dsi2->dsc_enable) { + cstate->dsc_enable = 1; + cstate->dsc_sink_cap.version_major = dsi2->version_major; + cstate->dsc_sink_cap.version_minor = dsi2->version_minor; + cstate->dsc_sink_cap.slice_width = dsi2->slice_width; + cstate->dsc_sink_cap.slice_height = dsi2->slice_height; + /* only can support rgb888 panel now */ + cstate->dsc_sink_cap.target_bits_per_pixel_x16 = 8 << 4; + cstate->dsc_sink_cap.native_420 = 0; + memcpy(&cstate->pps, dsi2->pps, sizeof(struct drm_dsc_picture_parameter_set)); + } + + return 0; +} + +/* + * Minimum D-PHY timings based on MIPI D-PHY specification. Derived + * from the valid ranges specified in Section 6.9, Table 14, Page 41 + * of the D-PHY specification (v2.1). + */ +int mipi_dphy_get_default_config(unsigned long long hs_clk_rate, + struct mipi_dphy_configure *cfg) +{ + unsigned long long ui; + + if (!cfg) + return -EINVAL; + + ui = ALIGN(PSEC_PER_SEC, hs_clk_rate); + do_div(ui, hs_clk_rate); + + cfg->clk_miss = 0; + cfg->clk_post = 60000 + 52 * ui; + cfg->clk_pre = 8000; + cfg->clk_prepare = 38000; + cfg->clk_settle = 95000; + cfg->clk_term_en = 0; + cfg->clk_trail = 60000; + cfg->clk_zero = 262000; + cfg->d_term_en = 0; + cfg->eot = 0; + cfg->hs_exit = 100000; + cfg->hs_prepare = 40000 + 4 * ui; + cfg->hs_zero = 105000 + 6 * ui; + cfg->hs_settle = 85000 + 6 * ui; + cfg->hs_skip = 40000; + + /* + * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40) + * contains this formula as: + * + * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui) + * + * where n = 1 for forward-direction HS mode and n = 4 for reverse- + * direction HS mode. There's only one setting and this function does + * not parameterize on anything other that ui, so this code will + * assumes that reverse-direction HS mode is supported and uses n = 4. + */ + cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui); + + cfg->init = 100; + cfg->lpx = 60000; + cfg->ta_get = 5 * cfg->lpx; + cfg->ta_go = 4 * cfg->lpx; + cfg->ta_sure = 2 * cfg->lpx; + cfg->wakeup = 1000; + + return 0; +} + +static void dw_mipi_dsi2_set_hs_clk(struct dw_mipi_dsi2 *dsi2, unsigned long rate) +{ + mipi_dphy_get_default_config(rate, &dsi2->mipi_dphy_cfg); + + if (!dsi2->c_option) + rockchip_phy_set_mode(dsi2->dcphy.phy, PHY_MODE_MIPI_DPHY); + + rate = rockchip_phy_set_pll(dsi2->dcphy.phy, rate); + dsi2->lane_hs_rate = DIV_ROUND_CLOSEST(rate, MSEC_PER_SEC); +} + +static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) +{ + dsi_write(dsi2, DSI2_SOFT_RESET, 0X0); + udelay(100); + dsi_write(dsi2, DSI2_SOFT_RESET, SYS_RSTN | PHY_RSTN | IPI_RSTN); +} + +static void +dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) +{ + /* + * select controller work in Manual mode + * Manual: MANUAL_MODE_EN + * Automatic: 0 + */ + dsi_write(dsi2, MANUAL_MODE_CFG, mode); +} + +static void dw_mipi_dsi2_phy_mode_cfg(struct dw_mipi_dsi2 *dsi2) +{ + u32 val = 0; + + /* PPI width is fixed to 16 bits in DCPHY */ + val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); + val |= PHY_TYPE(dsi2->c_option ? CPHY : DPHY); + dsi_write(dsi2, DSI2_PHY_MODE_CFG, val); +} + +static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) +{ + u32 sys_clk = SYS_CLK / USEC_PER_SEC; + u32 esc_clk_div; + u32 val = 0; + + if (dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + val |= NON_CONTINUOUS_CLK; + + /* The Escape clock ranges from 1MHz to 20MHz. */ + esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); + val |= PHY_LPTX_CLK_DIV(esc_clk_div); + + dsi_write(dsi2, DSI2_PHY_CLK_CFG, val); +} + +static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) +{ + u64 ipi_clk, phy_hsclk, tmp; + + /* + * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed + * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio + * high speed symbol rate. + */ + if (dsi2->c_option) + phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 7); + + else + phy_hsclk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); + + /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ + ipi_clk = dsi2->mipi_pixel_rate; + + tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, ipi_clk); + dsi_write(dsi2, DSI2_PHY_IPI_RATIO_MAN_CFG, PHY_IPI_RATIO(tmp)); + + /* SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / SYS_CLK */ + tmp = DIV_ROUND_CLOSEST(phy_hsclk << 16, SYS_CLK); + dsi_write(dsi2, DSI2_PHY_SYS_RATIO_MAN_CFG, PHY_SYS_RATIO(tmp)); +} + +static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) +{ + struct mipi_dphy_configure *cfg = &dsi2->mipi_dphy_cfg; + unsigned long long tmp, ui; + unsigned long long hstx_clk; + + hstx_clk = DIV_ROUND_CLOSEST(dsi2->lane_hs_rate * MSEC_PER_SEC, 16); + + ui = ALIGN(PSEC_PER_SEC, hstx_clk); + do_div(ui, hstx_clk); + + /* PHY_LP2HS_TIME = (TLPX + THS-PREPARE + THS-ZERO) / Tphy_hstx_clk */ + tmp = cfg->lpx + cfg->hs_prepare + cfg->hs_zero; + tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); + dsi_write(dsi2, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(tmp)); + + /* PHY_HS2LP_TIME = (THS-TRAIL + THS-EXIT) / Tphy_hstx_clk */ + tmp = cfg->hs_trail + cfg->hs_exit; + tmp = DIV_ROUND_CLOSEST(tmp << 16, ui); + dsi_write(dsi2, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(tmp)); +} + +static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) +{ + dw_mipi_dsi2_phy_mode_cfg(dsi2); + dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); + + if (dsi2->auto_calc_mode) + return; + + dw_mipi_dsi2_phy_ratio_cfg(dsi2); + dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); + + /* phy configuration 8 - 10 */ +} + +static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) +{ + u32 val; + + val = BTA_EN | EOTP_TX_EN; + + if (dsi2->mode_flags & MIPI_DSI_MODE_EOT_PACKET) + val &= ~EOTP_TX_EN; + + dsi_write(dsi2, DSI2_DSI_GENERAL_CFG, val); + dsi_write(dsi2, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); + + if (dsi2->scrambling_en) + dsi_write(dsi2, DSI2_DSI_SCRAMBLING_CFG, SCRAMBLING_EN); +} + +static void dw_mipi_dsi2_irq_enable(struct dw_mipi_dsi2 *dsi2, bool enable) +{ + if (enable) { + dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x1); + dsi_write(dsi2, DSI2_INT_MASK_TO, 0xf); + dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x1); + dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x1); + dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x1); + dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x1); + dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x1); + } else { + dsi_write(dsi2, DSI2_INT_MASK_PHY, 0x0); + dsi_write(dsi2, DSI2_INT_MASK_TO, 0x0); + dsi_write(dsi2, DSI2_INT_MASK_ACK, 0x0); + dsi_write(dsi2, DSI2_INT_MASK_IPI, 0x0); + dsi_write(dsi2, DSI2_INT_MASK_FIFO, 0x0); + dsi_write(dsi2, DSI2_INT_MASK_PRI, 0x0); + dsi_write(dsi2, DSI2_INT_MASK_CRI, 0x0); + }; +} + +static void mipi_dcphy_power_on(struct dw_mipi_dsi2 *dsi2) +{ + if (!dsi2->dcphy.phy) + return; + + rockchip_phy_power_on(dsi2->dcphy.phy); +} + +static void dw_mipi_dsi2_pre_enable(struct dw_mipi_dsi2 *dsi2) +{ + if (dsi2->prepared) + return; + + dw_mipi_dsi2_host_softrst(dsi2); + dsi_write(dsi2, DSI2_PWR_UP, RESET); + + dw_mipi_dsi2_work_mode(dsi2, dsi2->auto_calc_mode ? 0 : MANUAL_MODE_EN); + dw_mipi_dsi2_phy_init(dsi2); + dw_mipi_dsi2_tx_option_set(dsi2); + dw_mipi_dsi2_irq_enable(dsi2, 0); + mipi_dcphy_power_on(dsi2); + dsi_write(dsi2, DSI2_PWR_UP, POWER_UP); + dw_mipi_dsi2_set_cmd_mode(dsi2); + + dsi2->prepared = true; + + if (dsi2->slave) + dw_mipi_dsi2_pre_enable(dsi2->slave); +} + +static void dw_mipi_dsi2_get_mipi_pixel_clk(struct dw_mipi_dsi2 *dsi2, + CRTC_STATE *s) +{ + DRM_DISPLAY_MODE *mode = &dsi2->mode; + u8 k = dsi2->slave ? 2 : 1; + + /* 1.When MIPI works in uncompressed mode: + * (Video Timing Pixel Rate)/(4)=(MIPI Pixel ClockxK)=(dclk_out×K)=dclk_core + * 2.When MIPI works in compressed mode: + * MIPI Pixel Clock = cds_clk / 2 + * MIPI is configured as double channel display mode, K=2, otherwise K=1. + */ + if (dsi2->dsc_enable) { + dsi2->mipi_pixel_rate = s->dsc_cds_clk_rate / 2; + if (dsi2->slave) + dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; + + return; + } + + dsi2->mipi_pixel_rate = (mode->CrtcClock * MSEC_PER_SEC) / (4 * k); + if (dsi2->slave) + dsi2->slave->mipi_pixel_rate = dsi2->mipi_pixel_rate; +} + +static int dw_mipi_dsi2_connector_prepare(ROCKCHIP_CONNECTOR_PROTOCOL *conn, + DISPLAY_STATE *state) +{ + struct dw_mipi_dsi2 *dsi2 = DW_MIPI_DSI2_FROM_CONNECTOR_PROTOCOL(conn); + CONNECTOR_STATE *conn_state = &state->ConnectorState; + CRTC_STATE *cstate = &state->CrtcState; + unsigned long lane_rate; + + memcpy(&dsi2->mode, &conn_state->DisplayMode, sizeof(DRM_DISPLAY_MODE)); + if (dsi2->slave) + memcpy(&dsi2->slave->mode, &dsi2->mode, + sizeof(DRM_DISPLAY_MODE)); + + dw_mipi_dsi2_get_mipi_pixel_clk(dsi2, cstate); + + lane_rate = dw_mipi_dsi2_get_lane_rate(dsi2); + if (dsi2->dcphy.phy) + dw_mipi_dsi2_set_hs_clk(dsi2, lane_rate); + + if (dsi2->slave && dsi2->slave->dcphy.phy) + dw_mipi_dsi2_set_hs_clk(dsi2->slave, lane_rate); + + printf("final DSI-Link bandwidth: %u %a x %d\n", + dsi2->lane_hs_rate, dsi2->c_option ? "Ksps" : "Kbps", + dsi2->slave ? dsi2->lanes * 2 : dsi2->lanes); + + dw_mipi_dsi2_pre_enable(dsi2); + + return 0; +} + +static void dw_mipi_dsi2_connector_unprepare(ROCKCHIP_CONNECTOR_PROTOCOL *conn, + DISPLAY_STATE *state) +{ + struct dw_mipi_dsi2 *dsi2 = DW_MIPI_DSI2_FROM_CONNECTOR_PROTOCOL(conn); + + dw_mipi_dsi2_post_disable(dsi2); +} + +static int dw_mipi_dsi2_connector_enable(ROCKCHIP_CONNECTOR_PROTOCOL *conn, + DISPLAY_STATE *state) +{ + struct dw_mipi_dsi2 *dsi2 = DW_MIPI_DSI2_FROM_CONNECTOR_PROTOCOL(conn); + + dw_mipi_dsi2_enable(dsi2); + + rockchip_panel_init(dsi2); + + return 0; +} + +static int dw_mipi_dsi2_connector_disable(ROCKCHIP_CONNECTOR_PROTOCOL *conn, + DISPLAY_STATE *state) +{ + struct dw_mipi_dsi2 *dsi2 = DW_MIPI_DSI2_FROM_CONNECTOR_PROTOCOL(conn); + + dw_mipi_dsi2_disable(dsi2); + + return 0; +} + +EFI_STATUS +DwMipiDsi2ConnectorPreInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + ret = dw_mipi_dsi2_connector_pre_init(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +}; + +EFI_STATUS +DwMipiDsi2ConnectorInit ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + ret = dw_mipi_dsi2_connector_init(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +DwMipiDsi2ConnectorEnable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + /* this should be called by the GOP driver instead */ + dw_mipi_dsi2_connector_prepare (This, DisplayState); + + ret = dw_mipi_dsi2_connector_enable(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +DwMipiDsi2ConnectorDisable ( + OUT ROCKCHIP_CONNECTOR_PROTOCOL *This, + OUT DISPLAY_STATE *DisplayState + ) +{ + int ret; + + ret = dw_mipi_dsi2_connector_disable(This, DisplayState); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +ROCKCHIP_CONNECTOR_PROTOCOL mDwMipiDsi2ConnectorOps = { + NULL, + DwMipiDsi2ConnectorPreInit, + DwMipiDsi2ConnectorInit, + NULL, + NULL, + NULL, + NULL, + NULL, + DwMipiDsi2ConnectorEnable, + DwMipiDsi2ConnectorDisable, + NULL +}; + +static const u32 rk3588_dsi0_grf_reg_fields[MAX_FIELDS] = { + [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0000, 11, 11), + [GATING_EN] = GRF_REG_FIELD(0x0000, 10, 10), + [IPI_SHUTDN] = GRF_REG_FIELD(0x0000, 9, 9), + [IPI_COLORM] = GRF_REG_FIELD(0x0000, 8, 8), + [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0000, 4, 7), + [IPI_FORMAT] = GRF_REG_FIELD(0x0000, 0, 3), +}; + +static const u32 rk3588_dsi1_grf_reg_fields[MAX_FIELDS] = { + [TXREQCLKHS_EN] = GRF_REG_FIELD(0x0004, 11, 11), + [GATING_EN] = GRF_REG_FIELD(0x0004, 10, 10), + [IPI_SHUTDN] = GRF_REG_FIELD(0x0004, 9, 9), + [IPI_COLORM] = GRF_REG_FIELD(0x0004, 8, 8), + [IPI_COLOR_DEPTH] = GRF_REG_FIELD(0x0004, 4, 7), + [IPI_FORMAT] = GRF_REG_FIELD(0x0004, 0, 3), +}; + +static const struct dw_mipi_dsi2_plat_data rk3588_mipi_dsi2_plat_data = { + .dsi0_grf_reg_fields = rk3588_dsi0_grf_reg_fields, + .dsi1_grf_reg_fields = rk3588_dsi1_grf_reg_fields, + .dphy_max_bit_rate_per_lane = 4500000000ULL, + .cphy_max_symbol_rate_per_lane = 2000000000ULL, +}; + +static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + struct dw_mipi_dsi2 *dsi2 = DW_MIPI_DSI2_FROM_MIPI_DSI_HOST(host); + + return dw_mipi_dsi2_transfer(dsi2, msg); +} + +static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct dw_mipi_dsi2 *dsi2 = DW_MIPI_DSI2_FROM_MIPI_DSI_HOST(host); + + if (device->lanes < 1 || device->lanes > 8) + return -EINVAL; + + dsi2->lanes = device->lanes; + dsi2->channel = device->channel; + dsi2->format = device->format; + dsi2->mode_flags = device->mode_flags; + dsi2->device = device; + + return 0; +} + +static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { + .attach = dw_mipi_dsi2_host_attach, + .transfer = dw_mipi_dsi2_host_transfer, +}; + +static int dw_mipi_dsi2_child_post_bind(struct dw_mipi_dsi2 *dsi2) +{ + struct mipi_dsi_host *host = &dsi2->host; + struct mipi_dsi_device *device = NULL; + ROCKCHIP_DSI_PANEL_PROTOCOL *Panel = dsi2->RockchipDsiPanel; + + device = AllocatePool(sizeof (struct mipi_dsi_device)); + if (device == NULL) { + return -ENOMEM; + } + + host->ops = &dw_mipi_dsi2_host_ops; + + device->host = host; + + device->lanes = Panel->DsiLanes; + device->format = Panel->DsiFormat; + device->mode_flags = Panel->DsiFlags; + device->channel = 0; + + dw_mipi_dsi2_host_attach(host, device); + + return 0; +} + +struct dw_mipi_dsi2 mRk3588MipiDsi[] = { + { + .base = 0xfde20000, + .grf = RK3588_VOP_GRF_BASE, + .id = 0, + .pdata = &rk3588_mipi_dsi2_plat_data, + }, + { + .base = 0xfde30000, + .grf = RK3588_VOP_GRF_BASE, + .id = 1, + .pdata = &rk3588_mipi_dsi2_plat_data, + }, +}; + +STATIC VOID *mDsiPanelEventRegistration; + +STATIC +VOID +DsiPanelRegistrationEventHandler ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_HANDLE Handle; + UINTN BufferSize; + EFI_STATUS Status; + ROCKCHIP_DSI_PANEL_PROTOCOL *DsiPanel; + struct dw_mipi_dsi2 *dsi2; + UINTN Index; + + while (TRUE) { + BufferSize = sizeof (EFI_HANDLE); + Status = gBS->LocateHandle (ByRegisterNotify, + NULL, + mDsiPanelEventRegistration, + &BufferSize, + &Handle); + if (EFI_ERROR (Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG ((DEBUG_WARN, "%a: Failed to locate gRockchipDsiPanelProtocolGuid. Status=%r\n", + __FUNCTION__, Status)); + } + break; + } + + Status = gBS->HandleProtocol (Handle, &gRockchipDsiPanelProtocolGuid, (VOID **)&DsiPanel); + ASSERT_EFI_ERROR (Status); + + for (Index = 0; Index < ARRAY_SIZE (mRk3588MipiDsi); Index++) { + dsi2 = &mRk3588MipiDsi[Index]; + if (dsi2->id == DsiPanel->DsiId) { + dsi2->Signature = DW_MIPI_DSI2_SIGNATURE; + dsi2->dcphy.phy = rockchip_phy_by_id(dsi2->id); + dsi2->RockchipDsiPanel = DsiPanel; + CopyMem (&dsi2->connector, &mDwMipiDsi2ConnectorOps, sizeof (ROCKCHIP_CONNECTOR_PROTOCOL)); + + dw_mipi_dsi2_child_post_bind(dsi2); + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gRockchipConnectorProtocolGuid, + &dsi2->connector, + NULL + ); + break; + } + } + + ASSERT_EFI_ERROR (Status); + break; + } +} + +EFI_STATUS +EFIAPI +DwMipiDsi2Init ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EfiCreateProtocolNotifyEvent (&gRockchipDsiPanelProtocolGuid, + TPL_CALLBACK, + DsiPanelRegistrationEventHandler, + NULL, + &mDsiPanelEventRegistration); + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.inf new file mode 100644 index 0000000..b1e4487 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.inf @@ -0,0 +1,53 @@ +#/** @file +# +# Synopsys DesignWare MIPI DSI2 controller driver +# +# Copyright (c) 2023-2024, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DwMipiDsi2Lib + FILE_GUID = aa11f6f3-96a8-45f9-b757-47e1c793d409 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = DwMipiDsi2Init + +[Sources.common] + DwMipiDsi2Lib.c + drm_dsc.c + drm_mipi_dsi.c + rockchip_phy.c + samsung_mipi_dcphy.c + +[LibraryClasses] + UefiDriverEntryPoint + UefiLib + UefiBootServicesTableLib + TimerLib + DebugLib + IoLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + RockchipDisplayLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[BuildOptions] + +[Pcd] + +[Protocols] + gRockchipConnectorProtocolGuid ## PRODUCES + gRockchipDsiPanelProtocolGuid ## CONSUMES + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/PhyRockchipSamsungHdptx.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/PhyRockchipSamsungHdptx.c new file mode 100644 index 0000000..263b400 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/PhyRockchipSamsungHdptx.c @@ -0,0 +1,897 @@ +/** @file + + Rockchip HDMI/DP Combo PHY with Samsung IP block + Copyright (c) 2022, Linaro, Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define RO_REF_CLK_SEL GENMASK(11, 10) +#define LC_REF_CLK_SEL GENMASK(9, 8) +#define PLL_EN BIT(7) +#define BIAS_EN BIT(6) +#define BGR_EN BIT(5) +#define HDPTX_MODE_SEL BIT(0) +#define PLL_LOCK_DONE BIT(3) +#define PHY_CLK_RDY BIT(2) +#define PHY_RDY BIT(1) +#define SB_RDY BIT(0) + +/* cmn_reg0008 */ +#define OVRD_LCPLL_EN BIT(7) +#define LCPLL_EN BIT(6) + +/* cmn_reg003C */ +#define ANA_LCPLL_RESERVED7 BIT(7) + +/* cmn_reg003D */ +#define OVRD_ROPLL_EN BIT(7) +#define ROPLL_EN BIT(6) + +/* cmn_reg0046 */ +#define ROPLL_ANA_CPP_CTRL_COARSE GENMASK(7, 4) +#define ROPLL_ANA_CPP_CTRL_FINE GENMASK(3, 0) + +/* cmn_reg0047 */ +#define ROPLL_ANA_LPF_C_SEL_COARSE GENMASK(5, 3) +#define ROPLL_ANA_LPF_C_SEL_FINE GENMASK(2, 0) + +/* cmn_reg004E */ +#define ANA_ROPLL_PI_EN BIT(5) + +/* cmn_reg0051 */ +#define ROPLL_PMS_MDIV GENMASK(7, 0) + +/* cmn_reg0055 */ +#define ROPLL_PMS_MDIV_AFC GENMASK(7, 0) + +/* cmn_reg0059 */ +#define ANA_ROPLL_PMS_PDIV GENMASK(7, 4) +#define ANA_ROPLL_PMS_REFDIV GENMASK(3, 0) + +/* cmn_reg005A */ +#define ROPLL_PMS_SDIV_RBR GENMASK(7, 4) +#define ROPLL_PMS_SDIV_HBR GENMASK(3, 0) + +/* cmn_reg005B */ +#define ROPLL_PMS_SDIV_HBR2 GENMASK(7, 4) +#define ROPLL_PMS_SDIV_HBR3 GENMASK(3, 0) + +/* cmn_reg005D */ +#define OVRD_ROPLL_REF_CLK_SEL BIT(5) +#define ROPLL_REF_CLK_SEL GENMASK(4, 3) + +/* cmn_reg005E */ +#define ANA_ROPLL_SDM_EN BIT(6) +#define OVRD_ROPLL_SDM_RSTN BIT(5) +#define ROPLL_SDM_RSTN BIT(4) +#define ROPLL_SDC_FRACTIONAL_EN_RBR BIT(3) +#define ROPLL_SDC_FRACTIONAL_EN_HBR BIT(2) +#define ROPLL_SDC_FRACTIONAL_EN_HBR2 BIT(1) +#define ROPLL_SDC_FRACTIONAL_EN_HBR3 BIT(0) + +/* cmn_reg005F */ +#define OVRD_ROPLL_SDC_RSTN BIT(5) +#define ROPLL_SDC_RSTN BIT(4) + +/* cmn_reg0060 */ +#define ROPLL_SDM_DENOMINATOR GENMASK(7, 0) + +/* cmn_reg0064 */ +#define ROPLL_SDM_NUMERATOR_SIGN_RBR BIT(3) +#define ROPLL_SDM_NUMERATOR_SIGN_HBR BIT(2) +#define ROPLL_SDM_NUMERATOR_SIGN_HBR2 BIT(1) +#define ROPLL_SDM_NUMERATOR_SIGN_HBR3 BIT(0) + +/* cmn_reg0065 */ +#define ROPLL_SDM_NUMERATOR GENMASK(7, 0) + +/* cmn_reg0069 */ +#define ROPLL_SDC_N_RBR GENMASK(2, 0) + +/* cmn_reg006A */ +#define ROPLL_SDC_N_HBR GENMASK(5, 3) +#define ROPLL_SDC_N_HBR2 GENMASK(2, 0) + +/* cmn_reg006B */ +#define ROPLL_SDC_N_HBR3 GENMASK(3, 1) + +/* cmn_reg006C */ +#define ROPLL_SDC_NUMERATOR GENMASK(5, 0) + +/* cmn_reg0070 */ +#define ROPLL_SDC_DENOMINATOR GENMASK(5, 0) + +/* cmn_reg0074 */ +#define OVRD_ROPLL_SDC_NDIV_RSTN BIT(3) +#define ROPLL_SDC_NDIV_RSTN BIT(2) +#define OVRD_ROPLL_SSC_EN BIT(1) +#define ROPLL_SSC_EN BIT(0) + +/* cmn_reg0075 */ +#define ANA_ROPLL_SSC_FM_DEVIATION GENMASK(5, 0) + +/* cmn_reg0076 */ +#define ANA_ROPLL_SSC_FM_FREQ GENMASK(6, 2) + +/* cmn_reg0077 */ +#define ANA_ROPLL_SSC_CLK_DIV_SEL GENMASK(6, 3) + +/* cmn_reg0081 */ +#define ANA_PLL_CD_TX_SER_RATE_SEL BIT(3) +#define ANA_PLL_CD_HSCLK_WEST_EN BIT(1) +#define ANA_PLL_CD_HSCLK_EAST_EN BIT(0) + +/* cmn_reg0082 */ +#define ANA_PLL_CD_VREG_GAIN_CTRL GENMASK(3, 0) + +/* cmn_reg0083 */ +#define ANA_PLL_CD_VREG_ICTRL GENMASK(6, 5) + +/* cmn_reg0084 */ +#define PLL_LCRO_CLK_SEL BIT(5) + +/* cmn_reg0085 */ +#define ANA_PLL_SYNC_LOSS_DET_MODE GENMASK(1, 0) + +/* cmn_reg0087 */ +#define ANA_PLL_TX_HS_CLK_EN BIT(2) + +/* cmn_reg0095 */ +#define DP_TX_LINK_BW GENMASK(1, 0) + +/* cmn_reg0097 */ +#define DIG_CLK_SEL BIT(1) + +/* cmn_reg0099 */ +#define SSC_EN GENMASK(7, 6) +#define CMN_ROPLL_ALONE_MODE BIT(2) + +/* cmn_reg009A */ +#define HS_SPEED_SEL BIT(0) + +/* cmn_reg009B */ +#define LS_SPEED_SEL BIT(4) + +/* sb_reg0102 */ +#define OVRD_SB_RXTERM_EN BIT(5) +#define SB_RXRERM_EN BIT(4) +#define ANA_SB_RXTERM_OFFSP GENMASK(3, 0) + +/* sb_reg0103 */ +#define ANA_SB_RXTERM_OFFSN GENMASK(6, 3) +#define OVRD_SB_RX_RESCAL_DONE BIT(1) +#define SB_RX_RESCAL_DONE BIT(0) + +/* sb_reg0104 */ +#define OVRD_SB_EN BIT(5) +#define SB_EN BIT(4) +#define OVRD_SB_AUX_EN BIT(1) +#define SB_AUX_EN BIT(0) + +/* sb_reg0105 */ +#define ANA_SB_TX_HLVL_PROG GENMASK(2, 0) + +/* sb_reg0106 */ +#define ANA_SB_TX_LLVL_PROG GENMASK(6, 4) + +/* sb_reg010D */ +#define ANA_SB_DMRX_LPBK_DATA BIT(4) + +/* sb_reg010F */ +#define OVRD_SB_VREG_EN BIT(7) +#define SB_VREG_EN BIT(6) +#define ANA_SB_VREG_GAIN_CTRL GENMASK(3, 0) + +/* sb_reg0110 */ +#define ANA_SB_VREG_OUT_SEL BIT(1) +#define ANA_SB_VREG_REF_SEL BIT(0) + +/* sb_reg0113 */ +#define SB_RX_RCAL_OPT_CODE GENMASK(5, 4) +#define SB_RX_RTERM_CTRL GENMASK(3, 0) + +/* sb_reg0114 */ +#define SB_TG_SB_EN_DELAY_TIME GENMASK(5, 3) +#define SB_TG_RXTERN_EN_DELAY_TIME GENMASK(2, 0) + +/* sb_reg0115 */ +#define SB_READY_DELAY_TIME GENMASK(5, 3) +#define SB_TG_OSC_EN_DELAY_TIME GENMASK(2, 0) + +/* sb_reg0116 */ +#define SB_TG_OSC_EN_TO_AFC_RSTN_DELAT_TIME GENMASK(6, 4) + +/* sb_reg0117 */ +#define SB_TG_PLL_CD_VREG_FAST_PULSE_TIME GENMASK(3, 0) + +/* sb_reg0118 */ +#define SB_TG_EARC_DMRX_RECVRD_CLK_CNT GENMASK(7, 0) + +/* sb_reg011A */ +#define SB_TG_CNT_RUN_NO_7_0 GENMASK(7, 0) + +/* sb_reg011B */ +#define SB_EARC_SIG_DET_BYPASS BIT(4) +#define SB_AFC_TOL GENMASK(3, 0) + +/* sb_reg011C */ +#define SB_AFC_STB_NUM GENMASK(3, 0) + +/* sb_reg011D */ +#define SB_TG_OSC_CNT_MIN GENMASK(7, 0) + +/* sb_reg011E */ +#define SB_TG_OSC_CNT_MAX GENMASK(7, 0) + +/* sb_reg011F */ +#define SB_PWM_AFC_CTRL GENMASK(7, 2) +#define SB_RCAL_RSTN BIT(1) + +/* sb_reg0120 */ +#define SB_AUX_EN_IN BIT(7) + +/* sb_reg0123 */ +#define OVRD_SB_READY BIT(5) +#define SB_READY BIT(4) + +/* lntop_reg0200 */ +#define PROTOCOL_SEL BIT(2) + +/* lntop_reg0206 */ +#define DATA_BUS_WIDTH GENMASK(2, 1) +#define BUS_WIDTH_SEL BIT(0) + +/* lntop_reg0207 */ +#define LANE_EN GENMASK(3, 0) + +/* LANE_reg0301 */ +#define OVRD_LN_TX_DRV_EI_EN BIT(7) +#define LN_TX_DRV_EI_EN BIT(6) + +/* LANE_reg0303 */ +#define OVRD_LN_TX_DRV_LVL_CTRL BIT(5) +#define LN_TX_DRV_LVL_CTRL GENMASK(4, 0) + +/* LANE_reg0304 */ +#define OVRD_LN_TX_DRV_POST_LVL_CTRL BIT(4) +#define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0) +#define LN_TX_DRV_POST_LVL_CTRL GENMASK(3, 0) + +/* LANE_reg0305 */ +#define OVRD_LN_TX_DRV_PRE_LVL_CTRL BIT(6) +#define LN_TX_DRV_PRE_LVL_CTRL GENMASK(5, 2) + +/* LANE_reg0306 */ +#define LN_ANA_TX_DRV_IDRV_IDN_CTRL GENMASK(7, 5) +#define LN_ANA_TX_DRV_IDRV_IUP_CTRL GENMASK(4, 2) +#define LN_ANA_TX_DRV_ACCDRV_EN BIT(0) + +/* LANE_reg0307 */ +#define LN_ANA_TX_DRV_ACCDRV_POL_SEL BIT(6) +#define LN_ANA_TX_DRV_ACCDRV_CTRL GENMASK(5, 3) + +/* LANE_reg030A */ +#define LN_ANA_TX_JEQ_EN BIT(4) +#define LN_TX_JEQ_EVEN_CTRL_RBR GENMASK(3, 0) + +/* LANE_reg030B */ +#define LN_TX_JEQ_EVEN_CTRL_HBR GENMASK(7, 4) +#define LN_TX_JEQ_EVEN_CTRL_HBR2 GENMASK(3, 0) + +/* LANE_reg030C */ +#define LN_TX_JEQ_EVEN_CTRL_HBR3 GENMASK(7, 4) +#define LN_TX_JEQ_ODD_CTRL_RBR GENMASK(3, 0) + +/* LANE_reg030D */ +#define LN_TX_JEQ_ODD_CTRL_HBR GENMASK(7, 4) +#define LN_TX_JEQ_ODD_CTRL_HBR2 GENMASK(3, 0) + +/* LANE_reg030E */ +#define LN_TX_JEQ_ODD_CTRL_HBR3 GENMASK(7, 4) + +/* LANE_reg0310 */ +#define LN_ANA_TX_SYNC_LOSS_DET_MODE GENMASK(1, 0) + +/* LANE_reg0311 */ +#define LN_TX_SER_40BIT_EN_RBR BIT(3) +#define LN_TX_SER_40BIT_EN_HBR BIT(2) +#define LN_TX_SER_40BIT_EN_HBR2 BIT(1) +#define LN_TX_SER_40BIT_EN_HBR3 BIT(0) + +/* LANE_reg0316 */ +#define LN_ANA_TX_SER_VREG_GAIN_CTRL GENMASK(3, 0) + +/* LANE_reg031B */ +#define LN_ANA_TX_RESERVED GENMASK(7, 0) + +/* LANE_reg031E */ +#define LN_POLARITY_INV BIT(2) + +#define LANE_REG(LANE, offset) (0x400 * (LANE) + (offset)) + +enum { + DP_BW_RBR, + DP_BW_HBR, + DP_BW_HBR2, + DP_BW_HBR3, +}; + +struct TxDrvCtrl { + UINT8 Tx_Drv_Lvl_Ctrl; + UINT8 Tx_Drv_Post_Lvl_Ctrl; + UINT8 Ana_Tx_Drv_Idrv_Idn_Ctrl; + UINT8 Ana_Tx_Drv_Idrv_Iup_Ctrl; + UINT8 Ana_Tx_Drv_Accdrv_En; + UINT8 Ana_Tx_Drv_Accdrv_Ctrl; +}; + +STATIC CONST struct TxDrvCtrl TX_DRV_CTRL_RBR[4][4] = { + /* VOLTAGE swing 0, pre-emphasis 0->3 */ + { + { 0x1, 0x0, 0x4, 0x6, 0x0, 0x4 }, + { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4 }, + { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4 }, + { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 1, pre-emphasis 0->2 */ + { + { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4 }, + { 0xa, 0x5, 0x4, 0x6, 0x0, 0x4 }, + { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 2, pre-emphasis 0->1 */ + { + { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4 }, + { 0xd, 0x5, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 3, pre-emphasis 0 */ + { + { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, + } +}; + +STATIC CONST struct TxDrvCtrl TX_DRV_CTRL_HBR[4][4] = { + /* VOLTAGE swing 0, pre-emphasis 0->3 */ + { + { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, + { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, + { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4 }, + { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 1, pre-emphasis 0->2 */ + { + { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, + { 0xb, 0x6, 0x4, 0x6, 0x0, 0x4 }, + { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 2, pre-emphasis 0->1 */ + { + { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, + { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 3, pre-emphasis 0 */ + { + { 0xd, 0x1, 0x7, 0x7, 0x1, 0x4 }, + } +}; + +STATIC CONST struct TxDrvCtrl TX_DRV_CTRL_HBR2[4][4] = { + /* VOLTAGE swing 0, pre-emphasis 0->3 */ + { + { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4 }, + { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4 }, + { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4 }, + { 0xd, 0xb, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 1, pre-emphasis 0->2 */ + { + { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4 }, + { 0xc, 0x7, 0x4, 0x6, 0x0, 0x4 }, + { 0xd, 0x8, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 2, pre-emphasis 0->1 */ + { + { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4 }, + { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7 }, + }, + + /* VOLTAGE swing 3, pre-emphasis 0 */ + { + { 0xd, 0x0, 0x7, 0x7, 0x1, 0x4 }, + } +}; + +INLINE +VOID +PhyWrite ( + OUT struct RockchipHdptxPhy *Hdptx, + UINTN Reg, + UINTN Val + ) +{ + UINT32 Shift; + + if (!Hdptx->Id) + Shift = EDP0TX_PHY_BASE; + else + Shift = EDP1TX_PHY_BASE; + + MmioWrite32(Shift + Reg, Val ); +} + +INLINE +UINTN +PhyRead ( + OUT struct RockchipHdptxPhy *Hdptx, + UINTN Reg + ) +{ + UINT32 Shift; + + if(!Hdptx->Id) + Shift = EDP0TX_PHY_BASE; + else + Shift = EDP1TX_PHY_BASE; + + return MmioRead32(Shift + Reg); +} + +STATIC +VOID +PhyUpdateBits ( + OUT struct RockchipHdptxPhy *Hdptx, + UINTN Reg, + UINTN Mask, + UINTN Val + ) +{ + UINTN Orig, Tmp; + + Orig = PhyRead(Hdptx, Reg); + Tmp = Orig & ~Mask; + Tmp |= Val & Mask; + PhyWrite(Hdptx, Reg, Tmp); +}; + +STATIC +VOID +GrfWrite ( + OUT struct RockchipHdptxPhy *Hdptx, + UINTN Reg, + UINTN Mask, + UINTN Val + ) +{ + UINT32 TempVal = 0; + UINT32 Shift; + + if (!Hdptx->Id) + Shift = HDPTXPHY0_GRF_BASE; + else + Shift = HDPTXPHY1_GRF_BASE; + + TempVal = (Mask << 16) | (Val & Mask); + MmioWrite32(Shift + Reg, TempVal); +}; + +STATIC +VOID +RockchipHdptxPhyDpPllInit ( + struct RockchipHdptxPhy *Hdptx + ) +{ + PhyUpdateBits(Hdptx, 0x20, OVRD_LCPLL_EN | + LCPLL_EN, + 0x80); + PhyWrite(Hdptx, 0xf4, 0xC0); + PhyUpdateBits(Hdptx, 0x0138, ANA_ROPLL_PI_EN, + 0x20); + PhyWrite(Hdptx, 0x0144, 0x87); + PhyWrite(Hdptx, 0x0148, 0x71); + PhyWrite(Hdptx, 0x014c, 0x71); + PhyWrite(Hdptx, 0x0154, 0x87); + PhyWrite(Hdptx, 0x0158, 0x71); + PhyWrite(Hdptx, 0x015c, 0x71); + PhyWrite(Hdptx, 0x0164, 0x11); + PhyWrite(Hdptx, 0x0168, 0x31); + PhyUpdateBits(Hdptx, 0x016c, ROPLL_PMS_SDIV_HBR2, 0x0); + PhyWrite(Hdptx, 0x0178, 0x7f); + PhyWrite(Hdptx, 0x017c, 0x31); + PhyWrite(Hdptx, 0x0180, 0x21); + PhyWrite(Hdptx, 0x0184, 0x27); + PhyWrite(Hdptx, 0x0188, 0x27); + PhyWrite(Hdptx, 0x0190, 0x7); + PhyWrite(Hdptx, 0x0194, 0x0); + PhyWrite(Hdptx, 0x0198, 0xd); + PhyWrite(Hdptx, 0x019c, 0xd); + PhyWrite(Hdptx, 0x01a4, 0x2); + PhyWrite(Hdptx, 0x01a8, 0x09); + PhyWrite(Hdptx, 0x01b0, 0x3); + PhyWrite(Hdptx, 0x01b4, 0x7); + PhyWrite(Hdptx, 0x01b8, 0x7); + PhyWrite(Hdptx, 0x01c0, 0x8); + PhyWrite(Hdptx, 0x01c4, 0x18); + PhyWrite(Hdptx, 0x01c8, 0x18); + PhyWrite(Hdptx, 0x01d0, 0x0f); + PhyWrite(Hdptx, 0x01dc, 0x08); + PhyWrite(Hdptx, 0x0118, 0xee); + PhyWrite(Hdptx, 0x011c, 0x24); + PhyWrite(Hdptx, 0x0204, 0x01); + PhyUpdateBits(Hdptx, 0x025c, DIG_CLK_SEL, 0x2); + PhyUpdateBits(Hdptx, 0x021c, ANA_PLL_TX_HS_CLK_EN, 0x4); + PhyUpdateBits(Hdptx, 0x0204, ANA_PLL_CD_HSCLK_EAST_EN | + ANA_PLL_CD_HSCLK_WEST_EN, + 0x1); + PhyWrite(Hdptx, 0x0264, 0x84); + PhyWrite(Hdptx, 0x0208, 0x04); + PhyUpdateBits(Hdptx, 0x00f0, ANA_LCPLL_RESERVED7, + 0x80); + PhyWrite(Hdptx, 0x020c, 0x24); + PhyWrite(Hdptx, 0x0214, 0x03); + PhyUpdateBits(Hdptx, 0x0210, PLL_LCRO_CLK_SEL, + 0x20); + PhyUpdateBits(Hdptx, 0x0268, HS_SPEED_SEL, + 0x1); + PhyUpdateBits(Hdptx, 0x026c, LS_SPEED_SEL, + 0x10); +} + +STATIC +INTN +RockchipHdptxPhyDpAuxInit ( + struct RockchipHdptxPhy *Hdptx + ) +{ + PhyUpdateBits(Hdptx, 0x0414, ANA_SB_TX_HLVL_PROG, 0x7); + PhyUpdateBits(Hdptx, 0x0418, ANA_SB_TX_LLVL_PROG, 0x70); + PhyWrite(Hdptx, 0x044c, 0x13); + PhyWrite(Hdptx, 0x0450, 0x12); + PhyWrite(Hdptx, 0x0454, 0x12); + PhyWrite(Hdptx, 0x0458, 0x20); + PhyWrite(Hdptx, 0x045c, 0x04); + PhyWrite(Hdptx, 0x0460, 0x0a); + PhyWrite(Hdptx, 0x0468, 0x03); + PhyWrite(Hdptx, 0x046c, 0x13); + PhyWrite(Hdptx, 0x0470, 0x04); + PhyUpdateBits(Hdptx, 0x0474, SB_TG_OSC_CNT_MIN, 0x67); + PhyUpdateBits(Hdptx, 0x0478, SB_TG_OSC_CNT_MAX, 0x6a); + PhyWrite(Hdptx, 0x047c, 0x16); + PhyUpdateBits(Hdptx, 0x0434, ANA_SB_DMRX_LPBK_DATA, 0x10); + PhyWrite(Hdptx, 0x0440, 0x03); + PhyUpdateBits(Hdptx, 0x043c, ANA_SB_VREG_GAIN_CTRL, 0x0); + PhyUpdateBits(Hdptx, 0x0408, ANA_SB_RXTERM_OFFSP, 0x3); + PhyWrite(Hdptx, 0x040c, 0x1b); + PhyUpdateBits(Hdptx, 0x047c, SB_RCAL_RSTN, 0x2); + PhyUpdateBits(Hdptx, 0x0410, SB_AUX_EN, 0x0); + PhyUpdateBits(Hdptx, 0x0480, SB_AUX_EN_IN, 0x80); + PhyUpdateBits(Hdptx, 0x0410, OVRD_SB_EN, 0x20); + PhyUpdateBits(Hdptx, 0x0408, OVRD_SB_RXTERM_EN, 0x20); + PhyUpdateBits(Hdptx, 0x0410, OVRD_SB_AUX_EN, 0x2); + + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, BGR_EN, 0x21); + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, 0x61); + MicroSecondDelay(10); + + PhyUpdateBits(Hdptx, 0x0410, SB_EN, 0x10); + PhyUpdateBits(Hdptx, 0x0408, SB_RXRERM_EN, 0x10); + PhyWrite(Hdptx, 0x043c, 0xc0); + PhyUpdateBits(Hdptx, 0x0410, SB_AUX_EN, 0x1); + NanoSecondDelay (100000); + GrfWrite(Hdptx, HDPTXPHY_GRF_STATUS0, SB_RDY, 0x1); + MicroSecondDelay(10); + return 0; +} + +STATIC +VOID +RockchipHdptxPhyReset ( + struct RockchipHdptxPhy *Hdptx + ) +{ + UINT32 LANE; + + for (LANE = 0; LANE < 4; LANE++) + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c04), + OVRD_LN_TX_DRV_EI_EN | LN_TX_DRV_EI_EN, + 0x80); + + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, PLL_EN, 0x0); + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, 0x0); + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, BGR_EN, 0x0); +}; + +VOID +RockchipHdptxPhyInit ( + OUT struct RockchipHdptxPhy *Hdptx + ) +{ + RockchipHdptxPhyReset(Hdptx); + + MmioWrite32(0xFD7F0A0C, 0xFFFF8000); + + /* Todo lane-polarity-invert */ + PhyWrite(Hdptx, 0x0C78, 0x00); + PhyWrite(Hdptx, 0x1078, 0x00); + PhyWrite(Hdptx, 0x1478, 0x00); + PhyWrite(Hdptx, 0x1878, 0x00); + + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, HDPTX_MODE_SEL, 0x01); + + /* Todo RockchipHdptxPhyPowerOn */ + PhyWrite(Hdptx, 0x0800, 0x00); + PhyWrite(Hdptx, 0x0818, 0x02); + + RockchipHdptxPhyDpPllInit(Hdptx); + RockchipHdptxPhyDpAuxInit(Hdptx); + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, BGR_EN, 0x21); + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, BIAS_EN, 0x61); + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, PLL_EN, 0xe1); + MmioWrite32(0xFD7F0A0C, 0xFFFF8000); + MmioWrite32(0xFD7F0A0C, 0xFFFF0000); + MmioWrite32(0xFD7F0A10, 0xFFFF0000); +}; + +INTN +RockchipHdptxPhySetRate ( + OUT struct RockchipHdptxPhy *Hdptx, + OUT struct PhyConfigureOptsDp *Dp + ) +{ + UINT32 BW; + + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, PLL_EN, 0x0); + PhyUpdateBits(Hdptx, 0x081c, LANE_EN, 0x0); + DEBUG ((DEBUG_INFO, "[DRIVER]enter %a rate %d Dp->SSC %d \n", + __func__, Dp->LINKRATE, Dp->SSC)); + + switch (Dp->LINKRATE) { + case 1620: + BW = DP_BW_RBR; + break; + case 2700: + BW = DP_BW_HBR; + break; + case 5400: + BW = DP_BW_HBR2; + break; + default: + return -EINVAL; + } + + PhyUpdateBits(Hdptx, 0x0254, DP_TX_LINK_BW, BW); + + if (Dp->SSC) { + PhyUpdateBits(Hdptx, 0x01d0, OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, + 0x3); + PhyUpdateBits(Hdptx, 0x01d4, ANA_ROPLL_SSC_FM_DEVIATION, + 0xc); + PhyUpdateBits(Hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, + 0x7c); + PhyUpdateBits(Hdptx, 0x0264, SSC_EN, + 0x80); + } else { + PhyUpdateBits(Hdptx, 0x01d0, OVRD_ROPLL_SSC_EN | ROPLL_SSC_EN, + 0x3); + PhyUpdateBits(Hdptx, 0x01d4, ANA_ROPLL_SSC_FM_DEVIATION, + 0xe); + PhyUpdateBits(Hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, + 0xd); + PhyUpdateBits(Hdptx, 0x0264, SSC_EN, + 0x20); + PhyUpdateBits(Hdptx, 0x01d8, ANA_ROPLL_SSC_FM_FREQ, + 0x30); + } + PhyWrite(Hdptx, 0x081C, 0x03); + PhyWrite(Hdptx, 0x0C0C, 0x26); + PhyWrite(Hdptx, 0x0C10, 0x11); + PhyWrite(Hdptx, 0x100C, 0x26); + PhyWrite(Hdptx, 0x101C, 0x60); + PhyWrite(Hdptx, 0x140C, 0x00); + PhyWrite(Hdptx, 0x1410, 0x00); + PhyWrite(Hdptx, 0x141C, 0x00); + PhyWrite(Hdptx, 0x1428, 0x00); + PhyWrite(Hdptx, 0x142C, 0x00); + PhyWrite(Hdptx, 0x1434, 0x00); + PhyWrite(Hdptx, 0x1444, 0x00); + PhyWrite(Hdptx, 0x1458, 0x00); + PhyWrite(Hdptx, 0x146C, 0x00); + PhyWrite(Hdptx, 0x180C, 0x00); + PhyWrite(Hdptx, 0x1810, 0x00); + PhyWrite(Hdptx, 0x181C, 0x00); + PhyWrite(Hdptx, 0x1828, 0x00); + PhyWrite(Hdptx, 0x182C, 0x00); + PhyWrite(Hdptx, 0x1834, 0x00); + PhyWrite(Hdptx, 0x1844, 0x00); + PhyWrite(Hdptx, 0x1858, 0x00); + PhyWrite(Hdptx, 0x186C, 0x00); + GrfWrite(Hdptx, HDPTXPHY_GRF_CON0, PLL_EN, 0x80); + GrfWrite(Hdptx, HDPTXPHY_GRF_STATUS0, PLL_LOCK_DONE, 0x8); + PhyUpdateBits(Hdptx, 0x081c, LANE_EN, + GENMASK(Dp->LANES - 1, 0)); + NanoSecondDelay (100000); + GrfWrite(Hdptx, HDPTXPHY_GRF_STATUS0, PHY_RDY, 0x2); + NanoSecondDelay (10000); + return 0; +} + +VOID +RockchipHdptxPhySetVoltage ( + OUT struct RockchipHdptxPhy *Hdptx, + OUT struct PhyConfigureOptsDp *Dp, + UINT8 LANE + ) +{ + CONST struct TxDrvCtrl *ctrl; + DEBUG ((DEBUG_INFO, "[DRIVER]enter %a Dp->LINKRATE %d \n", + __func__, Dp->LINKRATE)); + + switch (Dp->LINKRATE) { + case 1620: + ctrl = &TX_DRV_CTRL_RBR[Dp->VOLTAGE[LANE]][Dp->PRE[LANE]]; + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c44), + LN_TX_SER_40BIT_EN_RBR, + 0x8); + break; + case 2700: + ctrl = &TX_DRV_CTRL_HBR[Dp->VOLTAGE[LANE]][Dp->PRE[LANE]]; + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c2c), + LN_TX_JEQ_EVEN_CTRL_HBR, + 0x70); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c34), + LN_TX_JEQ_ODD_CTRL_HBR, + 0x70); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c44), + LN_TX_SER_40BIT_EN_HBR, + 0x4); + break; + case 5400: + default: + ctrl = &TX_DRV_CTRL_HBR2[Dp->VOLTAGE[LANE]][Dp->PRE[LANE]]; + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c2c), + LN_TX_JEQ_EVEN_CTRL_HBR2, + 0x7); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c34), + LN_TX_JEQ_ODD_CTRL_HBR2, + 0x7); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c44), + LN_TX_SER_40BIT_EN_HBR2, + 0x2); + break; + } + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c0c), + OVRD_LN_TX_DRV_LVL_CTRL | LN_TX_DRV_LVL_CTRL, + 0x2d); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c10), + OVRD_LN_TX_DRV_POST_LVL_CTRL | LN_TX_DRV_POST_LVL_CTRL, + 0x10 | ctrl->Tx_Drv_Post_Lvl_Ctrl + ); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c18), + LN_ANA_TX_DRV_IDRV_IDN_CTRL | + LN_ANA_TX_DRV_IDRV_IUP_CTRL | + LN_ANA_TX_DRV_ACCDRV_EN, + 0x00); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c1c), + LN_ANA_TX_DRV_ACCDRV_POL_SEL | LN_ANA_TX_DRV_ACCDRV_CTRL, + 0x40 | ctrl->Ana_Tx_Drv_Accdrv_Ctrl); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c6c), + LN_ANA_TX_RESERVED, + 0x1); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c58), + LN_ANA_TX_SER_VREG_GAIN_CTRL, + 0x2); + PhyUpdateBits(Hdptx, LANE_REG(LANE, 0x0c40), + LN_ANA_TX_SYNC_LOSS_DET_MODE, + 0x3); +} + +INTN +RockchipHdptxPhySetVoltages ( + OUT struct RockchipHdptxPhy *Hdptx, + OUT struct PhyConfigureOptsDp *Dp + ) +{ + UINT8 LANE; + + for (LANE = 0; LANE < Dp->LANES; LANE++) + RockchipHdptxPhySetVoltage(Hdptx, Dp, LANE); + + return 0; +} + +STATIC +INTN +RockchipHdptxPhyVerifyConfig ( + OUT struct RockchipHdptxPhy *Hdptx, + OUT struct PhyConfigureOptsDp *Dp + ) +{ + INTN i; + + if (Dp->SETRATE) { + switch (Dp->LINKRATE) { + case 1620: + case 2700: + case 5400: + break; + default: + return -EINVAL; + } + } + + switch (Dp->LANES) { + case 1: + case 2: + case 4: + break; + default: + return -EINVAL; + } + + if (Dp->SETVOLTAGES) { + for (i = 0; i < Dp->LANES; i++) { + if (Dp->VOLTAGE[i] > 3 || Dp->PRE[i] > 3) + return -EINVAL; + + if (Dp->VOLTAGE[i] + Dp->PRE[i] > 3) + return -EINVAL; + } + } + + return 0; +} + +INTN +RockchipHdptxPhyConfigure ( + OUT struct RockchipHdptxPhy *Hdptx, + OUT struct PhyConfigureOptsDp *Dp + ) +{ + INTN Ret; + + Ret = RockchipHdptxPhyVerifyConfig(Hdptx, Dp); + if (Ret) { + DEBUG ((DEBUG_WARN, "Invalid params for phy configure\n")); + return Ret; + } + + if (Dp->SETRATE) { + Ret = RockchipHdptxPhySetRate(Hdptx, Dp); + if (Ret) { + DEBUG ((DEBUG_WARN, "Failed to set rate: %d\n",Ret)); + return Ret; + } + } + + if (Dp->SETVOLTAGES) { + Ret = RockchipHdptxPhySetVoltages(Hdptx, Dp); + if (Ret) { + DEBUG ((DEBUG_WARN, "Failed to set Voltages: %d\n",Ret)); + return Ret; + } + } + + return 0; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/PhyRockchipSamsungHdptxHdmi.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/PhyRockchipSamsungHdptxHdmi.c new file mode 100644 index 0000000..9970e46 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/PhyRockchipSamsungHdptxHdmi.c @@ -0,0 +1,1190 @@ +/** @file + + Rockchip HDMI/DP Combo PHY with Samsung IP block + Copyright (c) 2022, Linaro, Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) + +#define GRF_HDPTX_CON0 0x00 +#define LC_REF_CLK_SEL BIT(11) +#define HDPTX_I_PLL_EN BIT(7) +#define HDPTX_I_BIAS_EN BIT(6) +#define HDPTX_I_BGR_EN BIT(5) +#define GRF_HDPTX_STATUS 0x80 +#define HDPTX_O_PLL_LOCK_DONE BIT(3) +#define HDPTX_O_PHY_CLK_RDY BIT(2) +#define HDPTX_O_PHY_RDY BIT(1) +#define HDPTX_O_SB_RDY BIT(0) + +#define CMN_REG0000 0x0000 +#define CMN_REG0001 0x0004 +#define CMN_REG0002 0x0008 +#define CMN_REG0003 0x000C +#define CMN_REG0004 0x0010 +#define CMN_REG0005 0x0014 +#define CMN_REG0006 0x0018 +#define CMN_REG0007 0x001C +#define CMN_REG0008 0x0020 +#define LCPLL_EN_MASK BIT(6) +#define LCPLL_EN(x) UPDATE(x, 4, 4) +#define LCPLL_LCVCO_MODE_EN_MASK BIT(4) +#define LCPLL_LCVCO_MODE_EN(x) UPDATE(x, 4, 4) +#define CMN_REG0009 0x0024 +#define CMN_REG000A 0x0028 +#define CMN_REG000B 0x002C +#define CMN_REG000C 0x0030 +#define CMN_REG000D 0x0034 +#define CMN_REG000E 0x0038 +#define CMN_REG000F 0x003C +#define CMN_REG0010 0x0040 +#define CMN_REG0011 0x0044 +#define CMN_REG0012 0x0048 +#define CMN_REG0013 0x004C +#define CMN_REG0014 0x0050 +#define CMN_REG0015 0x0054 +#define CMN_REG0016 0x0058 +#define CMN_REG0017 0x005C +#define CMN_REG0018 0x0060 +#define CMN_REG0019 0x0064 +#define CMN_REG001A 0x0068 +#define CMN_REG001B 0x006C +#define CMN_REG001C 0x0070 +#define CMN_REG001D 0x0074 +#define CMN_REG001E 0x0078 +#define LCPLL_PI_EN_MASK BIT(5) +#define LCPLL_PI_EN(x) UPDATE(x, 5, 5) +#define LCPLL_100M_CLK_EN_MASK BIT(0) +#define LCPLL_100M_CLK_EN(x) UPDATE(x, 0, 0) +#define CMN_REG001F 0x007C +#define CMN_REG0020 0x0080 +#define CMN_REG0021 0x0084 +#define CMN_REG0022 0x0088 +#define CMN_REG0023 0x008C +#define CMN_REG0024 0x0090 +#define CMN_REG0025 0x0094 +#define LCPLL_PMS_IQDIV_RSTN BIT(4) +#define CMN_REG0026 0x0098 +#define CMN_REG0027 0x009C +#define CMN_REG0028 0x00A0 +#define LCPLL_SDC_FRAC_EN BIT(2) +#define LCPLL_SDC_FRAC_RSTN BIT(0) +#define CMN_REG0029 0x00A4 +#define CMN_REG002A 0x00A8 +#define CMN_REG002B 0x00AC +#define CMN_REG002C 0x00B0 +#define CMN_REG002D 0x00B4 +#define LCPLL_SDC_N_MASK GENMASK(3, 1) +#define LCPLL_SDC_N(x) UPDATE(x, 3, 1) +#define CMN_REG002E 0x00B8 +#define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0) +#define LCPLL_SDC_NUMBERATOR(x) UPDATE(x, 5, 0) +#define CMN_REG002F 0x00BC +#define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2) +#define LCPLL_SDC_DENOMINATOR(x) UPDATE(x, 7, 2) +#define LCPLL_SDC_NDIV_RSTN BIT(0) +#define CMN_REG0030 0x00C0 +#define CMN_REG0031 0x00C4 +#define CMN_REG0032 0x00C8 +#define CMN_REG0033 0x00CC +#define CMN_REG0034 0x00D0 +#define CMN_REG0035 0x00D4 +#define CMN_REG0036 0x00D8 +#define CMN_REG0037 0x00DC +#define CMN_REG0038 0x00E0 +#define CMN_REG0039 0x00E4 +#define CMN_REG003A 0x00E8 +#define CMN_REG003B 0x00EC +#define CMN_REG003C 0x00F0 +#define CMN_REG003D 0x00F4 +#define ROPLL_LCVCO_EN BIT(4) +#define CMN_REG003E 0x00F8 +#define CMN_REG003F 0x00FC +#define CMN_REG0040 0x0100 +#define CMN_REG0041 0x0104 +#define CMN_REG0042 0x0108 +#define CMN_REG0043 0x010C +#define CMN_REG0044 0x0110 +#define CMN_REG0045 0x0114 +#define CMN_REG0046 0x0118 +#define CMN_REG0047 0x011C +#define CMN_REG0048 0x0120 +#define CMN_REG0049 0x0124 +#define CMN_REG004A 0x0128 +#define CMN_REG004B 0x012C +#define CMN_REG004C 0x0130 +#define CMN_REG004D 0x0134 +#define CMN_REG004E 0x0138 +#define ROPLL_PI_EN BIT(5) +#define CMN_REG004F 0x013C +#define CMN_REG0050 0x0140 +#define CMN_REG0051 0x0144 +#define CMN_REG0052 0x0148 +#define CMN_REG0053 0x014C +#define CMN_REG0054 0x0150 +#define CMN_REG0055 0x0154 +#define CMN_REG0056 0x0158 +#define CMN_REG0057 0x015C +#define CMN_REG0058 0x0160 +#define CMN_REG0059 0x0164 +#define CMN_REG005A 0x0168 +#define CMN_REG005B 0x016C +#define CMN_REG005C 0x0170 +#define ROPLL_PMS_IQDIV_RSTN BIT(5) +#define CMN_REG005D 0x0174 +#define CMN_REG005E 0x0178 +#define ROPLL_SDM_EN_MASK BIT(6) +#define ROPLL_SDM_EN(x) UPDATE(x, 6, 6) +#define ROPLL_SDM_FRAC_EN_RBR BIT(3) +#define ROPLL_SDM_FRAC_EN_HBR BIT(2) +#define ROPLL_SDM_FRAC_EN_HBR2 BIT(1) +#define ROPLL_SDM_FRAC_EN_HBR3 BIT(0) +#define CMN_REG005F 0x017C +#define CMN_REG0060 0x0180 +#define CMN_REG0061 0x0184 +#define CMN_REG0062 0x0188 +#define CMN_REG0063 0x018C +#define CMN_REG0064 0x0190 +#define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3) +#define ROPLL_SDM_NUM_SIGN_RBR(x) UPDATE(x, 3, 3) +#define CMN_REG0065 0x0194 +#define CMN_REG0066 0x0198 +#define CMN_REG0067 0x019C +#define CMN_REG0068 0x01A0 +#define CMN_REG0069 0x01A4 +#define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0) +#define ROPLL_SDC_N_RBR(x) UPDATE(x, 2, 0) +#define CMN_REG006A 0x01A8 +#define CMN_REG006B 0x01AC +#define CMN_REG006C 0x01B0 +#define CMN_REG006D 0x01B4 +#define CMN_REG006E 0x01B8 +#define CMN_REG006F 0x01BC +#define CMN_REG0070 0x01C0 +#define CMN_REG0071 0x01C4 +#define CMN_REG0072 0x01C8 +#define CMN_REG0073 0x01CC +#define CMN_REG0074 0x01D0 +#define ROPLL_SDC_NDIV_RSTN BIT(2) +#define ROPLL_SSC_EN BIT(0) +#define CMN_REG0075 0x01D4 +#define CMN_REG0076 0x01D8 +#define CMN_REG0077 0x01DC +#define CMN_REG0078 0x01E0 +#define CMN_REG0079 0x01E4 +#define CMN_REG007A 0x01E8 +#define CMN_REG007B 0x01EC +#define CMN_REG007C 0x01F0 +#define CMN_REG007D 0x01F4 +#define CMN_REG007E 0x01F8 +#define CMN_REG007F 0x01FC +#define CMN_REG0080 0x0200 +#define CMN_REG0081 0x0204 +#define OVRD_PLL_CD_CLK_EN BIT(8) +#define PLL_CD_HSCLK_EAST_EN BIT(0) +#define CMN_REG0082 0x0208 +#define CMN_REG0083 0x020C +#define CMN_REG0084 0x0210 +#define CMN_REG0085 0x0214 +#define CMN_REG0086 0x0218 +#define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) +#define PLL_PCG_POSTDIV_SEL(x) UPDATE(x, 7, 4) +#define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) +#define PLL_PCG_CLK_SEL(x) UPDATE(x, 3, 1) +#define PLL_PCG_CLK_EN BIT(0) +#define CMN_REG0087 0x021C +#define PLL_FRL_MODE_EN BIT(3) +#define PLL_TX_HS_CLK_EN BIT(2) +#define CMN_REG0088 0x0220 +#define CMN_REG0089 0x0224 +#define LCPLL_ALONE_MODE BIT(1) +#define CMN_REG008A 0x0228 +#define CMN_REG008B 0x022C +#define CMN_REG008C 0x0230 +#define CMN_REG008D 0x0234 +#define CMN_REG008E 0x0238 +#define CMN_REG008F 0x023C +#define CMN_REG0090 0x0240 +#define CMN_REG0091 0x0244 +#define CMN_REG0092 0x0248 +#define CMN_REG0093 0x024C +#define CMN_REG0094 0x0250 +#define CMN_REG0095 0x0254 +#define CMN_REG0096 0x0258 +#define CMN_REG0097 0x025C +#define DIG_CLK_SEL BIT(1) +#define ROPLL_REF BIT(1) +#define LCPLL_REF 0 +#define CMN_REG0098 0x0260 +#define CMN_REG0099 0x0264 +#define CMN_ROPLL_ALONE_MODE BIT(2) +#define ROPLL_ALONE_MODE BIT(2) +#define CMN_REG009A 0x0268 +#define HS_SPEED_SEL BIT(0) +#define DIV_10_CLOCK BIT(0) +#define CMN_REG009B 0x026C +#define IS_SPEED_SEL BIT(4) +#define LINK_SYMBOL_CLOCK BIT(4) +#define LINK_SYMBOL_CLOCK1_2 0 +#define CMN_REG009C 0x0270 +#define CMN_REG009D 0x0274 +#define CMN_REG009E 0x0278 +#define CMN_REG009F 0x027C +#define CMN_REG00A0 0x0280 +#define CMN_REG00A1 0x0284 +#define CMN_REG00A2 0x0288 +#define CMN_REG00A3 0x028C +#define CMN_REG00AD 0x0290 +#define CMN_REG00A5 0x0294 +#define CMN_REG00A6 0x0298 +#define CMN_REG00A7 0x029C +#define SB_REG0100 0x0400 +#define SB_REG0101 0x0404 +#define SB_REG0102 0x0408 +#define OVRD_SB_RXTERM_EN_MASK BIT(5) +#define OVRD_SB_RXTERM_EN(x) UPDATE(x, 5, 5) +#define SB_RXTERM_EN_MASK BIT(4) +#define SB_RXTERM_EN(x) UPDATE(x, 4, 4) +#define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0) +#define ANA_SB_RXTERM_OFFSP(x) UPDATE(x, 3, 0) +#define SB_REG0103 0x040C +#define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3) +#define ANA_SB_RXTERM_OFFSN(x) UPDATE(x, 6, 3) +#define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1) +#define OVRD_SB_RX_RESCAL_DONE(x) UPDATE(x, 1, 1) +#define SB_RX_RESCAL_DONE_MASK BIT(0) +#define SB_RX_RESCAL_DONE(x) UPDATE(x, 0, 0) +#define SB_REG0104 0x0410 +#define OVRD_SB_EN_MASK BIT(5) +#define OVRD_SB_EN(x) UPDATE(x, 5, 5) +#define SB_EN_MASK BIT(4) +#define SB_EN(x) UPDATE(x, 4, 4) +#define SB_REG0105 0x0414 +#define OVRD_SB_EARC_CMDC_EN_MASK BIT(6) +#define OVRD_SB_EARC_CMDC_EN(x) UPDATE(x, 6, 6) +#define SB_EARC_CMDC_EN_MASK BIT(5) +#define SB_EARC_CMDC_EN(x) UPDATE(x, 5, 5) +#define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0) +#define ANA_SB_TX_HLVL_PROG(x) UPDATE(x, 2, 0) +#define SB_REG0106 0x0418 +#define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4) +#define ANA_SB_TX_LLVL_PROG(x) UPDATE(x, 6, 4) +#define SB_REG0107 0x041C +#define SB_REG0108 0x0420 +#define SB_REG0109 0x0424 +#define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0) +#define ANA_SB_DMRX_AFC_DIV_RATIO(x) UPDATE(x, 2, 0) +#define SB_REG010A 0x0428 +#define SB_REG010B 0x042C +#define SB_REG010C 0x0430 +#define SB_REG010D 0x0434 +#define SB_REG010E 0x0438 +#define SB_REG010F 0x043C +#define OVRD_SB_VREG_EN_MASK BIT(7) +#define OVRD_SB_VREG_EN(x) UPDATE(x, 7, 7) +#define SB_VREG_EN_MASK BIT(6) +#define SB_VREG_EN(x) UPDATE(x, 6, 6) +#define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5) +#define OVRD_SB_VREG_LPF_BYPASS(x) UPDATE(x, 5, 5) +#define SB_VREG_LPF_BYPASS_MASK BIT(4) +#define SB_VREG_LPF_BYPASS(x) UPDATE(x, 4, 4) +#define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0) +#define ANA_SB_VREG_GAIN_CTRL(x) UPDATE(x, 3, 0) +#define SB_REG0110 0x0440 +#define ANA_SB_VREG_REF_SEL_MASK BIT(0) +#define ANA_SB_VREG_REF_SEL(x) UPDATE(x, 0, 0) +#define SB_REG0111 0x0444 +#define SB_REG0112 0x0448 +#define SB_REG0113 0x044C +#define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4) +#define SB_RX_RCAL_OPT_CODE(x) UPDATE(x, 5, 4) +#define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0) +#define SB_RX_RTERM_CTRL(x) UPDATE(x, 3, 0) +#define SB_REG0114 0x0450 +#define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3) +#define SB_TG_SB_EN_DELAY_TIME(x) UPDATE(x, 5, 3) +#define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0) +#define SB_TG_RXTERM_EN_DELAY_TIME(x) UPDATE(x, 2, 0) +#define SB_REG0115 0x0454 +#define SB_READY_DELAY_TIME_MASK GENMASK(5, 3) +#define SB_READY_DELAY_TIME(x) UPDATE(x, 5, 3) +#define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0) +#define SB_TG_OSC_EN_DELAY_TIME(x) UPDATE(x, 2, 0) +#define SB_REG0116 0x0458 +#define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4) +#define AFC_RSTN_DELAY_TIME(x) UPDATE(x, 6, 4) +#define SB_REG0117 0x045C +#define FAST_PULSE_TIME_MASK GENMASK(3, 0) +#define FAST_PULSE_TIME(x) UPDATE(x, 3, 0) +#define SB_REG0118 0x0460 +#define SB_REG0119 0x0464 +#define SB_REG011A 0x0468 +#define SB_REG011B 0x046C +#define SB_EARC_SIG_DET_BYPASS_MASK BIT(4) +#define SB_EARC_SIG_DET_BYPASS(x) UPDATE(x, 4, 4) +#define SB_AFC_TOL_MASK GENMASK(3, 0) +#define SB_AFC_TOL(x) UPDATE(x, 3, 0) +#define SB_REG011C 0x0470 +#define SB_REG011D 0x0474 +#define SB_REG011E 0x0478 +#define SB_REG011F 0x047C +#define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2) +#define SB_PWM_AFC_CTRL(x) UPDATE(x, 7, 2) +#define SB_RCAL_RSTN_MASK BIT(1) +#define SB_RCAL_RSTN(x) UPDATE(x, 1, 1) +#define SB_REG0120 0x0480 +#define SB_EARC_EN_MASK BIT(1) +#define SB_EARC_EN(x) UPDATE(x, 1, 1) +#define SB_EARC_AFC_EN_MASK BIT(2) +#define SB_EARC_AFC_EN(x) UPDATE(x, 2, 2) +#define SB_REG0121 0x0484 +#define SB_REG0122 0x0488 +#define SB_REG0123 0x048C +#define OVRD_SB_READY_MASK BIT(5) +#define OVRD_SB_READY(x) UPDATE(x, 5, 5) +#define SB_READY_MASK BIT(4) +#define SB_READY(x) UPDATE(x, 4, 4) +#define SB_REG0124 0x0490 +#define SB_REG0125 0x0494 +#define SB_REG0126 0x0498 +#define SB_REG0127 0x049C +#define SB_REG0128 0x04A0 +#define SB_REG0129 0x04AD +#define LNTOP_REG0200 0x0800 +#define PROTOCOL_SEL BIT(2) +#define HDMI_MODE BIT(2) +#define HDMI_TMDS_FRL_SEL BIT(1) +#define LNTOP_REG0201 0x0804 +#define LNTOP_REG0202 0x0808 +#define LNTOP_REG0203 0x080C +#define LNTOP_REG0204 0x0810 +#define LNTOP_REG0205 0x0814 +#define LNTOP_REG0206 0x0818 +#define DATA_BUS_WIDTH (0x3 << 1) +#define WIDTH_40BIT (0x3 << 1) +#define WIDTH_36BIT (0x2 << 1) +#define DATA_BUS_SEL BIT(0) +#define DATA_BUS_36_40 BIT(0) +#define LNTOP_REG0207 0x081C +#define LANE_EN 0xf +#define ALL_LANE_EN 0xf +#define LNTOP_REG0208 0x0820 +#define LNTOP_REG0209 0x0824 +#define LNTOP_REG020A 0x0828 +#define LNTOP_REG020B 0x082C +#define LNTOP_REG020C 0x0830 +#define LNTOP_REG020D 0x0834 +#define LNTOP_REG020E 0x0838 +#define LNTOP_REG020F 0x083C +#define LNTOP_REG0210 0x0840 +#define LNTOP_REG0211 0x0844 +#define LNTOP_REG0212 0x0848 +#define LNTOP_REG0213 0x084C +#define LNTOP_REG0214 0x0850 +#define LNTOP_REG0215 0x0854 +#define LNTOP_REG0216 0x0858 +#define LNTOP_REG0217 0x085C +#define LNTOP_REG0218 0x0860 +#define LNTOP_REG0219 0x0864 +#define LNTOP_REG021A 0x0868 +#define LNTOP_REG021B 0x086C +#define LNTOP_REG021C 0x0870 +#define LNTOP_REG021D 0x0874 +#define LNTOP_REG021E 0x0878 +#define LNTOP_REG021F 0x087C +#define LNTOP_REG0220 0x0880 +#define LNTOP_REG0221 0x0884 +#define LNTOP_REG0222 0x0888 +#define LNTOP_REG0223 0x088C +#define LNTOP_REG0224 0x0890 +#define LNTOP_REG0225 0x0894 +#define LNTOP_REG0226 0x0898 +#define LNTOP_REG0227 0x089C +#define LNTOP_REG0228 0x08A0 +#define LNTOP_REG0229 0x08A4 +#define LANE_REG0300 0x0C00 +#define LANE_REG0301 0x0C04 +#define LANE_REG0302 0x0C08 +#define LANE_REG0303 0x0C0C +#define LANE_REG0304 0x0C10 +#define LANE_REG0305 0x0C14 +#define LANE_REG0306 0x0C18 +#define LANE_REG0307 0x0C1C +#define LANE_REG0308 0x0C20 +#define LANE_REG0309 0x0C24 +#define LANE_REG030A 0x0C28 +#define LANE_REG030B 0x0C2C +#define LANE_REG030C 0x0C30 +#define LANE_REG030D 0x0C34 +#define LANE_REG030E 0x0C38 +#define LANE_REG030F 0x0C3C +#define LANE_REG0310 0x0C40 +#define LANE_REG0311 0x0C44 +#define LANE_REG0312 0x0C48 +#define LN0_TX_SER_RATE_SEL_RBR BIT(5) +#define LN0_TX_SER_RATE_SEL_HBR BIT(4) +#define LN0_TX_SER_RATE_SEL_HBR2 BIT(3) +#define LN0_TX_SER_RATE_SEL_HBR3 BIT(2) +#define LANE_REG0313 0x0C4C +#define LANE_REG0314 0x0C50 +#define LANE_REG0315 0x0C54 +#define LANE_REG0316 0x0C58 +#define LANE_REG0317 0x0C5C +#define LANE_REG0318 0x0C60 +#define LANE_REG0319 0x0C64 +#define LANE_REG031A 0x0C68 +#define LANE_REG031B 0x0C6C +#define LANE_REG031C 0x0C70 +#define LANE_REG031D 0x0C74 +#define LANE_REG031E 0x0C78 +#define LANE_REG031F 0x0C7C +#define LANE_REG0320 0x0C80 +#define LANE_REG0321 0x0C84 +#define LANE_REG0322 0x0C88 +#define LANE_REG0323 0x0C8C +#define LANE_REG0324 0x0C90 +#define LANE_REG0325 0x0C94 +#define LANE_REG0326 0x0C98 +#define LANE_REG0327 0x0C9C +#define LANE_REG0328 0x0CA0 +#define LANE_REG0329 0x0CA4 +#define LANE_REG032A 0x0CA8 +#define LANE_REG032B 0x0CAC +#define LANE_REG032C 0x0CB0 +#define LANE_REG032D 0x0CB4 +#define LANE_REG0400 0x1000 +#define LANE_REG0401 0x1004 +#define LANE_REG0402 0x1008 +#define LANE_REG0403 0x100C +#define LANE_REG0404 0x1010 +#define LANE_REG0405 0x1014 +#define LANE_REG0406 0x1018 +#define LANE_REG0407 0x101C +#define LANE_REG0408 0x1020 +#define LANE_REG0409 0x1024 +#define LANE_REG040A 0x1028 +#define LANE_REG040B 0x102C +#define LANE_REG040C 0x1030 +#define LANE_REG040D 0x1034 +#define LANE_REG040E 0x1038 +#define LANE_REG040F 0x103C +#define LANE_REG0410 0x1040 +#define LANE_REG0411 0x1044 +#define LANE_REG0412 0x1048 +#define LN1_TX_SER_RATE_SEL_RBR BIT(5) +#define LN1_TX_SER_RATE_SEL_HBR BIT(4) +#define LN1_TX_SER_RATE_SEL_HBR2 BIT(3) +#define LN1_TX_SER_RATE_SEL_HBR3 BIT(2) +#define LANE_REG0413 0x104C +#define LANE_REG0414 0x1050 +#define LANE_REG0415 0x1054 +#define LANE_REG0416 0x1058 +#define LANE_REG0417 0x105C +#define LANE_REG0418 0x1060 +#define LANE_REG0419 0x1064 +#define LANE_REG041A 0x1068 +#define LANE_REG041B 0x106C +#define LANE_REG041C 0x1070 +#define LANE_REG041D 0x1074 +#define LANE_REG041E 0x1078 +#define LANE_REG041F 0x107C +#define LANE_REG0420 0x1080 +#define LANE_REG0421 0x1084 +#define LANE_REG0422 0x1088 +#define LANE_REG0423 0x108C +#define LANE_REG0424 0x1090 +#define LANE_REG0425 0x1094 +#define LANE_REG0426 0x1098 +#define LANE_REG0427 0x109C +#define LANE_REG0428 0x10A0 +#define LANE_REG0429 0x10A4 +#define LANE_REG042A 0x10A8 +#define LANE_REG042B 0x10AC +#define LANE_REG042C 0x10B0 +#define LANE_REG042D 0x10B4 +#define LANE_REG0500 0x1400 +#define LANE_REG0501 0x1404 +#define LANE_REG0502 0x1408 +#define LANE_REG0503 0x140C +#define LANE_REG0504 0x1410 +#define LANE_REG0505 0x1414 +#define LANE_REG0506 0x1418 +#define LANE_REG0507 0x141C +#define LANE_REG0508 0x1420 +#define LANE_REG0509 0x1424 +#define LANE_REG050A 0x1428 +#define LANE_REG050B 0x142C +#define LANE_REG050C 0x1430 +#define LANE_REG050D 0x1434 +#define LANE_REG050E 0x1438 +#define LANE_REG050F 0x143C +#define LANE_REG0510 0x1440 +#define LANE_REG0511 0x1444 +#define LANE_REG0512 0x1448 +#define LN2_TX_SER_RATE_SEL_RBR BIT(5) +#define LN2_TX_SER_RATE_SEL_HBR BIT(4) +#define LN2_TX_SER_RATE_SEL_HBR2 BIT(3) +#define LN2_TX_SER_RATE_SEL_HBR3 BIT(2) +#define LANE_REG0513 0x144C +#define LANE_REG0514 0x1450 +#define LANE_REG0515 0x1454 +#define LANE_REG0516 0x1458 +#define LANE_REG0517 0x145C +#define LANE_REG0518 0x1460 +#define LANE_REG0519 0x1464 +#define LANE_REG051A 0x1468 +#define LANE_REG051B 0x146C +#define LANE_REG051C 0x1470 +#define LANE_REG051D 0x1474 +#define LANE_REG051E 0x1478 +#define LANE_REG051F 0x147C +#define LANE_REG0520 0x1480 +#define LANE_REG0521 0x1484 +#define LANE_REG0522 0x1488 +#define LANE_REG0523 0x148C +#define LANE_REG0524 0x1490 +#define LANE_REG0525 0x1494 +#define LANE_REG0526 0x1498 +#define LANE_REG0527 0x149C +#define LANE_REG0528 0x14A0 +#define LANE_REG0529 0x14AD +#define LANE_REG052A 0x14A8 +#define LANE_REG052B 0x14AC +#define LANE_REG052C 0x14B0 +#define LANE_REG052D 0x14B4 +#define LANE_REG0600 0x1800 +#define LANE_REG0601 0x1804 +#define LANE_REG0602 0x1808 +#define LANE_REG0603 0x180C +#define LANE_REG0604 0x1810 +#define LANE_REG0605 0x1814 +#define LANE_REG0606 0x1818 +#define LANE_REG0607 0x181C +#define LANE_REG0608 0x1820 +#define LANE_REG0609 0x1824 +#define LANE_REG060A 0x1828 +#define LANE_REG060B 0x182C +#define LANE_REG060C 0x1830 +#define LANE_REG060D 0x1834 +#define LANE_REG060E 0x1838 +#define LANE_REG060F 0x183C +#define LANE_REG0610 0x1840 +#define LANE_REG0611 0x1844 +#define LANE_REG0612 0x1848 +#define LN3_TX_SER_RATE_SEL_RBR BIT(5) +#define LN3_TX_SER_RATE_SEL_HBR BIT(4) +#define LN3_TX_SER_RATE_SEL_HBR2 BIT(3) +#define LN3_TX_SER_RATE_SEL_HBR3 BIT(2) +#define LANE_REG0613 0x184C +#define LANE_REG0614 0x1850 +#define LANE_REG0615 0x1854 +#define LANE_REG0616 0x1858 +#define LANE_REG0617 0x185C +#define LANE_REG0618 0x1860 +#define LANE_REG0619 0x1864 +#define LANE_REG061A 0x1868 +#define LANE_REG061B 0x186C +#define LANE_REG061C 0x1870 +#define LANE_REG061D 0x1874 +#define LANE_REG061E 0x1878 +#define LANE_REG061F 0x187C +#define LANE_REG0620 0x1880 +#define LANE_REG0621 0x1884 +#define LANE_REG0622 0x1888 +#define LANE_REG0623 0x188C +#define LANE_REG0624 0x1890 +#define LANE_REG0625 0x1894 +#define LANE_REG0626 0x1898 +#define LANE_REG0627 0x189C +#define LANE_REG0628 0x18A0 +#define LANE_REG0629 0x18A4 +#define LANE_REG062A 0x18A8 +#define LANE_REG062B 0x18AC +#define LANE_REG062C 0x18B0 +#define LANE_REG062D 0x18B4 + +#define HDMI20_MAX_RATE 600000000 +#define DATA_RATE_MASK 0xFFFFFFF +#define COLOR_DEPTH_MASK BIT(31) +#define HDMI_MODE_MASK BIT(30) +#define HDMI_EARC_MASK BIT(29) + +#define FRL_8G_4LANES 3200000000ULL +#define FRL_6G_3LANES 1800000000 +#define FRL_3G_3LANES 900000000 + +struct RoPllConfig { + UINT32 Bit_Rate; + UINT8 Pms_Mdiv; + UINT8 Pms_Mdiv_Afc; + UINT8 Pms_Pdiv; + UINT8 Pms_Refdiv; + UINT8 Pms_Sdiv; + UINT8 Pms_Iqdiv_Rstn; + UINT8 Ref_Clk_Sel; + UINT8 Sdm_En; + UINT8 Sdm_Rstn; + UINT8 Sdc_Frac_En; + UINT8 Sdc_Rstn; + UINT8 Sdm_Clk_Div; + UINT8 Sdm_Deno; + UINT8 Sdm_Num_Sign; + UINT8 Sdm_Num; + UINT8 Sdc_N; + UINT8 Sdc_Num; + UINT8 Sdc_Deno; + UINT8 Sdc_Ndiv_Rstn; + UINT8 Ssc_En; + UINT8 Ssc_Fm_Dev; + UINT8 Ssc_Fm_Freq; + UINT8 Ssc_Clk_Div_Sel; + UINT8 Ana_Cpp_Ctrl; + UINT8 Ana_Lpf_C_Sel; + UINT8 Cd_Tx_Ser_Rate_Sel; +}; + +STATIC CONST struct RoPllConfig ROPLL_TMDS_CONFIG[] = { + { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, + 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, + 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 1462500, 122, 122, 1, 1, 4, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 1, 0, 1, + 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, + 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, + 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 855000, 125, 125, 1, 1, 6, 1, 1, 1, 1, 1, 1, 1, 80, 1, 16, 2, 0, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 1, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, + 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, + 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, + 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, + }, + { ~0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + }, +}; + +INLINE +VOID +PhyWrite ( + OUT struct RockchipHdptxPhyHdmi *Hdptx, + UINTN Reg, + UINTN Val + ) +{ + UINT32 Shift; + + if (!Hdptx->Id) + Shift = HDMI0TX_PHY_BASE; + else + Shift = HDMI1TX_PHY_BASE; + + MmioWrite32(Shift + Reg, Val ); +} + +INLINE +UINTN +PhyRead ( + OUT struct RockchipHdptxPhyHdmi *Hdptx, + UINTN Reg + ) +{ + UINT32 Shift; + + if(!Hdptx->Id) + Shift = HDMI0TX_PHY_BASE; + else + Shift = HDMI1TX_PHY_BASE; + + return MmioRead32(Shift + Reg); +} + +STATIC +VOID +PhyUpdateBits ( + OUT struct RockchipHdptxPhyHdmi *Hdptx, + UINTN Reg, + UINTN Mask, + UINTN Val + ) +{ + UINTN Orig, Tmp; + + Orig = PhyRead(Hdptx, Reg); + Tmp = Orig & ~Mask; + Tmp |= Val & Mask; + PhyWrite(Hdptx, Reg, Tmp); +}; + +STATIC +VOID +GrfWrite ( + OUT struct RockchipHdptxPhyHdmi *Hdptx, + UINTN Reg, + UINTN Mask, + UINTN Val + ) +{ + UINT32 TempVal = 0; + UINT32 Shift; + + if (!Hdptx->Id) + Shift = HDPTXPHY0_GRF_BASE; + else + Shift = HDPTXPHY1_GRF_BASE; + + TempVal = (Mask << 16) | (Val & Mask); + MmioWrite32(Shift + Reg, TempVal); +}; + +STATIC +UINT32 +GrfRead ( + OUT struct RockchipHdptxPhyHdmi *Hdptx, + UINTN Reg + ) +{ + UINT32 Shift; + + if (!Hdptx->Id) + Shift = HDPTXPHY0_GRF_BASE; + else + Shift = HDPTXPHY1_GRF_BASE; + + return MmioRead32(Shift + Reg); +}; + +STATIC +VOID +CruWrite ( + UINTN Reg, + UINTN Mask, + UINTN Val + ) +{ + UINT32 TempVal = 0; + + TempVal = (Mask << 16) | (Val & Mask); + MmioWrite32(PMU1CRU_BASE + Reg, TempVal); +}; + +VOID +HdptxPrePowerUp ( + OUT struct RockchipHdptxPhyHdmi *Hdptx + ) +{ + UINT32 Val = 0; + + /* assert lane/cmn/init reset */ + if (!Hdptx->Id) { + CruWrite(PMU1CRU_SOFTRST_CON03, 0x3800, 0x3800); + } else { + CruWrite(PMU1CRU_SOFTRST_CON03, BIT(15), BIT(15)); + CruWrite(PMU1CRU_SOFTRST_CON04, 0x3, 0x3); + } + + Val = HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; + GrfWrite(Hdptx, GRF_HDPTX_CON0, Val, 0); +} + +STATIC +UINT32 +HdptxPostEnablePll ( + OUT struct RockchipHdptxPhyHdmi *Hdptx + ) +{ + UINT32 Val = 0; + UINT32 i; + + Val = HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; + GrfWrite(Hdptx, GRF_HDPTX_CON0, Val, Val); + NanoSecondDelay (10000); + /* deassert init reset */ + if (!Hdptx->Id) + CruWrite(PMU1CRU_SOFTRST_CON03, BIT(11), 0); + else + CruWrite(PMU1CRU_SOFTRST_CON03, BIT(15), 0); + NanoSecondDelay (10000); + Val = HDPTX_I_PLL_EN; + GrfWrite(Hdptx, GRF_HDPTX_CON0, Val, Val); + NanoSecondDelay (10000); + /* deassert cmn reset */ + if (!Hdptx->Id) + CruWrite(PMU1CRU_SOFTRST_CON03, BIT(12), 0); + else + CruWrite(PMU1CRU_SOFTRST_CON04, BIT(0), 0); + + Val = 0; + for (i = 0; i < 50; i++) { + Val = GrfRead(Hdptx, GRF_HDPTX_STATUS); + + if (Val & HDPTX_O_PHY_CLK_RDY) + break; + NanoSecondDelay (20000); + } + + if (i == 50) { + DEBUG ((DEBUG_INIT, "%a hdptx phy pll can't lock!\n", __func__)); + return -EINVAL; + } + + DEBUG ((DEBUG_INIT, "%a hdptx phy pll locked!\n", __func__)); + + return 0; +} + +UINT32 +HdptxRopllCmnConfig ( + OUT struct RockchipHdptxPhyHdmi *Hdptx + ) +{ + CONST struct RoPllConfig *Cfg = ROPLL_TMDS_CONFIG; + + for (; Cfg->Bit_Rate != ~0; Cfg++) + if (Cfg->Bit_Rate == 1485000) + break; + DEBUG ((DEBUG_INIT, "%a HdptxRopllCmnConfig start\n", __func__)); + HdptxPrePowerUp(Hdptx); + DEBUG ((DEBUG_INIT, "%a HdptxRopllCmnConfig %d\n", __func__, Cfg->Bit_Rate)); + GrfWrite(Hdptx, GRF_HDPTX_CON0, LC_REF_CLK_SEL, 0); + + PhyWrite(Hdptx, CMN_REG0008, 0x00); + PhyWrite(Hdptx, CMN_REG0009, 0x0c); + PhyWrite(Hdptx, CMN_REG000A, 0x83); + PhyWrite(Hdptx, CMN_REG000B, 0x06); + PhyWrite(Hdptx, CMN_REG000C, 0x20); + PhyWrite(Hdptx, CMN_REG000D, 0xb8); + PhyWrite(Hdptx, CMN_REG000E, 0x0f); + PhyWrite(Hdptx, CMN_REG000F, 0x0f); + PhyWrite(Hdptx, CMN_REG0010, 0x04); + PhyWrite(Hdptx, CMN_REG0011, 0x01); + PhyWrite(Hdptx, CMN_REG0012, 0x26); + PhyWrite(Hdptx, CMN_REG0013, 0x22); + PhyWrite(Hdptx, CMN_REG0014, 0x24); + PhyWrite(Hdptx, CMN_REG0015, 0x77); + PhyWrite(Hdptx, CMN_REG0016, 0x08); + PhyWrite(Hdptx, CMN_REG0017, 0x20); + PhyWrite(Hdptx, CMN_REG0018, 0x04); + PhyWrite(Hdptx, CMN_REG0019, 0x48); + PhyWrite(Hdptx, CMN_REG001A, 0x01); + PhyWrite(Hdptx, CMN_REG001B, 0x00); + PhyWrite(Hdptx, CMN_REG001C, 0x01); + PhyWrite(Hdptx, CMN_REG001D, 0x64); + PhyWrite(Hdptx, CMN_REG001E, 0x14); + PhyWrite(Hdptx, CMN_REG001F, 0x00); + PhyWrite(Hdptx, CMN_REG0020, 0x00); + PhyWrite(Hdptx, CMN_REG0021, 0x00); + PhyWrite(Hdptx, CMN_REG0022, 0x11); + PhyWrite(Hdptx, CMN_REG0023, 0x00); + PhyWrite(Hdptx, CMN_REG0024, 0x00); + PhyWrite(Hdptx, CMN_REG0025, 0x53); + PhyWrite(Hdptx, CMN_REG0026, 0x00); + PhyWrite(Hdptx, CMN_REG0027, 0x00); + PhyWrite(Hdptx, CMN_REG0028, 0x01); + PhyWrite(Hdptx, CMN_REG0029, 0x01); + PhyWrite(Hdptx, CMN_REG002A, 0x00); + PhyWrite(Hdptx, CMN_REG002B, 0x00); + PhyWrite(Hdptx, CMN_REG002C, 0x00); + PhyWrite(Hdptx, CMN_REG002D, 0x00); + PhyWrite(Hdptx, CMN_REG002E, 0x04); + PhyWrite(Hdptx, CMN_REG002F, 0x00); + PhyWrite(Hdptx, CMN_REG0030, 0x20); + PhyWrite(Hdptx, CMN_REG0031, 0x30); + PhyWrite(Hdptx, CMN_REG0032, 0x0b); + PhyWrite(Hdptx, CMN_REG0033, 0x23); + PhyWrite(Hdptx, CMN_REG0034, 0x00); + PhyWrite(Hdptx, CMN_REG0035, 0x00); + PhyWrite(Hdptx, CMN_REG0038, 0x00); + PhyWrite(Hdptx, CMN_REG0039, 0x00); + PhyWrite(Hdptx, CMN_REG003A, 0x00); + PhyWrite(Hdptx, CMN_REG003B, 0x00); + PhyWrite(Hdptx, CMN_REG003C, 0x80); + PhyWrite(Hdptx, CMN_REG003D, 0x40); + PhyWrite(Hdptx, CMN_REG003E, 0x0c); + PhyWrite(Hdptx, CMN_REG003F, 0x83); + PhyWrite(Hdptx, CMN_REG0040, 0x06); + PhyWrite(Hdptx, CMN_REG0041, 0x20); + PhyWrite(Hdptx, CMN_REG0042, 0x78); + PhyWrite(Hdptx, CMN_REG0043, 0x00); + PhyWrite(Hdptx, CMN_REG0044, 0x46); + PhyWrite(Hdptx, CMN_REG0045, 0x24); + PhyWrite(Hdptx, CMN_REG0046, 0xdd); + PhyWrite(Hdptx, CMN_REG0047, 0x00); + PhyWrite(Hdptx, CMN_REG0048, 0x11); + PhyWrite(Hdptx, CMN_REG0049, 0xfa); + PhyWrite(Hdptx, CMN_REG004A, 0x08); + PhyWrite(Hdptx, CMN_REG004B, 0x00); + PhyWrite(Hdptx, CMN_REG004C, 0x01); + PhyWrite(Hdptx, CMN_REG004D, 0x64); + PhyWrite(Hdptx, CMN_REG004E, 0x34); + PhyWrite(Hdptx, CMN_REG004F, 0x00); + PhyWrite(Hdptx, CMN_REG0050, 0x00); + DEBUG ((DEBUG_INIT, "%a HdptxRopllCmnConfig 2\n", __func__)); + PhyWrite(Hdptx, CMN_REG0051, Cfg->Pms_Mdiv); + PhyWrite(Hdptx, CMN_REG0055, Cfg->Pms_Mdiv_Afc); + + PhyWrite(Hdptx, CMN_REG0059, (Cfg->Pms_Pdiv << 4) | Cfg->Pms_Refdiv); + + PhyWrite(Hdptx, CMN_REG005A, (Cfg->Pms_Sdiv << 4)); + + PhyWrite(Hdptx, CMN_REG005C, 0x25); + PhyWrite(Hdptx, CMN_REG005D, 0x0c); + PhyWrite(Hdptx, CMN_REG005E, 0x4f); + PhyUpdateBits(Hdptx, CMN_REG005E, ROPLL_SDM_EN_MASK, + ROPLL_SDM_EN(Cfg->Sdm_En)); + if (!Cfg->Sdm_En) + PhyUpdateBits(Hdptx, CMN_REG005E, 0xf, 0); + + PhyWrite(Hdptx, CMN_REG005F, 0x01); + + PhyUpdateBits(Hdptx, CMN_REG0064, ROPLL_SDM_NUM_SIGN_RBR_MASK, + ROPLL_SDM_NUM_SIGN_RBR(Cfg->Sdm_Num_Sign)); + PhyWrite(Hdptx, CMN_REG0065, Cfg->Sdm_Num); + PhyWrite(Hdptx, CMN_REG0060, Cfg->Sdm_Deno); + + PhyUpdateBits(Hdptx, CMN_REG0069, ROPLL_SDC_N_RBR_MASK, + ROPLL_SDC_N_RBR(Cfg->Sdc_N)); + + PhyWrite(Hdptx, CMN_REG006C, Cfg->Sdc_Num); + PhyWrite(Hdptx, CMN_REG0070, Cfg->Sdc_Deno); + + PhyWrite(Hdptx, CMN_REG006B, 0x04); + + PhyWrite(Hdptx, CMN_REG0073, 0x30); + PhyWrite(Hdptx, CMN_REG0074, 0x04); + PhyWrite(Hdptx, CMN_REG0075, 0x20); + PhyWrite(Hdptx, CMN_REG0076, 0x30); + PhyWrite(Hdptx, CMN_REG0077, 0x08); + PhyWrite(Hdptx, CMN_REG0078, 0x0c); + PhyWrite(Hdptx, CMN_REG0079, 0x00); + PhyWrite(Hdptx, CMN_REG007B, 0x00); + PhyWrite(Hdptx, CMN_REG007C, 0x00); + PhyWrite(Hdptx, CMN_REG007D, 0x00); + PhyWrite(Hdptx, CMN_REG007E, 0x00); + PhyWrite(Hdptx, CMN_REG007F, 0x00); + PhyWrite(Hdptx, CMN_REG0080, 0x00); + PhyWrite(Hdptx, CMN_REG0081, 0x01); + PhyWrite(Hdptx, CMN_REG0082, 0x04); + PhyWrite(Hdptx, CMN_REG0083, 0x24); + PhyWrite(Hdptx, CMN_REG0084, 0x20); + PhyWrite(Hdptx, CMN_REG0085, 0x03); + + PhyUpdateBits(Hdptx, CMN_REG0086, PLL_PCG_POSTDIV_SEL_MASK, + PLL_PCG_POSTDIV_SEL(Cfg->Pms_Sdiv)); + + PhyUpdateBits(Hdptx, CMN_REG0086, PLL_PCG_CLK_SEL_MASK, + PLL_PCG_CLK_SEL(8)); + + PhyUpdateBits(Hdptx, CMN_REG0086, PLL_PCG_CLK_EN, PLL_PCG_CLK_EN); + + PhyWrite(Hdptx, CMN_REG0087, 0x04); + PhyWrite(Hdptx, CMN_REG0089, 0x00); + PhyWrite(Hdptx, CMN_REG008A, 0x55); + PhyWrite(Hdptx, CMN_REG008B, 0x25); + PhyWrite(Hdptx, CMN_REG008C, 0x2c); + PhyWrite(Hdptx, CMN_REG008D, 0x22); + PhyWrite(Hdptx, CMN_REG008E, 0x14); + PhyWrite(Hdptx, CMN_REG008F, 0x20); + PhyWrite(Hdptx, CMN_REG0090, 0x00); + PhyWrite(Hdptx, CMN_REG0091, 0x00); + PhyWrite(Hdptx, CMN_REG0092, 0x00); + PhyWrite(Hdptx, CMN_REG0093, 0x00); + PhyWrite(Hdptx, CMN_REG0095, 0x00); + PhyWrite(Hdptx, CMN_REG0097, 0x02); + PhyWrite(Hdptx, CMN_REG0099, 0x04); + PhyWrite(Hdptx, CMN_REG009A, 0x11); + PhyWrite(Hdptx, CMN_REG009B, 0x00); + DEBUG ((DEBUG_INIT, "%a HdptxRopllCmnConfig end\n", __func__)); + return HdptxPostEnablePll(Hdptx); +} + +UINT32 +HdptxPostEnableLane ( + OUT struct RockchipHdptxPhyHdmi *Hdptx + ) +{ + UINT32 Val = 0; + UINT32 i; + + /* deassert lane reset */ + if (!Hdptx->Id) + CruWrite(PMU1CRU_SOFTRST_CON03, BIT(13), 0); + else + CruWrite(PMU1CRU_SOFTRST_CON04, BIT(1), 0); + + Val = HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; + GrfWrite(Hdptx, GRF_HDPTX_CON0, Val, Val); + + /* 4 lanes frl mode */ + PhyWrite(Hdptx, LNTOP_REG0207, 0x0f); + + Val = 0; + for (i = 0; i < 50; i++) { + Val = GrfRead(Hdptx, GRF_HDPTX_STATUS); + + if (Val & HDPTX_O_PHY_RDY && Val & HDPTX_O_PLL_LOCK_DONE) + break; + NanoSecondDelay (100000); + } + + if (i == 50) { + DEBUG ((DEBUG_INIT, "%a hdptx phy lane can't ready!\n", __func__)); + return -EINVAL; + } + + DEBUG ((DEBUG_INIT, "%a hdptx phy lane locked!\n", __func__)); + + return 0; +} + +UINT32 +HdptxRopllTmdsModeConfig ( + OUT struct RockchipHdptxPhyHdmi *Hdptx + ) +{ + PhyWrite(Hdptx, SB_REG0114, 0x00); + PhyWrite(Hdptx, SB_REG0115, 0x00); + PhyWrite(Hdptx, SB_REG0116, 0x00); + PhyWrite(Hdptx, SB_REG0117, 0x00); + PhyWrite(Hdptx, LNTOP_REG0200, 0x06); + + /* For 1/10 bitrate clk */ + PhyWrite(Hdptx, LNTOP_REG0201, 0x07); + PhyWrite(Hdptx, LNTOP_REG0202, 0xc1); + PhyWrite(Hdptx, LNTOP_REG0203, 0xf0); + PhyWrite(Hdptx, LNTOP_REG0204, 0x7c); + PhyWrite(Hdptx, LNTOP_REG0205, 0x1f); + + PhyWrite(Hdptx, LNTOP_REG0206, 0x07); + PhyWrite(Hdptx, LANE_REG0303, 0x0c); + PhyWrite(Hdptx, LANE_REG0307, 0x20); + PhyWrite(Hdptx, LANE_REG030A, 0x17); + PhyWrite(Hdptx, LANE_REG030B, 0x77); + PhyWrite(Hdptx, LANE_REG030C, 0x77); + PhyWrite(Hdptx, LANE_REG030D, 0x77); + PhyWrite(Hdptx, LANE_REG030E, 0x38); + PhyWrite(Hdptx, LANE_REG0310, 0x03); + PhyWrite(Hdptx, LANE_REG0311, 0x0f); + PhyWrite(Hdptx, LANE_REG0312, 0x00); + PhyWrite(Hdptx, LANE_REG0316, 0x02); + PhyWrite(Hdptx, LANE_REG031B, 0x01); + PhyWrite(Hdptx, LANE_REG031E, 0x00); + PhyWrite(Hdptx, LANE_REG031F, 0x15); + PhyWrite(Hdptx, LANE_REG0320, 0xa0); + PhyWrite(Hdptx, LANE_REG0403, 0x0c); + PhyWrite(Hdptx, LANE_REG0407, 0x20); + PhyWrite(Hdptx, LANE_REG040A, 0x17); + PhyWrite(Hdptx, LANE_REG040B, 0x77); + PhyWrite(Hdptx, LANE_REG040C, 0x77); + PhyWrite(Hdptx, LANE_REG040D, 0x77); + PhyWrite(Hdptx, LANE_REG040E, 0x38); + PhyWrite(Hdptx, LANE_REG0410, 0x03); + PhyWrite(Hdptx, LANE_REG0411, 0x0f); + PhyWrite(Hdptx, LANE_REG0412, 0x00); + PhyWrite(Hdptx, LANE_REG0416, 0x02); + PhyWrite(Hdptx, LANE_REG041B, 0x01); + PhyWrite(Hdptx, LANE_REG041E, 0x00); + PhyWrite(Hdptx, LANE_REG041F, 0x15); + PhyWrite(Hdptx, LANE_REG0420, 0xa0); + PhyWrite(Hdptx, LANE_REG0503, 0x0c); + PhyWrite(Hdptx, LANE_REG0507, 0x20); + PhyWrite(Hdptx, LANE_REG050A, 0x17); + PhyWrite(Hdptx, LANE_REG050B, 0x77); + PhyWrite(Hdptx, LANE_REG050C, 0x77); + PhyWrite(Hdptx, LANE_REG050D, 0x77); + PhyWrite(Hdptx, LANE_REG050E, 0x38); + PhyWrite(Hdptx, LANE_REG0510, 0x03); + PhyWrite(Hdptx, LANE_REG0511, 0x0f); + PhyWrite(Hdptx, LANE_REG0512, 0x00); + PhyWrite(Hdptx, LANE_REG0516, 0x02); + PhyWrite(Hdptx, LANE_REG051B, 0x01); + PhyWrite(Hdptx, LANE_REG051E, 0x00); + PhyWrite(Hdptx, LANE_REG051F, 0x15); + PhyWrite(Hdptx, LANE_REG0520, 0xa0); + PhyWrite(Hdptx, LANE_REG0603, 0x0c); + PhyWrite(Hdptx, LANE_REG0607, 0x20); + PhyWrite(Hdptx, LANE_REG060A, 0x17); + PhyWrite(Hdptx, LANE_REG060B, 0x77); + PhyWrite(Hdptx, LANE_REG060C, 0x77); + PhyWrite(Hdptx, LANE_REG060D, 0x77); + PhyWrite(Hdptx, LANE_REG060E, 0x38); + PhyWrite(Hdptx, LANE_REG0610, 0x03); + PhyWrite(Hdptx, LANE_REG0611, 0x0f); + PhyWrite(Hdptx, LANE_REG0612, 0x00); + PhyWrite(Hdptx, LANE_REG0616, 0x02); + PhyWrite(Hdptx, LANE_REG061B, 0x01); + PhyWrite(Hdptx, LANE_REG061E, 0x08); + PhyWrite(Hdptx, LANE_REG061F, 0x15); + PhyWrite(Hdptx, LANE_REG0620, 0xa0); + + PhyWrite(Hdptx, LANE_REG0303, 0x2f); + PhyWrite(Hdptx, LANE_REG0403, 0x2f); + PhyWrite(Hdptx, LANE_REG0503, 0x2f); + PhyWrite(Hdptx, LANE_REG0603, 0x2f); + PhyWrite(Hdptx, LANE_REG0305, 0x03); + PhyWrite(Hdptx, LANE_REG0405, 0x03); + PhyWrite(Hdptx, LANE_REG0505, 0x03); + PhyWrite(Hdptx, LANE_REG0605, 0x03); + PhyWrite(Hdptx, LANE_REG0306, 0x1c); + PhyWrite(Hdptx, LANE_REG0406, 0x1c); + PhyWrite(Hdptx, LANE_REG0506, 0x1c); + PhyWrite(Hdptx, LANE_REG0606, 0x1c); + + return HdptxPostEnableLane(Hdptx); +} + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.c new file mode 100644 index 0000000..4d692af --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.c @@ -0,0 +1,107 @@ +/** @file + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include + +#include +#include +#include +#include +#include +#include +#include + +EFIAPI +EFI_STATUS +DisplaySetCrtcInfo ( + OUT DRM_DISPLAY_MODE *Mode, + IN UINT32 AdjustFlags + ) +{ + if ((Mode == NULL) || ((Mode->Type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN)) + return EFI_UNSUPPORTED; + + if (Mode->Flags & DRM_MODE_FLAG_DBLCLK) + Mode->CrtcClock = 2 * Mode->Clock; + else + Mode->CrtcClock = Mode->Clock; + Mode->CrtcHDisplay = Mode->HDisplay; + Mode->CrtcHSyncStart = Mode->HSyncStart; + Mode->CrtcHSyncEnd = Mode->HSyncEnd; + Mode->CrtcHTotal = Mode->HTotal; + Mode->CrtcHSkew = Mode->HSkew; + Mode->CrtcVDisplay = Mode->VDisplay; + Mode->CrtcVSyncStart = Mode->VSyncStart; + Mode->CrtcVSyncEnd = Mode->VSyncEnd; + Mode->CrtcVTotal = Mode->VTotal; + + if (Mode->Flags & DRM_MODE_FLAG_INTERLACE) { + if (AdjustFlags & CRTC_INTERLACE_HALVE_V) { + Mode->CrtcVDisplay /= 2; + Mode->CrtcVSyncStart /= 2; + Mode->CrtcVSyncEnd /= 2; + Mode->CrtcVTotal /= 2; + } + } + + if (!(AdjustFlags & CRTC_NO_DBLSCAN)) { + if (Mode->Flags & DRM_MODE_FLAG_DBLSCAN) { + Mode->CrtcVDisplay *= 2; + Mode->CrtcVSyncStart *= 2; + Mode->CrtcVSyncEnd *= 2; + Mode->CrtcVTotal *= 2; + } + } + + if (!(AdjustFlags & CRTC_NO_VSCAN)) { + if (Mode->VScan > 1) { + Mode->CrtcVDisplay *= Mode->VScan; + Mode->CrtcVSyncStart *= Mode->VScan; + Mode->CrtcVSyncEnd *= Mode->VScan; + Mode->CrtcVTotal *= Mode->VScan; + } + } + + Mode->CrtcVBlankStart = MIN(Mode->CrtcVSyncStart, Mode->CrtcVDisplay); + Mode->CrtcVBlankEnd = MAX(Mode->CrtcVSyncEnd, Mode->CrtcVTotal); + Mode->CrtcHBlankStart = MIN(Mode->CrtcHSyncStart, Mode->CrtcHDisplay); + Mode->CrtcHBblankEnd = MAX(Mode->CrtcHSyncEnd, Mode->CrtcHTotal); + + return EFI_SUCCESS; +} + +UINT32 +EFIAPI +DrmModeVRefresh ( + DRM_DISPLAY_MODE *Mode + ) +{ + UINT32 Refresh = 0; + UINT32 CalcVal; + + if (Mode->VRefresh > 0) { + Refresh = Mode->VRefresh; + } else if (Mode->HTotal > 0 && Mode->VTotal > 0) { + int VTotal; + + VTotal = Mode->VTotal; + /* work out VRefresh the value will be x1000 */ + CalcVal = (Mode->Clock * 1000); + CalcVal /= Mode->HTotal; + Refresh = (CalcVal + VTotal / 2) / VTotal; + + if (Mode->Flags & DRM_MODE_FLAG_INTERLACE) + Refresh *= 2; + if (Mode->Flags & DRM_MODE_FLAG_DBLSCAN) + Refresh /= 2; + if (Mode->VScan > 1) + Refresh /= Mode->VScan; + } + return Refresh; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf new file mode 100644 index 0000000..84afd44 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf @@ -0,0 +1,35 @@ +## @file +# +# Copyright (c) 2022 Rockchip Electronics Co. Ltd. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RockchipDisplayLib + FILE_GUID = 967dc52a-7cfa-11ec-b45f-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = DisplayLib + +[Sources.common] + RockchipDisplayLib.c + +[LibraryClasses] + IoLib + DebugLib + UefiBootServicesTableLib + MemoryAllocationLib + BaseLib + BaseMemoryLib + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_dp_helper.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_dp_helper.c new file mode 100644 index 0000000..7b0ee2b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_dp_helper.c @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright © 2009 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include + +/** + * DOC: dp helpers + * + * These functions contain some common logic and helpers at various abstraction + * levels to deal with Display Port sink devices and related things like DP aux + * channel transfers, EDID reading over DP aux channels, decoding certain DPCD + * blocks, ... + */ + +/* Helpers for DP link training */ +static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) +{ + return link_status[r - DP_LANE0_1_STATUS]; +} + +static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_LANE0_1_STATUS + (lane >> 1); + int s = (lane & 1) * 4; + u8 l = dp_link_status(link_status, i); + + return (l >> s) & 0xf; +} + +bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count) +{ + u8 lane_align; + u8 lane_status; + int lane; + + lane_align = dp_link_status(link_status, + DP_LANE_ALIGN_STATUS_UPDATED); + if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) + return false; + for (lane = 0; lane < lane_count; lane++) { + lane_status = dp_get_lane_status(link_status, lane); + if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) + return false; + } + return true; +} + +bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count) +{ + int lane; + u8 lane_status; + + for (lane = 0; lane < lane_count; lane++) { + lane_status = dp_get_lane_status(link_status, lane); + if ((lane_status & DP_LANE_CR_DONE) == 0) + return false; + } + return true; +} + +u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? + DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : + DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); + u8 l = dp_link_status(link_status, i); + + return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; +} + +u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane) +{ + int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); + int s = ((lane & 1) ? + DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : + DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); + u8 l = dp_link_status(link_status, i); + + return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; +} + +void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_TRAINING_AUX_RD_MASK; + + if (rd_interval > 4) + printf("AUX interval %d, out of range (max 4)\n", rd_interval); + + if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) + udelay(100); + else + mdelay(rd_interval * 4); +} + +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_TRAINING_AUX_RD_MASK; + + if (rd_interval > 4) + printf("AUX interval %d, out of range (max 4)\n", rd_interval); + + if (rd_interval == 0) + udelay(400); + else + mdelay(rd_interval * 4); +} + +u8 drm_dp_link_rate_to_bw_code(int link_rate) +{ + switch (link_rate) { + default: + WARN(1, "unknown DP link rate %d, using %x\n", link_rate, + DP_LINK_BW_1_62); + case 162000: + return DP_LINK_BW_1_62; + case 270000: + return DP_LINK_BW_2_7; + case 540000: + return DP_LINK_BW_5_4; + case 810000: + return DP_LINK_BW_8_1; + } +} + +int drm_dp_bw_code_to_link_rate(u8 link_bw) +{ + switch (link_bw) { + default: + WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw); + case DP_LINK_BW_1_62: + return 162000; + case DP_LINK_BW_2_7: + return 270000; + case DP_LINK_BW_5_4: + return 540000; + case DP_LINK_BW_8_1: + return 810000; + } +} + +#define AUX_RETRY_INTERVAL 500 /* us */ + +static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, + unsigned int offset, void *buffer, size_t size) +{ + struct drm_dp_aux_msg msg; + unsigned int retry, native_reply; + int err = 0, ret = 0; + + memset(&msg, 0, sizeof(msg)); + msg.address = offset; + msg.request = request; + msg.buffer = buffer; + msg.size = size; + + /* + * The specification doesn't give any recommendation on how often to + * retry native transactions. We used to retry 7 times like for + * aux i2c transactions but real world devices this wasn't + * sufficient, bump to 32 which makes Dell 4k monitors happier. + */ + for (retry = 0; retry < 32; retry++) { + if (ret != 0 && ret != -ETIMEDOUT) + udelay(AUX_RETRY_INTERVAL); + + ret = aux->transfer(aux, &msg); + if (ret >= 0) { + native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; + if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { + if (ret == size) + goto out; + + ret = -EPROTO; + } else { + ret = -EIO; + } + } + + /* + * We want the error we return to be the error we received on + * the first transaction, since we may get a different error the + * next time we retry + */ + if (!err) + err = ret; + } + + printf("%s: Too many retries, giving up. First error: %d\n", + aux->name, err); + ret = err; + +out: + return ret; +} + +ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size) +{ + int ret; + + ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, + buffer, 1); + if (ret != 1) + goto out; + + ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, + buffer, size); + +out: + return ret; +} + +ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size) +{ + int ret; + + ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, + buffer, size); + + return ret; +} + +int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, + u8 status[DP_LINK_STATUS_SIZE]) +{ + return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, + DP_LINK_STATUS_SIZE); +} + +static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + u8 dpcd_ext[6]; + int ret; + + /* + * Prior to DP1.3 the bit represented by + * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. + * If it is set DP_DPCD_REV at 0000h could be at a value less than + * the true capability of the panel. The only way to check is to + * then compare 0000h and 2200h. + */ + if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) + return 0; + + ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, + sizeof(dpcd_ext)); + if (ret < 0) + return ret; + if (ret != sizeof(dpcd_ext)) + return -EIO; + + if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { + printf("%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", + aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); + return 0; + } + + if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) + return 0; + + debug("%s: Base DPCD: %*ph\n", + aux->name, DP_RECEIVER_CAP_SIZE, dpcd); + + memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); + + return 0; +} + +int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int ret; + + ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); + if (ret < 0) + return ret; + if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) + return -EIO; + + ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); + if (ret < 0) + return ret; + + debug("%s: DPCD: %*ph\n", + aux->name, DP_RECEIVER_CAP_SIZE, dpcd); + + return ret; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_dsc.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_dsc.c new file mode 100644 index 0000000..82a1576 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_dsc.c @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2018 Intel Corp + * + * Author: + * Manasi Navare + */ + +#include +#include +#include + +/** + * DOC: dsc helpers + * + * VESA specification for DP 1.4 adds a new feature called Display Stream + * Compression (DSC) used to compress the pixel bits before sending it on + * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing + * display interfaces can support high resolutions at higher frames rates using + * the maximum available link capacity of these interfaces. + * + * These functions contain some common logic and helpers to deal with VESA + * Display Stream Compression standard required for DSC on Display Port/eDP or + * MIPI display interfaces. + */ + +/** + * drm_dsc_dp_pps_header_init() - Initializes the PPS Header + * for DisplayPort as per the DP 1.4 spec. + * @pps_header: Secondary data packet header for DSC Picture + * Parameter Set as defined in &struct dp_sdp_header + * + * DP 1.4 spec defines the secondary data packet for sending the + * picture parameter infoframes from the source to the sink. + * This function populates the SDP header defined in + * &struct dp_sdp_header. + */ +void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header) +{ + memset(pps_header, 0, sizeof(*pps_header)); + + pps_header->HB1 = DP_SDP_PPS; + pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; +} + +/** + * drm_dsc_pps_payload_pack() - Populates the DSC PPS + * + * @pps_payload: + * Bitwise struct for DSC Picture Parameter Set. This is defined + * by &struct drm_dsc_picture_parameter_set + * @dsc_cfg: + * DSC Configuration data filled by driver as defined by + * &struct drm_dsc_config + * + * DSC source device sends a picture parameter set (PPS) containing the + * information required by the sink to decode the compressed frame. Driver + * populates the DSC PPS struct using the DSC configuration parameters in + * the order expected by the DSC Display Sink device. For the DSC, the sink + * device expects the PPS payload in big endian format for fields + * that span more than 1 byte. + */ +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, + const struct drm_dsc_config *dsc_cfg) +{ + int i; + + /* Protect against someone accidentally changing struct size */ + BUILD_BUG_ON(sizeof(*pps_payload) != + DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); + + memset(pps_payload, 0, sizeof(*pps_payload)); + + /* PPS 0 */ + pps_payload->dsc_version = + dsc_cfg->dsc_version_minor | + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; + + /* PPS 1, 2 is 0 */ + + /* PPS 3 */ + pps_payload->pps_3 = + dsc_cfg->line_buf_depth | + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; + + /* PPS 4 */ + pps_payload->pps_4 = + ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT) | + dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | + dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | + dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | + dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; + + /* PPS 5 */ + pps_payload->bits_per_pixel_low = + (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); + + /* + * The DSC panel expects the PPS packet to have big endian format + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert + * to big endian format. If format is little endian, it will swap + * bytes to convert to Big endian else keep it unchanged. + */ + + /* PPS 6, 7 */ + pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); + + /* PPS 8, 9 */ + pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); + + /* PPS 10, 11 */ + pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); + + /* PPS 12, 13 */ + pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); + + /* PPS 14, 15 */ + pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); + + /* PPS 16 */ + pps_payload->initial_xmit_delay_high = + ((dsc_cfg->initial_xmit_delay & + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 17 */ + pps_payload->initial_xmit_delay_low = + (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); + + /* PPS 18, 19 */ + pps_payload->initial_dec_delay = + cpu_to_be16(dsc_cfg->initial_dec_delay); + + /* PPS 20 is 0 */ + + /* PPS 21 */ + pps_payload->initial_scale_value = + dsc_cfg->initial_scale_value; + + /* PPS 22, 23 */ + pps_payload->scale_increment_interval = + cpu_to_be16(dsc_cfg->scale_increment_interval); + + /* PPS 24 */ + pps_payload->scale_decrement_interval_high = + ((dsc_cfg->scale_decrement_interval & + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 25 */ + pps_payload->scale_decrement_interval_low = + (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); + + /* PPS 26[7:0], PPS 27[7:5] RESERVED */ + + /* PPS 27 */ + pps_payload->first_line_bpg_offset = + dsc_cfg->first_line_bpg_offset; + + /* PPS 28, 29 */ + pps_payload->nfl_bpg_offset = + cpu_to_be16(dsc_cfg->nfl_bpg_offset); + + /* PPS 30, 31 */ + pps_payload->slice_bpg_offset = + cpu_to_be16(dsc_cfg->slice_bpg_offset); + + /* PPS 32, 33 */ + pps_payload->initial_offset = + cpu_to_be16(dsc_cfg->initial_offset); + + /* PPS 34, 35 */ + pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); + + /* PPS 36 */ + pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; + + /* PPS 37 */ + pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; + + /* PPS 38, 39 */ + pps_payload->rc_model_size = + cpu_to_be16(DSC_RC_MODEL_SIZE_CONST); + + /* PPS 40 */ + pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; + + /* PPS 41 */ + pps_payload->rc_quant_incr_limit0 = + dsc_cfg->rc_quant_incr_limit0; + + /* PPS 42 */ + pps_payload->rc_quant_incr_limit1 = + dsc_cfg->rc_quant_incr_limit1; + + /* PPS 43 */ + pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | + DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; + + /* PPS 44 - 57 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) + pps_payload->rc_buf_thresh[i] = + dsc_cfg->rc_buf_thresh[i]; + + /* PPS 58 - 87 */ + /* + * For DSC sink programming the RC Range parameter fields + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] + */ + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + pps_payload->rc_range_parameters[i] = + cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << + DSC_PPS_RC_RANGE_MINQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_max_qp << + DSC_PPS_RC_RANGE_MAXQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_bpg_offset)); + } + + /* PPS 88 */ + pps_payload->native_422_420 = dsc_cfg->native_422 | + dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; + + /* PPS 89 */ + pps_payload->second_line_bpg_offset = + dsc_cfg->second_line_bpg_offset; + + /* PPS 90, 91 */ + pps_payload->nsl_bpg_offset = + cpu_to_be16(dsc_cfg->nsl_bpg_offset); + + /* PPS 92, 93 */ + pps_payload->second_line_offset_adj = + cpu_to_be16(dsc_cfg->second_line_offset_adj); + + /* PPS 94 - 127 are O */ +} + +/** + * drm_dsc_compute_rc_parameters() - Write rate control + * parameters to the dsc configuration defined in + * &struct drm_dsc_config in accordance with the DSC 1.2 + * specification. Some configuration fields must be present + * beforehand. + * + * @vdsc_cfg: + * DSC Configuration data partially filled by driver + */ +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) +{ + unsigned long groups_per_line = 0; + unsigned long groups_total = 0; + unsigned long num_extra_mux_bits = 0; + unsigned long slice_bits = 0; + unsigned long hrd_delay = 0; + unsigned long final_scale = 0; + unsigned long rbs_min = 0; + + if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } else { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } + + if (vdsc_cfg->convert_rgb) + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + - 2); + else if (vdsc_cfg->native_422) + num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 3 * (4 * vdsc_cfg->bits_per_component) - 2; + else + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 2 * (4 * vdsc_cfg->bits_per_component) - 2; + /* Number of bits in one Slice */ + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; + + while ((num_extra_mux_bits > 0) && + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) + num_extra_mux_bits--; + + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) + vdsc_cfg->initial_scale_value = groups_per_line + 8; + + /* scale_decrement_interval calculation according to DSC spec 1.11 */ + if (vdsc_cfg->initial_scale_value > 8) + vdsc_cfg->scale_decrement_interval = groups_per_line / + (vdsc_cfg->initial_scale_value - 8); + else + vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; + + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - + (vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; + + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { + printf("FinalOfs < RcModelSze for this InitialXmitDelay\n"); + return -ERANGE; + } + + final_scale = (vdsc_cfg->rc_model_size * 8) / + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); + if (vdsc_cfg->slice_height > 1) + /* + * NflBpgOffset is 16 bit value with 11 fractional bits + * hence we multiply by 2^11 for preserving the + * fractional part + */ + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), + (vdsc_cfg->slice_height - 1)); + else + vdsc_cfg->nfl_bpg_offset = 0; + + /* Number of groups used to code the entire slice */ + groups_total = groups_per_line * vdsc_cfg->slice_height; + + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - + vdsc_cfg->initial_offset + + num_extra_mux_bits) << 11), + groups_total); + + if (final_scale > 9) { + /* + * ScaleIncrementInterval = + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, + * we need divide by 2^11 from pstDscCfg values + */ + vdsc_cfg->scale_increment_interval = + (vdsc_cfg->final_offset * (1 << 11)) / + ((vdsc_cfg->nfl_bpg_offset + + vdsc_cfg->slice_bpg_offset) * + (final_scale - 9)); + } else { + /* + * If finalScaleValue is less than or equal to 9, a value of 0 should + * be used to disable the scale increment at the end of the slice + */ + vdsc_cfg->scale_increment_interval = 0; + } + + /* + * DSC spec mentions that bits_per_pixel specifies the target + * bits/pixel (bpp) rate that is used by the encoder, + * in steps of 1/16 of a bit per pixel + */ + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel, 16) + + groups_per_line * vdsc_cfg->first_line_bpg_offset; + + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; + + return 0; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_mipi_dsi.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_mipi_dsi.c new file mode 100644 index 0000000..d4ca770 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/drm_mipi_dsi.c @@ -0,0 +1,791 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * MIPI DSI Bus + * + * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd. + * Andrzej Hajda + */ + +#include +#include + +/** + * mipi_dsi_attach - attach a DSI device to its DSI host + * @dsi: DSI peripheral + */ +int mipi_dsi_attach(struct mipi_dsi_device *dsi) +{ + const struct mipi_dsi_host_ops *ops = dsi->host->ops; + + if (!ops || !ops->attach) + return -ENOSYS; + + return ops->attach(dsi->host, dsi); +} + +/** + * mipi_dsi_detach - detach a DSI device from its DSI host + * @dsi: DSI peripheral + */ +int mipi_dsi_detach(struct mipi_dsi_device *dsi) +{ + const struct mipi_dsi_host_ops *ops = dsi->host->ops; + + if (!ops || !ops->detach) + return -ENOSYS; + + return ops->detach(dsi->host, dsi); +} + +static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi, + struct mipi_dsi_msg *msg) +{ + const struct mipi_dsi_host_ops *ops = dsi->host->ops; + + if (!ops || !ops->transfer) + return -ENOSYS; + + if (dsi->mode_flags & MIPI_DSI_MODE_LPM) + msg->flags |= MIPI_DSI_MSG_USE_LPM; + + return ops->transfer(dsi->host, msg); +} + +/** + * mipi_dsi_packet_format_is_short - check if a packet is of the short format + * @type: MIPI DSI data type of the packet + * + * Return: true if the packet for the given data type is a short packet, false + * otherwise. + */ +bool mipi_dsi_packet_format_is_short(u8 type) +{ + switch (type) { + case MIPI_DSI_V_SYNC_START: + case MIPI_DSI_V_SYNC_END: + case MIPI_DSI_H_SYNC_START: + case MIPI_DSI_H_SYNC_END: + case MIPI_DSI_COMPRESSION_MODE: + case MIPI_DSI_END_OF_TRANSMISSION: + case MIPI_DSI_COLOR_MODE_OFF: + case MIPI_DSI_COLOR_MODE_ON: + case MIPI_DSI_SHUTDOWN_PERIPHERAL: + case MIPI_DSI_TURN_ON_PERIPHERAL: + case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: + case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: + case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: + case MIPI_DSI_DCS_SHORT_WRITE: + case MIPI_DSI_DCS_SHORT_WRITE_PARAM: + case MIPI_DSI_DCS_READ: + case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: + return true; + } + + return false; +} + +/** + * mipi_dsi_packet_format_is_long - check if a packet is of the long format + * @type: MIPI DSI data type of the packet + * + * Return: true if the packet for the given data type is a long packet, false + * otherwise. + */ +bool mipi_dsi_packet_format_is_long(u8 type) +{ + switch (type) { + case MIPI_DSI_NULL_PACKET: + case MIPI_DSI_BLANKING_PACKET: + case MIPI_DSI_GENERIC_LONG_WRITE: + case MIPI_DSI_DCS_LONG_WRITE: + case MIPI_DSI_PICTURE_PARAMETER_SET: + case MIPI_DSI_COMPRESSED_PIXEL_STREAM: + case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20: + case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24: + case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16: + case MIPI_DSI_PACKED_PIXEL_STREAM_30: + case MIPI_DSI_PACKED_PIXEL_STREAM_36: + case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12: + case MIPI_DSI_PACKED_PIXEL_STREAM_16: + case MIPI_DSI_PACKED_PIXEL_STREAM_18: + case MIPI_DSI_PIXEL_STREAM_3BYTE_18: + case MIPI_DSI_PACKED_PIXEL_STREAM_24: + return true; + } + + return false; +} + +/** + * mipi_dsi_create_packet - create a packet from a message according to the + * DSI protocol + * @packet: pointer to a DSI packet structure + * @msg: message to translate into a packet + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_create_packet(struct mipi_dsi_packet *packet, + const struct mipi_dsi_msg *msg) +{ + if (!packet || !msg) + return -EINVAL; + + /* do some minimum sanity checking */ + if (!mipi_dsi_packet_format_is_short(msg->type) && + !mipi_dsi_packet_format_is_long(msg->type)) + return -EINVAL; + + if (msg->channel > 3) + return -EINVAL; + + memset(packet, 0, sizeof(*packet)); + packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); + if (mipi_dsi_packet_format_is_long(msg->type)) { + packet->header[1] = (msg->tx_len >> 0) & 0xff; + packet->header[2] = (msg->tx_len >> 8) & 0xff; + + packet->payload_length = msg->tx_len; + packet->payload = msg->tx_buf; + } else { + const u8 *tx = msg->tx_buf; + + packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0; + packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0; + } + + packet->size = sizeof(packet->header) + packet->payload_length; + + return 0; +} + +/** + * mipi_dsi_shutdown_peripheral() - sends a Shutdown Peripheral command + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_shutdown_peripheral(struct mipi_dsi_device *dsi) +{ + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .type = MIPI_DSI_SHUTDOWN_PERIPHERAL, + .tx_buf = (u8 [2]) { 0, 0 }, + .tx_len = 2, + }; + int ret = mipi_dsi_device_transfer(dsi, &msg); + + return (ret < 0) ? ret : 0; +} + +/** + * mipi_dsi_turn_on_peripheral() - sends a Turn On Peripheral command + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_turn_on_peripheral(struct mipi_dsi_device *dsi) +{ + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .type = MIPI_DSI_TURN_ON_PERIPHERAL, + .tx_buf = (u8 [2]) { 0, 0 }, + .tx_len = 2, + }; + int ret = mipi_dsi_device_transfer(dsi, &msg); + + return (ret < 0) ? ret : 0; +} + +/* + * mipi_dsi_set_maximum_return_packet_size() - specify the maximum size of the + * the payload in a long packet transmitted from the peripheral back to the + * host processor + * @dsi: DSI peripheral device + * @value: the maximum size of the payload + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_set_maximum_return_packet_size(struct mipi_dsi_device *dsi, + u16 value) +{ + u8 tx[2] = { value & 0xff, value >> 8 }; + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, + .tx_len = sizeof(tx), + .tx_buf = tx, + }; + int ret = mipi_dsi_device_transfer(dsi, &msg); + + return (ret < 0) ? ret : 0; +} + +/** + * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral + * @dsi: DSI peripheral device + * @enable: Whether to enable or disable the DSC + * + * Enable or disable Display Stream Compression on the peripheral using the + * default Picture Parameter Set and VESA DSC 1.1 algorithm. + * + * Return: 0 on success or a negative error code on failure. + */ +ssize_t mipi_dsi_compression_mode(struct mipi_dsi_device *dsi, bool enable) +{ + /* Note: Needs updating for non-default PPS or algorithm */ + u8 tx[2] = { enable << 0, 0 }; + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .type = MIPI_DSI_COMPRESSION_MODE, + .tx_len = sizeof(tx), + .tx_buf = tx, + }; + int ret = mipi_dsi_device_transfer(dsi, &msg); + + return (ret < 0) ? ret : 0; +} + +/** + * mipi_dsi_picture_parameter_set() - transmit the DSC PPS to the peripheral + * @dsi: DSI peripheral device + * @pps: VESA DSC 1.1 Picture Parameter Set + * + * Transmit the VESA DSC 1.1 Picture Parameter Set to the peripheral. + * + * Return: 0 on success or a negative error code on failure. + */ +ssize_t mipi_dsi_picture_parameter_set(struct mipi_dsi_device *dsi, + const struct drm_dsc_picture_parameter_set *pps) +{ + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .type = MIPI_DSI_PICTURE_PARAMETER_SET, + .tx_len = sizeof(*pps), + .tx_buf = pps, + }; + int ret = mipi_dsi_device_transfer(dsi, &msg); + + return (ret < 0) ? ret : 0; +} + +/** + * mipi_dsi_generic_write() - transmit data using a generic write packet + * @dsi: DSI peripheral device + * @payload: buffer containing the payload + * @size: size of payload buffer + * + * This function will automatically choose the right data type depending on + * the payload length. + * + * Return: The number of bytes transmitted on success or a negative error code + * on failure. + */ +ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload, + size_t size) +{ + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .tx_buf = payload, + .tx_len = size + }; + + switch (size) { + case 0: + msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; + break; + case 1: + msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; + break; + case 2: + msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; + break; + default: + msg.type = MIPI_DSI_GENERIC_LONG_WRITE; + break; + } + + return mipi_dsi_device_transfer(dsi, &msg); +} + +/** + * mipi_dsi_generic_read() - receive data using a generic read packet + * @dsi: DSI peripheral device + * @params: buffer containing the request parameters + * @num_params: number of request parameters + * @data: buffer in which to return the received data + * @size: size of receive buffer + * + * This function will automatically choose the right data type depending on + * the number of parameters passed in. + * + * Return: The number of bytes successfully read or a negative error code on + * failure. + */ +ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params, + size_t num_params, void *data, size_t size) +{ + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .tx_len = num_params, + .tx_buf = params, + .rx_len = size, + .rx_buf = data + }; + + switch (num_params) { + case 0: + msg.type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; + break; + + case 1: + msg.type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; + break; + + case 2: + msg.type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; + break; + + default: + return -EINVAL; + } + + return mipi_dsi_device_transfer(dsi, &msg); +} + +/** + * mipi_dsi_dcs_write_buffer() - transmit a DCS command with payload + * @dsi: DSI peripheral device + * @data: buffer containing data to be transmitted + * @len: size of transmission buffer + * + * This function will automatically choose the right data type depending on + * the command payload length. + * + * Return: The number of bytes successfully transmitted or a negative error + * code on failure. + */ +ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi, + const void *data, size_t len) +{ + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .tx_buf = data, + .tx_len = len + }; + + switch (len) { + case 0: + return -EINVAL; + + case 1: + msg.type = MIPI_DSI_DCS_SHORT_WRITE; + break; + + case 2: + msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + + default: + msg.type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + + return mipi_dsi_device_transfer(dsi, &msg); +} + +/** + * mipi_dsi_dcs_write() - send DCS write command + * @dsi: DSI peripheral device + * @cmd: DCS command + * @data: buffer containing the command payload + * @len: command payload length + * + * This function will automatically choose the right data type depending on + * the command payload length. + * + * Return: The number of bytes successfully transmitted or a negative error + * code on failure. + */ +ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd, + const void *data, size_t len) +{ + ssize_t err; + size_t size; + u8 *tx; + + if (len > 0) { + size = 1 + len; + + tx = malloc(size); + if (!tx) + return -ENOMEM; + + /* concatenate the DCS command byte and the payload */ + tx[0] = cmd; + memcpy(&tx[1], data, len); + } else { + tx = &cmd; + size = 1; + } + + err = mipi_dsi_dcs_write_buffer(dsi, tx, size); + + if (len > 0) + free(tx); + + return err; +} + +/** + * mipi_dsi_dcs_read() - send DCS read request command + * @dsi: DSI peripheral device + * @cmd: DCS command + * @data: buffer in which to receive data + * @len: size of receive buffer + * Return: The number of bytes read or a negative error code on failure. + */ +ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data, + size_t len) +{ + struct mipi_dsi_msg msg = { + .channel = dsi->channel, + .type = MIPI_DSI_DCS_READ, + .tx_buf = &cmd, + .tx_len = 1, + .rx_buf = data, + .rx_len = len + }; + + return mipi_dsi_device_transfer(dsi, &msg); +} + +/** + * mipi_dsi_dcs_nop() - send DCS nop packet + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_nop(struct mipi_dsi_device *dsi) +{ + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_NOP, NULL, 0); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_soft_reset() - perform a software reset of the display module + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_soft_reset(struct mipi_dsi_device *dsi) +{ + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SOFT_RESET, NULL, 0); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_get_power_mode() - query the display module's current power + * mode + * @dsi: DSI peripheral device + * @mode: return location for the current power mode + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode) +{ + ssize_t err; + + err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_POWER_MODE, mode, + sizeof(*mode)); + if (err <= 0) { + if (err == 0) + err = -ENODATA; + + return err; + } + + return 0; +} + +/** + * mipi_dsi_dcs_get_pixel_format() - gets the pixel format for the RGB image + * data used by the interface + * @dsi: DSI peripheral device + * @format: return location for the pixel format + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format) +{ + ssize_t err; + + err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_PIXEL_FORMAT, format, + sizeof(*format)); + if (err <= 0) { + if (err == 0) + err = -ENODATA; + + return err; + } + + return 0; +} + +/** + * mipi_dsi_dcs_enter_sleep_mode() - disable all unnecessary blocks inside the + * display module except interface communication + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_enter_sleep_mode(struct mipi_dsi_device *dsi) +{ + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_exit_sleep_mode() - enable all blocks inside the display + * module + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi) +{ + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_display_off() - stop displaying the image data on the + * display device + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_display_off(struct mipi_dsi_device *dsi) +{ + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_display_on() - start displaying the image data on the + * display device + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure + */ +int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi) +{ + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_column_address() - define the column extent of the frame + * memory accessed by the host processor + * @dsi: DSI peripheral device + * @start: first column of frame memory + * @end: last column of frame memory + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start, + u16 end) +{ + u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff }; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_COLUMN_ADDRESS, payload, + sizeof(payload)); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_page_address() - define the page extent of the frame + * memory accessed by the host processor + * @dsi: DSI peripheral device + * @start: first page of frame memory + * @end: last page of frame memory + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start, + u16 end) +{ + u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff }; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PAGE_ADDRESS, payload, + sizeof(payload)); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_tear_off() - turn off the display module's Tearing Effect + * output signal on the TE signal line + * @dsi: DSI peripheral device + * + * Return: 0 on success or a negative error code on failure + */ +int mipi_dsi_dcs_set_tear_off(struct mipi_dsi_device *dsi) +{ + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_OFF, NULL, 0); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_tear_on() - turn on the display module's Tearing Effect + * output signal on the TE signal line. + * @dsi: DSI peripheral device + * @mode: the Tearing Effect Output Line mode + * + * Return: 0 on success or a negative error code on failure + */ +int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, + enum mipi_dsi_dcs_tear_mode mode) +{ + u8 value = mode; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_ON, &value, + sizeof(value)); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_pixel_format() - sets the pixel format for the RGB image + * data used by the interface + * @dsi: DSI peripheral device + * @format: pixel format + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format) +{ + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PIXEL_FORMAT, &format, + sizeof(format)); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_tear_scanline() - set the scanline to use as trigger for + * the Tearing Effect output signal of the display module + * @dsi: DSI peripheral device + * @scanline: scanline to use as trigger + * + * Return: 0 on success or a negative error code on failure + */ +int mipi_dsi_dcs_set_tear_scanline(struct mipi_dsi_device *dsi, u16 scanline) +{ + u8 payload[3] = { MIPI_DCS_SET_TEAR_SCANLINE, scanline >> 8, + scanline & 0xff }; + ssize_t err; + + err = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_set_display_brightness() - sets the brightness value of the + * display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi, + u16 brightness) +{ + u8 payload[2] = { brightness & 0xff, brightness >> 8 }; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} + +/** + * mipi_dsi_dcs_get_display_brightness() - gets the current brightness value + * of the display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, + u16 *brightness) +{ + ssize_t err; + + err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_BRIGHTNESS, + brightness, sizeof(*brightness)); + if (err <= 0) { + if (err == 0) + err = -ENODATA; + + return err; + } + + return 0; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/rockchip_phy.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/rockchip_phy.c new file mode 100644 index 0000000..e7bd89e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/rockchip_phy.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "rockchip_phy.h" + +int rockchip_phy_init(struct rockchip_phy *phy) +{ + if (!phy) + return -ENODEV; + + if (phy->funcs && phy->funcs->init) + return phy->funcs->init(phy); + + return 0; +} + +int rockchip_phy_power_on(struct rockchip_phy *phy) +{ + if (!phy) + return -ENODEV; + + if (phy->funcs && phy->funcs->power_on) + return phy->funcs->power_on(phy); + + return 0; +} + +int rockchip_phy_power_off(struct rockchip_phy *phy) +{ + if (!phy) + return -ENODEV; + + if (phy->funcs && phy->funcs->power_off) + return phy->funcs->power_off(phy); + + return 0; +} + +unsigned long rockchip_phy_set_pll(struct rockchip_phy *phy, + unsigned long rate) +{ + if (!phy) + return -ENODEV; + + if (phy->funcs && phy->funcs->set_pll) + return phy->funcs->set_pll(phy, rate); + + return 0; +} + +int rockchip_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width) +{ + if (!phy) + return -ENODEV; + + if (phy->funcs && phy->funcs->set_bus_width) + return phy->funcs->set_bus_width(phy, bus_width); + + return 0; +} + +long rockchip_phy_round_rate(struct rockchip_phy *phy, unsigned long rate) +{ + if (!phy) + return -ENODEV; + + if (phy->funcs && phy->funcs->round_rate) + return phy->funcs->round_rate(phy, rate); + + return 0; +} + +int rockchip_phy_set_mode(struct rockchip_phy *phy, enum phy_mode mode) +{ + if (!phy) + return -ENODEV; + + if (phy->funcs && phy->funcs->set_mode) + return phy->funcs->set_mode(phy, mode); + + return 0; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/rockchip_phy.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/rockchip_phy.h new file mode 100644 index 0000000..865cdb4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/rockchip_phy.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ROCKCHIP_PHY_H_ +#define _ROCKCHIP_PHY_H_ + +enum phy_mode { + PHY_MODE_INVALID, + PHY_MODE_MIPI_DPHY, + PHY_MODE_VIDEO_LVDS, + PHY_MODE_VIDEO_TTL, +}; + +struct rockchip_phy; + +struct rockchip_phy_funcs { + int (*init)(struct rockchip_phy *phy); + int (*power_on)(struct rockchip_phy *phy); + int (*power_off)(struct rockchip_phy *phy); + unsigned long (*set_pll)(struct rockchip_phy *phy, unsigned long rate); + int (*set_bus_width)(struct rockchip_phy *phy, u32 bus_width); + long (*round_rate)(struct rockchip_phy *phy, unsigned long rate); + int (*set_mode)(struct rockchip_phy *phy, enum phy_mode mode); +}; + +struct rockchip_phy { + const struct rockchip_phy_funcs *funcs; +}; + +int rockchip_phy_init(struct rockchip_phy *phy); +int rockchip_phy_power_off(struct rockchip_phy *phy); +int rockchip_phy_power_on(struct rockchip_phy *phy); +unsigned long rockchip_phy_set_pll(struct rockchip_phy *phy, + unsigned long rate); +int rockchip_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width); +long rockchip_phy_round_rate(struct rockchip_phy *phy, unsigned long rate); +int rockchip_phy_set_mode(struct rockchip_phy *phy, enum phy_mode mode); + +struct rockchip_phy *rockchip_phy_by_id(unsigned int id); + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/samsung_mipi_dcphy.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/samsung_mipi_dcphy.c new file mode 100644 index 0000000..bd088b4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DisplayLib/samsung_mipi_dcphy.c @@ -0,0 +1,1830 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2008-2018 Fuzhou Rockchip Electronics Co., Ltd + * + * Author: Guochun Huang + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "rockchip_phy.h" + +#define MAX_DPHY_BW 4500000L +#define MAX_CPHY_BW 2000000L + +#define MSEC_PER_SEC 1000L +#define USEC_PER_SEC 1000000LL +#define PSEC_PER_SEC 1000000000000LL + +#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) +#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK((h), (l)) << 16)) + +#define BIAS_CON0 0x0000 +#define BIAS_CON1 0x0004 +#define BIAS_CON2 0x0008 +#define BIAS_CON4 0x0010 +#define I_MUX_SEL_MASK GENMASK(6, 5) +#define I_MUX_SEL(x) UPDATE(x, 6, 5) + +#define PLL_CON0 0x0100 +#define PLL_EN BIT(12) +#define S_MASK GENMASK(10, 8) +#define S(x) UPDATE(x, 10, 8) +#define P_MASK GENMASK(5, 0) +#define P(x) UPDATE(x, 5, 0) +#define PLL_CON1 0x0104 +#define PLL_CON2 0x0108 +#define M_MASK GENMASK(9, 0) +#define M(x) UPDATE(x, 9, 0) +#define PLL_CON3 0x010c +#define MRR_MASK GENMASK(13, 8) +#define MRR(x) UPDATE(x, 13, 8) +#define MFR_MASK GENMASK(7, 0) +#define MFR(x) UPDATE(x, 7, 0) +#define PLL_CON4 0x0110 +#define SSCG_EN BIT(11) +#define PLL_CON5 0x0114 +#define RESET_N_SEL BIT(10) +#define PLL_ENABLE_SEL BIT(8) +#define PLL_CON6 0x0118 +#define PLL_CON7 0x011c +#define PLL_LOCK_CNT(x) UPDATE(x, 15, 0) +#define PLL_CON8 0x0120 +#define PLL_STB_CNT(x) UPDATE(x, 15, 0) +#define PLL_STAT0 0x0140 +#define PLL_LOCK BIT(0) + +#define DPHY_MC_GNR_CON0 0x0300 +#define PHY_READY BIT(1) +#define PHY_ENABLE BIT(0) +#define DPHY_MC_GNR_CON1 0x0304 +#define T_PHY_READY(x) UPDATE(x, 15, 0) +#define DPHY_MC_ANA_CON0 0x0308 +#define DPHY_MC_ANA_CON1 0x030c +#define DPHY_MC_ANA_CON2 0x0310 +#define HS_VREG_AMP_ICON(x) UPDATE(x, 1, 0) +#define DPHY_MC_TIME_CON0 0x0330 +#define HSTX_CLK_SEL BIT(12) +#define T_LPX(x) UPDATE(x, 11, 4) +#define DPHY_MC_TIME_CON1 0x0334 +#define T_CLK_ZERO(x) UPDATE(x, 15, 8) +#define T_CLK_PREPARE(x) UPDATE(x, 7, 0) +#define DPHY_MC_TIME_CON2 0x0338 +#define T_HS_EXIT(x) UPDATE(x, 15, 8) +#define T_CLK_TRAIL(x) UPDATE(x, 7, 0) +#define DPHY_MC_TIME_CON3 0x033c +#define T_CLK_POST(x) UPDATE(x, 7, 0) +#define DPHY_MC_TIME_CON4 0x0340 +#define T_ULPS_EXIT(x) UPDATE(x, 9, 0) +#define DPHY_MC_DESKEW_CON0 0x0350 +#define SKEW_CAL_RUN_TIME(x) UPDATE(x, 15, 12) + +#define SKEW_CAL_INIT_RUN_TIME(x) UPDATE(x, 11, 8) +#define SKEW_CAL_INIT_WAIT_TIME(x) UPDATE(x, 7, 4) +#define SKEW_CAL_EN BIT(0) + +#define COMBO_MD0_GNR_CON0 0x0400 +#define COMBO_MD0_GNR_CON1 0x0404 +#define COMBO_MD0_ANA_CON0 0x0408 +#define COMBO_MD0_ANA_CON1 0x040C +#define COMBO_MD0_ANA_CON2 0x0410 + +#define COMBO_MD0_TIME_CON0 0x0430 +#define COMBO_MD0_TIME_CON1 0x0434 +#define COMBO_MD0_TIME_CON2 0x0438 +#define COMBO_MD0_TIME_CON3 0x043C +#define COMBO_MD0_TIME_CON4 0x0440 +#define COMBO_MD0_DATA_CON0 0x0444 + +#define COMBO_MD1_GNR_CON0 0x0500 +#define COMBO_MD1_GNR_CON1 0x0504 +#define COMBO_MD1_ANA_CON0 0x0508 +#define COMBO_MD1_ANA_CON1 0x050c +#define COMBO_MD1_ANA_CON2 0x0510 +#define COMBO_MD1_TIME_CON0 0x0530 +#define COMBO_MD1_TIME_CON1 0x0534 +#define COMBO_MD1_TIME_CON2 0x0538 +#define COMBO_MD1_TIME_CON3 0x053C +#define COMBO_MD1_TIME_CON4 0x0540 +#define COMBO_MD1_DATA_CON0 0x0544 + +#define COMBO_MD2_GNR_CON0 0x0600 +#define COMBO_MD2_GNR_CON1 0x0604 +#define COMBO_MD2_ANA_CON0 0X0608 +#define COMBO_MD2_ANA_CON1 0X060C +#define COMBO_MD2_ANA_CON2 0X0610 +#define COMBO_MD2_TIME_CON0 0x0630 +#define COMBO_MD2_TIME_CON1 0x0634 +#define COMBO_MD2_TIME_CON2 0x0638 +#define COMBO_MD2_TIME_CON3 0x063C +#define COMBO_MD2_TIME_CON4 0x0640 +#define COMBO_MD2_DATA_CON0 0x0644 + +#define DPHY_MD3_GNR_CON0 0x0700 +#define DPHY_MD3_GNR_CON1 0x0704 +#define DPHY_MD3_ANA_CON0 0X0708 +#define DPHY_MD3_ANA_CON1 0X070C +#define DPHY_MD3_ANA_CON2 0X0710 +#define DPHY_MD3_TIME_CON0 0x0730 +#define DPHY_MD3_TIME_CON1 0x0734 +#define DPHY_MD3_TIME_CON2 0x0738 +#define DPHY_MD3_TIME_CON3 0x073C +#define DPHY_MD3_TIME_CON4 0x0740 +#define DPHY_MD3_DATA_CON0 0x0744 + +#define T_LP_EXIT_SKEW(x) UPDATE(x, 3, 2) +#define T_LP_ENTRY_SKEW(x) UPDATE(x, 1, 0) +#define T_HS_ZERO(x) UPDATE(x, 15, 8) +#define T_HS_PREPARE(x) UPDATE(x, 7, 0) +#define T_HS_EXIT(x) UPDATE(x, 15, 8) +#define T_HS_TRAIL(x) UPDATE(x, 7, 0) +#define T_TA_GET(x) UPDATE(x, 7, 4) +#define T_TA_GO(x) UPDATE(x, 3, 0) + +/* MIPI_CDPHY_GRF registers */ +#define MIPI_DCPHY_GRF_CON0 0x0000 +#define S_CPHY_MODE HIWORD_UPDATE(1, 3, 3) +#define M_CPHY_MODE HIWORD_UPDATE(1, 0, 0) + +struct samsung_mipi_dphy_timing { + unsigned int max_lane_mbps; + u8 clk_prepare; + u8 clk_zero; + u8 clk_post; + u8 clk_trail_eot; + u8 hs_prepare; + u8 hs_zero; + u8 hs_trail_eot; + u8 lpx; + u8 hs_exit; + u8 hs_settle; +}; + +struct samsung_mipi_cphy_timing { + unsigned int max_lane_msps; + u8 prepare_3; + u8 prebegin_3; + u8 post_3; + u8 lpx; + u8 hs_exit; + u8 settle_3; +}; + +struct samsung_mipi_dcphy { + UINT32 Signature; + struct rockchip_phy phy; + enum phy_mode mode; + UINTN base; + UINTN grf; + int id; + int lanes; + bool c_option; + struct reset_ctl m_phy_rst; + + struct { + unsigned long long rate; + u8 prediv; + u16 fbdiv; + long dsm; + u8 scaler; + + bool ssc_en; + u8 mfr; + u8 mrr; + } pll; +}; + +#define SAMSUNG_MIPI_DCPHY_SIGNATURE SIGNATURE_32 ('S', 'M', 'D', 'c') + +#define SAMSUNG_MIPI_DCPHY_FROM_PHY(a) \ + CR (a, struct samsung_mipi_dcphy, phy, SAMSUNG_MIPI_DCPHY_SIGNATURE) + +static const +struct samsung_mipi_dphy_timing samsung_mipi_dphy_timing_table[] = { + {6500, 32, 117, 31, 28, 30, 56, 27, 24, 44, 37}, + {6490, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37}, + {6480, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37}, + {6470, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37}, + {6460, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37}, + {6450, 32, 115, 31, 28, 30, 56, 27, 24, 44, 37}, + {6440, 32, 115, 31, 28, 30, 56, 27, 24, 44, 37}, + {6430, 31, 116, 31, 28, 30, 55, 27, 24, 44, 37}, + {6420, 31, 116, 31, 28, 30, 55, 27, 24, 44, 37}, + {6410, 31, 116, 31, 27, 30, 55, 27, 24, 44, 37}, + {6400, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36}, + {6390, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36}, + {6380, 31, 115, 30, 27, 30, 55, 27, 23, 43, 36}, + {6370, 31, 115, 30, 27, 30, 55, 26, 23, 43, 36}, + {6360, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36}, + {6350, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36}, + {6340, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36}, + {6330, 31, 114, 30, 27, 30, 54, 26, 23, 43, 36}, + {6320, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36}, + {6310, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36}, + {6300, 31, 113, 30, 27, 30, 54, 26, 23, 43, 36}, + {6290, 31, 113, 30, 27, 29, 54, 26, 23, 43, 36}, + {6280, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36}, + {6270, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36}, + {6260, 31, 112, 30, 27, 29, 54, 26, 23, 43, 36}, + {6250, 31, 112, 30, 27, 29, 54, 26, 23, 42, 36}, + {6240, 30, 113, 30, 27, 29, 54, 26, 23, 42, 36}, + {6230, 30, 112, 30, 27, 29, 54, 26, 23, 42, 35}, + {6220, 30, 112, 30, 27, 29, 53, 26, 23, 42, 35}, + {6210, 30, 112, 30, 27, 29, 53, 26, 23, 42, 35}, + {6200, 30, 112, 29, 27, 29, 53, 26, 23, 42, 35}, + {6190, 30, 111, 29, 27, 29, 53, 26, 23, 42, 35}, + {6180, 30, 111, 29, 27, 29, 53, 26, 23, 42, 35}, + {6170, 30, 111, 29, 26, 29, 53, 26, 23, 42, 35}, + {6160, 30, 111, 29, 26, 29, 53, 26, 23, 42, 35}, + {6150, 30, 110, 29, 26, 29, 53, 26, 23, 42, 35}, + {6140, 30, 110, 29, 26, 29, 52, 26, 23, 42, 35}, + {6130, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35}, + {6120, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35}, + {6110, 30, 110, 29, 26, 29, 52, 25, 22, 42, 35}, + {6100, 30, 109, 29, 26, 29, 52, 25, 22, 41, 35}, + {6090, 30, 109, 29, 26, 29, 52, 25, 22, 41, 35}, + {6080, 30, 109, 29, 26, 28, 53, 25, 22, 41, 35}, + {6070, 30, 109, 29, 26, 28, 52, 25, 22, 41, 34}, + {6060, 30, 108, 29, 26, 28, 52, 25, 22, 41, 34}, + {6050, 30, 108, 29, 26, 28, 52, 25, 22, 41, 34}, + {6040, 29, 109, 29, 26, 28, 52, 25, 22, 41, 34}, + {6030, 29, 109, 29, 26, 28, 52, 25, 22, 41, 34}, + {6020, 29, 108, 29, 26, 28, 52, 25, 22, 41, 34}, + {6010, 29, 108, 29, 26, 28, 52, 25, 22, 41, 34}, + {6000, 29, 108, 28, 26, 28, 51, 25, 22, 41, 34}, + {5990, 29, 108, 28, 26, 28, 51, 25, 22, 41, 34}, + {5980, 29, 107, 28, 26, 28, 51, 25, 22, 41, 34}, + {5970, 29, 107, 28, 26, 28, 51, 25, 22, 41, 34}, + {5960, 29, 107, 28, 26, 28, 51, 25, 22, 40, 34}, + {5950, 29, 107, 28, 26, 28, 51, 25, 22, 40, 34}, + {5940, 29, 107, 28, 25, 28, 51, 25, 22, 40, 34}, + {5930, 29, 106, 28, 25, 28, 50, 25, 22, 40, 34}, + {5920, 29, 106, 28, 25, 28, 50, 25, 22, 40, 34}, + {5910, 29, 106, 28, 25, 28, 50, 25, 22, 40, 34}, + {5900, 29, 106, 28, 25, 28, 50, 24, 22, 40, 33}, + {5890, 29, 105, 28, 25, 28, 50, 24, 22, 40, 33}, + {5880, 29, 105, 28, 25, 28, 50, 24, 22, 40, 33}, + {5870, 29, 105, 28, 25, 27, 51, 24, 22, 40, 33}, + {5860, 29, 105, 28, 25, 27, 51, 24, 21, 40, 33}, + {5850, 29, 104, 28, 25, 27, 50, 24, 21, 40, 33}, + {5840, 28, 105, 28, 25, 27, 50, 24, 21, 40, 33}, + {5830, 28, 105, 28, 25, 27, 50, 24, 21, 40, 33}, + {5820, 28, 105, 28, 25, 27, 50, 24, 21, 40, 33}, + {5810, 28, 104, 28, 25, 27, 50, 24, 21, 39, 33}, + {5800, 28, 104, 27, 25, 27, 50, 24, 21, 39, 33}, + {5790, 28, 104, 27, 25, 27, 50, 24, 21, 39, 33}, + {5780, 28, 104, 27, 25, 27, 49, 24, 21, 39, 33}, + {5770, 28, 104, 27, 25, 27, 49, 24, 21, 39, 33}, + {5760, 28, 103, 27, 25, 27, 49, 24, 21, 39, 33}, + {5750, 28, 103, 27, 25, 27, 49, 24, 21, 39, 33}, + {5740, 28, 103, 27, 25, 27, 49, 24, 21, 39, 33}, + {5730, 28, 103, 27, 25, 27, 49, 24, 21, 39, 32}, + {5720, 28, 102, 27, 25, 27, 49, 24, 21, 39, 32}, + {5710, 28, 102, 27, 25, 27, 48, 24, 21, 39, 32}, + {5700, 28, 102, 27, 24, 27, 48, 24, 21, 39, 32}, + {5690, 28, 102, 27, 24, 27, 48, 24, 21, 39, 32}, + {5680, 28, 101, 27, 24, 27, 48, 24, 21, 39, 32}, + {5670, 28, 101, 27, 24, 27, 48, 23, 21, 38, 32}, + {5660, 28, 101, 27, 24, 26, 49, 23, 21, 38, 32}, + {5650, 28, 101, 27, 24, 26, 49, 23, 21, 38, 32}, + {5640, 27, 101, 27, 24, 26, 48, 23, 21, 38, 32}, + {5630, 27, 101, 27, 24, 26, 48, 23, 21, 38, 32}, + {5620, 27, 101, 27, 24, 26, 48, 23, 21, 38, 32}, + {5610, 27, 101, 27, 24, 26, 48, 23, 21, 38, 32}, + {5600, 27, 101, 26, 24, 26, 48, 23, 20, 38, 32}, + {5590, 27, 100, 26, 24, 26, 48, 23, 20, 38, 32}, + {5580, 27, 100, 26, 24, 26, 48, 23, 20, 38, 32}, + {5570, 27, 100, 26, 24, 26, 48, 23, 20, 38, 31}, + {5560, 27, 100, 26, 24, 26, 47, 23, 20, 38, 31}, + {5550, 27, 99, 26, 24, 26, 47, 23, 20, 38, 31}, + {5540, 27, 99, 26, 24, 26, 47, 23, 20, 38, 31}, + {5530, 27, 99, 26, 24, 26, 47, 23, 20, 38, 31}, + {5520, 27, 99, 26, 24, 26, 47, 23, 20, 37, 31}, + {5510, 27, 98, 26, 24, 26, 47, 23, 20, 37, 31}, + {5500, 27, 98, 26, 24, 26, 47, 23, 20, 37, 31}, + {5490, 27, 98, 26, 24, 26, 46, 23, 20, 37, 31}, + {5480, 27, 98, 26, 24, 26, 46, 23, 20, 37, 31}, + {5470, 27, 97, 26, 23, 26, 46, 23, 20, 37, 31}, + {5460, 27, 97, 26, 23, 26, 46, 23, 20, 37, 31}, + {5450, 27, 97, 26, 23, 25, 47, 23, 20, 37, 31}, + {5440, 26, 98, 26, 23, 25, 47, 23, 20, 37, 31}, + {5430, 26, 98, 26, 23, 25, 47, 22, 20, 37, 31}, + {5420, 26, 97, 26, 23, 25, 46, 22, 20, 37, 31}, + {5410, 26, 97, 26, 23, 25, 46, 22, 20, 37, 31}, + {5400, 26, 97, 25, 23, 25, 46, 22, 20, 37, 30}, + {5390, 26, 97, 25, 23, 25, 46, 22, 20, 37, 30}, + {5380, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30}, + {5370, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30}, + {5360, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30}, + {5350, 26, 96, 25, 23, 25, 46, 22, 20, 36, 30}, + {5340, 26, 95, 25, 23, 25, 45, 22, 20, 36, 30}, + {5330, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30}, + {5320, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30}, + {5310, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30}, + {5300, 26, 95, 25, 23, 25, 45, 22, 19, 36, 30}, + {5290, 26, 94, 25, 23, 25, 45, 22, 19, 36, 30}, + {5280, 26, 94, 25, 23, 25, 45, 22, 19, 36, 30}, + {5270, 26, 94, 25, 23, 25, 44, 22, 19, 36, 30}, + {5260, 26, 94, 25, 23, 25, 44, 22, 19, 36, 30}, + {5250, 25, 94, 25, 23, 24, 45, 22, 19, 36, 30}, + {5240, 25, 94, 25, 23, 24, 45, 22, 19, 36, 29}, + {5230, 25, 94, 25, 22, 24, 45, 22, 19, 35, 29}, + {5220, 25, 94, 25, 22, 24, 45, 22, 19, 35, 29}, + {5210, 25, 93, 25, 22, 24, 45, 22, 19, 35, 29}, + {5200, 25, 93, 24, 22, 24, 44, 21, 19, 35, 29}, + {5190, 25, 93, 24, 22, 24, 44, 21, 19, 35, 29}, + {5180, 25, 93, 24, 22, 24, 44, 21, 19, 35, 29}, + {5170, 25, 92, 24, 22, 24, 44, 21, 19, 35, 29}, + {5160, 25, 92, 24, 22, 24, 44, 21, 19, 35, 29}, + {5150, 25, 92, 24, 22, 24, 44, 21, 19, 35, 29}, + {5140, 25, 92, 24, 22, 24, 44, 21, 19, 35, 29}, + {5130, 25, 92, 24, 22, 24, 43, 21, 19, 35, 29}, + {5120, 25, 91, 24, 22, 24, 43, 21, 19, 35, 29}, + {5110, 25, 91, 24, 22, 24, 43, 21, 19, 35, 29}, + {5100, 25, 91, 24, 22, 24, 43, 21, 19, 35, 29}, + {5090, 25, 91, 24, 22, 24, 43, 21, 19, 34, 29}, + {5080, 25, 90, 24, 22, 24, 43, 21, 19, 34, 29}, + {5070, 25, 90, 24, 22, 24, 43, 21, 19, 34, 28}, + {5060, 25, 90, 24, 22, 24, 43, 21, 18, 34, 28}, + {5050, 24, 91, 24, 22, 24, 42, 21, 18, 34, 28}, + {5040, 24, 90, 24, 22, 23, 43, 21, 18, 34, 28}, + {5030, 24, 90, 24, 22, 23, 43, 21, 18, 34, 28}, + {5020, 24, 90, 24, 22, 23, 43, 21, 18, 34, 28}, + {5010, 24, 90, 24, 22, 23, 43, 21, 18, 34, 28}, + {5000, 24, 89, 23, 21, 23, 43, 21, 18, 34, 28}, + {4990, 24, 89, 23, 21, 23, 43, 21, 18, 34, 28}, + {4980, 24, 89, 23, 21, 23, 42, 21, 18, 34, 28}, + {4970, 24, 89, 23, 21, 23, 42, 21, 18, 34, 28}, + {4960, 24, 89, 23, 21, 23, 42, 20, 18, 34, 28}, + {4950, 24, 88, 23, 21, 23, 42, 20, 18, 34, 28}, + {4940, 24, 88, 23, 21, 23, 42, 20, 18, 33, 28}, + {4930, 24, 88, 23, 21, 23, 42, 20, 18, 33, 28}, + {4920, 24, 88, 23, 21, 23, 42, 20, 18, 33, 28}, + {4910, 24, 87, 23, 21, 23, 41, 20, 18, 33, 28}, + {4900, 24, 87, 23, 21, 23, 41, 20, 18, 33, 27}, + {4890, 24, 87, 23, 21, 23, 41, 20, 18, 33, 27}, + {4880, 24, 87, 23, 21, 23, 41, 20, 18, 33, 27}, + {4870, 24, 86, 23, 21, 23, 41, 20, 18, 33, 27}, + {4860, 24, 86, 23, 21, 23, 41, 20, 18, 33, 27}, + {4850, 23, 87, 23, 21, 23, 41, 20, 18, 33, 27}, + {4840, 23, 87, 23, 21, 23, 40, 20, 18, 33, 27}, + {4830, 23, 86, 23, 21, 22, 41, 20, 18, 33, 27}, + {4820, 23, 86, 23, 21, 22, 41, 20, 18, 33, 27}, + {4810, 23, 86, 23, 21, 22, 41, 20, 18, 33, 27}, + {4800, 23, 86, 22, 21, 22, 41, 20, 17, 32, 27}, + {4790, 23, 86, 22, 21, 22, 41, 20, 17, 32, 27}, + {4780, 23, 85, 22, 21, 22, 41, 20, 17, 32, 27}, + {4770, 23, 85, 22, 21, 22, 41, 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33, 4, 47, 24, 4, 41}, + { 820, 32, 12, 3, 54, 33, 4, 47, 24, 4, 41}, + { 810, 32, 12, 3, 53, 33, 4, 47, 24, 4, 40}, + { 800, 31, 12, 2, 53, 32, 4, 46, 23, 4, 40}, + { 790, 31, 12, 2, 53, 32, 4, 46, 23, 4, 39}, + { 780, 30, 12, 2, 52, 31, 4, 46, 23, 4, 39}, + { 770, 30, 11, 2, 52, 31, 4, 45, 23, 4, 39}, + { 760, 30, 11, 2, 52, 31, 3, 45, 22, 4, 38}, + { 750, 29, 11, 2, 51, 30, 3, 45, 22, 4, 38}, + { 740, 29, 11, 2, 51, 30, 3, 44, 22, 4, 37}, + { 730, 28, 11, 2, 51, 31, 3, 44, 22, 4, 37}, + { 720, 28, 10, 2, 50, 30, 3, 44, 22, 4, 36}, + { 710, 28, 10, 2, 50, 30, 3, 43, 22, 4, 36}, + { 700, 27, 10, 2, 50, 28, 3, 43, 20, 3, 35}, + { 690, 27, 10, 2, 49, 28, 3, 43, 20, 3, 35}, + { 680, 26, 10, 2, 49, 28, 3, 42, 20, 3, 34}, + { 670, 26, 10, 2, 49, 27, 3, 42, 20, 3, 34}, + { 660, 26, 9, 2, 48, 27, 3, 42, 19, 3, 33}, + { 650, 25, 9, 2, 48, 26, 3, 41, 19, 3, 33}, + { 640, 25, 9, 2, 48, 26, 2, 41, 19, 3, 32}, + { 630, 24, 9, 2, 47, 26, 2, 40, 18, 3, 32}, + { 620, 24, 9, 2, 47, 26, 2, 40, 19, 3, 31}, + { 610, 24, 8, 2, 47, 26, 2, 40, 19, 3, 31}, + { 600, 23, 8, 1, 46, 26, 2, 39, 18, 3, 30}, + { 590, 23, 8, 1, 46, 24, 2, 39, 17, 3, 30}, + { 580, 22, 8, 1, 46, 24, 2, 39, 17, 3, 29}, + { 570, 22, 8, 1, 45, 23, 2, 38, 17, 3, 29}, + { 560, 22, 7, 1, 45, 23, 2, 38, 16, 2, 28}, + { 550, 21, 7, 1, 45, 23, 2, 38, 16, 2, 28}, + { 540, 21, 7, 1, 44, 22, 2, 37, 16, 2, 27}, + { 530, 20, 7, 1, 44, 22, 1, 37, 15, 2, 27}, + { 520, 20, 7, 1, 43, 21, 1, 37, 15, 2, 27}, + { 510, 20, 6, 1, 43, 21, 1, 36, 15, 2, 26}, + { 500, 19, 6, 1, 43, 22, 1, 36, 15, 2, 26}, + { 490, 19, 6, 1, 42, 21, 1, 36, 15, 2, 25}, + { 480, 18, 6, 1, 42, 21, 1, 35, 15, 2, 25}, + { 470, 18, 6, 1, 42, 21, 1, 35, 15, 2, 24}, + { 460, 18, 6, 1, 41, 19, 1, 35, 13, 2, 24}, + { 450, 17, 5, 1, 41, 19, 1, 34, 13, 2, 23}, + { 440, 17, 5, 1, 41, 18, 1, 34, 13, 2, 23}, + { 430, 16, 5, 1, 40, 18, 0, 34, 12, 2, 22}, + { 420, 16, 5, 1, 40, 18, 0, 33, 12, 2, 22}, + { 410, 16, 5, 1, 40, 17, 0, 33, 12, 1, 21}, + { 400, 15, 5, 0, 39, 17, 0, 33, 11, 1, 21}, + { 390, 15, 4, 0, 39, 17, 0, 32, 12, 1, 20}, + { 380, 14, 4, 0, 39, 17, 0, 32, 12, 1, 20}, + { 370, 14, 4, 0, 38, 17, 0, 32, 12, 1, 19}, + { 360, 14, 4, 0, 38, 15, 0, 31, 10, 1, 19}, + { 350, 13, 4, 0, 38, 15, 0, 31, 10, 1, 18}, + { 340, 13, 3, 0, 37, 15, 0, 31, 10, 1, 18}, + { 330, 12, 3, 0, 37, 14, 0, 30, 9, 1, 17}, + { 320, 12, 3, 0, 37, 14, 0, 30, 9, 1, 17}, + { 310, 12, 3, 0, 36, 13, 0, 30, 9, 1, 16}, + { 300, 11, 3, 0, 36, 13, 0, 29, 8, 1, 16}, + { 290, 11, 2, 0, 36, 13, 0, 29, 8, 1, 15}, + { 280, 10, 2, 0, 35, 12, 0, 29, 8, 1, 15}, + { 270, 10, 2, 0, 35, 12, 0, 28, 8, 0, 14}, + { 260, 9, 2, 0, 35, 12, 0, 28, 8, 0, 14}, + { 250, 9, 2, 0, 34, 12, 0, 28, 8, 0, 14}, + { 240, 9, 2, 0, 34, 12, 0, 27, 8, 0, 13}, + { 230, 8, 1, 0, 34, 10, 0, 27, 6, 0, 13}, + { 220, 8, 1, 0, 33, 10, 0, 27, 6, 0, 12}, + { 210, 7, 1, 0, 33, 10, 0, 26, 6, 0, 12}, + { 200, 7, 1, 0, 33, 9, 0, 26, 5, 0, 11}, + { 190, 7, 1, 0, 32, 9, 0, 25, 5, 0, 11}, + { 180, 6, 1, 0, 32, 8, 0, 25, 5, 0, 10}, + { 170, 6, 0, 0, 32, 8, 0, 25, 5, 0, 10}, + { 160, 5, 0, 0, 31, 8, 0, 24, 4, 0, 9}, + { 150, 5, 0, 0, 31, 8, 0, 24, 5, 0, 9}, + { 140, 5, 0, 0, 31, 8, 0, 24, 5, 0, 8}, + { 130, 4, 0, 0, 30, 6, 0, 23, 3, 0, 8}, + { 120, 4, 0, 0, 30, 6, 0, 23, 3, 0, 7}, + { 110, 3, 0, 0, 30, 6, 0, 23, 3, 0, 7}, + { 100, 3, 0, 0, 29, 5, 0, 22, 2, 0, 6}, + { 90, 3, 0, 0, 29, 5, 0, 22, 2, 0, 6}, + { 80, 2, 0, 0, 28, 5, 0, 22, 2, 0, 5}, +}; + +static const +struct samsung_mipi_cphy_timing samsung_mipi_cphy_timing_table[] = { + { 3500, 39, 50, 25, 29, 54, 1 }, + { 3490, 39, 50, 25, 29, 54, 1 }, + { 3480, 39, 50, 25, 29, 54, 1 }, + { 3470, 39, 50, 25, 29, 54, 1 }, + { 3460, 39, 50, 25, 29, 54, 1 }, + { 3450, 39, 50, 25, 29, 54, 1 }, + { 3440, 38, 50, 25, 29, 54, 1 }, + { 3430, 38, 50, 25, 29, 53, 1 }, + { 3420, 38, 50, 25, 29, 53, 1 }, + { 3410, 38, 50, 25, 29, 53, 1 }, + { 3400, 38, 50, 25, 29, 53, 1 }, + { 3390, 38, 50, 25, 29, 53, 1 }, + { 3380, 38, 50, 25, 28, 53, 1 }, + { 3370, 38, 50, 25, 28, 52, 1 }, + { 3360, 37, 50, 25, 28, 52, 1 }, + { 3350, 37, 50, 25, 28, 52, 1 }, + { 3340, 37, 50, 25, 28, 52, 1 }, + { 3330, 37, 50, 25, 28, 52, 1 }, + { 3320, 37, 50, 25, 28, 52, 1 }, + { 3310, 37, 50, 25, 28, 52, 1 }, + { 3300, 37, 50, 25, 28, 51, 1 }, + { 3290, 37, 50, 25, 28, 51, 1 }, + { 3280, 37, 50, 25, 28, 51, 1 }, + { 3270, 36, 50, 25, 28, 51, 1 }, + { 3260, 36, 50, 25, 27, 51, 1 }, + { 3250, 36, 50, 25, 27, 51, 1 }, + { 3240, 36, 50, 25, 27, 50, 1 }, + { 3230, 36, 50, 25, 27, 50, 1 }, + { 3220, 36, 50, 25, 27, 50, 1 }, + { 3210, 36, 50, 25, 27, 50, 1 }, + { 3200, 36, 50, 25, 27, 50, 1 }, + { 3190, 36, 50, 25, 27, 50, 1 }, + { 3180, 35, 50, 25, 27, 49, 1 }, + { 3170, 35, 50, 25, 27, 49, 1 }, + { 3160, 35, 50, 25, 27, 49, 1 }, + { 3150, 35, 50, 25, 26, 49, 1 }, + { 3140, 35, 50, 25, 26, 49, 1 }, + { 3130, 35, 50, 25, 26, 49, 1 }, + { 3120, 35, 50, 25, 26, 49, 1 }, + { 3110, 35, 50, 25, 26, 48, 1 }, + { 3100, 34, 50, 25, 26, 48, 1 }, + { 3090, 34, 50, 25, 26, 48, 1 }, + { 3080, 34, 50, 25, 26, 48, 1 }, + { 3070, 34, 50, 25, 26, 48, 1 }, + { 3060, 34, 50, 25, 26, 48, 1 }, + { 3050, 34, 50, 25, 26, 47, 1 }, + { 3040, 34, 50, 25, 26, 47, 1 }, + { 3030, 34, 50, 25, 25, 47, 1 }, + { 3020, 34, 50, 25, 25, 47, 1 }, + { 3010, 33, 50, 25, 25, 47, 1 }, + { 3000, 33, 50, 25, 25, 47, 1 }, + { 2990, 33, 50, 25, 25, 46, 1 }, + { 2980, 33, 50, 25, 25, 46, 1 }, + { 2970, 33, 50, 25, 25, 46, 1 }, + { 2960, 33, 50, 25, 25, 46, 1 }, + { 2950, 33, 50, 25, 25, 46, 1 }, + { 2940, 33, 50, 25, 25, 46, 1 }, + { 2930, 33, 50, 25, 25, 46, 1 }, + { 2920, 32, 50, 25, 25, 45, 1 }, + { 2910, 32, 50, 25, 24, 45, 1 }, + { 2900, 32, 50, 25, 24, 45, 1 }, + { 2890, 32, 50, 25, 24, 45, 1 }, + { 2880, 32, 50, 25, 24, 45, 1 }, + { 2870, 32, 50, 25, 24, 45, 1 }, + { 2860, 32, 50, 25, 24, 44, 1 }, + { 2850, 32, 50, 25, 24, 44, 1 }, + { 2840, 31, 50, 25, 24, 44, 1 }, + { 2830, 31, 50, 25, 24, 44, 1 }, + { 2820, 31, 50, 25, 24, 44, 1 }, + { 2810, 31, 50, 25, 24, 44, 1 }, + { 2800, 31, 50, 25, 23, 43, 1 }, + { 2790, 31, 50, 25, 23, 43, 1 }, + { 2780, 31, 50, 25, 23, 43, 1 }, + { 2770, 31, 50, 25, 23, 43, 1 }, + { 2760, 31, 50, 25, 23, 43, 1 }, + { 2750, 30, 50, 25, 23, 43, 1 }, + { 2740, 30, 50, 25, 23, 43, 1 }, + { 2730, 30, 50, 25, 23, 42, 1 }, + { 2720, 30, 50, 25, 23, 42, 1 }, + { 2710, 30, 50, 25, 23, 42, 1 }, + { 2700, 30, 50, 25, 23, 42, 1 }, + { 2690, 30, 50, 25, 23, 42, 1 }, + { 2680, 30, 50, 25, 22, 42, 1 }, + { 2670, 30, 50, 25, 22, 41, 1 }, + { 2660, 29, 50, 25, 22, 41, 1 }, + { 2650, 29, 50, 25, 22, 41, 1 }, + { 2640, 29, 50, 25, 22, 41, 1 }, + { 2630, 29, 50, 25, 22, 41, 1 }, + { 2620, 29, 50, 25, 22, 41, 1 }, + { 2610, 29, 50, 25, 22, 41, 1 }, + { 2600, 29, 50, 25, 22, 40, 1 }, + { 2590, 29, 50, 25, 22, 40, 1 }, + { 2580, 28, 50, 25, 22, 40, 1 }, + { 2570, 28, 50, 25, 22, 40, 1 }, + { 2560, 28, 50, 25, 21, 40, 1 }, + { 2550, 28, 50, 25, 21, 40, 1 }, + { 2540, 28, 50, 25, 21, 39, 1 }, + { 2530, 28, 50, 25, 21, 39, 1 }, + { 2520, 28, 50, 25, 21, 39, 1 }, + { 2510, 28, 50, 25, 21, 39, 1 }, + { 2500, 28, 50, 25, 21, 39, 1 }, + { 2490, 27, 50, 25, 21, 39, 1 }, + { 2480, 27, 50, 25, 21, 38, 1 }, + { 2470, 27, 50, 25, 21, 38, 1 }, + { 2460, 27, 50, 25, 21, 38, 1 }, + { 2450, 27, 50, 25, 20, 38, 1 }, + { 2440, 27, 50, 25, 20, 38, 1 }, + { 2430, 27, 50, 25, 20, 38, 1 }, + { 2420, 27, 50, 25, 20, 38, 1 }, + { 2410, 27, 50, 25, 20, 37, 1 }, + { 2400, 26, 50, 25, 20, 37, 1 }, + { 2390, 26, 50, 25, 20, 37, 1 }, + { 2380, 26, 50, 25, 20, 37, 1 }, + { 2370, 26, 50, 25, 20, 37, 1 }, + { 2360, 26, 50, 25, 20, 37, 1 }, + { 2350, 26, 50, 25, 20, 36, 1 }, + { 2340, 26, 50, 25, 20, 36, 1 }, + { 2330, 26, 50, 25, 19, 36, 1 }, + { 2320, 25, 50, 25, 19, 36, 1 }, + { 2310, 25, 50, 25, 19, 36, 1 }, + { 2300, 25, 50, 25, 19, 36, 1 }, + { 2290, 25, 50, 25, 19, 35, 1 }, + { 2280, 25, 50, 25, 19, 35, 1 }, + { 2270, 25, 50, 25, 19, 35, 1 }, + { 2260, 25, 50, 25, 19, 35, 1 }, + { 2250, 25, 50, 25, 19, 35, 1 }, + { 2240, 25, 50, 25, 19, 35, 1 }, + { 2230, 24, 50, 25, 19, 35, 1 }, + { 2220, 24, 50, 25, 19, 34, 1 }, + { 2210, 24, 50, 25, 18, 34, 1 }, + { 2200, 24, 50, 25, 18, 34, 1 }, + { 2190, 24, 50, 25, 18, 34, 1 }, + { 2180, 24, 50, 25, 18, 34, 1 }, + { 2170, 24, 50, 25, 18, 34, 1 }, + { 2160, 24, 50, 25, 18, 33, 1 }, + { 2150, 24, 50, 25, 18, 33, 1 }, + { 2140, 23, 50, 25, 18, 33, 1 }, + { 2130, 23, 50, 25, 18, 33, 1 }, + { 2120, 23, 50, 25, 18, 33, 1 }, + { 2110, 23, 50, 25, 18, 33, 1 }, + { 2100, 23, 50, 25, 17, 32, 1 }, + { 2090, 23, 50, 25, 17, 32, 1 }, + { 2080, 23, 50, 25, 17, 32, 1 }, + { 2070, 23, 50, 25, 17, 32, 1 }, + { 2060, 22, 50, 25, 17, 32, 1 }, + { 2050, 22, 50, 25, 17, 32, 1 }, + { 2040, 22, 50, 25, 17, 32, 1 }, + { 2030, 22, 50, 25, 17, 31, 1 }, + { 2020, 22, 50, 25, 17, 31, 1 }, + { 2010, 22, 50, 25, 17, 31, 1 }, + { 2000, 22, 50, 25, 17, 31, 1 }, + { 1990, 22, 50, 25, 17, 31, 1 }, + { 1980, 22, 50, 25, 16, 31, 1 }, + { 1970, 21, 50, 25, 16, 30, 1 }, + { 1960, 21, 50, 25, 16, 30, 1 }, + { 1950, 21, 50, 25, 16, 30, 1 }, + { 1940, 21, 50, 25, 16, 30, 1 }, + { 1930, 21, 50, 25, 16, 30, 1 }, + { 1920, 21, 50, 25, 16, 30, 1 }, + { 1910, 21, 50, 25, 16, 30, 1 }, + { 1900, 21, 50, 25, 16, 29, 1 }, + { 1890, 21, 50, 25, 16, 29, 1 }, + { 1880, 20, 50, 25, 16, 29, 1 }, + { 1870, 20, 50, 25, 16, 29, 1 }, + { 1860, 20, 50, 25, 15, 29, 1 }, + { 1850, 20, 50, 25, 15, 29, 1 }, + { 1840, 20, 50, 25, 15, 28, 1 }, + { 1830, 20, 50, 25, 15, 28, 1 }, + { 1820, 20, 50, 25, 15, 28, 1 }, + { 1810, 20, 50, 25, 15, 28, 1 }, + { 1800, 19, 50, 25, 15, 28, 1 }, + { 1790, 19, 50, 25, 15, 28, 1 }, + { 1780, 19, 50, 25, 15, 27, 1 }, + { 1770, 19, 50, 25, 15, 27, 1 }, + { 1760, 19, 50, 25, 15, 27, 1 }, + { 1750, 19, 50, 25, 14, 27, 1 }, + { 1740, 19, 50, 25, 14, 27, 1 }, + { 1730, 19, 50, 25, 14, 27, 1 }, + { 1720, 19, 50, 25, 14, 27, 1 }, + { 1710, 18, 50, 25, 14, 26, 1 }, + { 1700, 18, 50, 25, 14, 26, 1 }, + { 1690, 18, 50, 25, 14, 26, 1 }, + { 1680, 18, 50, 25, 14, 26, 1 }, + { 1670, 18, 50, 25, 14, 26, 1 }, + { 1660, 18, 50, 25, 14, 26, 1 }, + { 1650, 18, 50, 25, 14, 25, 1 }, + { 1640, 18, 50, 25, 14, 25, 1 }, + { 1630, 18, 50, 25, 13, 25, 1 }, + { 1620, 17, 50, 25, 13, 25, 1 }, + { 1610, 17, 50, 25, 13, 25, 1 }, + { 1600, 17, 50, 25, 13, 25, 1 }, + { 1590, 17, 50, 25, 13, 24, 1 }, + { 1580, 17, 50, 25, 13, 24, 1 }, + { 1570, 17, 50, 25, 13, 24, 1 }, + { 1560, 17, 50, 25, 13, 24, 1 }, + { 1550, 17, 50, 25, 13, 24, 1 }, + { 1540, 16, 50, 25, 13, 24, 1 }, + { 1530, 16, 50, 25, 13, 24, 1 }, + { 1520, 16, 50, 25, 13, 23, 1 }, + { 1510, 16, 50, 25, 12, 23, 1 }, + { 1500, 16, 50, 25, 12, 23, 1 }, + { 1490, 16, 50, 25, 12, 23, 1 }, + { 1480, 16, 50, 25, 12, 23, 1 }, + { 1470, 16, 50, 25, 12, 23, 1 }, + { 1460, 16, 50, 25, 12, 22, 1 }, + { 1450, 15, 50, 25, 12, 22, 1 }, + { 1440, 15, 50, 25, 12, 22, 1 }, + { 1430, 15, 50, 25, 12, 22, 1 }, + { 1420, 15, 50, 25, 12, 22, 1 }, + { 1410, 15, 50, 25, 12, 22, 1 }, + { 1400, 15, 50, 25, 11, 21, 1 }, + { 1390, 15, 50, 25, 11, 21, 1 }, + { 1380, 15, 50, 25, 11, 21, 1 }, + { 1370, 15, 50, 25, 11, 21, 1 }, + { 1360, 14, 50, 25, 11, 21, 1 }, + { 1350, 14, 50, 25, 11, 21, 1 }, + { 1340, 14, 50, 25, 11, 21, 1 }, + { 1330, 14, 50, 25, 11, 20, 1 }, + { 1320, 14, 50, 25, 11, 20, 1 }, + { 1310, 14, 50, 25, 11, 20, 1 }, + { 1300, 14, 50, 25, 11, 20, 1 }, + { 1290, 14, 50, 25, 11, 20, 1 }, + { 1280, 13, 50, 25, 10, 20, 1 }, + { 1270, 13, 50, 25, 10, 19, 1 }, + { 1260, 13, 50, 25, 10, 19, 1 }, + { 1250, 13, 50, 25, 10, 19, 1 }, + { 1240, 13, 50, 25, 10, 19, 1 }, + { 1230, 13, 50, 25, 10, 19, 1 }, + { 1220, 13, 50, 25, 10, 19, 1 }, + { 1210, 13, 50, 25, 10, 19, 1 }, + { 1200, 13, 50, 25, 10, 18, 1 }, + { 1190, 12, 50, 25, 10, 18, 1 }, + { 1180, 12, 50, 25, 10, 18, 1 }, + { 1170, 12, 50, 25, 10, 18, 1 }, + { 1160, 12, 50, 25, 9, 18, 1 }, + { 1150, 12, 50, 25, 9, 18, 1 }, + { 1140, 12, 50, 25, 9, 17, 1 }, + { 1130, 12, 50, 25, 9, 17, 1 }, + { 1120, 12, 50, 25, 9, 17, 1 }, + { 1110, 12, 50, 25, 9, 17, 1 }, + { 1100, 11, 50, 25, 9, 17, 1 }, + { 1090, 11, 50, 25, 9, 17, 1 }, + { 1080, 11, 50, 25, 9, 16, 1 }, + { 1070, 11, 50, 25, 9, 16, 1 }, + { 1060, 11, 50, 25, 9, 16, 1 }, + { 1050, 11, 50, 25, 8, 16, 1 }, + { 1040, 11, 50, 25, 8, 16, 1 }, + { 1030, 11, 50, 25, 8, 16, 1 }, + { 1020, 10, 50, 25, 8, 16, 1 }, + { 1010, 10, 50, 25, 8, 15, 1 }, + { 1000, 10, 50, 25, 8, 15, 1 }, + { 990, 10, 50, 25, 8, 15, 2 }, + { 980, 10, 50, 25, 8, 15, 2 }, + { 970, 10, 50, 25, 8, 15, 2 }, + { 960, 10, 50, 25, 8, 15, 2 }, + { 950, 10, 50, 25, 8, 14, 2 }, + { 940, 10, 50, 25, 8, 14, 2 }, + { 930, 9, 50, 25, 7, 14, 2 }, + { 920, 9, 50, 25, 7, 14, 2 }, + { 910, 9, 50, 25, 7, 14, 2 }, + { 900, 9, 50, 25, 7, 14, 2 }, + { 890, 9, 50, 25, 7, 13, 2 }, + { 880, 9, 50, 25, 7, 13, 2 }, + { 870, 9, 50, 25, 7, 13, 2 }, + { 860, 9, 50, 25, 7, 13, 2 }, + { 850, 9, 50, 25, 7, 13, 2 }, + { 840, 8, 50, 25, 7, 13, 2 }, + { 830, 8, 50, 25, 7, 13, 2 }, + { 820, 8, 50, 25, 7, 12, 2 }, + { 810, 8, 50, 25, 6, 12, 2 }, + { 800, 8, 50, 25, 6, 12, 2 }, + { 790, 8, 50, 25, 6, 12, 2 }, + { 780, 8, 50, 25, 6, 12, 2 }, + { 770, 8, 50, 25, 6, 12, 2 }, + { 760, 7, 50, 25, 6, 11, 2 }, + { 750, 7, 50, 25, 6, 11, 2 }, + { 740, 7, 50, 25, 6, 11, 2 }, + { 730, 7, 50, 25, 6, 11, 2 }, + { 720, 7, 50, 25, 6, 11, 2 }, + { 710, 7, 50, 25, 6, 11, 2 }, + { 700, 7, 50, 25, 5, 10, 2 }, + { 690, 7, 50, 25, 5, 10, 2 }, + { 680, 7, 50, 25, 5, 10, 2 }, + { 670, 6, 50, 25, 5, 10, 2 }, + { 660, 6, 50, 25, 5, 10, 2 }, + { 650, 6, 50, 25, 5, 10, 2 }, + { 640, 6, 50, 25, 5, 10, 2 }, + { 630, 6, 50, 25, 5, 9, 2 }, + { 620, 6, 50, 25, 5, 9, 2 }, + { 610, 6, 50, 25, 5, 9, 2 }, + { 600, 6, 50, 25, 5, 9, 2 }, + { 590, 6, 50, 25, 5, 9, 2 }, + { 580, 5, 50, 25, 4, 9, 2 }, + { 570, 5, 50, 25, 4, 8, 2 }, + { 560, 5, 50, 25, 4, 8, 2 }, + { 550, 5, 50, 25, 4, 8, 2 }, + { 540, 5, 50, 25, 4, 8, 2 }, + { 530, 5, 50, 25, 4, 8, 2 }, + { 520, 5, 50, 25, 4, 8, 2 }, + { 510, 5, 50, 25, 4, 8, 2 }, + { 500, 4, 50, 25, 4, 7, 2 }, + { 490, 18, 50, 25, 14, 6, 2 }, + { 480, 17, 50, 25, 14, 6, 2 }, + { 470, 17, 50, 25, 14, 6, 2 }, + { 460, 17, 50, 25, 13, 6, 2 }, + { 450, 16, 50, 25, 13, 6, 2 }, + { 440, 16, 50, 25, 13, 6, 2 }, + { 430, 15, 50, 25, 12, 6, 2 }, + { 420, 15, 50, 25, 12, 5, 2 }, + { 410, 15, 50, 25, 12, 5, 2 }, + { 400, 14, 50, 25, 11, 5, 2 }, + { 390, 14, 50, 25, 11, 5, 2 }, + { 380, 13, 50, 25, 11, 5, 2 }, + { 370, 13, 50, 25, 11, 5, 2 }, + { 360, 13, 50, 25, 10, 4, 2 }, + { 350, 12, 50, 25, 10, 4, 2 }, + { 340, 12, 50, 25, 10, 4, 2 }, + { 330, 11, 50, 25, 9, 4, 2 }, + { 320, 11, 50, 25, 9, 4, 2 }, + { 310, 11, 50, 25, 9, 4, 2 }, + { 300, 10, 50, 25, 8, 3, 2 }, + { 290, 10, 50, 25, 8, 3, 2 }, + { 280, 9, 50, 25, 8, 3, 2 }, + { 270, 9, 50, 25, 8, 3, 2 }, + { 260, 8, 50, 25, 7, 3, 2 }, + { 250, 8, 50, 25, 7, 3, 2 }, + { 240, 8, 50, 25, 7, 3, 2 }, + { 230, 7, 50, 25, 6, 2, 2 }, + { 220, 7, 50, 25, 6, 2, 2 }, + { 210, 6, 50, 25, 6, 2, 2 }, + { 200, 6, 50, 25, 5, 2, 2 }, + { 190, 6, 50, 25, 5, 2, 2 }, + { 180, 5, 50, 25, 5, 2, 2 }, + { 170, 5, 50, 25, 5, 1, 2 }, + { 160, 4, 50, 25, 4, 1, 2 }, + { 150, 4, 50, 25, 4, 1, 2 }, + { 140, 4, 50, 25, 4, 1, 2 }, + { 130, 3, 50, 25, 3, 1, 2 }, + { 120, 3, 50, 25, 3, 1, 2 }, + { 110, 2, 50, 25, 3, 1, 2 }, + { 100, 2, 50, 25, 2, 0, 2 }, + { 90, 2, 50, 25, 2, 0, 2 }, + { 80, 1, 50, 25, 2, 0, 2 }, +}; + +static inline void +phy_write(struct samsung_mipi_dcphy *samsung, u32 reg, u32 val) +{ + writel(val, samsung->base + reg); +} + +static inline u32 phy_read(struct samsung_mipi_dcphy *samsung, u32 reg) +{ + return readl(samsung->base + reg); +} + +static inline void phy_update_bits(struct samsung_mipi_dcphy *samsung, + u32 reg, u32 mask, u32 val) +{ + u32 orig, tmp; + + orig = phy_read(samsung, reg); + tmp = orig & ~mask; + tmp |= val & mask; + phy_write(samsung, reg, tmp); +} + +static inline void grf_write(struct samsung_mipi_dcphy *samsung, + u32 reg, u32 val) +{ + regmap_write(samsung->grf, reg, val); +} + +static const struct samsung_mipi_dphy_timing * +samsung_mipi_dphy_get_timing(struct samsung_mipi_dcphy *samsung) +{ + const struct samsung_mipi_dphy_timing *timings; + unsigned int num_timings; + unsigned int lane_mbps = samsung->pll.rate / USEC_PER_SEC; + unsigned int i; + + timings = samsung_mipi_dphy_timing_table; + num_timings = ARRAY_SIZE(samsung_mipi_dphy_timing_table); + + for (i = num_timings; i > 0; i--) + if (lane_mbps <= timings[i - 1].max_lane_mbps) + break; + + if (i == 0) + ++i; + + return &timings[i - 1]; +} + +static const struct samsung_mipi_cphy_timing * +samsung_mipi_cphy_get_timing(struct samsung_mipi_dcphy *samsung) +{ + const struct samsung_mipi_cphy_timing *timings; + unsigned int num_timings; + unsigned int lane_msps = div64_ul(samsung->pll.rate, USEC_PER_SEC); + unsigned int i; + + timings = samsung_mipi_cphy_timing_table; + num_timings = ARRAY_SIZE(samsung_mipi_cphy_timing_table); + + for (i = num_timings; i > 0; i--) + if (lane_msps <= timings[i - 1].max_lane_msps) + break; + + if (i == 0) + ++i; + + return &timings[i - 1]; +} + +static void samsung_mipi_dcphy_bias_block_enable(struct samsung_mipi_dcphy *samsung) +{ + phy_write(samsung, BIAS_CON0, 0x0010); + phy_write(samsung, BIAS_CON1, 0x0110); + phy_write(samsung, BIAS_CON2, 0x3223); + + if (samsung->c_option) + phy_update_bits(samsung, BIAS_CON4, I_MUX_SEL_MASK, I_MUX_SEL(2)); +} + +static void samsung_mipi_dcphy_bias_block_disable(struct samsung_mipi_dcphy *samsung) +{ +} + +static void samsung_mipi_dcphy_pll_configure(struct samsung_mipi_dcphy *samsung) +{ + phy_update_bits(samsung, PLL_CON0, S_MASK | P_MASK, + S(samsung->pll.scaler) | P(samsung->pll.prediv)); + + if (samsung->pll.dsm < 0) { + u16 dsm_tmp; + + /* Using opposite number subtraction to find complement */ + dsm_tmp = abs(samsung->pll.dsm); + dsm_tmp = dsm_tmp - 1; + dsm_tmp ^= 0xffff; + phy_write(samsung, PLL_CON1, dsm_tmp); + } else { + phy_write(samsung, PLL_CON1, samsung->pll.dsm); + } + + phy_update_bits(samsung, PLL_CON2, M_MASK, M(samsung->pll.fbdiv)); + + if (samsung->pll.ssc_en) { + phy_write(samsung, PLL_CON3, + MRR(samsung->pll.mrr) | MFR(samsung->pll.mfr)); + phy_update_bits(samsung, PLL_CON4, SSCG_EN, SSCG_EN); + } + + phy_write(samsung, PLL_CON5, RESET_N_SEL | PLL_ENABLE_SEL); + phy_write(samsung, PLL_CON7, PLL_LOCK_CNT(0xf000)); + phy_write(samsung, PLL_CON8, PLL_STB_CNT(0xf000)); +} + +static void +samsung_mipi_dphy_clk_lane_timing_init(struct samsung_mipi_dcphy *samsung) +{ + const struct samsung_mipi_dphy_timing *timing; + unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC); + u32 val = 0; + + timing = samsung_mipi_dphy_get_timing(samsung); + phy_write(samsung, DPHY_MC_GNR_CON0, 0xf000); + phy_write(samsung, DPHY_MC_ANA_CON0, 0x7133); + + if (lane_hs_rate >= 4500) + phy_write(samsung, DPHY_MC_ANA_CON1, 0x0001); + + /* + * Divide-by-2 Clock from Serial Clock. Use this when data rate is under + * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock + */ + if (lane_hs_rate < 1500) + val = HSTX_CLK_SEL; + + val |= T_LPX(timing->lpx); + /* T_LP_EXIT_SKEW/T_LP_ENTRY_SKEW unconfig */ + phy_write(samsung, DPHY_MC_TIME_CON0, val); + + val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare); + phy_write(samsung, DPHY_MC_TIME_CON1, val); + + val = T_HS_EXIT(timing->hs_exit) | T_CLK_TRAIL(timing->clk_trail_eot); + phy_write(samsung, DPHY_MC_TIME_CON2, val); + + val = T_CLK_POST(timing->clk_post); + phy_write(samsung, DPHY_MC_TIME_CON3, val); + + /* Escape Clock is 20.00MHz */ + phy_write(samsung, DPHY_MC_TIME_CON4, 0x1f4); + + /* + * skew calibration should be off, if the operation data rate is + * under 1.5Gbps or equal to 1.5Gbps. + */ + if (lane_hs_rate > 1500) + phy_write(samsung, DPHY_MC_DESKEW_CON0, 0x9cb1); +} + +static void +samsung_mipi_dphy_data_lane_timing_init(struct samsung_mipi_dcphy *samsung) +{ + const struct samsung_mipi_dphy_timing *timing; + unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC); + u32 val = 0; + + timing = samsung_mipi_dphy_get_timing(samsung); + + phy_write(samsung, COMBO_MD0_ANA_CON0, 0x7133); + phy_write(samsung, COMBO_MD1_ANA_CON0, 0x7133); + phy_write(samsung, COMBO_MD2_ANA_CON0, 0x7133); + phy_write(samsung, DPHY_MD3_ANA_CON0, 0x7133); + + if (lane_hs_rate >= 1500) { + phy_write(samsung, COMBO_MD0_ANA_CON1, 0x0001); + phy_write(samsung, COMBO_MD1_ANA_CON1, 0x0001); + phy_write(samsung, COMBO_MD2_ANA_CON1, 0x0001); + phy_write(samsung, DPHY_MD3_ANA_CON1, 0x0001); + } + + /* + * Divide-by-2 Clock from Serial Clock. Use this when data rate is under + * 1500Mbps, otherwise divide-by-16 Clock from Serial Clock + */ + if (lane_hs_rate < 1500) + val = HSTX_CLK_SEL; + + val |= T_LPX(timing->lpx); + /* T_LP_EXIT_SKEW/T_LP_ENTRY_SKEW unconfig */ + phy_write(samsung, COMBO_MD0_TIME_CON0, val); + phy_write(samsung, COMBO_MD1_TIME_CON0, val); + phy_write(samsung, COMBO_MD2_TIME_CON0, val); + phy_write(samsung, DPHY_MD3_TIME_CON0, val); + + val = T_HS_ZERO(timing->hs_zero) | T_HS_PREPARE(timing->hs_prepare); + phy_write(samsung, COMBO_MD0_TIME_CON1, val); + phy_write(samsung, COMBO_MD1_TIME_CON1, val); + phy_write(samsung, COMBO_MD2_TIME_CON1, val); + phy_write(samsung, DPHY_MD3_TIME_CON1, val); + + val = T_HS_EXIT(timing->hs_exit) | T_HS_TRAIL(timing->hs_trail_eot); + phy_write(samsung, COMBO_MD0_TIME_CON2, val); + phy_write(samsung, COMBO_MD1_TIME_CON2, val); + phy_write(samsung, COMBO_MD2_TIME_CON2, val); + phy_write(samsung, DPHY_MD3_TIME_CON2, val); + + /* TTA-GET/TTA-GO Timing Counter register use default value */ + val = T_TA_GET(0x3) | T_TA_GO(0x0); + phy_write(samsung, COMBO_MD0_TIME_CON3, val); + phy_write(samsung, COMBO_MD1_TIME_CON3, val); + phy_write(samsung, COMBO_MD2_TIME_CON3, val); + phy_write(samsung, DPHY_MD3_TIME_CON3, val); + + /* Escape Clock is 20.00MHz */ + phy_write(samsung, COMBO_MD0_TIME_CON4, 0x1f4); + phy_write(samsung, COMBO_MD1_TIME_CON4, 0x1f4); + phy_write(samsung, COMBO_MD2_TIME_CON4, 0x1f4); + phy_write(samsung, DPHY_MD3_TIME_CON4, 0x1f4); +} + +static void samsung_mipi_dcphy_pll_enable(struct samsung_mipi_dcphy *samsung) +{ + u32 sts; + int ret; + + phy_update_bits(samsung, PLL_CON0, PLL_EN, PLL_EN); + + ret = readl_poll_timeout(samsung->base + PLL_STAT0, + sts, (sts & PLL_LOCK), 20000); + if (ret < 0) + dev_err(samsung->dev, "DC-PHY pll is not locked\n"); +} + +static void samsung_mipi_dcphy_pll_disable(struct samsung_mipi_dcphy *samsung) +{ + phy_update_bits(samsung, PLL_CON0, PLL_EN, 0); +} + +static void samsung_mipi_dphy_lane_enable(struct samsung_mipi_dcphy *samsung) +{ + phy_write(samsung, DPHY_MC_GNR_CON1, T_PHY_READY(0x2000)); + phy_update_bits(samsung, DPHY_MC_GNR_CON0, PHY_ENABLE, PHY_ENABLE); + + switch (samsung->lanes) { + case 4: + phy_write(samsung, DPHY_MD3_GNR_CON1, T_PHY_READY(0x2000)); + phy_update_bits(samsung, DPHY_MD3_GNR_CON0, + PHY_ENABLE, PHY_ENABLE); + //fallthrough; + case 3: + phy_write(samsung, COMBO_MD2_GNR_CON1, T_PHY_READY(0x2000)); + phy_update_bits(samsung, COMBO_MD2_GNR_CON0, + PHY_ENABLE, PHY_ENABLE); + //fallthrough; + case 2: + phy_write(samsung, COMBO_MD1_GNR_CON1, T_PHY_READY(0x2000)); + phy_update_bits(samsung, COMBO_MD1_GNR_CON0, + PHY_ENABLE, PHY_ENABLE); + //fallthrough; + case 1: + default: + phy_write(samsung, COMBO_MD0_GNR_CON1, T_PHY_READY(0x2000)); + phy_update_bits(samsung, COMBO_MD0_GNR_CON0, + PHY_ENABLE, PHY_ENABLE); + break; + } +} + +static void samsung_mipi_cphy_timing_init(struct samsung_mipi_dcphy *samsung) +{ + const struct samsung_mipi_cphy_timing *timing; + unsigned int lane_hs_rate = div64_ul(samsung->pll.rate, USEC_PER_SEC); + u32 val = 0; + + timing = samsung_mipi_cphy_get_timing(samsung); + + /* + * Divide-by-2 Clock from Serial Clock. Use this when data rate is under + * 500Msps, otherwise divide-by-16 Clock from Serial Clock + */ + if (lane_hs_rate < 500) + val = HSTX_CLK_SEL; + + val |= T_LPX(timing->lpx); + /* T_LP_EXIT_SKEW/T_LP_ENTRY_SKEW unconfig */ + phy_write(samsung, COMBO_MD0_TIME_CON0, val); + phy_write(samsung, COMBO_MD1_TIME_CON0, val); + phy_write(samsung, COMBO_MD2_TIME_CON0, val); + + val = T_HS_ZERO(timing->prebegin_3) | T_HS_PREPARE(timing->prepare_3); + phy_write(samsung, COMBO_MD0_TIME_CON1, val); + phy_write(samsung, COMBO_MD1_TIME_CON1, val); + phy_write(samsung, COMBO_MD2_TIME_CON1, val); + + val = T_HS_EXIT(timing->hs_exit) | T_HS_TRAIL(timing->post_3); + phy_write(samsung, DPHY_MD3_TIME_CON2, val); + phy_write(samsung, COMBO_MD0_TIME_CON2, val); + phy_write(samsung, COMBO_MD1_TIME_CON2, val); + phy_write(samsung, COMBO_MD2_TIME_CON2, val); + + /* TTA-GET/TTA-GO Timing Counter register use default value */ + val = T_TA_GET(0x3) | T_TA_GO(0x0); + phy_write(samsung, COMBO_MD0_TIME_CON3, val); + phy_write(samsung, COMBO_MD1_TIME_CON3, val); + phy_write(samsung, COMBO_MD2_TIME_CON3, val); + + /* Escape Clock is 20.00MHz */ + phy_write(samsung, COMBO_MD0_TIME_CON4, 0x1f4); + phy_write(samsung, COMBO_MD1_TIME_CON4, 0x1f4); + phy_write(samsung, COMBO_MD2_TIME_CON4, 0x1f4); + + /* set T_ERR_SOT_SYNC default value */ +} + +static void samsung_mipi_cphy_lane_enable(struct samsung_mipi_dcphy *samsung) +{ + phy_write(samsung, COMBO_MD0_GNR_CON1, T_PHY_READY(0x2000)); + phy_write(samsung, COMBO_MD1_GNR_CON1, T_PHY_READY(0x2000)); + phy_write(samsung, COMBO_MD2_GNR_CON1, T_PHY_READY(0x2000)); + + phy_update_bits(samsung, COMBO_MD0_GNR_CON0, PHY_ENABLE, PHY_ENABLE); + phy_update_bits(samsung, COMBO_MD1_GNR_CON0, PHY_ENABLE, PHY_ENABLE); + phy_update_bits(samsung, COMBO_MD2_GNR_CON0, PHY_ENABLE, PHY_ENABLE); +} + +static void +samsung_mipi_dcphy_hs_vreg_amp_config(struct samsung_mipi_dcphy *samsung) +{ + phy_write(samsung, DPHY_MC_ANA_CON2, HS_VREG_AMP_ICON(2)); +} + +static void samsung_mipi_dphy_power_on(struct samsung_mipi_dcphy *samsung) +{ + reset_assert(&samsung->m_phy_rst); + + samsung_mipi_dcphy_bias_block_enable(samsung); + samsung_mipi_dcphy_pll_configure(samsung); + samsung_mipi_dphy_clk_lane_timing_init(samsung); + samsung_mipi_dphy_data_lane_timing_init(samsung); + samsung_mipi_dcphy_pll_enable(samsung); + samsung_mipi_dphy_lane_enable(samsung); + + reset_deassert(&samsung->m_phy_rst); + + /* The Tskewcal maximum is 100 usec at initial calibration. */ + udelay(100); +} + +static void samsung_mipi_cphy_power_on(struct samsung_mipi_dcphy *samsung) +{ + grf_write(samsung, MIPI_DCPHY_GRF_CON0, M_CPHY_MODE); + reset_assert(&samsung->m_phy_rst); + + samsung_mipi_dcphy_bias_block_enable(samsung); + samsung_mipi_dcphy_hs_vreg_amp_config(samsung); + samsung_mipi_dcphy_pll_configure(samsung); + samsung_mipi_cphy_timing_init(samsung); + samsung_mipi_dcphy_pll_enable(samsung); + samsung_mipi_cphy_lane_enable(samsung); + + reset_deassert(&samsung->m_phy_rst); +} + +static void samsung_mipi_dphy_lane_disable(struct samsung_mipi_dcphy *samsung) +{ + phy_update_bits(samsung, DPHY_MC_GNR_CON0, PHY_ENABLE, 0); + phy_update_bits(samsung, COMBO_MD0_GNR_CON0, PHY_ENABLE, 0); + phy_update_bits(samsung, COMBO_MD1_GNR_CON0, PHY_ENABLE, 0); + phy_update_bits(samsung, COMBO_MD2_GNR_CON0, PHY_ENABLE, 0); + phy_update_bits(samsung, DPHY_MD3_GNR_CON0, PHY_ENABLE, 0); +} + +static void samsung_mipi_cphy_lane_disable(struct samsung_mipi_dcphy *samsung) +{ + phy_update_bits(samsung, COMBO_MD0_GNR_CON0, PHY_ENABLE, 0); + phy_update_bits(samsung, COMBO_MD1_GNR_CON0, PHY_ENABLE, 0); + phy_update_bits(samsung, COMBO_MD2_GNR_CON0, PHY_ENABLE, 0); +} + +static int samsung_mipi_dcphy_power_on(struct rockchip_phy *phy) +{ + struct samsung_mipi_dcphy *samsung = SAMSUNG_MIPI_DCPHY_FROM_PHY(phy); + + if (samsung->mode == PHY_MODE_MIPI_DPHY) + samsung_mipi_dphy_power_on(samsung); + else + samsung_mipi_cphy_power_on(samsung); + + return 0; +} + +static int samsung_mipi_dcphy_power_off(struct rockchip_phy *phy) +{ + struct samsung_mipi_dcphy *samsung = SAMSUNG_MIPI_DCPHY_FROM_PHY(phy); + + if (samsung->mode == PHY_MODE_MIPI_DPHY) + samsung_mipi_dphy_lane_disable(samsung); + else + samsung_mipi_cphy_lane_disable(samsung); + + samsung_mipi_dcphy_pll_disable(samsung); + samsung_mipi_dcphy_bias_block_disable(samsung); + + return 0; +} + +static int +samsung_mipi_dcphy_pll_ssc_modulation_calc(struct samsung_mipi_dcphy *samsung, + u8 *mfr, u8 *mrr) +{ + unsigned long fin = 24000; + u16 prediv = samsung->pll.prediv; + u16 fbdiv = samsung->pll.fbdiv; + u16 min_mfr, max_mfr; + u16 _mfr, best_mfr = 0; + u16 mr, _mrr, best_mrr = 0; + + /* 20KHz ≤ MF ≤ 150KHz */ + max_mfr = DIV_ROUND_UP(fin, (20 * prediv) << 5); + min_mfr = div64_ul(fin, ((150 * prediv) << 5)); + /*0 ≤ mfr ≤ 255 */ + if (max_mfr > 256) + max_mfr = 256; + + for (_mfr = min_mfr; _mfr < max_mfr; _mfr++) { + /* 1 ≤ mrr ≤ 31 */ + for (_mrr = 1; _mrr < 32; _mrr++) { + mr = DIV_ROUND_UP(_mfr * _mrr * 100, fbdiv << 6); + /* 0 ≤ MR ≤ 5% */ + if (mr > 5) + continue; + + if (_mfr * _mrr < 513) { + best_mfr = _mfr; + best_mrr = _mrr; + break; + } + } + } + + if (best_mrr) { + *mfr = best_mfr & 0xff; + *mrr = best_mrr & 0x3f; + } else { + dev_err(samsung->dev, "failed to calc ssc parameter mfr and mrr\n"); + return -EINVAL; + } + + return 0; +} + +static unsigned long +samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung, + unsigned long prate, unsigned long rate, + u8 *prediv, u16 *fbdiv, int *dsm, u8 *scaler) +{ + u64 max_fout = samsung->c_option ? MAX_CPHY_BW : MAX_DPHY_BW; + u64 best_freq = 0; + u64 fin, fvco, fout; + u8 min_prediv, max_prediv; + u8 _prediv, best_prediv = 1; + u16 _fbdiv, best_fbdiv = 1; + u8 _scaler, best_scaler = 0; + long _dsm, best_dsm = 0; + u32 min_delta = 0xffffffff; + + /* + * The PLL output frequency can be calculated using a simple formula: + * Fvco = ((m+k/65536) x 2 x Fin) / p + * Fout = ((m+k/65536) x 2 x Fin) / (p x 2^s) + */ + fin = div64_ul(prate, MSEC_PER_SEC); + + while (!best_freq) { + fout = div64_ul(rate, MSEC_PER_SEC); + if (fout > max_fout) + fout = max_fout; + + /* 0 ≤ S[2:0] ≤ 6 */ + for (_scaler = 0; _scaler < 7; _scaler++) { + fvco = fout << _scaler; + + /* + * 2600MHz ≤ FVCO ≤ 6600MHz + */ + if (fvco < 2600 * MSEC_PER_SEC || fvco > 6600 * MSEC_PER_SEC) + continue; + + /* 6MHz ≤ Fref(Fin / p) ≤ 30MHz */ + min_prediv = DIV_ROUND_UP(fin, 30 * MSEC_PER_SEC); + max_prediv = DIV_ROUND_CLOSEST(fin, 6 * MSEC_PER_SEC); + + for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { + u64 delta, tmp; + + _fbdiv = DIV_ROUND_CLOSEST(fvco * _prediv, 2 * fin); + + /* 64 ≤ M[9:0] ≤ 1023 */ + if ((_fbdiv < 64) || (_fbdiv > 1023)) + continue; + + /* -32767 ≤ K[15:0] ≤ 32767 */ + _dsm = ((_prediv * fvco) - (2 * _fbdiv * fin)); + _dsm = DIV_ROUND_UP(_dsm << 15, fin); + if (abs(_dsm) > 32767) + continue; + + tmp = DIV_ROUND_CLOSEST((_fbdiv * fin * 2 * 1000), _prediv); + tmp += DIV_ROUND_CLOSEST((_dsm * fin * 1000), _prediv << 15); + + delta = abs(fvco * MSEC_PER_SEC - tmp); + if (delta < min_delta) { + best_prediv = _prediv; + best_fbdiv = _fbdiv; + best_dsm = _dsm; + best_scaler = _scaler; + min_delta = delta; + best_freq = DIV_ROUND_CLOSEST(tmp, 1000) * MSEC_PER_SEC; + } + } + } + + rate += 100 * MSEC_PER_SEC; + } + + *prediv = best_prediv; + *fbdiv = best_fbdiv; + *dsm = (int)best_dsm & 0xffff; + *scaler = best_scaler; + dev_info(samsung->dev, "p: %d, m: %d, dsm:%ld, scaler: %d\n", + best_prediv, best_fbdiv, best_dsm, best_scaler); + + return best_freq >> best_scaler; +} + +static unsigned long samsung_mipi_dcphy_set_pll(struct rockchip_phy *phy, + unsigned long rate) +{ + struct samsung_mipi_dcphy *samsung = SAMSUNG_MIPI_DCPHY_FROM_PHY(phy); + unsigned long fin = 24000000, fout; + u8 scaler = 0, mfr = 0, mrr = 0; + u16 fbdiv = 1; + u8 prediv = 1; + int dsm = 0; + int ret; + + samsung->c_option = (samsung->mode == PHY_MODE_MIPI_DPHY) ? false : true; + fout = samsung_mipi_dcphy_pll_round_rate(samsung, fin, rate, &prediv, + &fbdiv, &dsm, &scaler); + + dev_info(samsung->dev, "fin=%lu, req_rate=%lu\n", fin, rate); + dev_info(samsung->dev, "fout=%lu, prediv=%u, fbdiv=%u\n", fout, prediv, fbdiv); + + samsung->pll.prediv = prediv; + samsung->pll.fbdiv = fbdiv; + samsung->pll.dsm = dsm; + samsung->pll.scaler = scaler; + samsung->pll.rate = fout; + + /* + * All DPHY 2.0 compliant Transmitters shall support SSC operating above + * 2.5 Gbps + */ + if (fout > 2500000000LL) { + ret = samsung_mipi_dcphy_pll_ssc_modulation_calc(samsung, + &mfr, &mrr); + if (!ret) { + samsung->pll.ssc_en = true; + samsung->pll.mfr = mfr; + samsung->pll.mrr = mrr; + } + } + + return fout; +} + +static int samsung_mipi_dcphy_set_mode(struct rockchip_phy *phy, + enum phy_mode mode) +{ + struct samsung_mipi_dcphy *samsung = SAMSUNG_MIPI_DCPHY_FROM_PHY(phy); + + samsung->mode = mode; + + return 0; +} + +static const struct rockchip_phy_funcs samsung_mipi_dcphy_funcs = { + .power_on = samsung_mipi_dcphy_power_on, + .power_off = samsung_mipi_dcphy_power_off, + .set_pll = samsung_mipi_dcphy_set_pll, + .set_mode = samsung_mipi_dcphy_set_mode, +}; + +struct samsung_mipi_dcphy mMipiDcPhy[] = { + { + .Signature = SAMSUNG_MIPI_DCPHY_SIGNATURE, + .base = 0xfeda0000, + .grf = 0xfd5e8000, + .id = 0, + .lanes = 4, + .m_phy_rst = { 0x30A10, 3 }, /* mresetn_mipi_dcphy0 */ + .phy = { + .funcs = &samsung_mipi_dcphy_funcs + }, + }, + { + .Signature = SAMSUNG_MIPI_DCPHY_SIGNATURE, + .base = 0xfedb0000, + .grf = 0xfd5ec000, + .id = 1, + .lanes = 4, + .m_phy_rst = { 0x30A10, 5 }, /* mresetn_mipi_dcphy1 */ + .phy = { + .funcs = &samsung_mipi_dcphy_funcs + }, + }, +}; + +struct rockchip_phy *rockchip_phy_by_id(unsigned int id) +{ + for (int i = 0; i < ARRAY_SIZE(mMipiDcPhy); i++) { + if (id == mMipiDcPhy[i].id) { + return &mMipiDcPhy[i].phy; + } + } + return NULL; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/DebugDw8250SerialPortLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/DebugDw8250SerialPortLib.c new file mode 100644 index 0000000..f056332 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/DebugDw8250SerialPortLib.c @@ -0,0 +1,40 @@ +/** @file + UART Serial Port library functions + + Copyright (c) 2006 - 2009, Intel Corporation + Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. + Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ +**/ +#include +#include +#include +#include +#include + +#include "Dw8250SerialPortLib.h" + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfuly initialized, then return RETURN_SUCCESS. + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serail device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + // + // Assume already initialized. + // + return RETURN_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/DebugDw8250SerialPortLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/DebugDw8250SerialPortLib.inf new file mode 100644 index 0000000..a9dc5fe --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/DebugDw8250SerialPortLib.inf @@ -0,0 +1,35 @@ +#/** @file +# +# Copyright (c) 2011, ARM Ltd. All rights reserved.
    +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
    +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
    +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Dw8250SerialPortLib + FILE_GUID = e9b88aa0-16a5-447b-9c05-a77521db1a9e + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SerialPortLib + +[Sources.common] + DebugDw8250SerialPortLib.c + Dw8250SerialPortLibCommon.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseLib + IoLib + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gHisiTokenSpaceGuid.PcdSerialPortSendDelay diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c new file mode 100644 index 0000000..ad093b3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.c @@ -0,0 +1,50 @@ +/** @file + UART Serial Port library functions + + Copyright (c) 2006 - 2009, Intel Corporation + Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. + Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ +**/ +#include +#include +#include +#include +#include + +#include "Dw8250SerialPortLib.h" + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfuly initialized, then return RETURN_SUCCESS. + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serail device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINT32 ulUartClkFreq; + + MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8); + MmioWrite8 (UART_FCR_REG, UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR); + MmioWrite8 (UART_LCR_REG, UART_LCR_DLAB | UART_LCR_DLS8); + + ulUartClkFreq = PcdGet32(PcdUartClkInHz); + + MmioWrite8 (UART_DLL_REG, (ulUartClkFreq / (16 * (UINT32)BAUDRATE) ) & 0xff); + MmioWrite8 (UART_DLH_REG, ((ulUartClkFreq/ (16 * (UINT32)BAUDRATE) ) >> 8 ) & 0xff); + MmioWrite8 (UART_LCR_REG, UART_LCR_DLS8); + MmioWrite8 (UART_IEL_REG, 0x00); + + return RETURN_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h new file mode 100644 index 0000000..a1d3668 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.h @@ -0,0 +1,110 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015-2016, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ +**/ + +#ifndef __DW8250_SERIALPORTLIB_H__ +#define __DW8250_SERIALPORTLIB_H__ + + +#define SERIAL_0_BASE_ADR (PcdGet64(PcdSerialRegisterBase)) + + +#define UART_SEND_DELAY (PcdGet32(PcdSerialPortSendDelay)) +#define BAUDRATE (PcdGet64(PcdUartDefaultBaudRate)) + + +#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_THR) +#define UART_RBR_REG (SERIAL_0_BASE_ADR + UART_RBR) +#define UART_DLL_REG (SERIAL_0_BASE_ADR + UART_DLL) +#define UART_DLH_REG (SERIAL_0_BASE_ADR + UART_DLH) +#define UART_IEL_REG (SERIAL_0_BASE_ADR + UART_IEL) +#define UART_IIR_REG (SERIAL_0_BASE_ADR + UART_IIR) +#define UART_FCR_REG (SERIAL_0_BASE_ADR + UART_FCR) +#define UART_LCR_REG (SERIAL_0_BASE_ADR + UART_LCR) +#define UART_LSR_REG (SERIAL_0_BASE_ADR + UART_LSR) +#define UART_USR_REG (SERIAL_0_BASE_ADR + UART_USR) + + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_DLL 0x00 +#define UART_DLH 0x04 +#define UART_IEL 0x04 +#define UART_IIR 0x08 +#define UART_FCR 0x08 +#define UART_LCR 0x0C +#define UART_MCR 0x10 +#define UART_LSR 0x14 +#define UART_USR 0x7C + +/* register definitions */ + +#define UART_FCR_EN 0x01 +#define UART_FCR_RXCLR 0x02 +#define UART_FCR_TXCLR 0x04 +#define UART_FCR_CLEARFIFO 0x00 +#define UART_FCR_RXL1 0x00 +#define UART_FCR_RXL4 0x40 +#define UART_FCR_RXL8 0x80 +#define UART_FCR_RXL14 0xc0 +#define UART_FCR_TXL0 0x00 +#define UART_FCR_TXL4 0x20 +#define UART_FCR_TXL8 0x30 +#define UART_FCR_TXL14 0x10 + +/*LCR Name: Line Control Register fields*/ +#define UART_LCR_DLAB 0x80 +#define UART_LCR_EPS 0x10 +#define UART_LCR_PEN 0x08 +#define UART_LCR_STOP 0x04 +#define UART_LCR_DLS8 0x03 +#define UART_LCR_DLS7 0x02 +#define UART_LCR_DLS6 0x01 +#define UART_LCR_DLS5 0x00 + + +#define UART_DLH_AND_DLL_WIDTH 0xFF + + +#define UART_IER_PTIME 0x80 +#define UART_IER_ELSI 0x04 +#define UART_IER_ETBEI 0x02 +#define UART_IER_ERBFI 0x01 + + +#define UART_IIR_FIFOSE 0xC0 + + +#define UART_IIR_InterruptID 0x01 +#define UART_IIR_INTIDTE 0x02 +#define UART_IIR_INTIDRA 0x04 +#define UART_IIR_INTIDRLS 0x06 +#define UART_IIR_INTMASK 0x0f +#define UART_IIR_RDA 0x04 +#define UART_IIR_TE 0x02 + +#define UART_LSR_TEMT 0x40 +#define UART_LSR_THRE 0x20 +#define UART_LSR_BI 0x10 +#define UART_LSR_FE 0x08 +#define UART_LSR_PE 0x04 +#define UART_LSR_R 0x02 +#define UART_LSR_DR 0x01 + + +#define UART_USR_BUSY 0x01 + +#define FIFO_MAXSIZE 32 + +extern UINT8 SerialPortReadChar(VOID); +extern VOID SerialPortWriteChar(UINT8 scShowChar); + +#endif + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf new file mode 100644 index 0000000..752f468 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf @@ -0,0 +1,37 @@ +#/** @file +# +# Copyright (c) 2011, ARM Ltd. All rights reserved.
    +# Copyright (c) 2015-2016, Hisilicon Limited. All rights reserved.
    +# Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
    +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Dw8250SerialPortLib + FILE_GUID = e7016ad2-40dd-406f-81ef-535da603c8e1 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SerialPortLib + +[Sources.common] + Dw8250SerialPortLib.c + Dw8250SerialPortLibCommon.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[LibraryClasses] + BaseLib + IoLib + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gHisiTokenSpaceGuid.PcdSerialPortSendDelay + gHisiTokenSpaceGuid.PcdUartClkInHz diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLibCommon.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLibCommon.c new file mode 100644 index 0000000..a65497b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLibCommon.c @@ -0,0 +1,260 @@ +/** @file + UART Serial Port library functions + + Copyright (c) 2006 - 2009, Intel Corporation + Copyright (c) 2015 - 2016, Hisilicon Limited. All rights reserved. + Copyright (c) 2015 - 2016, Linaro Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent + + Based on the files under ArmPlatformPkg/Library/PL011SerialPortLib/ +**/ +#include +#include +#include +#include +#include + +#include "Dw8250SerialPortLib.h" + +/** + Write data from buffer to serial device. + + Writes NumberOfBytes data bytes from Buffer to the serial device. + The number of bytes actually written to the serial device is returned. + If the return value is less than NumberOfBytes, then the write operation failed. + + If Buffer is NULL, then ASSERT(). + + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to be written. + @param NumberOfBytes Number of bytes to written to the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes written to the serial device. + If this value is less than NumberOfBytes, then the read operation failed. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINTN Result; + + if (NULL == Buffer) { + return 0; + } + + Result = NumberOfBytes; + + while (NumberOfBytes--) { + + SerialPortWriteChar(*Buffer); + Buffer++; + } + + return Result; +} + + +/** + Reads data from a serial device into a buffer. + + @param Buffer Pointer to the data buffer to store the data read from the serial device. + @param NumberOfBytes Number of bytes to read from the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes read from the serial device. + If this value is less than NumberOfBytes, then the read operation failed. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINTN Result; + + if (NULL == Buffer) { + return 0; + } + + Result = 0; + + while (NumberOfBytes--) { + // + // Wait for the serail port to be ready. + // + *Buffer=SerialPortReadChar(); + Buffer++ ; + Result++; + } + + return Result; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls aserial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is returned. + If there is no data waiting to be read from the serial device, then FALSE is returned. + + @retval TRUE Data is waiting to be read from the serial device. + @retval FALSE There is no data waiting to be read from the serial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + + return (BOOLEAN) ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR); + +} + + +VOID SerialPortWriteChar(UINT8 scShowChar) +{ + UINT32 ulLoop = 0; + + while(ulLoop < (UINT32)UART_SEND_DELAY) + { + + if ((MmioRead8 (UART_USR_REG) & 0x02) == 0x02) + { + break; + } + + ulLoop++; + } + MmioWrite8 (UART_THR_REG, (UINT8)scShowChar); + + ulLoop = 0; + while(ulLoop < (UINT32)UART_SEND_DELAY) + { + if ((MmioRead8 (UART_USR_REG) & 0x04) == 0x04) + { + break; + } + ulLoop++; + } + + return; +} + + +UINT8 SerialPortReadChar(VOID) +{ + UINT8 recvchar = 0; + + while(1) + { + if ((MmioRead8 (UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR) + { + break; + } + } + + recvchar = MmioRead8 (UART_RBR_REG); + + return recvchar; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0 will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive side of the + serial interface. A ReceiveFifoDepth value of 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character in microseconds. + This timeout applies to both the transmit and receive side of the + interface. A Timeout value of 0 will use the device's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial device. A Parity value of + DefaultParity will use the device's default parity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial device. A DataBits + vaule of 0 will use the device's default data bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial device. A StopBits + value of DefaultStopBits will use the device's default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the serial device. + @retval RETURN_UNSUPPORTED The serial device does not support this operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an unsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return RETURN_UNSUPPORTED; +} + +/** + Set the serial device control bits. + + @param Control Control bits which are to be set on the serial device. + + @retval EFI_SUCCESS The new control bits were set on the serial device. + @retval EFI_UNSUPPORTED The serial device does not support this operation. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Get the serial device control bits. + + @param Control Control signals read from the serial device. + + @retval EFI_SUCCESS The control bits were read from the serial device. + @retval EFI_DEVICE_ERROR The serial device is not functioning correctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + + if (SerialPortPoll ()) { + // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY + *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } else { + *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY; + } + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DwcSdhciPlatformLibNull/DwcSdhciPlatformLibNull.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DwcSdhciPlatformLibNull/DwcSdhciPlatformLibNull.c new file mode 100644 index 0000000..4f947c4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DwcSdhciPlatformLibNull/DwcSdhciPlatformLibNull.c @@ -0,0 +1,30 @@ +/** @file + * + * DwcSdhciDxe platform helper library. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include + +EFI_STATUS +EFIAPI +DwcSdhciSetClockRate ( + IN UINTN Frequency + ) +{ + return EFI_UNSUPPORTED; +} + +VOID +EFIAPI +DwcSdhciSetIoMux ( + VOID + ) +{ + return; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DwcSdhciPlatformLibNull/DwcSdhciPlatformLibNull.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DwcSdhciPlatformLibNull/DwcSdhciPlatformLibNull.inf new file mode 100644 index 0000000..1e13c87 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/DwcSdhciPlatformLibNull/DwcSdhciPlatformLibNull.inf @@ -0,0 +1,24 @@ +#/** @file +# +# DwcSdhciDxe platform helper library. +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = DwcSdhciPlatformLibNull + FILE_GUID = 98fc1cd7-aeca-4b8d-894f-5d2f9899a47d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = DwcSdhciPlatformLib + +[Sources] + DwcSdhciPlatformLibNull.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/FspiLib/FspiLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/FspiLib/FspiLib.c new file mode 100644 index 0000000..b502b06 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/FspiLib/FspiLib.c @@ -0,0 +1,497 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + */ + +#include "Soc.h" +#include +#include +#include +#include +#include +#include + +#define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0) +/********************* Private MACRO Definition ******************************/ +// #define FSPI_DEBUG +#ifdef FSPI_DEBUG +#define FSPI_DBG(...) +#else +#define FSPI_DBG(...) +#endif + +/* FSPI_CTRL */ +#define FSPI_CTRL_SHIFTPHASE_NEGEDGE 1 + +/* FSPI_RCVR */ +#define FSPI_RCVR_RCVR_RESET (1 << FSPI_RCVR_RCVR_SHIFT) /* Recover The FSPI State Machine */ + +/* FSPI_ISR */ +#define FSPI_ISR_DMAS_ACTIVE (1 << FSPI_ISR_DMAS_SHIFT) /* DMA Finish Interrupt Active */ +#define FSPI_ISR_NSPIS_ACTIVE (1 << FSPI_ISR_NSPIS_SHIFT) /* SPI Error Interrupt Active */ +#define FSPI_ISR_AHBS_ACTIVE (1 << FSPI_ISR_AHBS_SHIFT) /* AHB Error Interrupt Active */ +#define FSPI_ISR_TRANSS_ACTIVE (1 << FSPI_ISR_TRANSS_SHIFT) /* Transfer finish Interrupt Active */ +#define FSPI_ISR_TXES_ACTIVE (1 << FSPI_ISR_TXES_SHIFT) /* Transmit FIFO Empty Interrupt Active */ +#define FSPI_ISR_TXOS_ACTIVE (1 << FSPI_ISR_TXOS_SHIFT) /* Transmit FIFO Overflow Interrupt Active */ +#define FSPI_ISR_RXUS_ACTIVE (1 << FSPI_ISR_RXUS_SHIFT) /* Receive FIFO Underflow Interrupt Active */ +#define FSPI_ISR_RXFS_ACTIVE (1 << FSPI_ISR_RXFS_SHIFT) /* Receive FIFO Full Interrupt Active */ + +/* FSPI_FSR */ +#define FSPI_FSR_RXFS_EMPTY (1 << FSPI_FSR_RXFS_SHIFT) /* Receive FIFO Full */ +#define FSPI_FSR_RXES_EMPTY (1 << FSPI_FSR_RXES_SHIFT) /* Receive FIFO Empty */ +#define FSPI_FSR_TXFS_FULL (1 << FSPI_FSR_TXFS_SHIFT) /* Transmit FIFO Full */ +#define FSPI_FSR_TXES_EMPTY (1 << FSPI_FSR_TXES_SHIFT) /* Transmit FIFO Empty */ + +/* FSPI_SR */ +#define FSPI_SR_SR_BUSY (1 << FSPI_SR_SR_SHIFT) /* When busy, do not set the control register. */ + +/* FSPI_DMATR */ +#define FSPI_DMATR_DMATR_START (1 << FSPI_DMATR_DMATR_SHIFT) /* Write 1 to start the dma transfer. */ + +/* FSPI_RISR */ +#define FSPI_RISR_TRANSS_ACTIVE (1 << FSPI_RISR_TRANSS_SHIFT) + +/* FSPI attributes */ +#define FSPI_VER_VER_1 1 +#define FSPI_VER_VER_3 3 +#define FSPI_VER_VER_5 5 + +#define FSPI_NOR_FLASH_PAGE_SIZE 0x100 + +#define FSPI_MAX_IOSIZE_VER3 (1024U * 8) +#define FSPI_MAX_IOSIZE_VER4 (0xFFFFFFFFU) + +/********************* Private Structure Definition **************************/ + +typedef union { + UINT32 d32; + struct { + unsigned txempty : 1; /* tx fifo empty */ + unsigned txfull : 1; /* tx fifo full */ + unsigned rxempty : 1; /* rx fifo empty */ + unsigned rxfull : 1; /* tx fifo empty interrupt mask */ + unsigned reserved7_4 : 4; + unsigned txlevel : 5; /* tx fifo: 0: full; 1: left 1 entry; ... */ + unsigned reserved15_13 : 3; + unsigned rxlevel : 5; /* rx fifo: 0: full; 1: left 1 entry; ... */ + unsigned reserved31_21 : 11; + } b; +} FSPIFSR_DATA; + +/** FSPI_XMMC bit union */ +typedef union { + UINT32 d32; + struct { + unsigned reserverd1 : 5; + unsigned devHwEn : 1; /* device Hwrite Enable */ + unsigned prefetch : 1; /* prefetch enable */ + unsigned uincrPrefetchEn : 1; /* undefine INCR Burst Prefetch Enable */ + unsigned uincrLen : 4; /* undefine INCR length */ + unsigned devWrapEn : 1; /* device Wrap Enable */ + unsigned devIncrEn : 1; /* device INCR2/4/8/16 Enable */ + unsigned devUdfincrEn : 1; /* device Undefine INCR Enable */ + unsigned reserved2 : 17; + } b; +} FSPIXMMCCTRL_DATA; +/********************* Private Variable Definition ***************************/ + +/********************* Private Function Definition ***************************/ +static void FSPI_Reset(struct HAL_FSPI_HOST *host) +{ + INT32 timeout = 10000; + + host->instance->RCVR = FSPI_RCVR_RCVR_RESET; + while ((host->instance->RCVR == FSPI_RCVR_RCVR_RESET) && (timeout > 0)) { + HAL_CPUDelayUs(1); + timeout--; + } + host->instance->ICLR = 0xFFFFFFFF; +} + +static void FSPI_ContModeInit(struct HAL_FSPI_HOST *host) +{ + /* Setup when FSPI->AX = 0xa5, Cancel when FSPI->AX = 0x0 */ + WRITE_REG(host->instance->EXT_AX, 0xa5 << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT | + 0x5a << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT); + /* Skip Continuous mode in default */ + switch (host->cs) { + case 0: + WRITE_REG(host->instance->AX0, 0 << FSPI_AX0_AX_SHIFT); + break; + case 1: + WRITE_REG(host->instance->AX1, 0 << FSPI_AX1_AX_SHIFT); + break; + default: + break; + } +} + +static void FSPI_ContModeDeInit(struct HAL_FSPI_HOST *host) +{ + /* FSPI avoid setup pattern match with FSPI->AX */ + WRITE_REG(host->instance->EXT_AX, 0x77 << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT | + 0x88 << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT); +} + +/** + * @brief Configuration register with flash operation protocol. + * @param host: FSPI host. + * @param op: flash operation protocol. + * @return RETURN_STATUS. + * @attention Set host->cs to select chip. + */ +RETURN_STATUS HAL_FSPI_XferStart(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op) +{ + struct FSPI_REG *pReg = host->instance; + FSPICMD_DATA FSPICmd; + FSPICTRL_DATA FSPICtrl; + + FSPICmd.d32 = 0; + FSPICtrl.d32 = 0; + + /* set CMD */ + FSPICmd.b.cmd = op->cmd.opcode; + if (op->cmd.buswidth == 4) { + FSPICtrl.b.cmdlines = FSPI_LINES_X4; + FSPICtrl.b.datalines = FSPI_LINES_X4; /* cmdlines work with datalines */ + } + + /* set ADDR */ + if (op->addr.nbytes) { + if (op->addr.nbytes == 4) { + FSPICmd.b.addrbits = FSPI_ADDR_32BITS; + } else if (op->addr.nbytes == 3) { + FSPICmd.b.addrbits = FSPI_ADDR_24BITS; + } else { + FSPICmd.b.addrbits = FSPI_ADDR_XBITS; + pReg->ABIT0 = op->addr.nbytes * 8 - 1; + } + + FSPICtrl.b.addrlines = op->addr.buswidth == 4 ? FSPI_LINES_X4 : FSPI_LINES_X1; + } + + /* set DUMMY*/ + if (op->dummy.nbytes) { + switch (op->dummy.buswidth) { + case 4: + FSPICmd.b.dummybits = op->dummy.nbytes * 2; + break; + case 2: + FSPICmd.b.dummybits = op->dummy.nbytes * 4; + break; + default: + FSPICmd.b.dummybits = op->dummy.nbytes * 8; + break; + } + } + + /* set DATA */ + WRITE_REG(pReg->LEN_EXT, op->data.nbytes); + if (op->data.nbytes) { + if (op->data.dir == HAL_SPI_MEM_DATA_OUT) { + FSPICmd.b.rw = FSPI_WRITE; + } + if (op->data.buswidth == 4) { + FSPICtrl.b.datalines = FSPI_LINES_X4; + } else if (op->data.buswidth == 2) { + FSPICtrl.b.datalines = FSPI_LINES_X2; + } else { + FSPICtrl.b.datalines = FSPI_LINES_X1; + } + } + + /* spitial setting */ + FSPICtrl.b.sps = host->mode & HAL_SPI_CPHA; + FSPICmd.b.cs = host->cs; + if (op->data.nbytes == 0 && op->addr.nbytes) { + FSPICmd.b.rw = FSPI_WRITE; + } + + if (!(pReg->FSR & FSPI_FSR_TXES_EMPTY) || !(pReg->FSR & FSPI_FSR_RXES_EMPTY) || (pReg->SR & FSPI_SR_SR_BUSY)) { + FSPI_Reset(host); + } + + // FSPI_DBG("%s 1 %x %x %x\n", __func__, op->addr.nbytes, op->dummy.nbytes, op->data.nbytes); + // FSPI_DBG("%s 2 %lx %lx %lx %x\n", __func__, FSPICtrl.d32, FSPICmd.d32, op->addr.val, host->cs); + + /* config FSPI */ + switch (host->cs) { + case 0: + pReg->CTRL0 = FSPICtrl.d32; + break; + case 1: + pReg->CTRL1 = FSPICtrl.d32; + break; + default: + break; + } + pReg->CMD = FSPICmd.d32; + if (op->addr.nbytes) { + pReg->ADDR = op->addr.val; + } + + return RETURN_SUCCESS; +} + +/** + * @brief IO transfer. + * @param host: FSPI host. + * @param len: data n bytes. + * @param data: transfer buffer. + * @param dir: transfer direction. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_FSPI_XferData(struct HAL_FSPI_HOST *host, UINT32 len, void *data, UINT32 dir) +{ + RETURN_STATUS ret = RETURN_SUCCESS; + __IO FSPIFSR_DATA fifostat; + INT32 timeout = 0; + UINT32 i, words; + UINT32 *pData = (UINT32 *)data; + struct FSPI_REG *pReg = host->instance; + UINT32 temp = 0; + + HAL_ASSERT(data && len); + + if (len && len < 4 && dir == FSPI_WRITE) { + if (len == 1) { + temp = *((uint8_t *)data); + } else if (len == 2) { + temp = *((uint16_t *)data); + } else { + temp = ((uint8_t *)data)[0] | ((uint8_t *)data)[1] << 8 | ((uint8_t *)data)[2] << 16; + } + pData = &temp; + } else if (len >= 4 && !HAL_IS_ALIGNED((long)data, 4)) { + FSPI_DBG("%s data unaligned access\n", __func__); + } + + /* FSPI_DBG("%s %p len %lx word0 %lx dir %lx\n", __func__, pData, len, pData[0], dir); */ + if (dir == FSPI_WRITE) { + words = (len + 3) >> 2; + while (words) { + fifostat.d32 = pReg->FSR; + if (fifostat.b.txlevel > 0) { + UINT32 count = MIN(words, fifostat.b.txlevel); + + for (i = 0; i < count; i++) { + pReg->DATA = *pData++; + words--; + } + if (words == 0) { + break; + } + timeout = 0; + } else { + HAL_CPUDelayUs(1); + if (timeout++ > 10000) { + ret = RETURN_TIMEOUT; + break; + } + } + } + } else { + UINT32 bytes = len & 0x3; + + words = len >> 2; + while (words) { + fifostat.d32 = pReg->FSR; + if (fifostat.b.rxlevel > 0) { + UINT32 count = MIN(words, fifostat.b.rxlevel); + if (count == 15) { /* Reduce CPU cost */ + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + *pData++ = pReg->DATA; + words -= 15; + } else { + for (i = 0; i < count; i++) { + *pData++ = pReg->DATA; + } + words -= count; + } + + if (0 == words) { + break; + } + timeout = 0; + } else { + HAL_CPUDelayUs(1); + if (timeout++ > 10000) { + ret = RETURN_TIMEOUT; + break; + } + } + } + + timeout = 0; + while (bytes) { + fifostat.d32 = pReg->FSR; + if (fifostat.b.rxlevel > 0) { + uint8_t *pData1 = (uint8_t *)pData; + words = pReg->DATA; + for (i = 0; i < bytes; i++) { + pData1[i] = (uint8_t)((words >> (i * 8)) & 0xFF); + } + break; + } else { + HAL_CPUDelayUs(1); + if (timeout++ > 10000) { + ret = RETURN_TIMEOUT; + break; + } + } + } + } + + return ret; +} + +/** + * @brief Wait for FSPI host transfer finished. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_FSPI_XferDone(struct HAL_FSPI_HOST *host) +{ + RETURN_STATUS ret = RETURN_SUCCESS; + INT32 timeout = 0; + struct FSPI_REG *pReg = host->instance; + + while (pReg->SR & FSPI_SR_SR_BUSY) { + HAL_CPUDelayUs(1); + if (timeout++ > 100000) { /*wait 100ms*/ + ret = RETURN_TIMEOUT; + break; + } + } + HAL_CPUDelayUs(1); //CS# High Time (read/write) >100ns + + return ret; +} + +/** + * @brief SPI Nor flash data transmission interface to support open source specifications SNOR. + * @param host: FSPI host. + * @param op: flash operation protocol. + * @return RETURN_STATUS. + * @attention Set host->cs to select chip. + */ +RETURN_STATUS HAL_FSPI_SpiXfer(struct HAL_FSPI_HOST *host, struct HAL_SPI_MEM_OP *op) +{ + RETURN_STATUS ret = RETURN_SUCCESS; + UINT32 dir = op->data.dir; + void *pData = NULL; + + HAL_ASSERT(IS_FSPI_INSTANCE(host->instance)); + + if (op->data.buf.in) { + pData = (void *)op->data.buf.in; + } else if (op->data.buf.out) { + pData = (void *)op->data.buf.out; + } + + HAL_FSPI_XferStart(host, op); + if (pData) { + ret = HAL_FSPI_XferData(host, op->data.nbytes, pData, dir); + if (ret) { + FSPI_DBG("%s xfer data failed ret %d\n", __func__, ret); + + return ret; + } + } + + return HAL_FSPI_XferDone(host); +} + +/** @} */ + +/** @defgroup FSPI_Exported_Functions_Group4 Init and DeInit Functions + + This section provides functions allowing to init and deinit the module: + + * @{ + */ + +/** + * @brief Init FSPI. + * @param host: FSPI host. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_FSPI_Init(struct HAL_FSPI_HOST *host) +{ + INT32 timeout = 0; + struct FSPI_REG *pReg; + RETURN_STATUS ret = RETURN_SUCCESS; + + HAL_ASSERT(IS_FSPI_INSTANCE(host->instance)); + + pReg = host->instance; + pReg->MODE = 0; + while (pReg->SR & FSPI_SR_SR_BUSY) { + HAL_CPUDelayUs(1); + if (timeout++ > 1000) { + return RETURN_TIMEOUT; + } + } + FSPI_ContModeInit(host); + pReg->CTRL0 = 0; + +#if (FSPI_VER > FSPI_VER_VER_3) + WRITE_REG(pReg->LEN_CTRL, FSPI_LEN_CTRL_TRB_SEL_MASK); +#endif + + return ret; +} + +/** + * @brief DeInit FSPI. + * @param host: FSPI host. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_FSPI_DeInit(struct HAL_FSPI_HOST *host) +{ + HAL_ASSERT(IS_FSPI_INSTANCE(host->instance)); + + host->instance->MODE = 0; + FSPI_ContModeDeInit(host); + FSPI_Reset(host); + + return RETURN_SUCCESS; +} + +/** + * @brief Set FSPI delay line. + * @param host: FSPI host. + * @param cells: delay line cells. + * @return RETURN_STATUS. + */ +RETURN_STATUS HAL_FSPI_SetDelayLines(struct HAL_FSPI_HOST *host, uint8_t cells) +{ + HAL_ASSERT(IS_FSPI_INSTANCE(host->instance)); + if (host->cs == 0) { + WRITE_REG(host->instance->DLL_CTRL0, 1 << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT | cells); + } else { + WRITE_REG(host->instance->DLL_CTRL1, 1 << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT | cells); + } + + return RETURN_SUCCESS; +} + +UINT32 HAL_FSPI_GetMaxIoSize(struct HAL_FSPI_HOST *host) +{ + HAL_ASSERT(IS_FSPI_INSTANCE(host->instance)); + + return FSPI_MAX_IOSIZE_VER4; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/FspiLib/FspiLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/FspiLib/FspiLib.inf new file mode 100644 index 0000000..9eaa4a4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/FspiLib/FspiLib.inf @@ -0,0 +1,39 @@ +#/** @file +# +# Component description file for Uart module +# +# Copyright (c) 2022, Rockchip Inc. All rights reserved.
    +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = FspiLib + FILE_GUID = b1bbeb92-9df6-11ec-9573-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = FspiLib + +[Sources.common] + FspiLib.c + +[LibraryClasses] + DebugLib + IoLib + TimerLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[Pcd] + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PWMLib/PWMLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PWMLib/PWMLib.c new file mode 100644 index 0000000..e2b5a79 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PWMLib/PWMLib.c @@ -0,0 +1,139 @@ +/** @file + Rockchip PWM Driver. + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#define PWM_INT_EN(ch) (1 << (ch)) +#define PWM_PWR_INT_EN(ch) (1 << ((ch) + 4 )) + +#define PWM_DISABLE (0 << PWM_PWM0_CTRL_PWM_EN_SHIFT) +#define PWM_ENABLE (1 << PWM_PWM0_CTRL_PWM_EN_SHIFT) + +#define PWM_MODE_SHIFT (1) +#define PWM_MODE_MASK (0x3U << PWM_MODE_SHIFT) + +#define PWM_DUTY_POSTIVE (1 << PWM_PWM0_CTRL_DUTY_POL_SHIFT) +#define PWM_DUTY_NEGATIVE (0 << PWM_PWM0_CTRL_DUTY_POL_SHIFT) +#define PWM_DUTY_MASK (1 << 3) + +#define PWM_INACTIVE_POSTIVE (1 << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) +#define PWM_INACTIVE_NEGATIVE (0 << PWM_PWM0_CTRL_INACTIVE_POL_SHIFT) +#define PWM_INACTIVE_MASK (1 << 4) + +#define PWM_OUTPUT_LEFT (0 << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) +#define PWM_OUTPUT_CENTER (1 << PWM_PWM0_CTRL_OUTPUT_MODE_SHIFT) + +#define PWM_UNLOCK (0 << PWM_PWM0_CTRL_CONLOCK_SHIFT) +#define PWM_LOCK (1 << PWM_PWM0_CTRL_CONLOCK_SHIFT) + +#define PWM_LP_DISABLE (0 << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) +#define PWM_LP_ENABLE (1 << PWM_PWM0_CTRL_FORCE_CLK_EN_SHIFT) + +#define PWM_SEL_SRC_CLK (0 << PWM_PWM0_CTRL_CLK_SEL_SHIFT) +#define PWM_SEL_SCALE_CLK (1 << PWM_PWM0_CTRL_CLK_SEL_SHIFT) + +#define PWM_CTRL_SCALE_SHIFT (PWM_PWM0_CTRL_SCALE_SHIFT) +#define PWM_CTRL_SCALE_MASK (PWM_PWM0_CTRL_SCALE_MASK) + +#define PWM_PWRMATCH_MAX_SHIFT (PWM_PWRMATCH_LPRE_CNT_MIN_SHIFT) + +#define PWM_CTRL_OFFSET (PWM_PWM0_CTRL_OFFSET) +#define PWM_PERIOD_HPR_OFFSET (PWM_PWM0_PERIOD_HPR_OFFSET) +#define PWM_DUTY_LPR_OFFSET (PWM_PWM0_DUTY_LPR_OFFSET) + +#define PWM_ONE_SHOT_MODE (0) +#define PWM_CONTINUOUS_MODE (1) +#define PWM_CAPTURE_MODE (2) + +#define FREQUENCY_24M (24000000) + +#define PWM_MAX_CONTROLLER_NUM (4) + +UINTN mPwmControllerBase[PWM_MAX_CONTROLLER_NUM] = { + RK3588_PWM0_BASE, + RK3588_PWM1_BASE, + RK3588_PWM2_BASE, + RK3588_PWM3_BASE +}; + +RETURN_STATUS +EFIAPI +RkPwmSetConfig ( + IN PWM_DATA *Data + ) +{ + UINTN Base = mPwmControllerBase[Data->ControllerID]; + UINT32 Ctrl; + UINT32 PeriodCycle, DutyCycle; + UINT64 ChannelOffset = Data->ChannelID * 0x10; + + PeriodCycle = ((UINT64)FREQUENCY_24M * Data->PeriodNs / 1000000000); + DutyCycle = ((UINT64)FREQUENCY_24M * Data->DutyNs / 1000000000); + + Ctrl = MmioRead32(Base + ChannelOffset + PWM_CTRL_OFFSET); + Ctrl |= PWM_LOCK; + MmioWrite32(Base + ChannelOffset + PWM_CTRL_OFFSET, Ctrl); + MicroSecondDelay (1); + + MmioWrite32(Base + ChannelOffset + PWM_PERIOD_HPR_OFFSET, PeriodCycle); + MmioWrite32(Base + ChannelOffset + PWM_DUTY_LPR_OFFSET, DutyCycle); + + Ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK); + + if (Data->Polarity) { + Ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE; + } else { + Ctrl |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE; + } + + Ctrl &= ~PWM_LOCK; + MmioWrite32(Base + ChannelOffset + PWM_CTRL_OFFSET, Ctrl); + + return RETURN_SUCCESS; +} + +RETURN_STATUS +EFIAPI +RkPwmEnable ( + IN PWM_DATA *Data + ) +{ + UINTN Base = mPwmControllerBase[Data->ControllerID]; + UINT32 Ctrl; + UINT64 ChannelOffset = Data->ChannelID * 0x10; + + Ctrl = MmioRead32(Base + ChannelOffset + PWM_CTRL_OFFSET); + Ctrl &= ~PWM_MODE_MASK; + Ctrl |= (PWM_CONTINUOUS_MODE << PWM_MODE_SHIFT) | PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE; + + MmioWrite32(Base + ChannelOffset + PWM_CTRL_OFFSET, Ctrl); + + return RETURN_SUCCESS; +} + +RETURN_STATUS +EFIAPI +RkPwmDisable ( + IN PWM_DATA *Data + ) +{ + UINTN Base = mPwmControllerBase[Data->ControllerID]; + UINT32 Ctrl; + UINT64 ChannelOffset = Data->ChannelID * 0x10; + + Ctrl = MmioRead32(Base + ChannelOffset + PWM_CTRL_OFFSET); + Ctrl &= ~PWM_ENABLE; + + MmioWrite32(Base + ChannelOffset + PWM_CTRL_OFFSET, Ctrl); + + return RETURN_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PWMLib/PWMLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PWMLib/PWMLib.inf new file mode 100644 index 0000000..a02d6f1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PWMLib/PWMLib.inf @@ -0,0 +1,35 @@ +/** @file + Component description file for Rockchip PWM Driver. + + Copyright (c) 2022 Rockchip Electronics Co. Ltd. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PWMLib + FILE_GUID = 2f34109a-6f62-11ec-ac42-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PWMLib + +[Sources.common] + PWMLib.c + +[LibraryClasses] + DebugLib + IoLib + TimerLib + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[BuildOptions] + +[Pcd] + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootDescriptionLib/PlatformBootDescriptionLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootDescriptionLib/PlatformBootDescriptionLib.c new file mode 100644 index 0000000..f17b1e5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootDescriptionLib/PlatformBootDescriptionLib.c @@ -0,0 +1,416 @@ +/** @file + * + * Boot Manager device description handler. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +RKATAG_BOOTDEV_TYPE mBootDeviceType; + +CHAR16 mBootDescUefiPrefix[] = L"UEFI "; +CHAR16 mBootDescGenericManufacturer[] = L"Generic"; +CHAR16 mBootDescEmmc[] = L" eMMC"; +CHAR16 mBootDescEmmcUserData[] = L" eMMC User Data"; +CHAR16 mBootDescEmmcBoot1[] = L" eMMC Boot 1"; +CHAR16 mBootDescEmmcBoot2[] = L" eMMC Boot 2"; +CHAR16 mBootDescEmmcGp1[] = L" eMMC GP 1"; +CHAR16 mBootDescEmmcGp2[] = L" eMMC GP 2"; +CHAR16 mBootDescEmmcGp3[] = L" eMMC GP 3"; +CHAR16 mBootDescEmmcGp4[] = L" eMMC GP 4"; +CHAR16 mBootDescSd[] = L" SD Device"; +CHAR16 mBootDescFirmwareSuffix[] = L" [Fw]"; + +typedef struct { + UINT8 Id; + CHAR16 *Name; +} SDMMC_MANUFACTURER; + +// +// List based on: +// - https://www.cameramemoryspeed.com/sd-memory-card-faq/reading-sd-card-cid-serial-psn-internal-numbers/ +// - https://git.kernel.org/pub/scm/utils/mmc/mmc-utils.git/tree/lsmmc.c +// +STATIC SDMMC_MANUFACTURER mSdManufacturers[] = { + { 0x01, L"Panasonic" }, + { 0x02, L"Toshiba/Kingston/Viking" }, + { 0x03, L"SanDisk" }, + { 0x08, L"Silicon Power" }, + { 0x18, L"Infineon" }, + { 0x1b, L"Transcend/Samsung" }, + { 0x1c, L"Transcend" }, + { 0x1d, L"Corsair/AData" }, + { 0x1e, L"Transcend" }, + { 0x1f, L"Kingston" }, + { 0x27, L"Delkin/Phison" }, + { 0x28, L"Lexar" }, + { 0x30, L"SanDisk" }, + { 0x31, L"Silicon Power" }, + { 0x33, L"STMicroelectronics" }, + { 0x41, L"Kingston" }, + { 0x6f, L"STMicroelectronics" }, + { 0x74, L"Transcend" }, + { 0x76, L"Patriot" }, + { 0x82, L"Gobe/Sony" }, + { 0x9c, L"Angelbird/Hoodman" }, +}; + +STATIC SDMMC_MANUFACTURER mMmcManufacturers[] = { + { 0x00, L"SanDisk" }, + { 0x02, L"Kingston/SanDisk" }, + { 0x03, L"Toshiba" }, + { 0x11, L"Toshiba" }, + { 0x13, L"Micron" }, + { 0x15, L"Samsung" }, + { 0x37, L"KingMax" }, + { 0x44, L"ATP" }, + { 0x45, L"SanDisk" }, + { 0x2c, L"Kingston" }, + { 0x70, L"Kingston" }, + { 0x88, L"Foresee" }, + { 0x9b, L"YMTC" }, + { 0xd6, L"Foresee" }, + { 0xfe, L"Micron" }, +}; + +STATIC +NON_DISCOVERABLE_DEVICE * +GetNonDiscoverableDevice ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath + ) +{ + EFI_STATUS Status; + EFI_HANDLE DeviceHandle; + NON_DISCOVERABLE_DEVICE *Device; + EFI_DEVICE_PATH_PROTOCOL *CurrentDevicePath; + + CurrentDevicePath = DevicePath; + + if (DevicePath->Type != HARDWARE_DEVICE_PATH + || DevicePath->SubType != HW_VENDOR_DP) { + return NULL; + } + + Status = gBS->LocateDevicePath (&gEdkiiNonDiscoverableDeviceProtocolGuid, + &CurrentDevicePath, &DeviceHandle); + if (EFI_ERROR (Status)) { + return NULL; + } + + Status = gBS->HandleProtocol (DeviceHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, (VOID **) &Device); + if (EFI_ERROR (Status)) { + return NULL; + } + + return Device; +} + +STATIC +BOOLEAN +CheckIsBootDevice ( + IN NON_DISCOVERABLE_DEVICE *Device + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + Descriptor = &Device->Resources[0]; + + if (Descriptor->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR || + Descriptor->ResType != ACPI_ADDRESS_SPACE_TYPE_MEM) { + return FALSE; + } + + if (mBootDeviceType == RkAtagBootDevTypeEmmc) { + return Descriptor->AddrRangeMin == PcdGet32 (PcdDwcSdhciBaseAddress); + } + if (mBootDeviceType == RkAtagBootDevTypeSd0) { + return Descriptor->AddrRangeMin == PcdGet32 (PcdRkSdmmcBaseAddress); + } + + return FALSE; +} + +STATIC +EFI_STATUS +GetDiskInfoInquiryData ( + IN EFI_HANDLE Handle, + OUT VOID *InquiryData, + IN UINT32 InquiryDataSize + ) +{ + EFI_STATUS Status; + EFI_DISK_INFO_PROTOCOL *DiskInfo; + + if (InquiryData == NULL || InquiryDataSize == 0) { + return EFI_INVALID_PARAMETER; + } + + Status = gBS->HandleProtocol (Handle, + &gEfiDiskInfoProtocolGuid, (VOID **) &DiskInfo); + if (EFI_ERROR (Status)) { + return Status; + } + + // InquiryDataSize is set to the expected size if EFI_BUFFER_TOO_SMALL + // is returned but we'll always call with the correct size. + Status = DiskInfo->Inquiry (DiskInfo, InquiryData, &InquiryDataSize); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + +STATIC +CHAR16 * +GetSdMmcManufacturerName ( + IN UINT8 Id, + IN BOOLEAN IsMmc + ) +{ + SDMMC_MANUFACTURER *List; + UINT8 Count; + + List = IsMmc ? mMmcManufacturers : mSdManufacturers; + Count = IsMmc ? ARRAY_SIZE (mMmcManufacturers) + : ARRAY_SIZE (mSdManufacturers); + + for (UINT8 Index; Index < Count; ++Index) { + if (List[Index].Id == Id) { + return List[Index].Name; + } + } + return mBootDescGenericManufacturer; +} + +STATIC +EFI_STATUS +AsciiSwapAppendToUnicode ( + IN CHAR8 *Source, + IN UINTN Length, + IN CHAR16 *Destination, + IN UINTN DestMax + ) +{ + EFI_STATUS Status; + CHAR8 Temp; + UINTN ConvertedLength; + + if (StrLen (Destination) + Length + 1 > DestMax) { + return EFI_BUFFER_TOO_SMALL; + } + + for (UINTN Index = 0; Index < Length / 2; ++Index) { + Temp = Source[Index]; + Source[Index] = Source[Length - 1 - Index]; + Source[Length - 1 - Index] = Temp; + } + + Status = AsciiStrnToUnicodeStrS (Source, Length, + Destination + StrLen (Destination), + DestMax, &ConvertedLength); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + +STATIC +CHAR16 * +GetEmmcDescription ( + CONTROLLER_DEVICE_PATH *DevicePath + ) +{ + switch (DevicePath->ControllerNumber) { + case EmmcPartitionUserData: + return mBootDescEmmcUserData; + case EmmcPartitionBoot1: + return mBootDescEmmcBoot1; + case EmmcPartitionBoot2: + return mBootDescEmmcBoot2; + case EmmcPartitionGP1: + return mBootDescEmmcGp1; + case EmmcPartitionGP2: + return mBootDescEmmcGp2; + case EmmcPartitionGP3: + return mBootDescEmmcGp3; + case EmmcPartitionGP4: + return mBootDescEmmcGp4; + } + return mBootDescEmmc; +} + +STATIC +CHAR16 * +GetSdMmcUefiBootDescription ( + IN CHAR16 *ManufacturerName, + IN UINT8 *ProductName, + IN UINT8 ProductNameLength, + IN UINT8 SerialNumber[4], + IN CHAR16 *DeviceType, + IN BOOLEAN IsBootDevice + ) +{ + CHAR16 *Desc; + UINTN DescSize; + UINT32 Serial32; + + Desc = mBootDescUefiPrefix; + + DescSize = StrSize (Desc) - sizeof (CHAR16) // "UEFI " + + StrSize (ManufacturerName) - sizeof (CHAR16) // "Samsung" + + sizeof (CHAR16) // " " + + ProductNameLength * sizeof (CHAR16) // "BJTD4R" + + sizeof (CHAR16) // " " + + sizeof (UINT32) * 2 * sizeof (CHAR16) // "00000000" + + StrSize (DeviceType) - sizeof (CHAR16); // " EMMC User Data" + if (IsBootDevice) { + DescSize += StrSize (mBootDescFirmwareSuffix) - sizeof (CHAR16); // " [Fw]" + } + DescSize += sizeof (CHAR16); // '\0' + + Desc = AllocateCopyPool (DescSize, Desc); + if (Desc == NULL) { + return NULL; + } + + StrCatS (Desc, DescSize / sizeof (CHAR16), ManufacturerName); + StrCatS (Desc, DescSize / sizeof (CHAR16), L" "); + + AsciiSwapAppendToUnicode ((CHAR8 *) ProductName, + ProductNameLength, + Desc, + DescSize / sizeof (CHAR16)); + + Serial32 = (SerialNumber[0] + | (SerialNumber[1]) << 8 + | (SerialNumber[2]) << 16 + | (SerialNumber[3] << 24)); + + StrCatS (Desc, DescSize / sizeof (CHAR16), L" "); + + UnicodeValueToStringS (Desc + StrLen (Desc), + DescSize - StrSize (Desc), + RADIX_HEX | PREFIX_ZERO, + Serial32, 8); + + StrCatS (Desc, DescSize / sizeof (CHAR16), DeviceType); + + if (IsBootDevice) { + StrCatS (Desc, DescSize / sizeof (CHAR16), mBootDescFirmwareSuffix); + } + + return Desc; +} + +STATIC +CHAR16 * +EFIAPI +PlatformBootDescriptionHandler ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *DefaultDescription + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + NON_DISCOVERABLE_DEVICE *NonDiscoverableDevice; + BOOLEAN IsBootDevice; + CHAR16 *Desc; + EMMC_CID EmmcCid; + CHAR16 *EmmcDesc; + SD_CID SdCid; + + DevicePath = DevicePathFromHandle (Handle); + + NonDiscoverableDevice = GetNonDiscoverableDevice (DevicePath); + if (NonDiscoverableDevice == NULL) { + return NULL; + } + + IsBootDevice = CheckIsBootDevice (NonDiscoverableDevice); + + DevicePath = NextDevicePathNode (DevicePath); + + if (DevicePath->SubType == MSG_EMMC_DP) { + Status = GetDiskInfoInquiryData (Handle, &EmmcCid, sizeof (EMMC_CID)); + if (EFI_ERROR (Status)) { + return NULL; + } + + EmmcDesc = mBootDescEmmc; + + DevicePath = NextDevicePathNode (DevicePath); + if (DevicePath->SubType == HW_CONTROLLER_DP) { + if (((CONTROLLER_DEVICE_PATH *) DevicePath)->ControllerNumber != EmmcPartitionUserData) { + // + // There can only be one boot device. + // eMMC has multiple partitions, but I don't know if it's possible + // to load UEFI from anything other than UserData. + // If it turns out to be a possibility, we'd need to create a protocol + // for RkFvbDxe that would allow getting the Device Path of the block + // device that holds the NVRAM. + // + IsBootDevice = FALSE; + } + + EmmcDesc = GetEmmcDescription ((CONTROLLER_DEVICE_PATH *) DevicePath); + } + + Desc = GetSdMmcUefiBootDescription ( + GetSdMmcManufacturerName (EmmcCid.ManufacturerId, TRUE), + EmmcCid.ProductName, + ARRAY_SIZE (EmmcCid.ProductName), + EmmcCid.ProductSerialNumber, + EmmcDesc, + IsBootDevice); + + } else if (DevicePath->SubType == MSG_SD_DP) { + Status = GetDiskInfoInquiryData (Handle, &SdCid, sizeof (SD_CID)); + if (EFI_ERROR (Status)) { + return NULL; + } + + Desc = GetSdMmcUefiBootDescription ( + GetSdMmcManufacturerName (SdCid.ManufacturerId, FALSE), + SdCid.ProductName, + ARRAY_SIZE (SdCid.ProductName), + SdCid.ProductSerialNumber, + mBootDescSd, + IsBootDevice); + } else { + return NULL; + } + + return Desc; +} + +EFI_STATUS +EFIAPI +PlatformBootDescriptionLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + RKATAG_BOOTDEV *BootDevice; + + BootDevice = RkAtagsGetBootDev (); + mBootDeviceType = BootDevice != NULL ? BootDevice->DevType : RkAtagBootDevTypeUnknown; + + return EfiBootManagerRegisterBootDescriptionHandler (PlatformBootDescriptionHandler); +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootDescriptionLib/PlatformBootDescriptionLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootDescriptionLib/PlatformBootDescriptionLib.inf new file mode 100644 index 0000000..035f01a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootDescriptionLib/PlatformBootDescriptionLib.inf @@ -0,0 +1,42 @@ +#/** @file +# +# Boot Manager device description handler. +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformBootDescriptionLib + FILE_GUID = 8d63c2d3-b621-41f1-80fe-037c46d23790 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL|DXE_DRIVER UEFI_APPLICATION + CONSTRUCTOR = PlatformBootDescriptionLibConstructor + +[Sources] + PlatformBootDescriptionLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + UefiLib + UefiBootServicesTableLib + UefiBootManagerLib + MemoryAllocationLib + DevicePathLib + RkAtagsLib + +[Protocols] + gEdkiiNonDiscoverableDeviceProtocolGuid ## SOMETIMES_CONSUMES + gEfiDiskInfoProtocolGuid ## SOMETIMES_CONSUMES + +[Pcd] + gRockchipTokenSpaceGuid.PcdDwcSdhciBaseAddress + gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBm.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBm.c new file mode 100644 index 0000000..c289907 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBm.c @@ -0,0 +1,1331 @@ +/** @file + Implementation for PlatformBootManagerLib library class interfaces. + + Copyright (C) 2015-2016, Red Hat, Inc. + Copyright (c) 2014 - 2021, ARM Ltd. All rights reserved.
    + Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
    + Copyright (c) 2016, Linaro Ltd. All rights reserved.
    + Copyright (c) 2021, Semihalf All rights reserved.
    + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PlatformBm.h" + +#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) } + +#pragma pack (1) +typedef struct { + VENDOR_DEVICE_PATH SerialDxe; + UART_DEVICE_PATH Uart; + VENDOR_DEFINED_DEVICE_PATH TermType; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_SERIAL_CONSOLE; +#pragma pack () + +STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { + // + // VENDOR_DEVICE_PATH SerialDxe + // + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) }, + EDKII_SERIAL_PORT_LIB_VENDOR_GUID + }, + + // + // UART_DEVICE_PATH Uart + // + { + { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) }, + 0, // Reserved + 0, // BaudRate + 0, // DataBits + 0, // Parity + 0, // StopBits + }, + + // + // VENDOR_DEFINED_DEVICE_PATH TermType + // + { + { + MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, + DP_NODE_LEN (VENDOR_DEFINED_DEVICE_PATH) + } + // + // Guid to be filled in dynamically + // + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + +#pragma pack (1) +typedef struct { + USB_CLASS_DEVICE_PATH Keyboard; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_USB_KEYBOARD; +#pragma pack () + +STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = { + // + // USB_CLASS_DEVICE_PATH Keyboard + // + { + { + MESSAGING_DEVICE_PATH, MSG_USB_CLASS_DP, + DP_NODE_LEN (USB_CLASS_DEVICE_PATH) + }, + 0xFFFF, // VendorId: any + 0xFFFF, // ProductId: any + 3, // DeviceClass: HID + 1, // DeviceSubClass: boot + 1 // DeviceProtocol: keyboard + }, + + // + // EFI_DEVICE_PATH_PROTOCOL End + // + { + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, + DP_NODE_LEN (EFI_DEVICE_PATH_PROTOCOL) + } +}; + +/** + Check if the handle satisfies a particular condition. + + @param[in] Handle The handle to check. + @param[in] ReportText A caller-allocated string passed in for reporting + purposes. It must never be NULL. + + @retval TRUE The condition is satisfied. + @retval FALSE Otherwise. This includes the case when the condition could not + be fully evaluated due to an error. +**/ +typedef +BOOLEAN +(EFIAPI *FILTER_FUNCTION)( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ); + +/** + Process a handle. + + @param[in] Handle The handle to process. + @param[in] ReportText A caller-allocated string passed in for reporting + purposes. It must never be NULL. +**/ +typedef +VOID +(EFIAPI *CALLBACK_FUNCTION)( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ); + +/** + Locate all handles that carry the specified protocol, filter them with a + callback function, and pass each handle that passes the filter to another + callback. + + @param[in] ProtocolGuid The protocol to look for. + + @param[in] Filter The filter function to pass each handle to. If this + parameter is NULL, then all handles are processed. + + @param[in] Process The callback function to pass each handle to that + clears the filter. +**/ +STATIC +VOID +FilterAndProcess ( + IN EFI_GUID *ProtocolGuid, + IN FILTER_FUNCTION Filter OPTIONAL, + IN CALLBACK_FUNCTION Process + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN NoHandles; + UINTN Idx; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + ProtocolGuid, + NULL /* SearchKey */, + &NoHandles, + &Handles + ); + if (EFI_ERROR (Status)) { + // + // This is not an error, just an informative condition. + // + DEBUG (( + DEBUG_VERBOSE, + "%a: %g: %r\n", + __FUNCTION__, + ProtocolGuid, + Status + )); + return; + } + + ASSERT (NoHandles > 0); + for (Idx = 0; Idx < NoHandles; ++Idx) { + CHAR16 *DevicePathText; + STATIC CHAR16 Fallback[] = L""; + + // + // The ConvertDevicePathToText() function handles NULL input transparently. + // + DevicePathText = ConvertDevicePathToText ( + DevicePathFromHandle (Handles[Idx]), + FALSE, // DisplayOnly + FALSE // AllowShortcuts + ); + if (DevicePathText == NULL) { + DevicePathText = Fallback; + } + + if ((Filter == NULL) || Filter (Handles[Idx], DevicePathText)) { + Process (Handles[Idx], DevicePathText); + } + + if (DevicePathText != Fallback) { + FreePool (DevicePathText); + } + } + + gBS->FreePool (Handles); +} + +/** + This FILTER_FUNCTION checks if a handle corresponds to a PCI display device. +**/ +STATIC +BOOLEAN +EFIAPI +IsPciDisplay ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + + Status = gBS->HandleProtocol ( + Handle, + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + // + // This is not an error worth reporting. + // + return FALSE; + } + + Status = PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + 0 /* Offset */, + sizeof Pci / sizeof (UINT32), + &Pci + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status)); + return FALSE; + } + + return IS_PCI_DISPLAY (&Pci); +} + +/** + This FILTER_FUNCTION checks if a handle corresponds to a non-discoverable + USB host controller. +**/ +STATIC +BOOLEAN +EFIAPI +IsUsbHost ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + NON_DISCOVERABLE_DEVICE *Device; + EFI_STATUS Status; + + Status = gBS->HandleProtocol ( + Handle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + (VOID **)&Device + ); + if (EFI_ERROR (Status)) { + return FALSE; + } + + if (CompareGuid (Device->Type, &gEdkiiNonDiscoverableUhciDeviceGuid) || + CompareGuid (Device->Type, &gEdkiiNonDiscoverableEhciDeviceGuid) || + CompareGuid (Device->Type, &gEdkiiNonDiscoverableXhciDeviceGuid)) + { + return TRUE; + } + + return FALSE; +} + +/** + This FILTER_FUNCTION checks if the Block I/O protocol handle + corresponds to that of the boot SD/eMMC device. + + This code is almost identical to FvbCheckIsBootDevice from RkFvbDxe. +**/ +STATIC +BOOLEAN +EFIAPI +IsSdBootBlockIo ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_HANDLE DeviceHandle; + NON_DISCOVERABLE_DEVICE *Device; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + RKATAG_BOOTDEV *BootDevice; + + BootDevice = RkAtagsGetBootDev (); + if (BootDevice == NULL) { + return FALSE; + } + + DevicePath = DevicePathFromHandle (Handle); + + if (DevicePath->Type != HARDWARE_DEVICE_PATH + || DevicePath->SubType != HW_VENDOR_DP) { + return FALSE; + } + + Status = gBS->LocateDevicePath (&gEdkiiNonDiscoverableDeviceProtocolGuid, + &DevicePath, &DeviceHandle); + if (EFI_ERROR (Status)) { + return FALSE; + } + + Status = gBS->HandleProtocol (DeviceHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, (VOID **) &Device); + if (EFI_ERROR (Status)) { + return FALSE; + } + + Descriptor = &Device->Resources[0]; + + if (Descriptor->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR || + Descriptor->ResType != ACPI_ADDRESS_SPACE_TYPE_MEM) { + return FALSE; + } + + if (BootDevice->DevType == RkAtagBootDevTypeEmmc) { + return Descriptor->AddrRangeMin == PcdGet32 (PcdDwcSdhciBaseAddress); + } + if (BootDevice->DevType == RkAtagBootDevTypeSd0) { + return Descriptor->AddrRangeMin == PcdGet32 (PcdRkSdmmcBaseAddress); + } + + return FALSE; +} + +/** + This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking + the matching driver to produce all first-level child handles. +**/ +STATIC +VOID +EFIAPI +Connect ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + + Status = gBS->ConnectController ( + Handle, // ControllerHandle + NULL, // DriverImageHandle + NULL, // RemainingDevicePath -- produce all children + FALSE // Recursive + ); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, + "%a: %s: %r\n", + __FUNCTION__, + ReportText, + Status + )); +} + +/** + This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the + handle, and adds it to ConOut and ErrOut. +**/ +STATIC +VOID +EFIAPI +AddOutput ( + IN EFI_HANDLE Handle, + IN CONST CHAR16 *ReportText + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + DevicePath = DevicePathFromHandle (Handle); + if (DevicePath == NULL) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: handle %p: device path not found\n", + __FUNCTION__, + ReportText, + Handle + )); + return; + } + + Status = EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: adding to ConOut: %r\n", + __FUNCTION__, + ReportText, + Status + )); + return; + } + + Status = EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: %s: adding to ErrOut: %r\n", + __FUNCTION__, + ReportText, + Status + )); + return; + } + + DEBUG (( + DEBUG_VERBOSE, + "%a: %s: added to ConOut and ErrOut\n", + __FUNCTION__, + ReportText + )); +} + +STATIC +VOID +PlatformRegisterFvBootOption ( + CONST EFI_GUID *FileGuid, + CHAR16 *Description, + UINT32 Attributes, + EFI_INPUT_KEY *Key + ) +{ + EFI_STATUS Status; + INTN OptionIndex; + EFI_BOOT_MANAGER_LOAD_OPTION NewOption; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status = gBS->HandleProtocol ( + gImageHandle, + &gEfiLoadedImageProtocolGuid, + (VOID **)&LoadedImage + ); + ASSERT_EFI_ERROR (Status); + + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); + DevicePath = DevicePathFromHandle (LoadedImage->DeviceHandle); + ASSERT (DevicePath != NULL); + DevicePath = AppendDevicePathNode ( + DevicePath, + (EFI_DEVICE_PATH_PROTOCOL *)&FileNode + ); + ASSERT (DevicePath != NULL); + + Status = EfiBootManagerInitializeLoadOption ( + &NewOption, + LoadOptionNumberUnassigned, + LoadOptionTypeBoot, + Attributes, + Description, + DevicePath, + NULL, + 0 + ); + ASSERT_EFI_ERROR (Status); + FreePool (DevicePath); + + BootOptions = EfiBootManagerGetLoadOptions ( + &BootOptionCount, + LoadOptionTypeBoot + ); + + OptionIndex = EfiBootManagerFindLoadOption ( + &NewOption, + BootOptions, + BootOptionCount + ); + + if (OptionIndex == -1) { + Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN); + ASSERT_EFI_ERROR (Status); + Status = EfiBootManagerAddKeyOptionVariable ( + NULL, + (UINT16)NewOption.OptionNumber, + 0, + Key, + NULL + ); + ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED); + } + + EfiBootManagerFreeLoadOption (&NewOption); + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); +} + +STATIC +VOID +GetPlatformOptions ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MANAGER_LOAD_OPTION *CurrentBootOptions; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + EFI_INPUT_KEY *BootKeys; + PLATFORM_BOOT_MANAGER_PROTOCOL *PlatformBootManager; + UINTN CurrentBootOptionCount; + UINTN Index; + UINTN BootCount; + + Status = gBS->LocateProtocol ( + &gPlatformBootManagerProtocolGuid, + NULL, + (VOID **)&PlatformBootManager + ); + if (EFI_ERROR (Status)) { + return; + } + + Status = PlatformBootManager->GetPlatformBootOptionsAndKeys ( + &BootCount, + &BootOptions, + &BootKeys + ); + if (EFI_ERROR (Status)) { + return; + } + + // + // Fetch the existent boot options. If there are none, CurrentBootCount + // will be zeroed. + // + CurrentBootOptions = EfiBootManagerGetLoadOptions ( + &CurrentBootOptionCount, + LoadOptionTypeBoot + ); + // + // Process the platform boot options. + // + for (Index = 0; Index < BootCount; Index++) { + INTN Match; + UINTN BootOptionNumber; + + // + // If there are any preexistent boot options, and the subject platform boot + // option is already among them, then don't try to add it. Just get its + // assigned boot option number so we can associate a hotkey with it. Note + // that EfiBootManagerFindLoadOption() deals fine with (CurrentBootOptions + // == NULL) if (CurrentBootCount == 0). + // + Match = EfiBootManagerFindLoadOption ( + &BootOptions[Index], + CurrentBootOptions, + CurrentBootOptionCount + ); + if (Match >= 0) { + BootOptionNumber = CurrentBootOptions[Match].OptionNumber; + } else { + // + // Add the platform boot options as a new one, at the end of the boot + // order. Note that if the platform provided this boot option with an + // unassigned option number, then the below function call will assign a + // number. + // + Status = EfiBootManagerAddLoadOptionVariable ( + &BootOptions[Index], + MAX_UINTN + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: failed to register \"%s\": %r\n", + __FUNCTION__, + BootOptions[Index].Description, + Status + )); + continue; + } + + BootOptionNumber = BootOptions[Index].OptionNumber; + } + + // + // Register a hotkey with the boot option, if requested. + // + if (BootKeys[Index].UnicodeChar == L'\0') { + continue; + } + + Status = EfiBootManagerAddKeyOptionVariable ( + NULL, + BootOptionNumber, + 0, + &BootKeys[Index], + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: failed to register hotkey for \"%s\": %r\n", + __FUNCTION__, + BootOptions[Index].Description, + Status + )); + } + } + + EfiBootManagerFreeLoadOptions (CurrentBootOptions, CurrentBootOptionCount); + EfiBootManagerFreeLoadOptions (BootOptions, BootCount); + FreePool (BootKeys); +} + +/** + Remove all MemoryMapped(...)/FvFile(...) and Fv(...)/FvFile(...) boot options + whose device paths do not resolve exactly to an FvFile in the system. + + This removes any boot options that point to binaries built into the firmware + and have become stale due to any of the following: + - DXEFV's base address or size changed (historical), + - DXEFV's FvNameGuid changed, + - the FILE_GUID of the pointed-to binary changed, + - the referenced binary is no longer built into the firmware. + + EfiBootManagerFindLoadOption() used in PlatformRegisterFvBootOption() only + avoids exact duplicates. +**/ +VOID +RemoveStaleFvFileOptions ( + VOID + ) +{ + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + UINTN Index; + + BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, + LoadOptionTypeBoot); + + for (Index = 0; Index < BootOptionCount; ++Index) { + EFI_DEVICE_PATH_PROTOCOL *Node1, *Node2, *SearchNode; + EFI_STATUS Status; + EFI_HANDLE FvHandle; + + // + // If the device path starts with neither MemoryMapped(...) nor Fv(...), + // then keep the boot option. + // + Node1 = BootOptions[Index].FilePath; + if (!(DevicePathType (Node1) == HARDWARE_DEVICE_PATH && + DevicePathSubType (Node1) == HW_MEMMAP_DP) && + !(DevicePathType (Node1) == MEDIA_DEVICE_PATH && + DevicePathSubType (Node1) == MEDIA_PIWG_FW_VOL_DP)) { + continue; + } + + // + // If the second device path node is not FvFile(...), then keep the boot + // option. + // + Node2 = NextDevicePathNode (Node1); + if (DevicePathType (Node2) != MEDIA_DEVICE_PATH || + DevicePathSubType (Node2) != MEDIA_PIWG_FW_FILE_DP) { + continue; + } + + // + // Locate the Firmware Volume2 protocol instance that is denoted by the + // boot option. If this lookup fails (i.e., the boot option references a + // firmware volume that doesn't exist), then we'll proceed to delete the + // boot option. + // + SearchNode = Node1; + Status = gBS->LocateDevicePath (&gEfiFirmwareVolume2ProtocolGuid, + &SearchNode, &FvHandle); + + if (!EFI_ERROR (Status)) { + // + // The firmware volume was found; now let's see if it contains the FvFile + // identified by GUID. + // + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *FvFileNode; + UINTN BufferSize; + EFI_FV_FILETYPE FoundType; + EFI_FV_FILE_ATTRIBUTES FileAttributes; + UINT32 AuthenticationStatus; + + Status = gBS->HandleProtocol (FvHandle, &gEfiFirmwareVolume2ProtocolGuid, + (VOID **)&FvProtocol); + ASSERT_EFI_ERROR (Status); + + FvFileNode = (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *)Node2; + // + // Buffer==NULL means we request metadata only: BufferSize, FoundType, + // FileAttributes. + // + Status = FvProtocol->ReadFile ( + FvProtocol, + &FvFileNode->FvFileName, // NameGuid + NULL, // Buffer + &BufferSize, + &FoundType, + &FileAttributes, + &AuthenticationStatus + ); + if (!EFI_ERROR (Status)) { + // + // The FvFile was found. Keep the boot option. + // + continue; + } + } + + // + // Delete the boot option. + // + Status = EfiBootManagerDeleteLoadOptionVariable ( + BootOptions[Index].OptionNumber, LoadOptionTypeBoot); + DEBUG_CODE ( + CHAR16 *DevicePathString; + + DevicePathString = ConvertDevicePathToText(BootOptions[Index].FilePath, + FALSE, FALSE); + DEBUG (( + EFI_ERROR (Status) ? DEBUG_WARN : DEBUG_VERBOSE, + "%a: removing stale Boot#%04x %s: %r\n", + __FUNCTION__, + (UINT32)BootOptions[Index].OptionNumber, + DevicePathString == NULL ? L"" : DevicePathString, + Status + )); + if (DevicePathString != NULL) { + FreePool (DevicePathString); + } + ); + } + + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); +} + +STATIC +VOID +PlatformRegisterOptionsAndKeys ( + VOID + ) +{ + EFI_STATUS Status; + EFI_INPUT_KEY Enter; + EFI_INPUT_KEY F2; + EFI_INPUT_KEY Esc; + EFI_BOOT_MANAGER_LOAD_OPTION BootOption; + + GetPlatformOptions (); + + // + // Register ENTER as CONTINUE key + // + Enter.ScanCode = SCAN_NULL; + Enter.UnicodeChar = CHAR_CARRIAGE_RETURN; + Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL); + ASSERT_EFI_ERROR (Status); + + // + // Map F2 and ESC to Boot Manager Menu + // + F2.ScanCode = SCAN_F2; + F2.UnicodeChar = CHAR_NULL; + Esc.ScanCode = SCAN_ESC; + Esc.UnicodeChar = CHAR_NULL; + Status = EfiBootManagerGetBootManagerMenu (&BootOption); + ASSERT_EFI_ERROR (Status); + Status = EfiBootManagerAddKeyOptionVariable ( + NULL, + (UINT16)BootOption.OptionNumber, + 0, + &F2, + NULL + ); + ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED); + Status = EfiBootManagerAddKeyOptionVariable ( + NULL, + (UINT16)BootOption.OptionNumber, + 0, + &Esc, + NULL + ); + ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED); +} + +// +// BDS Platform Functions +// + +/** + Do the platform init, can be customized by OEM/IBV + Possible things that can be done in PlatformBootManagerBeforeConsole: + > Update console variable: 1. include hot-plug devices; + > 2. Clear ConIn and add SOL for AMT + > Register new Driver#### or Boot#### + > Register new Key####: e.g.: F12 + > Signal ReadyToLock event + > Authentication action: 1. connect Auth devices; + > 2. Identify auto logon user. +**/ +VOID +EFIAPI +PlatformBootManagerBeforeConsole ( + VOID + ) +{ + // + // Signal EndOfDxe PI Event + // + EfiEventGroupSignal (&gEfiEndOfDxeEventGroupGuid); + + // + // Dispatch deferred images after EndOfDxe event. + // + EfiBootManagerDispatchDeferredImages (); + + // + // Add the hardcoded short-form USB keyboard device path to ConIn. + // This must be done prior to connecting any USB bus controllers, because + // when a keyboard gets installed, ConPlatformDxe will immediately check + // that its device path exists in the ConIn variable before enabling input + // from it. Since this variable is not initially populated at first boot, + // we would otherwise end up with no keyboard input during BDS countdown. + // + EfiBootManagerUpdateConsoleVariable ( + ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, + NULL + ); + + // + // Locate the PCI root bridges and make the PCI bus driver connect each, + // non-recursively. This will produce a number of child handles with PciIo on + // them. + // + FilterAndProcess (&gEfiPciRootBridgeIoProtocolGuid, NULL, Connect); + + // + // Find all display class PCI devices (using the handles from the previous + // step), and connect them non-recursively. This should produce a number of + // child handles with GOPs on them. + // + FilterAndProcess (&gEfiPciIoProtocolGuid, IsPciDisplay, Connect); + + // + // Now add the device path of all handles with GOP on them to ConOut and + // ErrOut. + // + FilterAndProcess (&gEfiGraphicsOutputProtocolGuid, NULL, AddOutput); + + // + // The core BDS code connects short-form USB device paths by explicitly + // looking for handles with PCI I/O installed, and checking the PCI class + // code whether it matches the one for a USB host controller. This means + // non-discoverable USB host controllers need to have the non-discoverable + // PCI driver attached first. + // + FilterAndProcess (&gEdkiiNonDiscoverableDeviceProtocolGuid, IsUsbHost, Connect); + + // + // Connect USB OHCI controller(s) + // + FilterAndProcess (&gOhciDeviceProtocolGuid, NULL, Connect); + + // + // Connect the Block I/O device produced by the SD/eMMC device that + // booted UEFI. We don't want BDS to ignore this device as it would + // prevent RkFvbDxe from detecting it and dumping the NVRAM variables + // in time. + // + FilterAndProcess (&gEfiBlockIoProtocolGuid, IsSdBootBlockIo, Connect); + + // + // Add the hardcoded serial console device path to ConIn, ConOut, ErrOut. + // + STATIC_ASSERT ( + FixedPcdGet8 (PcdDefaultTerminalType) == 4, + "PcdDefaultTerminalType must be TTYTERM" + ); + STATIC_ASSERT ( + FixedPcdGet8 (PcdUartDefaultParity) != 0, + "PcdUartDefaultParity must be set to an actual value, not 'default'" + ); + STATIC_ASSERT ( + FixedPcdGet8 (PcdUartDefaultStopBits) != 0, + "PcdUartDefaultStopBits must be set to an actual value, not 'default'" + ); + + mSerialConsole.Uart.BaudRate = PcdGet64 (PcdUartDefaultBaudRate); + mSerialConsole.Uart.DataBits = PcdGet8 (PcdUartDefaultDataBits); + mSerialConsole.Uart.Parity = PcdGet8 (PcdUartDefaultParity); + mSerialConsole.Uart.StopBits = PcdGet8 (PcdUartDefaultStopBits); + + CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid); + + EfiBootManagerUpdateConsoleVariable ( + ConIn, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + EfiBootManagerUpdateConsoleVariable ( + ConOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + EfiBootManagerUpdateConsoleVariable ( + ErrOut, + (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, + NULL + ); + + // + // Register platform-specific boot options and keyboard shortcuts. + // + PlatformRegisterOptionsAndKeys (); +} + +STATIC +VOID +HandleCapsules ( + VOID + ) +{ + ESRT_MANAGEMENT_PROTOCOL *EsrtManagement; + EFI_PEI_HOB_POINTERS HobPointer; + EFI_CAPSULE_HEADER *CapsuleHeader; + BOOLEAN NeedReset; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a: processing capsules ...\n", __FUNCTION__)); + + Status = gBS->LocateProtocol ( + &gEsrtManagementProtocolGuid, + NULL, + (VOID **)&EsrtManagement + ); + if (!EFI_ERROR (Status)) { + EsrtManagement->SyncEsrtFmp (); + } + + // + // Find all capsule images from hob + // + HobPointer.Raw = GetHobList (); + NeedReset = FALSE; + while ((HobPointer.Raw = GetNextHob ( + EFI_HOB_TYPE_UEFI_CAPSULE, + HobPointer.Raw + )) != NULL) + { + CapsuleHeader = (VOID *)(UINTN)HobPointer.Capsule->BaseAddress; + + Status = ProcessCapsuleImage (CapsuleHeader); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "%a: failed to process capsule %p - %r\n", + __FUNCTION__, + CapsuleHeader, + Status + )); + return; + } + + NeedReset = TRUE; + HobPointer.Raw = GET_NEXT_HOB (HobPointer); + } + + if (NeedReset) { + DEBUG (( + DEBUG_WARN, + "%a: capsule update successful, resetting ...\n", + __FUNCTION__ + )); + + gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL); + CpuDeadLoop (); + } +} + +#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version " + +/** + This functions checks the value of BootDiscoverPolicy variable and + connect devices of class specified by that variable. Then it refreshes + Boot order for newly discovered boot device. + + @retval EFI_SUCCESS Devices connected successfully or connection + not required. + @retval others Return values from GetVariable(), LocateProtocol() + and ConnectDeviceClass(). +**/ +STATIC +EFI_STATUS +BootDiscoveryPolicyHandler ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 DiscoveryPolicy; + UINT32 DiscoveryPolicyOld; + UINTN Size; + EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy; + EFI_GUID *Class; + + Size = sizeof (DiscoveryPolicy); + Status = gRT->GetVariable ( + BOOT_DISCOVERY_POLICY_VAR, + &gBootDiscoveryPolicyMgrFormsetGuid, + NULL, + &Size, + &DiscoveryPolicy + ); + if (Status == EFI_NOT_FOUND) { + DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy); + Status = PcdSet32S (PcdBootDiscoveryPolicy, DiscoveryPolicy); + if (Status == EFI_NOT_FOUND) { + return EFI_SUCCESS; + } else if (EFI_ERROR (Status)) { + return Status; + } + } else if (EFI_ERROR (Status)) { + return Status; + } + + if (DiscoveryPolicy == BDP_CONNECT_MINIMAL) { + return EFI_SUCCESS; + } + + switch (DiscoveryPolicy) { + case BDP_CONNECT_NET: + Class = &gEfiBootManagerPolicyNetworkGuid; + break; + case BDP_CONNECT_ALL: + Class = &gEfiBootManagerPolicyConnectAllGuid; + break; + default: + DEBUG (( + DEBUG_INFO, + "%a - Unexpected DiscoveryPolicy (0x%x). Run Minimal Discovery Policy\n", + __FUNCTION__, + DiscoveryPolicy + )); + return EFI_SUCCESS; + } + + Status = gBS->LocateProtocol ( + &gEfiBootManagerPolicyProtocolGuid, + NULL, + (VOID **)&BMPolicy + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid." + "Driver connect will be skipped.\n", + __FUNCTION__ + )); + return Status; + } + + Status = BMPolicy->ConnectDeviceClass (BMPolicy, Class); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a - ConnectDeviceClass returns - %r\n", __FUNCTION__, Status)); + return Status; + } + + // + // Refresh Boot Options if Boot Discovery Policy has been changed + // + Size = sizeof (DiscoveryPolicyOld); + Status = gRT->GetVariable ( + BOOT_DISCOVERY_POLICY_OLD_VAR, + &gBootDiscoveryPolicyMgrFormsetGuid, + NULL, + &Size, + &DiscoveryPolicyOld + ); + if ((Status == EFI_NOT_FOUND) || (DiscoveryPolicyOld != DiscoveryPolicy)) { + EfiBootManagerRefreshAllBootOption (); + + Status = gRT->SetVariable ( + BOOT_DISCOVERY_POLICY_OLD_VAR, + &gBootDiscoveryPolicyMgrFormsetGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof (DiscoveryPolicyOld), + &DiscoveryPolicy + ); + } + + return EFI_SUCCESS; +} + +/** + Do the platform specific action after the console is ready + Possible things that can be done in PlatformBootManagerAfterConsole: + > Console post action: + > Dynamically switch output mode from 100x31 to 80x25 for certain scenario + > Signal console ready platform customized event + > Run diagnostics like memory testing + > Connect certain devices + > Dispatch additional option roms + > Special boot: e.g.: USB boot, enter UI +**/ +VOID +EFIAPI +PlatformBootManagerAfterConsole ( + VOID + ) +{ + EFI_STATUS Status; + EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput; + UINTN FirmwareVerLength; + UINTN PosX; + UINTN PosY; + EFI_INPUT_KEY Key; + + EfiEventGroupSignal (&gRockchipEventPlatformBmAfterConsoleGuid); + + FirmwareVerLength = StrLen (PcdGetPtr (PcdFirmwareVersionString)); + + // + // Show the splash screen. + // + Status = BootLogoEnableLogo (); + if (EFI_ERROR (Status)) { + if (FirmwareVerLength > 0) { + Print ( + VERSION_STRING_PREFIX L"%s\n", + PcdGetPtr (PcdFirmwareVersionString) + ); + } + Print (L"Press ESCAPE for boot options"); + } else if (FirmwareVerLength > 0) { + Status = gBS->HandleProtocol ( + gST->ConsoleOutHandle, + &gEfiGraphicsOutputProtocolGuid, + (VOID **)&GraphicsOutput + ); + if (!EFI_ERROR (Status)) { + PosX = (GraphicsOutput->Mode->Info->HorizontalResolution - + (StrLen (VERSION_STRING_PREFIX) + FirmwareVerLength) * + EFI_GLYPH_WIDTH) / 2; + PosY = 0; + + PrintXY ( + PosX, + PosY, + NULL, + NULL, + VERSION_STRING_PREFIX L"%s", + PcdGetPtr (PcdFirmwareVersionString) + ); + } + } + + // + // Connect device specified by BootDiscoverPolicy variable and + // refresh Boot order for newly discovered boot devices + // + BootDiscoveryPolicyHandler (); + + // + // On ARM, there is currently no reason to use the phased capsule + // update approach where some capsules are dispatched before EndOfDxe + // and some are dispatched after. So just handle all capsules here, + // when the console is up and we can actually give the user some + // feedback about what is going on. + // + HandleCapsules (); + + // + // Register UEFI Shell + // + Key.ScanCode = SCAN_NULL; + Key.UnicodeChar = L's'; + PlatformRegisterFvBootOption (&gUefiShellFileGuid, L"UEFI Shell", 0, &Key); + + RemoveStaleFvFileOptions (); +} + +/** + This function is called each second during the boot manager waits the + timeout. + + @param TimeoutRemain The remaining timeout. +**/ +VOID +EFIAPI +PlatformBootManagerWaitCallback ( + UINT16 TimeoutRemain + ) +{ + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White; + UINT16 Timeout; + EFI_STATUS Status; + + Timeout = PcdGet16 (PcdPlatformBootTimeOut); + + Black.Raw = 0x00000000; + White.Raw = 0x00FFFFFF; + + Status = BootLogoUpdateProgress ( + White.Pixel, + Black.Pixel, + L"Press ESCAPE for boot options", + White.Pixel, + (Timeout - TimeoutRemain) * 100 / Timeout, + 0 + ); + if (EFI_ERROR (Status)) { + Print (L"."); + } +} + +/** + The function is called when no boot option could be launched, + including platform recovery options and options pointing to applications + built into firmware volumes. + + If this function returns, BDS attempts to enter an infinite loop. +**/ +VOID +EFIAPI +PlatformBootManagerUnableToBoot ( + VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN OldBootOptionCount; + UINTN NewBootOptionCount; + + // + // Record the total number of boot configured boot options + // + BootOptions = EfiBootManagerGetLoadOptions ( + &OldBootOptionCount, + LoadOptionTypeBoot + ); + EfiBootManagerFreeLoadOptions (BootOptions, OldBootOptionCount); + + // + // Connect all devices, and regenerate all boot options + // + EfiBootManagerConnectAll (); + EfiBootManagerRefreshAllBootOption (); + + // + // Record the updated number of boot configured boot options + // + BootOptions = EfiBootManagerGetLoadOptions ( + &NewBootOptionCount, + LoadOptionTypeBoot + ); + EfiBootManagerFreeLoadOptions (BootOptions, NewBootOptionCount); + + // + // If the number of configured boot options has changed, reboot + // the system so the new boot options will be taken into account + // while executing the ordinary BDS bootflow sequence. + // *Unless* persistent varstore is being emulated, since we would + // then end up in an endless reboot loop. + // + if (!PcdGetBool (PcdEmuVariableNvModeEnable)) { + if (NewBootOptionCount != OldBootOptionCount) { + DEBUG (( + DEBUG_WARN, + "%a: rebooting after refreshing all boot options\n", + __FUNCTION__ + )); + gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL); + } + } + + Status = EfiBootManagerGetBootManagerMenu (&BootManagerMenu); + if (EFI_ERROR (Status)) { + return; + } + + for ( ; ;) { + EfiBootManagerBoot (&BootManagerMenu); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBm.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBm.h new file mode 100644 index 0000000..a40a2ff --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBm.h @@ -0,0 +1,53 @@ +/** @file + Head file for BDS Platform specific code + + Copyright (C) 2015-2016, Red Hat, Inc. + Copyright (c) 2004 - 2008, Intel Corporation. All rights reserved.
    + Copyright (c) 2016, Linaro Ltd. All rights reserved.
    + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PLATFORM_BM_H_ +#define PLATFORM_BM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Use SystemTable Conout to stop video based Simple Text Out consoles from + going to the video device. Put up LogoFile on every video device that is a + console. + + @param[in] LogoFile File name of logo to display on the center of the + screen. + + @retval EFI_SUCCESS ConsoleControl has been flipped to graphics and logo + displayed. + @retval EFI_UNSUPPORTED Logo not found +**/ +EFI_STATUS +EnableQuietBoot ( + IN EFI_GUID *LogoFile + ); + +/** + Use SystemTable Conout to turn on video based Simple Text Out consoles. The + Simple Text Out screens will now be synced up with all non video output + devices + + @retval EFI_SUCCESS UGA devices are back in text mode and synced up. +**/ +EFI_STATUS +DisableQuietBoot ( + VOID + ); + +#endif // PLATFORM_BM_H_ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf new file mode 100644 index 0000000..deab399 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf @@ -0,0 +1,100 @@ +## @file +# Implementation for PlatformBootManagerLib library class interfaces. +# +# Copyright (C) 2015-2016, Red Hat, Inc. +# Copyright (c) 2014, ARM Ltd. All rights reserved.
    +# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.
    +# Copyright (c) 2016, Linaro Ltd. All rights reserved.
    +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformBootManagerLib + FILE_GUID = 92FD2DE3-B9CB-4B35-8141-42AD34D73C9F + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = ARM AARCH64 +# + +[Sources] + PlatformBm.c + PlatformBm.h + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + ShellPkg/ShellPkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + BootLogoLib + CapsuleLib + DebugLib + DevicePathLib + DxeServicesLib + HobLib + MemoryAllocationLib + PcdLib + PrintLib + UefiBootManagerLib + UefiBootServicesTableLib + UefiLib + UefiRuntimeServicesTableLib + RkAtagsLib + +[FeaturePcd] + gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits + gEfiMdeModulePkgTokenSpaceGuid.PcdBootDiscoveryPolicy + gRockchipTokenSpaceGuid.PcdDwcSdhciBaseAddress + gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress + +[Guids] + gBootDiscoveryPolicyMgrFormsetGuid + gEdkiiNonDiscoverableEhciDeviceGuid + gEdkiiNonDiscoverableUhciDeviceGuid + gEdkiiNonDiscoverableXhciDeviceGuid + gEfiBootManagerPolicyNetworkGuid + gEfiBootManagerPolicyConnectAllGuid + gEfiFileInfoGuid + gEfiFileSystemInfoGuid + gEfiFileSystemVolumeLabelInfoIdGuid + gEfiEndOfDxeEventGroupGuid + gEfiTtyTermGuid + gUefiShellFileGuid + gRockchipEventPlatformBmAfterConsoleGuid + +[Protocols] + gEdkiiNonDiscoverableDeviceProtocolGuid + gEfiBootManagerPolicyProtocolGuid + gEfiDevicePathProtocolGuid + gEfiGraphicsOutputProtocolGuid + gEfiLoadedImageProtocolGuid + gEfiPciRootBridgeIoProtocolGuid + gEfiSimpleFileSystemProtocolGuid + gEfiBlockIoProtocolGuid + gEsrtManagementProtocolGuid + gPlatformBootManagerProtocolGuid + gOhciDeviceProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c new file mode 100644 index 0000000..9f29ae7 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.c @@ -0,0 +1,172 @@ +/** @file + Platform Flash Access library. + + Copyright (c) 2018, Hisilicon Limited. All rights reserved. + Copyright (c) 2018, Linaro Limited. All rights reserved. + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
    + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress; +STATIC EFI_PHYSICAL_ADDRESS mSFCMEM0BaseAddress; + +STATIC UNI_NOR_FLASH_PROTOCOL *mSpiProtocol; + +/** + Perform flash write operation with progress indicator. The start and end + completion percentage values are passed into this function. If the requested + flash write operation is broken up, then completion percentage between the + start and end values may be passed to the provided Progress function. The + caller of this function is required to call the Progress function for the + start and end completion percentage values. This allows the Progress, + StartPercentage, and EndPercentage parameters to be ignored if the requested + flash write operation can not be broken up + + @param[in] FirmwareType The type of firmware. + @param[in] FlashAddress The address of flash device to be accessed. + @param[in] FlashAddressType The type of flash device address. + @param[in] Buffer The pointer to the data buffer. + @param[in] Length The length of data buffer in bytes. + @param[in] Progress A function used report the progress of the + firmware update. This is an optional parameter + that may be NULL. + @param[in] StartPercentage The start completion percentage value that may + be used to report progress during the flash + write operation. + @param[in] EndPercentage The end completion percentage value that may + be used to report progress during the flash + write operation. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS +EFIAPI +PerformFlashWriteWithProgress ( + IN PLATFORM_FIRMWARE_TYPE FirmwareType, + IN EFI_PHYSICAL_ADDRESS FlashAddress, + IN FLASH_ADDRESS_TYPE FlashAddressType, + IN VOID *Buffer, + IN UINTN Length, + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, OPTIONAL + IN UINTN StartPercentage, + IN UINTN EndPercentage + ) +{ + UINT32 RomAddress; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, + "PerformFlashWrite - 0x%x(%x) - 0x%x\n", + (UINTN)FlashAddress, + (UINTN)FlashAddressType, + Length)); + + if (FlashAddressType == FlashAddressTypeAbsoluteAddress) { + FlashAddress = FlashAddress - mInternalFdAddress; + } + + RomAddress = (UINT32)FlashAddress + (mInternalFdAddress - mSFCMEM0BaseAddress); + + DEBUG ((DEBUG_INFO, "Erase and Write Flash Start\n")) + + Status = mSpiProtocol->Update ( + mSpiProtocol, + (UINT32) RomAddress, + (UINT8 *)Buffer, + (UINT32) Length + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Erase and Write Status = %r \n", Status)); + } + + return Status; +} + +/** + Perform flash write operation. + + @param[in] FirmwareType The type of firmware. + @param[in] FlashAddress The address of flash device to be accessed. + @param[in] FlashAddressType The type of flash device address. + @param[in] Buffer The pointer to the data buffer. + @param[in] Length The length of data buffer in bytes. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS +EFIAPI +PerformFlashWrite ( + IN PLATFORM_FIRMWARE_TYPE FirmwareType, + IN EFI_PHYSICAL_ADDRESS FlashAddress, + IN FLASH_ADDRESS_TYPE FlashAddressType, + IN VOID *Buffer, + IN UINTN Length + ) +{ + return PerformFlashWriteWithProgress ( + FirmwareType, + FlashAddress, + FlashAddressType, + Buffer, + Length, + NULL, + 0, + 0 + ); +} + +/** + Platform Flash Access Lib Constructor. + + @param[in] ImageHandle The firmware allocated handle for the EFI image. + @param[in] SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS Constructor returns successfully. +**/ +EFI_STATUS +EFIAPI +PerformFlashAccessLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mInternalFdAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdFdBaseAddress); + + mSFCMEM0BaseAddress = (EFI_PHYSICAL_ADDRESS) PcdGet64 (PcdSFCMEM0BaseAddress); + + DEBUG ((DEBUG_INFO, + "PcdFlashAreaBaseAddress - 0x%x, PcdSFCMEM0BaseAddress - 0x%x \n", + mInternalFdAddress, + mSFCMEM0BaseAddress)); + + Status = gBS->LocateProtocol ( + &gUniNorFlashProtocolGuid, + NULL, + (VOID **)&mSpiProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "LocateProtocol gUniNorFlashProtocolGuid Status = %r \n", + Status)); + } + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf new file mode 100644 index 0000000..9e2f265 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf @@ -0,0 +1,45 @@ +## @file +# Platform Flash Access library. +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# Copyright (c) 2016, Intel Corporation. All rights reserved.
    +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformFlashAccessLibDxe + FILE_GUID = a6f6d6ea-3177-11ec-95b4-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformFlashAccessLib|DXE_DRIVER + CONSTRUCTOR = PerformFlashAccessLibConstructor + +[Sources] + PlatformFlashAccessLibDxe.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + SignedCapsulePkg/SignedCapsulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + PcdLib + UefiBootServicesTableLib + +[Protocols] + gUniNorFlashProtocolGuid + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gRockchipTokenSpaceGuid.PcdSFCMEM0BaseAddress + +[Depex] + gUniNorFlashProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 0000000..ec4c939 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,164 @@ +/** @file + ResetSystemLib implementation for RK35xx platform + + Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved. + Copyright (c) 2019, Intel Corporation. All rights reserved. + Copyright (c) 2022, Xilin Wu + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +STATIC +VOID +SignalResetEvent ( + VOID + ) +{ + if (!EfiAtRuntime ()) { + EfiEventGroupSignal (&gRockchipEventResetGuid); + } +} + +/** + This function causes a system-wide initialization (warm reset), in which all processors + are set to their initial state. Pending cycles are not corrupted. + + If this function returns, it means that the system does not support warm reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + SignalResetEvent (); + + // RK3588-specific! + // Should be moved into a lib if SoC abstraction is needed. + + // First global software reset by programming CRU_GLB_SRST_FST as 0xfdb9 + MmioWrite32 (0xFD7C0C08, 0xfdb9); +} + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + ARM_SMC_ARGS ArmSmcArgs; + + SignalResetEvent (); + + // Send a PSCI 0.2 SYSTEM_RESET command + ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET; + ArmCallSmc (&ArmSmcArgs); +} + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shutdown reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + ARM_SMC_ARGS ArmSmcArgs; + + SignalResetEvent (); + + // Send a PSCI 0.2 SYSTEM_OFF command + ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF; + ArmCallSmc (&ArmSmcArgs); +} + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string passed + into ResetData. If the platform does not recognize the EFI_GUID in ResetData + the platform must pick a supported reset type to perform.The platform may + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated string, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ) +{ + SignalResetEvent (); + + ResetCold(); +} + +/** + The ResetSystem function resets the entire platform. + + @param[in] ResetType The type of reset to perform. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown + the data buffer starts with a Null-terminated string, optionally + followed by additional binary data. The string is a description + that the caller may use to further indicate the reason for the + system reset. +**/ +VOID +EFIAPI +ResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + return; + + case EfiResetPlatformSpecific: + ResetPlatformSpecific (DataSize, ResetData); + return; + + default: + return; + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 0000000..524f349 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,35 @@ +#/** @file +# ResetSystemLib implementation for RK35xx platform +# +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
    +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = ResetSystemLib + FILE_GUID = 18B12C83-7718-4D83-ADA4-87F2FE698DD4 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ResetSystemLib + +[Sources] + ResetSystemLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmSmcLib + BaseLib + DebugLib + UefiLib + UefiRuntimeLib + +[Guids] + gRockchipEventResetGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkAtagsLib/RkAtagsLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkAtagsLib/RkAtagsLib.c new file mode 100644 index 0000000..d7f1da1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkAtagsLib/RkAtagsLib.c @@ -0,0 +1,213 @@ +/** @file + * + * Rockchip ATAGS library. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include + +#define ATAGS_BASE 0x1FE000 +#define ATAGS_SIZE 0x2000 + +#define ATAG_SIZE_BYTES(Size) (Size * 4) + +#define ATAG_ID_HASH 0x47C6A7E6 +#define ATAG_HASH_LENGTH sizeof (UINT32) + +typedef enum { + RkAtagTypeNone = 0x00000000, + RkAtagTypeCore = 0x54410001, + RkAtagTypeSerial = 0x54410050, + RkAtagTypeBootDev = 0x54410051, + RkAtagTypeDdrMem = 0x54410052, + RkAtagTypeTosMem = 0x54410053, + RkAtagTypeRamPartition = 0x54410054, + RkAtagTypeAtfMem = 0x54410055, + RkAtagTypePubKey = 0x54410056, + RkAtagTypeSocInfo = 0x54410057, + RkAtagTypeBoot1Param = 0x54410058, + RkAtagTypeMax = 0x544100ff +} RKATAG_TYPE; + +#pragma pack(1) + +typedef struct { + UINT32 Flags; + UINT32 Pagesize; + UINT32 RootDev; +} RKATAG_CORE; + +typedef struct { + UINT32 Size; + RKATAG_TYPE Type; +} RKATAG_HEADER; + +#pragma pack() + +STATIC +UINT32 +ComputeHash ( + IN VOID *Buffer, + IN UINT32 Length + ) +{ + UINT32 Index; + UINT32 Hash; + UINT8 *Data; + + Hash = ATAG_ID_HASH; + Data = Buffer; + + if (Data == NULL) { + return Hash; + } + + for (Index = 0; Index < Length; Index++) { + Hash ^= ((Hash << 5) + Data[Index] + (Hash >> 2)); + } + + return Hash; +} + +STATIC +VOID * +RkAtagsGetTagBuffer ( + IN RKATAG_TYPE Type + ) +{ + VOID *TagBuffer; + RKATAG_HEADER *TagHeader; + UINT32 TagHashOffset; + UINT32 *TagHash; + UINT32 ComputedTagHash; + + TagBuffer = (VOID *) ATAGS_BASE; + TagHeader = (RKATAG_HEADER *) TagBuffer; + + if (TagHeader->Type != RkAtagTypeCore) { + DEBUG ((DEBUG_ERROR, "%a: ATAGS not initialized!\n", + __FUNCTION__)); + return NULL; + } + + if (Type <= RkAtagTypeCore || Type > RkAtagTypeMax) { + DEBUG ((DEBUG_ERROR, "%a: Type=%x unsupported!\n", + __FUNCTION__, Type)); + return NULL; + } + + while (TagHeader->Size > 0) { + if ((UINTN)TagBuffer + ATAG_SIZE_BYTES(TagHeader->Size) - ATAGS_BASE > ATAGS_SIZE) { + DEBUG ((DEBUG_ERROR, "%a: Type=%x overflown!\n", + __FUNCTION__, TagHeader->Type)); + return NULL; + } + + if (TagHeader->Type == Type) { + TagHashOffset = ATAG_SIZE_BYTES(TagHeader->Size) - ATAG_HASH_LENGTH; + TagHash = (UINT32 *)(TagBuffer + TagHashOffset); + + if (*TagHash == 0) { + DEBUG ((DEBUG_WARN, "%a: Tag hash missing! Type=%x. Ignoring.\n", + __FUNCTION__, TagHeader->Type)); + return TagBuffer + sizeof (RKATAG_HEADER); + } + + ComputedTagHash = ComputeHash(TagBuffer, TagHashOffset); + + if (ComputedTagHash != *TagHash) { + DEBUG ((DEBUG_ERROR, "%a: Corrupted tag hash! Type=%x, TagHash=%x, ComputedTagHash=%x\n", + __FUNCTION__, TagHeader->Type, *TagHash, ComputedTagHash)); + return NULL; + } + + return TagBuffer + sizeof (RKATAG_HEADER); + } + + TagBuffer = (VOID *)((UINT32 *) TagBuffer + TagHeader->Size); + TagHeader = (RKATAG_HEADER *) TagBuffer; + } + + DEBUG ((DEBUG_ERROR, "%a: Tag not found! Type=%x.\n", + __FUNCTION__, Type)); + return NULL; +} + +RKATAG_SERIAL * +RkAtagsGetSerial ( + VOID + ) +{ + return (RKATAG_SERIAL *) RkAtagsGetTagBuffer (RkAtagTypeSerial); +} + +RKATAG_BOOTDEV * +RkAtagsGetBootDev ( + VOID + ) +{ + return (RKATAG_BOOTDEV *) RkAtagsGetTagBuffer (RkAtagTypeBootDev); +} + +RKATAG_DDR_MEM * +RkAtagsGetDdrMem ( + VOID + ) +{ + return (RKATAG_DDR_MEM *) RkAtagsGetTagBuffer (RkAtagTypeDdrMem); +} + +RKATAG_TOS_MEM * +RkAtagsGetTosMem ( + VOID + ) +{ + return (RKATAG_TOS_MEM *) RkAtagsGetTagBuffer (RkAtagTypeTosMem); +} + +RKATAG_RAM_PARTITION * +RkAtagsGetRamPartition ( + VOID + ) +{ + return (RKATAG_RAM_PARTITION *) RkAtagsGetTagBuffer (RkAtagTypeRamPartition); +} + +RKATAG_ATF_MEM * +RkAtagsGetAtfMem ( + VOID + ) +{ + return (RKATAG_ATF_MEM *) RkAtagsGetTagBuffer (RkAtagTypeAtfMem); +} + +RKATAG_PUB_KEY * +RkAtagsGetPubKey ( + VOID + ) +{ + return (RKATAG_PUB_KEY *) RkAtagsGetTagBuffer (RkAtagTypePubKey); +} + +RKATAG_SOC_INFO * +RkAtagsGetSocInfo ( + VOID + ) +{ + return (RKATAG_SOC_INFO *) RkAtagsGetTagBuffer (RkAtagTypeSocInfo); +} + +RKATAG_BOOT1_PARAM * +RkAtagsGetBoot1Param ( + VOID + ) +{ + return (RKATAG_BOOT1_PARAM *) RkAtagsGetTagBuffer (RkAtagTypeBoot1Param); +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkAtagsLib/RkAtagsLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkAtagsLib/RkAtagsLib.inf new file mode 100644 index 0000000..204ac57 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkAtagsLib/RkAtagsLib.inf @@ -0,0 +1,28 @@ +#/** @file +# +# Rockchip ATAGS library. +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = RkAtagsLib + FILE_GUID = EEA8B68F-1262-44D6-9D89-2AE700B969F3 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RkAtagsLib + +[Sources] + RkAtagsLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + BaseLib + DebugLib diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.c new file mode 100644 index 0000000..cd9664a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.c @@ -0,0 +1,197 @@ +/** @file + + Copyright (c) 2021, Jared McNeill + Copyright (c) 2017-2018, Arm Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "RkMtlPrivateLib.h" + +// Shared mailbox +STATIC CONST MTL_CHANNEL Channels[NUM_CHANNELS] = { + { + MTL_CHANNEL_TYPE_LOW, + (MTL_MAILBOX*)(MTL_MAILBOX_BASE) + }, + }; + +/** Wait until channel is free. + + @param[in] Channel Pointer to a channel. + @param[in] TimeOutInMicroSeconds Time out in micro seconds. + + @retval EFI_SUCCESS Channel is free. + @retval EFI_TIMEOUT Time out error. +**/ +EFI_STATUS +MtlWaitUntilChannelFree ( + IN MTL_CHANNEL *Channel, + IN UINTN TimeOutInMicroSeconds + ) +{ + while (TimeOutInMicroSeconds != 0) { + ArmDataSynchronizationBarrier (); + + // If channel is free then we have received the reply. + if (Channel->MailBox->ChannelStatus == MTL_CHANNEL_FREE) { + return EFI_SUCCESS; + } + if (TimeOutInMicroSeconds < MTL_POLL_WAIT_TIME) { + gBS->Stall (TimeOutInMicroSeconds); + break; + } + // Wait for some arbitrary time. + gBS->Stall (MTL_POLL_WAIT_TIME); + TimeOutInMicroSeconds -= MTL_POLL_WAIT_TIME; + } + + // No response from SCP. + if (Channel->MailBox->ChannelStatus != MTL_CHANNEL_FREE) { + ASSERT (FALSE); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +/** Return the address of the message payload. + + @param[in] Channel Pointer to a channel. + + @retval UINT32* Pointer to the payload. +**/ +UINT32* +MtlGetChannelPayload ( + IN MTL_CHANNEL *Channel + ) +{ + return Channel->MailBox->Payload; +} + +/** Return pointer to a channel for the requested channel type. + + @param[in] ChannelType ChannelType, only supports Low priority channel. + MTL_CHANNEL_TYPE_LOW + + @param[out] Channel Holds pointer to the channel. + + @retval EFI_SUCCESS Pointer to channel is returned. + @retval EFI_UNSUPPORTED Requested channel type not supported. +**/ +EFI_STATUS +MtlGetChannel ( + IN MTL_CHANNEL_TYPE ChannelType, + OUT MTL_CHANNEL **Channel + ) +{ + if (ChannelType != MTL_CHANNEL_TYPE_LOW) { + return EFI_UNSUPPORTED; + } + + *Channel = (MTL_CHANNEL*)&Channels[ChannelType]; + + return EFI_SUCCESS; +} + +/** Mark the channel busy and ring the doorbell. + + @param[in] Channel Pointer to a channel. + @param[in] MessageHeader Message header. + + @param[out] PayloadLength Message length. + + @retval EFI_SUCCESS Message sent successfully. + @retval EFI_DEVICE_ERROR Channel is busy. +**/ +EFI_STATUS +MtlSendMessage ( + IN MTL_CHANNEL *Channel, + IN UINT32 MessageHeader, + OUT UINT32 PayloadLength + ) +{ + MTL_MAILBOX *MailBox = Channel->MailBox; + ARM_SMC_ARGS SmcRegs = {0}; + + ArmDataSynchronizationBarrier (); + if (Channel->MailBox->ChannelStatus != MTL_CHANNEL_FREE) { + DEBUG ((DEBUG_WARN, "Mailbox is busy\n")); + return EFI_DEVICE_ERROR; + } + + // Mark the channel busy before ringing doorbell. + Channel->MailBox->ChannelStatus = MTL_CHANNEL_BUSY; + ArmDataSynchronizationBarrier (); + + MailBox->Flags = MTL_POLL; + MailBox->MessageHeader = MessageHeader; + + // Add length of message header. + MailBox->Length = PayloadLength + sizeof (MessageHeader); + + ArmDataSynchronizationBarrier (); + + DEBUG ((DEBUG_INFO, "MtlSendMessage ringing doorbell 0x%08X with message header 0x%08X length 0x%08X\n", + FixedPcdGet32 (PcdRkMtlMailBoxSmcId), MailBox->MessageHeader, MailBox->Length)); + + // Ring the doorbell. + SmcRegs.Arg0 = FixedPcdGet32 (PcdRkMtlMailBoxSmcId); + ArmCallSmc (&SmcRegs); + + if (SmcRegs.Arg0 != 0) { + DEBUG ((DEBUG_WARN, "SMC doorbell call failed: 0x%lX\n", FixedPcdGet32 (PcdRkMtlMailBoxSmcId), SmcRegs.Arg0)); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** Wait for a response on a channel. + + If channel is free after sending message, it implies SCP responded + with a response on the channel. + + @param[in] Channel Pointer to a channel. + + @retval EFI_SUCCESS Message received successfully. + @retval EFI_TIMEOUT Time out error. +**/ +EFI_STATUS +MtlReceiveMessage ( + IN MTL_CHANNEL *Channel, + OUT UINT32 *MessageHeader, + OUT UINT32 *PayloadLength + ) +{ + EFI_STATUS Status; + + MTL_MAILBOX *MailBox = Channel->MailBox; + + Status = MtlWaitUntilChannelFree (Channel, RESPONSE_TIMEOUT); + if (EFI_ERROR (Status)) { + return Status; + } + + *MessageHeader = MailBox->MessageHeader; + + // Deduct message header length. + *PayloadLength = MailBox->Length - sizeof (*MessageHeader); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf new file mode 100644 index 0000000..a8c66c5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf @@ -0,0 +1,35 @@ +#/** @file +# Copyright (c) 2021, Jared McNeill +# Copyright (c) 2017-2018, Arm Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = RkMtlLib + FILE_GUID = 8C4393C9-3012-4862-A19C-259477D6F518 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmMtlLib + +[Sources.common] + RkMtlLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + ArmSmcLib + DebugLib + IoLib + UefiBootServicesTableLib + +[FixedPcd.common] + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSmcId \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlPrivateLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlPrivateLib.h new file mode 100644 index 0000000..49e75a4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/RkMtlPrivateLib.h @@ -0,0 +1,33 @@ +/** @file + + Copyright (c) 2017-2018, Arm Limited. All rights reserved. + Copyright (c) 2021, Jared McNeill + + SPDX-License-Identifier: BSD-2-Clause-Patent + + System Control and Management Interface V1.0 + http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/ + DEN0056A_System_Control_and_Management_Interface.pdf +**/ + +#ifndef RK_MTL_PRIVATE_LIB_H_ +#define RK_MTL_PRIVATE_LIB_H_ + +// Mailbox transport layer. +#define MTL_MAILBOX_BASE (FixedPcdGet64 (PcdRkMtlMailBoxBase)) +#define MTL_MAILBOX_SIZE (FixedPcdGet32 (PcdRkMtlMailBoxSize)) + +#define MTL_POLL 0 + +#define MTL_CHANNEL_BUSY 0 +#define MTL_CHANNEL_FREE 1 + +// Response time out value on a channel 1s. +#define RESPONSE_TIMEOUT 1000000 +#define NUM_CHANNELS 1 + +// Arbitarary poll time. +#define MTL_POLL_WAIT_TIME 100000 + +#endif /* RK_MTL_PRIVATE_LIB_H_ */ + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/source.txt b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/source.txt new file mode 100644 index 0000000..8b97dec --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkMtlLib/source.txt @@ -0,0 +1 @@ +Source: https://github.com/jaredmcneill/quartz64_uefi diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkSdmmcPlatformLibNull/RkSdmmcPlatformLibNull.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkSdmmcPlatformLibNull/RkSdmmcPlatformLibNull.c new file mode 100644 index 0000000..c35f80a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkSdmmcPlatformLibNull/RkSdmmcPlatformLibNull.c @@ -0,0 +1,39 @@ +/** @file + * + * RkSdmmcDxe platform helper library. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include + +EFI_STATUS +EFIAPI +RkSdmmcSetClockRate ( + IN UINTN Frequency + ) +{ + return EFI_UNSUPPORTED; +} + +VOID +EFIAPI +RkSdmmcSetIoMux ( + VOID + ) +{ + return; +} + +RKSDMMC_CARD_PRESENCE_STATE +EFIAPI +RkSdmmcGetCardPresenceState ( + VOID + ) +{ + return RkSdmmcCardPresenceUnsupported; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkSdmmcPlatformLibNull/RkSdmmcPlatformLibNull.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkSdmmcPlatformLibNull/RkSdmmcPlatformLibNull.inf new file mode 100644 index 0000000..0cf0702 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/RkSdmmcPlatformLibNull/RkSdmmcPlatformLibNull.inf @@ -0,0 +1,24 @@ +#/** @file +# +# RkSdmmcDxe platform helper library. +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = RkSdmmcPlatformLibNull + FILE_GUID = 3e414bfa-0637-4e2a-a272-eb3767cc5061 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RkSdmmcPlatformLib + +[Sources] + RkSdmmcPlatformLibNull.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SdramLib/SdramLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SdramLib/SdramLib.c new file mode 100644 index 0000000..a9a88c2 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SdramLib/SdramLib.c @@ -0,0 +1,144 @@ +/** @file + * + * SDRAM size detection for Rockchip SoCs + * + * Copyright (c) 2022, Jared McNeill + * Copyright (c) 2023, Gábor Stefanik + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +// TODO convert these to PCDs +#define SDRAM_OS_REG_BASE 0xFD58A208 +#define SDRAM_BANK_COUNT 2 + +typedef enum { + SDRAM_DDR4 = 0, + SDRAM_DDR2 = 2, + SDRAM_DDR3 = 3, + SDRAM_LPDDR2 = 5, + SDRAM_LPDDR3 = 6, + SDRAM_LPDDR4 = 7, + SDRAM_LPDDR4X = 8, + SDRAM_LPDDR5 = 9, + SDRAM_DDR5 = 10 +} SDRAM_DDRTYPE; + +#define SYS_REG_DDRTYPE(x) (((x) >> 13) & 0x7) +#define SYS_REG_CHANNELNUM(x) (((x) >> 12) & 0x1) +#define SYS_REG_RANK_CH(x, c) (((x) >> ((c) ? 27 : 11)) & 0x1) +#define SYS_REG_COL_CH(x, c) (((x) >> ((c) ? 25 : 9)) & 0x3) +#define SYS_REG_BK_CH(x, c) (((x) >> ((c) ? 24 : 8)) & 0x1) +#define SYS_REG_CS0_ROW_CH_LO(x, c) (((x) >> ((c) ? 22 : 6)) & 0x3) +#define SYS_REG_CS1_ROW_CH_LO(x, c) (((x) >> ((c) ? 20 : 4)) & 0x3) +#define SYS_REG_BW_CH(x, c) (((x) >> ((c) ? 18 : 2)) & 0x3) +#define SYS_REG_ROW34_CH(x, c) (((x) >> ((c) ? 31 : 30)) & 0x1) +#define SYS_REG_DBW_CH(x, c) (((x) >> ((c) ? 16 : 0)) & 0x3) + +#define SYS_REG1_VERSION(x) (((x) >> 28) & 0xF) +#define SYS_REG1_CS0_ROW_CH_HI(x, c) (((x) >> ((c) ? 7 : 5)) & 0x1) +#define SYS_REG1_CS1_ROW_CH_HI(x, c) (((x) >> ((c) ? 6 : 4)) & 0x1) +#define SYS_REG1_CS1_COL_CH(x, c) (((x) >> ((c) ? 2 : 0)) & 0x3) +#define SYS_REG1_EXTENDED_DDRTYPE(x) (((x) >> 12) & 0x3) + +UINT64 +SdramGetMemorySize ( + VOID + ) +{ + UINT32 OsReg; + UINT32 OsReg1; + INT32 Bank; + INT32 ChNum; + INT32 Ch; + INT32 Rank; + INT32 Cs0Col, Cs1Col; + INT32 Cs0Row, Cs1Row; + INT32 Bk; + INT32 Bw; + INT32 Row34; + INT32 Bg; + INT32 ChSizeMb; + INT32 SizeMb = 0; + UINT32 Version; + UINT32 DdrType; + + for (Bank = 0; Bank < SDRAM_BANK_COUNT; Bank++) { + OsReg = MmioRead32 (SDRAM_OS_REG_BASE + 8 * Bank); + OsReg1 = MmioRead32 (SDRAM_OS_REG_BASE + 8 * Bank + 4); + + Version = SYS_REG1_VERSION(OsReg1); + + DdrType = SYS_REG_DDRTYPE(OsReg); + if (Version >= 3) { + DdrType |= SYS_REG1_EXTENDED_DDRTYPE(OsReg1) << 3; + } + + ChNum = 1 + SYS_REG_CHANNELNUM(OsReg); + + DEBUG ((DEBUG_INFO, "%a(): Bank #%d: %d channel(s), type 0x%X, version 0x%X\n", + __func__, Bank, ChNum, SYS_REG_DDRTYPE(OsReg), Version)); + + for (Ch = 0; Ch < ChNum; Ch++) { + Rank = 1 + SYS_REG_RANK_CH(OsReg, Ch); + Cs0Col = 9 + SYS_REG_COL_CH(OsReg, Ch); + Cs1Col = Cs0Col; + + if (DdrType == SDRAM_LPDDR5) { + Bk = 3 + SYS_REG_BK_CH(OsReg, Ch); + } else { + Bk = 3 - SYS_REG_BK_CH(OsReg, Ch); + } + + if (Version >= 0x2) { + Cs1Col = 9 + SYS_REG1_CS1_COL_CH(OsReg1, Ch); + if (((SYS_REG1_CS0_ROW_CH_HI(OsReg1, Ch) << 2) + + SYS_REG_CS0_ROW_CH_LO(OsReg, Ch)) == 7) { + Cs0Row = 12; + } else { + Cs0Row = 13 + (SYS_REG1_CS0_ROW_CH_HI(OsReg1, Ch) << 2) + + SYS_REG_CS0_ROW_CH_LO(OsReg, Ch); + } + if (((SYS_REG1_CS1_ROW_CH_HI(OsReg1, Ch) << 2) + + SYS_REG_CS1_ROW_CH_LO(OsReg, Ch)) == 7) { + Cs1Row = 12; + } else { + Cs1Row = 13 + (SYS_REG1_CS1_ROW_CH_HI(OsReg1, Ch) << 2) + + SYS_REG_CS1_ROW_CH_LO(OsReg, Ch); + } + } else { + Cs0Row = 13 + SYS_REG_CS0_ROW_CH_LO(OsReg, Ch); + Cs1Row = 13 + SYS_REG_CS1_ROW_CH_LO(OsReg, Ch); + } + Bw = 2 >> SYS_REG_BW_CH(OsReg, Ch); + Row34 = SYS_REG_ROW34_CH(OsReg, Ch); + if (DdrType == SDRAM_DDR4 && Version != 0x3) { + Bg = SYS_REG_DBW_CH(OsReg, Ch) == 2 ? 2 : 1; + } else { + Bg = 0; + } + + ChSizeMb = 1 << (Cs0Row + Cs0Col + Bk + Bg + Bw - 20); + if (Rank > 1) { + ChSizeMb += ChSizeMb >> ((Cs0Row - Cs1Row) + (Cs0Col - Cs1Col)); + } + if (Row34) { + ChSizeMb = ChSizeMb * 3 / 4; + } + + DEBUG ((DEBUG_INFO, "%a(): Ch #%d: %u MB\n", __func__, Ch + Bank * 2, ChSizeMb)); + SizeMb += ChSizeMb; + } + } + + DEBUG ((DEBUG_INFO, "%a(): Detected %u MB RAM\n", __func__, SizeMb)); + + ASSERT (SizeMb != 0); + + return (UINT64)SizeMb * 1024 * 1024; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SdramLib/SdramLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SdramLib/SdramLib.inf new file mode 100644 index 0000000..516be60 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SdramLib/SdramLib.inf @@ -0,0 +1,36 @@ +#/** @file +# +# Rockchip SDRAM Library. +# +# Copyright (c) 2022, Jared McNeill +# Copyright (c) 2023, Gábor Stefanik +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = SdramLib + FILE_GUID = F1722CDD-AB5E-4341-8E98-C04CA151D5FB + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SdramLib + +[Sources] + SdramLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + +[FixedPcd] + +[Guids] diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/RK806.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/RK806.c new file mode 100644 index 0000000..75567fa --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/RK806.c @@ -0,0 +1,611 @@ + +#include +#include "Soc.h" +#include +#include +#include +#include +#include +#if 0 +/* Not used or exisit register and configure */ +#define NA -1 +#define BIT(n) (1 << (n)) +#define RK806_DBG DEBUG_ERROR +/* rk806 buck*/ +#define RK806_BUCK_ON_VSEL(n) (0x1a + n - 1) +#define RK806_BUCK_SLP_VSEL(n) (0x24 + n - 1) +#define RK806_BUCK_CONFIG(n) (0x10 + n - 1) +#define RK806_BUCK_VSEL_MASK 0xff + +/* RK806 LDO */ +#define RK806_NLDO_ON_VSEL(n) (0x43 + n - 1) +#define RK806_NLDO_SLP_VSEL(n) (0x48 + n - 1) +#define RK806_NLDO_VSEL_MASK 0xff +#define RK806_PLDO_ON_VSEL(n) (0x4e + n - 1) +#define RK806_PLDO_SLP_VSEL(n) (0x54 + n - 1) +#define RK806_PLDO_VSEL_MASK 0xff + +/* RK806 ENABLE */ +#define RK806_POWER_EN(n) (0x00 + n) +#define RK806_NLDO_EN(n) (0x03 + n) +#define RK806_PLDO_EN(n) (0x04 + n) +#define RK806_RAMP_RATE_MASK1 0xc0 +#define RK806_RAMP_RATE_REG1(n) (0x10 + n) +#define RK806_RAMP_RATE_REG1_8 0xeb +#define RK806_RAMP_RATE_REG9_10 0xea + +#define RK806_RAMP_RATE_4LSB_PER_1CLK 0x00/* LDO 100mV/uS buck 50mV/us */ +#define RK806_RAMP_RATE_2LSB_PER_1CLK 0x01/* LDO 50mV/uS buck 25mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_1CLK 0x02/* LDO 25mV/uS buck 12.5mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_2CLK 0x03/* LDO 12.5mV/uS buck 6.25mV/us */ + +#define RK806_RAMP_RATE_1LSB_PER_4CLK 0x04/* LDO 6.28/2mV/uS buck 3.125mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_8CLK 0x05/* LDO 3.12mV/uS buck 1.56mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_13CLK 0x06/* LDO 1.9mV/uS buck 961mV/us */ +#define RK806_RAMP_RATE_1LSB_PER_32CLK 0x07/* LDO 0.78mV/uS buck 0.39mV/us */ + +#define RK806_PLDO0_2_MSK(pldo) (BIT(pldo + 5)) +#define RK806_PLDO0_2_SET(pldo) (BIT(pldo + 1) | RK806_PLDO0_2_MSK(pldo)) +#define RK806_PLDO0_2_CLR(pldo) RK806_PLDO0_2_MSK(pldo) + +#define RK806_CHIP_NAME 0x5A +#define RK806_CHIP_VER 0x5B + +#define RK806_CMD_READ 0 +#define RK806_CMD_WRITE BIT(7) +#define RK806_CMD_CRC_EN BIT(6) +#define RK806_CMD_CRC_DIS 0 +#define RK806_CMD_LEN_MSK 0x0f +#define RK806_REG_H 0x00 + +#define RK806_SYS_CFG1 0x5f +#define RK806_SYS_CFG3 0x72 +#define RK806_PWRON_KEY 0x76 +#define RK806_INT_STS0 0x77 +#define RK806_INT_MSK0 0x78 +#define RK806_INT_STS1 0x79 +#define RK806_INT_MSK1 0x7A +#define RK806_GPIO_INT_CONFIG 0x7B +#define RK806_IRQ_PWRON_FALL_MSK BIT(0) +#define RK806_IRQ_PWRON_RISE_MSK BIT(1) +#define RK806_DEV_OFF BIT(0) +#define RK806_RST_MODE1 0x01 +#define RK806_RST_MODE2 0x02 +#define VERSION_AB 0x01 + +struct regulator_init_data { + const char *supply_regulator; /* or NULL for system supply */ + INT32 reg_id; + INT32 init_voltage_mv; +}; + +struct rk8xx_reg_info { + UINT32 min_uv; + UINT32 step_uv; + UINT8 vsel_reg; + UINT8 vsel_sleep_reg; + UINT8 config_reg; + UINT8 vsel_mask; + UINT8 min_sel; + /* only for buck now */ + UINT8 max_sel; + UINT8 range_num; +}; + +#define RK8XX_DESC_COM(_name, _reg_info, _ops) \ +{ \ + .reg_info = (_reg_info), \ + .name = (_reg_id), \ + .ops = _ops, \ +} + +#define RK8XX_VOLTAGE_INIT(_id, _voltage) \ +{ \ + .reg_id = (_id),\ + .init_voltage_mv = (_voltage),\ +} + +/****************************************** +8 -12: MASTER, SLAVE +4 -7: BUCK, NLDO, PLDO +0 -3: num +******************************************/ +#define MASTER (0x0 << 8) +#define SLAVER (0x1 << 8) +#define BUCK (0x0 << 4) +#define NLDO (0x1 << 4) +#define PLDO (0x2 << 4) + +enum master_num { + MASTER_BUCK1 = (MASTER | BUCK | 0), + MASTER_BUCK2 = (MASTER | BUCK | 1), + MASTER_BUCK3 = (MASTER | BUCK | 2), + MASTER_BUCK4 = (MASTER | BUCK | 3), + MASTER_BUCK5 = (MASTER | BUCK | 4), + MASTER_BUCK6 = (MASTER | BUCK | 5), + MASTER_BUCK7 = (MASTER | BUCK | 6), + MASTER_BUCK8 = (MASTER | BUCK | 7), + MASTER_BUCK9 = (MASTER | BUCK | 8), + MASTER_BUCK10 = (MASTER | BUCK | 9), + + MASTER_NLDO1 = (MASTER | NLDO | 0), + MASTER_NLDO2 = (MASTER | NLDO | 1), + MASTER_NLDO3 = (MASTER | NLDO | 2), + MASTER_NLDO4 = (MASTER | NLDO | 3), + MASTER_NLDO5 = (MASTER | NLDO | 4), + + MASTER_PLDO1 = (MASTER | PLDO | 0), + MASTER_PLDO2 = (MASTER | PLDO | 1), + MASTER_PLDO3 = (MASTER | PLDO | 2), + MASTER_PLDO4 = (MASTER | PLDO | 3), + MASTER_PLDO5 = (MASTER | PLDO | 4), + MASTER_PLDO6 = (MASTER | PLDO | 5), +}; + +enum slaver_num { + SLAVER_BUCK1 = (SLAVER | BUCK | 0), + SLAVER_BUCK2 = (SLAVER | BUCK | 1), + SLAVER_BUCK3 = (SLAVER | BUCK | 2), + SLAVER_BUCK4 = (SLAVER | BUCK | 3), + SLAVER_BUCK5 = (SLAVER | BUCK | 4), + SLAVER_BUCK6 = (SLAVER | BUCK | 5), + SLAVER_BUCK7 = (SLAVER | BUCK | 6), + SLAVER_BUCK8 = (SLAVER | BUCK | 7), + SLAVER_BUCK9 = (SLAVER | BUCK | 8), + SLAVER_BUCK10 = (SLAVER | BUCK | 9), + + SLAVER_NLDO1 = (SLAVER | NLDO | 0), + SLAVER_NLDO2 = (SLAVER | NLDO | 1), + SLAVER_NLDO3 = (SLAVER | NLDO | 2), + SLAVER_NLDO4 = (SLAVER | NLDO | 3), + SLAVER_NLDO5 = (SLAVER | NLDO | 4), + + SLAVER_PLDO1 = (SLAVER | PLDO | 0), + SLAVER_PLDO2 = (SLAVER | PLDO | 1), + SLAVER_PLDO3 = (SLAVER | PLDO | 2), + SLAVER_PLDO4 = (SLAVER | PLDO | 3), + SLAVER_PLDO5 = (SLAVER | PLDO | 4), + SLAVER_PLDO6 = (SLAVER | PLDO | 5), +}; +#endif + +struct SPI_HANDLE gSPI; + +static const struct rk8xx_reg_info rk806_buck[] = { + /* buck 1 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(1), RK806_BUCK_SLP_VSEL(1), RK806_BUCK_CONFIG(1), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 2 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(2), RK806_BUCK_SLP_VSEL(2), RK806_BUCK_CONFIG(2), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 3 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(3), RK806_BUCK_SLP_VSEL(3), RK806_BUCK_CONFIG(3), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 4 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(4), RK806_BUCK_SLP_VSEL(4), RK806_BUCK_CONFIG(4), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 5 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(5), RK806_BUCK_SLP_VSEL(5), RK806_BUCK_CONFIG(5), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 6 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(6), RK806_BUCK_SLP_VSEL(6), RK806_BUCK_CONFIG(6), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 7 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(7), RK806_BUCK_SLP_VSEL(7), RK806_BUCK_CONFIG(7), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 8 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(8), RK806_BUCK_SLP_VSEL(8), RK806_BUCK_CONFIG(8), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 9 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(9), RK806_BUCK_SLP_VSEL(9), RK806_BUCK_CONFIG(9), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, + /* buck 10 */ + { 500000, 6250, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0x00, 0xa0, 3}, + { 1500000, 25000, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xa1, 0xed, 3}, + { 3400000, 0, RK806_BUCK_ON_VSEL(10), RK806_BUCK_SLP_VSEL(10), RK806_BUCK_CONFIG(10), RK806_BUCK_VSEL_MASK, 0xee, 0xff, 3}, +}; + +static const struct rk8xx_reg_info rk806_nldo[] = { + /* nldo1 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_NLDO_ON_VSEL(1), RK806_NLDO_SLP_VSEL(1), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, + /* nldo2 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_NLDO_ON_VSEL(2), RK806_NLDO_SLP_VSEL(2), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, + /* nldo3 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_NLDO_ON_VSEL(3), RK806_NLDO_SLP_VSEL(3), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, + /* nldo4 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_NLDO_ON_VSEL(4), RK806_NLDO_SLP_VSEL(4), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, + /* nldo5 */ + { 500000, 12500, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_NLDO_ON_VSEL(5), RK806_NLDO_SLP_VSEL(5), NA, RK806_NLDO_VSEL_MASK, 0xE8, }, +}; + +static const struct rk8xx_reg_info rk806_pldo[] = { + /* pldo1 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_PLDO_ON_VSEL(1), RK806_PLDO_SLP_VSEL(1), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, + /* pldo2 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_PLDO_ON_VSEL(2), RK806_PLDO_SLP_VSEL(2), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, + /* pldo3 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_PLDO_ON_VSEL(3), RK806_PLDO_SLP_VSEL(3), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, + /* pldo4 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_PLDO_ON_VSEL(4), RK806_PLDO_SLP_VSEL(4), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, + /* pldo5 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_PLDO_ON_VSEL(5), RK806_PLDO_SLP_VSEL(5), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, + /* pldo6 */ + { 500000, 12500, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0x00, }, + { 3400000, 0, RK806_PLDO_ON_VSEL(6), RK806_PLDO_SLP_VSEL(6), NA, RK806_PLDO_VSEL_MASK, 0xE8, }, +}; + +#if 0 +static void io_mem_show(const char *label, unsigned long base, unsigned int start, unsigned int end) +{ + unsigned int val, offset = start, nr = 0; + + if (label) + DEBUG ((DEBUG_ERROR, "%a:\n", label)); + + DEBUG ((DEBUG_ERROR, "%08lx: ", base + offset)); + for (offset = start; offset <= end; offset += 0x04) { + if (nr >= 4) { + DEBUG ((DEBUG_ERROR, "\n%08lx: ", base + offset)); + nr = 0; + } + val = MmioRead32(base + offset); + DEBUG ((DEBUG_ERROR, "%08lx ", val)); + nr++; + } + DEBUG ((DEBUG_ERROR, "\n")); +} +#endif + +static RETURN_STATUS _spi_read(INT32 cs_id, UINT32 reg, UINT8 *buffer, INT32 len) +{ + UINT8 txbuf[8]; + RETURN_STATUS status; + + txbuf[0] = RK806_CMD_READ; + txbuf[1] = reg; + txbuf[2] = RK806_REG_H; + + SPI_SetCS(&gSPI, cs_id, 1); + status = SPI_Configure(&gSPI, txbuf, NULL, 3); + status = SPI_PioTransfer(&gSPI); + SPI_Stop(&gSPI); + status = SPI_Configure(&gSPI, NULL, buffer, 1); + status = SPI_PioTransfer(&gSPI); + SPI_Stop(&gSPI); + SPI_SetCS(&gSPI, cs_id, 0); + + return status; +} + +static RETURN_STATUS _spi_write(INT32 cs_id, UINT32 reg, const UINT8 *buffer, INT32 len) +{ + UINT8 txbuf[4]; + RETURN_STATUS status; + + txbuf[0] = RK806_CMD_WRITE; + txbuf[1] = reg; + txbuf[2] = RK806_REG_H; + txbuf[3] = *buffer; + SPI_SetCS(&gSPI, cs_id, 1); + status = SPI_Configure(&gSPI, txbuf, NULL, 4); + status = SPI_PioTransfer(&gSPI); + + SPI_Stop(&gSPI); + SPI_SetCS(&gSPI, cs_id, 0); + + return status; +} + +static RETURN_STATUS pmic_reg_read(INT32 cs_id, + UINT32 reg, + UINT8 *buffer, + INT32 len) +{ + RETURN_STATUS ret; + + ret = _spi_read(cs_id, reg, buffer, len); + if (ret) + DEBUG ((DEBUG_ERROR, "cs_id %d rk806 read reg(0x%x) error: %d buffer = %x\n", + cs_id, reg, ret, buffer[0])); + + return ret; +} + +static INT32 pmic_reg_write(INT32 cs_id, + UINT32 reg, + const UINT8 *buffer, + INT32 len) +{ + RETURN_STATUS ret; + + ret = _spi_write(cs_id, reg, buffer, len); + if (ret) + DEBUG ((DEBUG_ERROR, "cs_id %d rk806 write reg(0x%x) error: %d %x\n", + cs_id, reg, ret, buffer[0])); + + return ret; +} + +static RETURN_STATUS pmic_clrsetbits(INT32 cs_id, UINT32 reg, UINT32 clr, UINT32 set) +{ + UINT8 byte; + RETURN_STATUS ret; + + ret = pmic_reg_read(cs_id, reg, &byte, 0x01); + if (ret < 0) + return ret; + byte = (ret & ~clr) | set; + + pmic_reg_write(cs_id, reg, &byte, 1); + ret = pmic_reg_read(cs_id, reg, &byte, 0x01); + return ret; +} + +static const struct rk8xx_reg_info *get_buck_reg(INT32 num, INT32 uvolt) +{ + if (uvolt < 1500000) + return &rk806_buck[num * 3 + 0]; + else if (uvolt < 3400000) + return &rk806_buck[num * 3 + 1]; + else + return &rk806_buck[num * 3 + 2]; +} + +static const struct rk8xx_reg_info *get_nldo_reg(INT32 num, INT32 uvolt) +{ + if (uvolt < 3400000) + return &rk806_nldo[num * 2]; + else + return &rk806_nldo[num * 2 + 1]; +} + +static const struct rk8xx_reg_info *get_pldo_reg(INT32 num, INT32 uvolt) +{ + if (uvolt < 3400000) + return &rk806_pldo[num * 2]; + else + return &rk806_pldo[num * 2 + 1]; +} +static RETURN_STATUS buck_set_voltage(INT32 reg_id, INT32 uvolt) +{ + INT32 buck = reg_id & 0x0f; + const struct rk8xx_reg_info *info = get_buck_reg(buck, uvolt); + INT32 mask = info->vsel_mask; + INT32 cs_id = (reg_id & 0xf00) >> 8; + INT32 val; + + if (info->vsel_reg == NA) + return RETURN_INVALID_PARAMETER; + + if (info->step_uv == 0) /* Fixed voltage */ + val = info->min_sel; + else + val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; + + DEBUG ((DEBUG_INFO, "%a: volt=%d, buck=%d, reg=0x%x, mask=0x%x, val=0x%x\n", + __func__, uvolt, buck + 1, info->vsel_reg, mask, val)); + + return pmic_clrsetbits(cs_id, info->vsel_reg, mask, val); +} + +static RETURN_STATUS nldo_set_voltage(INT32 reg_id, INT32 uvolt) +{ + INT32 ldo = reg_id & 0x0f; + const struct rk8xx_reg_info *info = get_nldo_reg(ldo, uvolt); + INT32 mask = info->vsel_mask; + INT32 cs_id = (reg_id & 0xf00) >> 8; + INT32 val; + + if (info->vsel_reg == NA) + return RETURN_INVALID_PARAMETER; + + if (info->step_uv == 0) + val = info->min_sel; + else + val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; + + DEBUG ((DEBUG_INFO, "%a: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", + __func__, uvolt, ldo + 1, info->vsel_reg, mask, val)); + + return pmic_clrsetbits(cs_id, info->vsel_reg, mask, val); +} + +static RETURN_STATUS pldo_set_voltage(INT32 reg_id, INT32 uvolt) +{ + INT32 ldo = reg_id & 0x0f; + const struct rk8xx_reg_info *info = get_pldo_reg(ldo, uvolt); + INT32 mask = info->vsel_mask; + INT32 cs_id = (reg_id & 0xf00) >> 8; + INT32 val; + + if (info->vsel_reg == NA) + return RETURN_INVALID_PARAMETER; + + if (info->step_uv == 0) + val = info->min_sel; + else + val = ((uvolt - info->min_uv) / info->step_uv) + info->min_sel; + + DEBUG ((DEBUG_INFO, "%s: volt=%d, ldo=%d, reg=0x%x, mask=0x%x, val=0x%x\n", + __func__, uvolt, ldo + 1, info->vsel_reg, mask, val)); + + return pmic_clrsetbits(cs_id, info->vsel_reg, mask, val); +} + +static RETURN_STATUS buck_set_enable(INT32 reg_id, BOOLEAN enable) +{ + INT32 cs_id = (reg_id & 0xf00) >> 8; + INT32 buck = reg_id & 0x0f; + UINT8 value, en_reg; + RETURN_STATUS ret; + + en_reg = RK806_POWER_EN(buck / 4); + if (enable) + value = ((1 << buck % 4) | (1 << (buck % 4 + 4))); + else + value = ((0 << buck % 4) | (1 << (buck % 4 + 4))); + + ret = pmic_reg_write(cs_id, en_reg, &value, 1); + + return ret; +} + +static RETURN_STATUS nldo_set_enable(INT32 reg_id, BOOLEAN enable) +{ + INT32 cs_id = (reg_id & 0xf00) >> 8; + INT32 ldo = reg_id & 0x0f; + UINT8 value, en_reg; + RETURN_STATUS ret; + + if (ldo < 4) { + en_reg = RK806_NLDO_EN(0); + if (enable) + value = ((1 << ldo % 4) | (1 << (ldo % 4 + 4))); + else + value = ((0 << ldo % 4) | (1 << (ldo % 4 + 4))); + ret = pmic_reg_write(cs_id, en_reg, &value, 1); + } else { + en_reg = RK806_NLDO_EN(2); + if (enable) + value = 0x44; + else + value = 0x40; + ret = pmic_reg_write(cs_id, en_reg, &value, 1); + } + + return ret; +} + +static RETURN_STATUS pldo_set_enable(INT32 reg_id, BOOLEAN enable) +{ + INT32 cs_id = (reg_id & 0xf00) >> 8; + INT32 pldo = reg_id & 0x0f; + UINT8 value, en_reg; + RETURN_STATUS ret; + + if (pldo < 3) { + en_reg = RK806_PLDO_EN(0); + if (enable) + value = RK806_PLDO0_2_SET(pldo); + else + value = RK806_PLDO0_2_CLR(pldo); + ret = pmic_reg_write(cs_id, en_reg, &value, 1); + } else if (pldo == 3) { + en_reg = RK806_PLDO_EN(1); + if (enable) { + value = ((1 << 0) | (1 << 4)); + } else { + value = (1 << 4); + } + + ret = pmic_reg_write(cs_id, en_reg, &value, 1); + } else if (pldo == 4) { + en_reg = RK806_PLDO_EN(1); + if (enable) + value = ((1 << 1) | (1 << 5)); + else + value = ((0 << 1) | (1 << 5)); + ret = pmic_reg_write(cs_id, en_reg, &value, 1); + } else if (pldo == 5) { + en_reg = RK806_PLDO_EN(0); + if (enable) + value = ((1 << 0) | (1 << 4)); + else + value = ((0 << 0) | (1 << 4)); + ret = pmic_reg_write(cs_id, en_reg, &value, 1); + } + + return ret; +} + +void RK806RegulatorInit(struct regulator_init_data init_data) +{ + INT32 reg_id; + INT32 init_voltage; + + init_voltage = init_data.init_voltage_mv; + reg_id = init_data.reg_id; + + if ((reg_id & 0xf0) == BUCK) { + buck_set_voltage(reg_id, init_voltage); + buck_set_enable(reg_id, 1); + } else if ((reg_id & 0xf0) == NLDO) { + nldo_set_voltage(reg_id, init_voltage); + nldo_set_enable(reg_id, 1); + } if ((reg_id & 0xf0) == PLDO) { + pldo_set_voltage(reg_id, init_voltage); + pldo_set_enable(reg_id, 1); + } +} + +static +RETURN_STATUS +SpiCongig(struct SPI_HANDLE *pSPI) +{ + struct SPI_CONFIG *pSPIConfig = &pSPI->config; + DEBUG ((DEBUG_INFO, "%a(%u): 0: %x\n", "SpiCongig", __LINE__, 0)); + + /* Data width */ + pSPIConfig->nBytes = CR0_DATA_FRAME_SIZE_8BIT; + + /* CPOL */ + //pSPIConfig->clkPolarity = CR0_POLARITY_HIGH; + pSPIConfig->clkPolarity = CR0_POLARITY_LOW; + + /* CPHA */ + //pSPIConfig->clkPhase = CR0_PHASE_2EDGE; + pSPIConfig->clkPhase = CR0_PHASE_1EDGE; + + /* MSB or LSB */ + pSPIConfig->firstBit = CR0_FIRSTBIT_MSB; + //pSPIConfig->firstBit = CR0_FIRSTBIT_LSB; + + /* Master or Slave */ + //pSPIConfig->opMode = CR0_OPM_SLAVE; + pSPIConfig->opMode = CR0_OPM_MASTER; + + /* CSM cycles */ + pSPIConfig->csm = 0; + + pSPI->maxFreq = 24000000; + pSPIConfig->speed = 2000000; + + if (pSPI->config.speed > HAL_SPI_MASTER_MAX_SCLK_OUT) { + pSPI->config.speed = HAL_SPI_MASTER_MAX_SCLK_OUT; + } + + return RETURN_SUCCESS; +} + +RETURN_STATUS RK806Init(void) +{ + UINT32 base = FixedPcdGet32 (SpiRK806BaseAddr); + + Rk806SpiIomux(); + + DEBUG ((DEBUG_INIT, "%a(%u): base: %x\n", "RK806Init", __LINE__, base)); + + SPI_Init(&gSPI, base); + SpiCongig(&gSPI); + + return RETURN_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/RK806.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/RK806.inf new file mode 100644 index 0000000..284d880 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/RK806.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Component description file for Uart module +# +# Copyright (c) 2011-2016, ARM Ltd. All rights reserved.
    +# Copyright (c) 2017, Rockchip Inc. All rights reserved.
    +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RK806Lib + FILE_GUID = b90498c8-728a-11ec-ac42-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RK806Lib + +[Sources.common] + RK806.c + +[LibraryClasses] + DebugLib + IoLib + SpiLib + RockchipPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[Pcd] + gRockchipTokenSpaceGuid.SpiRK806BaseAddr diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/SpiLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/SpiLib.c new file mode 100755 index 0000000..8eecd18 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/SpiLib.c @@ -0,0 +1,491 @@ +/** + Copyright (c) 2021, Rockchip Inc. All rights reserved.
    + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include "Soc.h" +#include +#include +#include +#include + +/** @defgroup How_To_Use How To Use + * + + The SPI HAL driver can be used as follows: + + - Declare a SPI_Handle handle structure, for example: + ``` + SPI_Handle instance; + ``` + + - Invoke SPI_Init() API to configure default config: + - opMode: slave or master + - apbTransform + - endianMode + - ssd + - Clock rate + + - Invoke SPI_Configure() API to program other mode: + - Data size + - Clock polarity and phase + - FirstBit + - Clock div + - Number of data frames received at RX only mode + - IT FIFO Level and DMA FIFO Level + - Transfer Mode + + - Blocking transfer: + - The communication is performed in polling mode by calling SPI_PioTransfer(). + - after transfer done, invoke SPI_Stop to release the chip select. + + */ + +#define HAL_SPI_FIFO_LENGTH 64 +/* Bit fields in SR */ +#define HAL_SPI_SR_BUSY (0x1 << SPI_SR_BSF_SHIFT) +#define HAL_SPI_SR_STB_BUSY (0x1 << SPI_SR_STB_SHIFT) + +/* Bit fields in ISR, IMR, RISR, 7 bits */ +#define SPI_INT_TXEI (1 << SPI_IMR_TFEIM_SHIFT) +#define SPI_INT_TXOI (1 << SPI_IMR_TFOIM_SHIFT) +#define SPI_INT_RXUI (1 << SPI_IMR_RFUIM_SHIFT) +#define SPI_INT_RXOI (1 << SPI_IMR_RFOIM_SHIFT) +#define SPI_INT_RXFI (1 << SPI_IMR_RFFIM_SHIFT) +#define SPI_INT_TOI (1 << SPI_IMR_TOIM_SHIFT) +#define SPI_INT_SSPI (1 << SPI_IMR_SSPIM_SHIFT) +#define SPI_INT_TXFIM (1 << SPI_IMR_TXFIM_SHIFT) + +/* Bit fields in ICR */ +#define SPI_CLEAR_INT_ALL (1 << SPI_ICR_CCI_SHIFT) +#define SPI_CLEAR_INT_RXUI (1 << SPI_ICR_CRFUI_SHIFT) +#define SPI_CLEAR_INT_RXOI (1 << SPI_ICR_CRFOI_SHIFT) +#define SPI_CLEAR_INT_TXOI (1 << SPI_ICR_CTFOI_SHIFT) +#define SPI_CLEAR_INT_TOI (1 << SPI_ICR_CTOI_SHIFT) +#define SPI_ICR_SSPI_SHIFT (1 << SPI_ICR_CSSPI_SHIFT) +#define SPI_CLEAR_INT_TXFI (1 << SPI_ICR_CTXFI_SHIFT) + +/* Bit fields in DMACR */ +#define SPI_DMACR_TX_ENABLE (1 << SPI_DMACR_TDE_SHIFT) +#define SPI_DMACR_RX_ENABLE (1 << SPI_DMACR_RDE_SHIFT) + +/* Bit fields in SPI TIMEOUT */ +#define SPI_TIMEOUT_ENABLE (1 << SPI_TIMEOUT_TOE_SHIFT) +#define SPI_TIMEOUT_DISABLE 0 + +#define IS_SPI_MODE(__MODE__) (((__MODE__) == CR0_OPM_SLAVE) || \ + ((__MODE__) == CR0_OPM_MASTER)) + +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == CR0_XFM_TR) || \ + ((__MODE__) == CR0_XFM_TO) || \ + ((__MODE__) == CR0_XFM_RO)) + +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == CR0_DATA_FRAME_SIZE_4BIT) || \ + ((__DATASIZE__) == CR0_DATA_FRAME_SIZE_8BIT) || \ + ((__DATASIZE__) == CR0_DATA_FRAME_SIZE_16BIT)) + +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == CR0_POLARITY_LOW) || \ + ((__CPOL__) == CR0_POLARITY_HIGH)) + +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == CR0_PHASE_1EDGE) || \ + ((__CPHA__) == CR0_PHASE_2EDGE)) + +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == CR0_FIRSTBIT_MSB) || \ + ((__BIT__) == CR0_FIRSTBIT_LSB)) + +#define IS_SPI_APBTRANSFORM(__MODE__) (((__MODE__) == CR0_BHT_16BIT) || \ + ((__MODE__) == CR0_BHT_8BIT)) + +#define IS_SPI_ENDIAN_MODE(__MODE__) (((__MODE__) == CR0_EM_BIG) || \ + ((__MODE__) == CR0_EM_LITTLE)) + +#define IS_SPI_SSD_BIT(__MODE__) (((__MODE__) == CR0_SSD_HALF) || \ + ((__MODE__) == CR0_SSD_ONE)) + +#define IS_SPI_CSM(__NCYCLES__) (((__NCYCLES__) == CR0_CSM_0CYCLE) || \ + ((__NCYCLES__) == CR0_CSM_1CYCLE) || \ + ((__NCYCLES__) == CR0_CSM_2CYCLES) || \ + ((__NCYCLES__) == CR0_CSM_3CYCLES)) + +/** + * @brief Initialize the SPI according to the specified parameters. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param base: SPI controller register base address. + * @return status + */ +RETURN_STATUS +EFIAPI +SPI_Init(struct SPI_HANDLE *pSPI, UINT32 base) +{ + pSPI->pReg = (struct SPI_REG *)(long)base; + + pSPI->config.opMode = CR0_OPM_MASTER; + + /* Default config */ + pSPI->config.apbTransform = CR0_BHT_8BIT; + pSPI->config.endianMode = CR0_EM_BIG; + pSPI->config.ssd = CR0_SSD_ONE; + pSPI->config.csm = CR0_CSM_0CYCLE; + + return RETURN_SUCCESS; +} + +/** + * @brief Start or stop the spi module. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param enable: start or stop the spi module. + * @return status + */ +static inline RETURN_STATUS SPI_EnableChip(struct SPI_HANDLE *pSPI, int enable) +{ + WRITE_REG(pSPI->pReg->ENR, (enable ? 1 : 0)); + + return RETURN_SUCCESS; +} + +/** + * @brief Configure the spi clock division. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param div: clock division. + * @return status + */ +static inline RETURN_STATUS SPI_SetClock(struct SPI_HANDLE *pSPI, UINT16 div) +{ + WRITE_REG(pSPI->pReg->BAUDR, div); + + return RETURN_SUCCESS; +} + +/** + * @brief Configure the cs signal. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param select: cs number select. + * @param enable: active or inactive the cs signal. + * @return status + */ +RETURN_STATUS +EFIAPI +SPI_SetCS(struct SPI_HANDLE *pSPI, UINT8 select, UINT8 enable) +{ + UINT32 ser; + + ASSERT(pSPI != NULL); + + ser = READ_REG(pSPI->pReg->SER) & SPI_SER_SER_MASK; + + if (enable) { + ser |= 1 << select; + } else { + ser &= ~(1 << select); + } + + WRITE_REG(pSPI->pReg->SER, ser); + + return RETURN_SUCCESS; +} + +/** + * @brief Wait for the transfer finished. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return status + */ +RETURN_STATUS +EFIAPI +SPI_FlushFifo(struct SPI_HANDLE *pSPI) +{ + ASSERT(pSPI != NULL); + + while (READ_REG(pSPI->pReg->RXFLR)) { + READ_REG(pSPI->pReg->RXDR); + } + + return RETURN_SUCCESS; +} + +/** + * @brief The max amount of data can be written in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return Max bytes can xfer. + */ +static inline UINT32 SPI_TxMax(struct SPI_HANDLE *pSPI) +{ + UINT32 txLeft, txRoom; + + txLeft = (pSPI->pTxBufferEnd - pSPI->pTxBuffer) / pSPI->config.nBytes; + txRoom = HAL_SPI_FIFO_LENGTH - READ_REG(pSPI->pReg->TXFLR); + + return MIN(txLeft, txRoom); +} + +/** + * @brief Send an amount of data in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return status + */ +static RETURN_STATUS SPI_PioWrite(struct SPI_HANDLE *pSPI) +{ + UINT32 max = SPI_TxMax(pSPI); + UINT32 txw = 0; + + while (max--) { + if (pSPI->config.nBytes == 1) { + txw = *(const UINT8 *)(pSPI->pTxBuffer); + } else { + txw = *(const UINT16 *)(pSPI->pTxBuffer); + } + + WRITE_REG(pSPI->pReg->TXDR, txw); + pSPI->pTxBuffer += pSPI->config.nBytes; + } + + return RETURN_SUCCESS; +} + +/** + * @brief Read an amount of data(byte) in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return status + */ +static RETURN_STATUS SPI_PioReadByte(struct SPI_HANDLE *pSPI) +{ + UINT32 rxLeft = pSPI->pRxBufferEnd - pSPI->pRxBuffer; + UINT32 rxRoom = READ_REG(pSPI->pReg->RXFLR); + UINT32 max = MIN(rxLeft, rxRoom); + + while (max > 7) { + *(pSPI->pRxBuffer + 0) = (UINT8)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 1) = (UINT8)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 2) = (UINT8)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 3) = (UINT8)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 4) = (UINT8)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 5) = (UINT8)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 6) = (UINT8)READ_REG(pSPI->pReg->RXDR); + *(pSPI->pRxBuffer + 7) = (UINT8)READ_REG(pSPI->pReg->RXDR); + pSPI->pRxBuffer += 8; + max -= 8; + } + + while (max--) { + *pSPI->pRxBuffer = (UINT8)READ_REG(pSPI->pReg->RXDR); + pSPI->pRxBuffer++; + } + + return RETURN_SUCCESS; +} + +/** + * @brief Read an amount of data(short) in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return status + */ +static RETURN_STATUS SPI_PioReadShort(struct SPI_HANDLE *pSPI) +{ + UINT32 rxLeft = (pSPI->pRxBufferEnd - pSPI->pRxBuffer) >> 1; + UINT32 rxRoom = READ_REG(pSPI->pReg->RXFLR); + UINT32 max = MIN(rxLeft, rxRoom); + + while (max > 7) { + *((UINT16 *)pSPI->pRxBuffer + 0) = (UINT16)READ_REG(pSPI->pReg->RXDR); + *((UINT16 *)pSPI->pRxBuffer + 1) = (UINT16)READ_REG(pSPI->pReg->RXDR); + *((UINT16 *)pSPI->pRxBuffer + 2) = (UINT16)READ_REG(pSPI->pReg->RXDR); + *((UINT16 *)pSPI->pRxBuffer + 3) = (UINT16)READ_REG(pSPI->pReg->RXDR); + *((UINT16 *)pSPI->pRxBuffer + 4) = (UINT16)READ_REG(pSPI->pReg->RXDR); + *((UINT16 *)pSPI->pRxBuffer + 5) = (UINT16)READ_REG(pSPI->pReg->RXDR); + *((UINT16 *)pSPI->pRxBuffer + 6) = (UINT16)READ_REG(pSPI->pReg->RXDR); + *((UINT16 *)pSPI->pRxBuffer + 7) = (UINT16)READ_REG(pSPI->pReg->RXDR); + pSPI->pRxBuffer += 16; + max -= 8; + } + + while (max--) { + *((UINT16 *)pSPI->pRxBuffer) = (UINT16)READ_REG(pSPI->pReg->RXDR); + pSPI->pRxBuffer += 2; + } + + return RETURN_SUCCESS; +} + +/** + * @brief Transmit an amount of data in blocking mode. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return status + */ +RETURN_STATUS +EFIAPI +SPI_PioTransfer(struct SPI_HANDLE *pSPI) +{ + UINT32 remain = 0; + + ASSERT(pSPI != NULL); + + pSPI->type = SPI_POLL; + SPI_EnableChip(pSPI, 1); + + do { + if (pSPI->pTxBuffer) { + remain = pSPI->pTxBufferEnd - pSPI->pTxBuffer; + SPI_PioWrite(pSPI); + } + + if (pSPI->pRxBuffer) { + remain = pSPI->pRxBufferEnd - pSPI->pRxBuffer; + + if (pSPI->config.nBytes == 1) { + SPI_PioReadByte(pSPI); + } else { + SPI_PioReadShort(pSPI); + } + } + } while (remain); + + return RETURN_SUCCESS; +} + +/** + * @brief Query the SPI bus state is idle or busy. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return HAL status + */ +RETURN_STATUS SPI_QueryBusState(struct SPI_HANDLE *pSPI) +{ + HAL_ASSERT(pSPI != NULL); + if (!(READ_REG(pSPI->pReg->SR) & HAL_SPI_SR_BUSY)) { + return RETURN_SUCCESS; + } + + return -2; +} + +/** + * @brief Stop the transmit. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return status + */ +RETURN_STATUS +EFIAPI +SPI_Stop(struct SPI_HANDLE *pSPI) +{ + UINT32 ret; + ASSERT(pSPI != NULL); + + do + { + ret = SPI_QueryBusState(pSPI); + if (ret == RETURN_SUCCESS) + break; + } while(1); + + SPI_EnableChip(pSPI, 0); + + return RETURN_SUCCESS; +} + +/** + * @brief Configure the SPI transfer mode depend on the tx/rx buffer. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @return status + */ +static RETURN_STATUS HAL_SPI_ConfigureTransferMode(struct SPI_HANDLE *pSPI) +{ + UINT32 cr0; + + if (pSPI->pTxBuffer && pSPI->pRxBuffer) { + pSPI->config.xfmMode = CR0_XFM_TR; + } else if (pSPI->pTxBuffer) { + pSPI->config.xfmMode = CR0_XFM_TO; + } else if (pSPI->pRxBuffer) { + pSPI->config.xfmMode = CR0_XFM_RO; + } + + cr0 = READ_REG(pSPI->pReg->CTRLR[0]); + cr0 &= ~SPI_CTRLR0_XFM_MASK; + cr0 |= pSPI->config.xfmMode; + + WRITE_REG(pSPI->pReg->DMARDLR, pSPI->dmaBurstSize - 1); + WRITE_REG(pSPI->pReg->CTRLR[0], cr0); + + return RETURN_SUCCESS; +} + +/** + * @brief Program the SPI config via this api. + * @param pSPI: pointer to a SPI_Handle structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to TX buffer. + * @param pRxData: pointer to RX buffer. + * @param size: amount of data to be sent. + * @return status + */ +RETURN_STATUS +EFIAPI +SPI_Configure(struct SPI_HANDLE *pSPI, const UINT8 *pTxData, UINT8 *pRxData, UINT32 size) +{ + UINT32 cr0 = 0; + UINT32 div = 0; + + cr0 |= pSPI->config.opMode; + + cr0 |= pSPI->config.apbTransform | pSPI->config.endianMode | pSPI->config.ssd; + /* Data width */ + cr0 |= pSPI->config.nBytes; + + /* Mode for polarity, phase, first bit and endian */ + cr0 |= pSPI->config.clkPolarity | pSPI->config.clkPhase | pSPI->config.firstBit; + + /* Config CSM cycles */ + cr0 |= pSPI->config.csm; + + /* div doesn't support odd number */ + div = DIV_ROUND_UP(pSPI->maxFreq, pSPI->config.speed); + div = (div + 1) & 0xfffe; + + WRITE_REG(pSPI->pReg->CTRLR[0], cr0); + + WRITE_REG(pSPI->pReg->TXFTLR, HAL_SPI_FIFO_LENGTH / 2 - 1); + WRITE_REG(pSPI->pReg->RXFTLR, HAL_SPI_FIFO_LENGTH / 2 - 1); + + WRITE_REG(pSPI->pReg->DMATDLR, HAL_SPI_FIFO_LENGTH / 2 - 1); + WRITE_REG(pSPI->pReg->DMARDLR, 0); + + SPI_SetClock(pSPI, div); + + pSPI->pTxBuffer = pTxData; + pSPI->pTxBufferEnd = pTxData + size; + pSPI->pRxBuffer = pRxData; + pSPI->pRxBufferEnd = pRxData + size; + pSPI->len = size; + + HAL_SPI_ConfigureTransferMode(pSPI); + + if (pSPI->config.xfmMode == CR0_XFM_RO) { + if (pSPI->config.nBytes == 1) { + WRITE_REG(pSPI->pReg->CTRLR[1], pSPI->len - 1); + } else if (pSPI->config.nBytes == 2) { + WRITE_REG(pSPI->pReg->CTRLR[1], (pSPI->len / 2) - 1); + } else { + WRITE_REG(pSPI->pReg->CTRLR[1], (pSPI->len * 2) - 1); + } + } + + return RETURN_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/SpiLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/SpiLib.inf new file mode 100644 index 0000000..856bfbf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Library/SpiLib/SpiLib.inf @@ -0,0 +1,39 @@ +#/** @file +# +# Component description file for Uart module +# +# Copyright (c) 2011-2016, ARM Ltd. All rights reserved.
    +# Copyright (c) 2017, Rockchip Inc. All rights reserved.
    +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SpiLib + FILE_GUID = b90498c8-728a-11ec-ac42-f42a7dcb925d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SpiLib + +[Sources.common] + SpiLib.c + +[LibraryClasses] + DebugLib + IoLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[Pcd] + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Cpu.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Cpu.asl new file mode 100644 index 0000000..16fbd7d --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Cpu.asl @@ -0,0 +1,134 @@ +/** @file + * + * RK3588 CPU devices. + * + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018-2020, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +Device (PKG0) +{ + Name (_HID, "ACPI0010") + Name (_UID, 8) + Method (_STA) + { + Return (0xF) + } + + Device (CLU0) + { + Name (_HID, "ACPI0010") + Name (_UID, 9) + Method (_STA) + { + Return (0xF) + } + + Device (CPU0) + { + Name (_HID, "ACPI0007") + Name (_UID, 0) + Method (_STA) + { + Return (0xF) + } + } + + Device (CPU1) + { + Name (_HID, "ACPI0007") + Name (_UID, 1) + Method (_STA) + { + Return (0xF) + } + } + + Device (CPU2) + { + Name (_HID, "ACPI0007") + Name (_UID, 2) + Method (_STA) + { + Return (0xF) + } + } + + Device (CPU3) + { + Name (_HID, "ACPI0007") + Name (_UID, 3) + Method (_STA) + { + Return (0xF) + } + } + } + + Device (CLU1) + { + Name (_HID, "ACPI0010") + Name (_UID, 10) + Method (_STA) + { + Return (0xF) + } + + Device (CPU4) + { + Name (_HID, "ACPI0007") + Name (_UID, 4) + Method (_STA) + { + Return (0xF) + } + } + + Device (CPU5) + { + Name (_HID, "ACPI0007") + Name (_UID, 5) + Method (_STA) + { + Return (0xF) + } + } + } + + Device (CLU2) + { + Name (_HID, "ACPI0010") + Name (_UID, 11) + Method (_STA) + { + Return (0xF) + } + + Device (CPU6) + { + Name (_HID, "ACPI0007") + Name (_UID, 6) + Method (_STA) + { + Return (0xF) + } + } + + Device (CPU7) + { + Name (_HID, "ACPI0007") + Name (_UID, 7) + Method (_STA) + { + Return (0xF) + } + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Dbg2.aslc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Dbg2.aslc new file mode 100644 index 0000000..7534cec --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Dbg2.aslc @@ -0,0 +1,69 @@ +/** @file +* Debug Port Table (DBG2) +* +* Copyright (c) 2021, Jared McNeill +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#include +#include +#include +#include + +#include "AcpiTables.h" + +#pragma pack(1) + +#define UART_STR { '\\', '_', 'S', 'B', '.', 'U', 'A', 'R', '2', 0x00 } + +typedef struct { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device; + EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister; + UINT32 AddressSize; + UINT8 NameSpaceString[10]; +} DBG2_DEBUG_DEVICE_INFORMATION; + +typedef struct { + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description; + DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo; +} DBG2_TABLE; + + +STATIC DBG2_TABLE Dbg2 = { + { + ACPI_HEADER ( + EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE, + DBG2_TABLE, + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION + ), + OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo), + 1 /* NumberOfDebugPorts */ + }, + { + { + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, + sizeof (DBG2_DEBUG_DEVICE_INFORMATION), + 1, /* NumberofGenericAddressRegisters */ + 10, /* NameSpaceStringLength */ + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString), + 0, /* OemDataLength */ + 0, /* OemDataOffset */ + EFI_ACPI_DBG2_PORT_TYPE_SERIAL, + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_WITH_GAS, + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister), + OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize) + }, + ARM_GAS32 (FixedPcdGet64(PcdSerialRegisterBase)), /* BaseAddressRegister */ + 0x1000, /* AddressSize */ + UART_STR, /* NameSpaceString */ + } +}; + +#pragma pack() + +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable = &Dbg2; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Dma.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Dma.asl new file mode 100644 index 0000000..53a69b7 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Dma.asl @@ -0,0 +1,104 @@ +/** @file + * + * Copyright (c) 2022, Rockchip Electronics Co. Ltd. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ +#include "AcpiTables.h" + +// +// Description: DMA +// + Device (DMA0) + { + Name (_HID, "ARMH0330") + Name (_UID, 0) + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFEA10000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000076, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000077, + } + }) + Return (RBUF) /* \_SB_.DMA0._CRS.RBUF */ + } + Name (_DSD, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) {"ctlrName", "DMA0"} + } + }) + } + + Device (DMA1) + { + Name (_HID, "ARMH0330") + Name (_UID, 1) + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFEA30000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000078, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000079, + } + }) + Return (RBUF) /* \_SB_.DMA0._CRS.RBUF */ + } + Name (_DSD, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) {"ctlrName", "DMA1"} + } + }) + } + + Device (DMA2) + { + Name (_HID, "ARMH0330") + Name (_UID, 2) + Method (_CRS, 0, Serialized) + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED10000, // Address Base + 0x00004000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000007A, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000007B, + } + }) + Return (RBUF) /* \_SB_.DMA0._CRS.RBUF */ + } + Name (_DSD, Package() { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) {"ctlrName", "DMA2"} + } + }) + } \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/DsdtCommon.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/DsdtCommon.asl new file mode 100644 index 0000000..7b8afe6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/DsdtCommon.asl @@ -0,0 +1,13 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +Scope (\_SB_) { + Include ("Scmi.asl") +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Emmc.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Emmc.asl new file mode 100644 index 0000000..0d08672 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Emmc.asl @@ -0,0 +1,133 @@ +/** @file + * + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ +#include "AcpiTables.h" + + + Device (SDC3) { + Name (_HID, "RKCP0D40") + Name (_UID, 3) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe2e0000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 237 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk3588-dwcmshc" }, + Package () { "max-frequency", 200000000 }, + Package () { "bus-width", 8 }, + Package () { "no-sd", 0x1 }, + Package () { "no-sdio", 0x1 }, + Package () { "mmc-hs400-1_8v", 0x1 }, + Package () { "mmc-hs400-enhanced-strobe", 0x1 }, + Package () { "non-removable", 0x1 }, + } + }) + + OperationRegion(EMMC, SystemMemory, 0xFD7C0434, 0x4) + Field(EMMC, DWordAcc, NoLock, WriteAsZeros) { + PLLE, 32, + } + + Method (_DSM, 4) { + If (LEqual (Arg0, ToUUID("434addb0-8ff3-49d5-a724-95844b79ad1f"))) { + Switch (ToInteger (Arg2)) { + Case (0) { + Return (0x3) + } + Case (1) { + Local0 = DerefOf (Arg3 [0]) + If (Local0 >= 200000000) { + Store (0xFF000500, PLLE) + Return (200000000) + } + If (Local0 >= 150000000) { + Store (0xFF000700, PLLE) + Return (150000000) + } + If (Local0 >= 100000000) { + Store (0xFF000B00, PLLE) + Return (100000000) + } + If (Local0 >= 50000000) { + Store (0xFF001700, PLLE) + Return (50000000) + } + If (Local0 >= 24000000) { + Store (0xFF008000, PLLE) + Return (24000000) + } + if (Local0 >= 375000) { + Store (0xFF00BF00, PLLE) + Return (375000) + } + Return (0) + } + } + } + Return (0) + } + + // Used by downstream Linux driver. + Method(SCLK, 1, Serialized) { + If (Arg0 <= 400000) + { + Store (0xFF00BF00, PLLE) + } + ElseIF (Arg0 <= 50000000) + { + Store (0xFF008000, PLLE) + } + Else + { + Store (0xFF000600, PLLE) + } + } + + /* TODO: + Method(_PS3) { + + } + + Method(_PS2) { + Store (0xFF00BF00, PLLE) + } + + Method(_PS1) { + Store (0xFF008000, PLLE) + } + + Method(_PS0) { + Store (0xFF000600, PLLE) + } + + Method(_PSC) { + Return(0x01) + } + */ + + // + // A child device that represents the non-removable eMMC. + // + Device (SDMM) + { + Method (_ADR) + { + Return (0) + } + Method (_RMV) // Is removable + { + Return (0) // 0 - fixed + } + } + } \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Es8388.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Es8388.asl new file mode 100644 index 0000000..964432a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Es8388.asl @@ -0,0 +1,28 @@ +/** @file + * + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ +#include "AcpiTables.h" + + Device (JACK) { + Name (_HID, BOARD_AUDIO_CODEC_HID) + Name (_UID, 0) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + I2cSerialBusV2(BOARD_CODEC_I2C_ADDR, ControllerInitiated, 0x000186A0, + AddressingMode7Bit, BOARD_CODEC_I2C, + 0x00, ResourceConsumer, , Exclusive) + GpioInt (Edge, ActiveHigh, Exclusive, PullNone, 0x0000, + BOARD_CODEC_GPIO, 0x00, ResourceConsumer) + { + BOARD_CODEC_GPIO_PIN + } + }) + Return (RBUF) + } + } \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Fadt.aslc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Fadt.aslc new file mode 100644 index 0000000..c2d079c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Fadt.aslc @@ -0,0 +1,86 @@ +/** @file + * + * Fixed ACPI Description Table (FADT) + * + * Copyright (c) 2019, Pete Batard + * Copyright (c) 2018, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "AcpiTables.h" + +EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt = { + ACPI_HEADER ( + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION + ), + 0, // UINT32 FirmwareCtrl + 0, // UINT32 Dsdt + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0 + EFI_ACPI_6_3_PM_PROFILE_APPLIANCE_PC, // UINT8 PreferredPmProfile + 0, // UINT16 SciInt + 0, // UINT32 SmiCmd + 0, // UINT8 AcpiEnable + 0, // UINT8 AcpiDisable + 0, // UINT8 S4BiosReq + 0, // UINT8 PstateCnt + 0, // UINT32 Pm1aEvtBlk + 0, // UINT32 Pm1bEvtBlk + 0, // UINT32 Pm1aCntBlk + 0, // UINT32 Pm1bCntBlk + 0, // UINT32 Pm2CntBlk + 0, // UINT32 PmTmrBlk + 0, // UINT32 Gpe0Blk + 0, // UINT32 Gpe1Blk + 0, // UINT8 Pm1EvtLen + 0, // UINT8 Pm1CntLen + 0, // UINT8 Pm2CntLen + 0, // UINT8 PmTmrLen + 0, // UINT8 Gpe0BlkLen + 0, // UINT8 Gpe1BlkLen + 0, // UINT8 Gpe1Base + 0, // UINT8 CstCnt + 0, // UINT16 PLvl2Lat + 0, // UINT16 PLvl3Lat + 0, // UINT16 FlushSize + 0, // UINT16 FlushStride + 0, // UINT8 DutyOffset + 0, // UINT8 DutyWidth + 0, // UINT8 DayAlrm + 0, // UINT8 MonAlrm + 0, // UINT8 Century + EFI_ACPI_6_3_MSI_NOT_SUPPORTED, // UINT16 IaPcBootArch (Reserved on ARM) + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved1 + EFI_ACPI_6_3_WBINVD | EFI_ACPI_6_3_SLP_BUTTON | // UINT32 Flags + EFI_ACPI_6_3_HW_REDUCED_ACPI, + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResetReg + 0, // UINT8 ResetValue + EFI_ACPI_6_3_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision + 0, // UINT64 XFirmwareCtrl + 0, // UINT64 XDsdt + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe0Blk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE XGpe1Blk + NULL_GAS, // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepControlReg + NULL_GAS // EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE SleepStatusReg +}; + +// +// Reference the table being generated to prevent the optimizer from removing the +// data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Fadt; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac0.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac0.asl new file mode 100644 index 0000000..a800b7e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac0.asl @@ -0,0 +1,96 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +// Gigabit Media Access Controller (GMAC0) +Device (MAC0) { + Name (_HID, "RKCP6543") + Name (_CID, Package() { + "PRP0001" + }) + Name (_UID, 60) + Name (_CCA, 0) + Name (_STA, 0xF) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe1b0000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 259, 258 } + }) + Return (RBUF) + } + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", Package () { "snps,dwmac-4.20a", "snps,dwmac" } }, + Package () { "interrupt-names", Package () { "macirq", "eth_wake_irq" } }, + Package () { "snps,mixed-burst", 1 }, + Package () { "snps,tso", 1 }, + Package () { "snps,axi-config", "AXIC" }, + } + }) + + Name (AXIC, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "snps,wr_osr_lmt", 4 }, + Package () { "snps,rd_osr_lmt", 8 }, + Package () { "snps,blen", Package () { 0, 0, 0, 0, 16, 8, 4 } }, + } + }) + + Method (_DSM, 4, Serialized) { + // PHP_GRF_CLK_CON1 + OperationRegion (PGRF, SystemMemory, 0xfd5b0070, 0x4) + Field (PGRF, DWordAcc, NoLock, Preserve) { + CON1, 32 + } + + // Check the UUID + If (Arg0 == ToUUID ("d637828d-556c-4829-966a-237072f00ff1")) { + // Check the revision + If (Arg1 >= 0) { + // Check the function index + Switch (ToInteger (Arg2)) { + // + // Supported functions: + // Bit 0 - Indicates support for functions other than 0 + // Bit 1 - Indicates support for setting the MII speed + // + Case (0) { + Return (Buffer () { 0x03 }) + } + + // + // Function Index 1: Set MII speed + // + Case (1) { + Local0 = DerefOf (Arg3[0]) + + Switch (ToInteger (Local0)) { + Case (1000) { + CON1 = 0x000c0000 + } + Case (100) { + CON1 = 0x000c000c + } + Case (10) { + CON1 = 0x000c0008 + } + } + Return (Buffer () { 0x00 }) + } + } // Function index check + } // Revision check + } // UUID check + Return (Buffer () { 0x0 }) + } // _DSM +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac1.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac1.asl new file mode 100644 index 0000000..314c4bb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gmac1.asl @@ -0,0 +1,96 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +// Gigabit Media Access Controller (GMAC1) +Device (MAC1) { + Name (_HID, "RKCP6543") + Name (_CID, Package() { + "PRP0001" + }) + Name (_UID, 61) + Name (_CCA, 0) + Name (_STA, 0xF) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe1c0000, 0x10000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 266, 265 } + }) + Return (RBUF) + } + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", Package () { "snps,dwmac-4.20a", "snps,dwmac" } }, + Package () { "interrupt-names", Package () { "macirq", "eth_wake_irq" } }, + Package () { "snps,mixed-burst", 1 }, + Package () { "snps,tso", 1 }, + Package () { "snps,axi-config", "AXIC" }, + } + }) + + Name (AXIC, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "snps,wr_osr_lmt", 4 }, + Package () { "snps,rd_osr_lmt", 8 }, + Package () { "snps,blen", Package () { 0, 0, 0, 0, 16, 8, 4 } }, + } + }) + + Method (_DSM, 4, Serialized) { + // PHP_GRF_CLK_CON1 + OperationRegion (PGRF, SystemMemory, 0xfd5b0070, 0x4) + Field (PGRF, DWordAcc, NoLock, Preserve) { + CON1, 32 + } + + // Check the UUID + If (Arg0 == ToUUID ("d637828d-556c-4829-966a-237072f00ff1")) { + // Check the revision + If (Arg1 >= 0) { + // Check the function index + Switch (ToInteger (Arg2)) { + // + // Supported functions: + // Bit 0 - Indicates support for functions other than 0 + // Bit 1 - Indicates support for setting the MII speed + // + Case (0) { + Return (Buffer () { 0x03 }) + } + + // + // Function Index 1: Set MII speed + // + Case (1) { + Local0 = DerefOf (Arg3[0]) + + Switch (ToInteger (Local0)) { + Case (1000) { + CON1 = 0x01800000 + } + Case (100) { + CON1 = 0x01800180 + } + Case (10) { + CON1 = 0x01800100 + } + } + Return (Buffer () { 0x00 }) + } + } // Function index check + } // Revision check + } // UUID check + Return (Buffer () { 0x0 }) + } // _DSM +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gpio.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gpio.asl new file mode 100644 index 0000000..59255c0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gpio.asl @@ -0,0 +1,166 @@ +/** @file + * + * Copyright (c) 2022, Rockchip Electronics Co. Ltd. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ +#include "AcpiTables.h" + +// +// Description: GPIO +// +Device (GPI0) +{ + Name (_HID, "RKCP3002") + Name (_CID, "PRP0001") + Name (_UID, 0x0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "rockchip,gpio-bank" }, + } + }) + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFD8A0000, 0x100) + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {309} + }) + Return(RBUF) + } + Method (_STA) + { + Return(0xf) + } +}//GPIO0 + + +Device (GPI1) +{ + Name (_HID, "RKCP3002") + Name (_CID, "PRP0001") + Name (_UID, 0x1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "rockchip,gpio-bank" }, + } + }) + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFEC20000, 0x100) + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {310} + }) + Return(RBUF) + } + Method (_STA) + { + Return(0xf) + } +}//GPIO1 + +Device (GPI2) +{ + Name (_HID, "RKCP3002") + Name (_CID, "PRP0001") + Name (_UID, 0x2) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "rockchip,gpio-bank" }, + } + }) + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFEC30000, 0x100) + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {311} + }) + Return(RBUF) + } + Method (_STA) + { + Return(0xf) + } +}//GPIO2 + +Device (GPI3) +{ + Name (_HID, "RKCP3002") + Name (_CID, "PRP0001") + Name (_UID, 0x3) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "rockchip,gpio-bank" }, + } + }) + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFEC40000, 0x100) + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {312} + }) + Return(RBUF) + } + Method (_STA) + { + Return(0xf) + } +}//GPIO3 + +Device (GPI4) +{ + Name (_HID, "RKCP3002") + Name (_CID, "PRP0001") + Name (_UID, 0x4) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "rockchip,gpio-bank" }, + } + }) + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFEC50000, 0x100) + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) {313} + }) + Return(RBUF) + } + Method (_STA) + { + Return(0xf) + } +}//GPIO4 + +Device (PINC) +{ + Name (_HID, "PRP0001") + Name (_UID, 0x4) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "rockchip,rk3588-pinctrl" }, + } + }) + Method (_CRS, 0x0, NotSerialized) + { + Name (RBUF, ResourceTemplate() + { + Memory32Fixed(ReadWrite, 0xFD5F0000, 0x10000) + }) + Return(RBUF) + } + Method (_STA) + { + Return(0xf) + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gtdt.aslc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gtdt.aslc new file mode 100644 index 0000000..e17ebc1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Gtdt.aslc @@ -0,0 +1,71 @@ +/** @file +* Generic Timer Description Table (GTDT) +* +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +#include "AcpiTables.h" + +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0 +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE +#define GTDT_GLOBAL_FLAGS_LEVEL 0 + +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer +#ifdef SYSTEM_TIMER_BASE_ADDRESS + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) +#else + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL) + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF +#endif + +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE +#define GTDT_TIMER_LEVEL_TRIGGERED 0 +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY +#define GTDT_TIMER_ACTIVE_HIGH 0 + +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED) + +#pragma pack (1) + +typedef struct { + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt; +} GENERIC_TIMER_DESCRIPTION_TABLE; + +#pragma pack () + +GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = { + { + ACPI_HEADER( + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, + GENERIC_TIMER_DESCRIPTION_TABLE, + EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION + ), + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress + 0, // UINT32 Reserved + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress + 0, // UINT32 PlatformTimerCount + }, +}; + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Gtdt; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/I2c.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/I2c.asl new file mode 100644 index 0000000..428a738 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/I2c.asl @@ -0,0 +1,200 @@ +/** @file + * + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ +#include "AcpiTables.h" + + Device (I2C1) { + Name (_HID, "RKCP3001") + Name (_CID, "PRP0001") + Name (_UID, 1) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfea90000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 350 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "i2c,clk-rate", 198000000 }, + Package (2) { "rockchip,bclk", 198000000 }, + Package (2) { "#address-cells", 1 }, + Package (2) { "#size-cells", 0 }, + } + }) + } + + Device (I2C2) { + Name (_HID, "RKCP3001") + Name (_CID, "PRP0001") + Name (_UID, 2) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfeaa0000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 351 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "i2c,clk-rate", 198000000 }, + Package (2) { "rockchip,bclk", 198000000 }, + Package (2) { "#address-cells", 1 }, + Package (2) { "#size-cells", 0 }, + } + }) + } + + Device (I2C3) { + Name (_HID, "RKCP3001") + Name (_CID, "PRP0001") + Name (_UID, 3) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfeab0000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 352 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "i2c,clk-rate", 198000000 }, + Package (2) { "rockchip,bclk", 198000000 }, + Package (2) { "#address-cells", 1 }, + Package (2) { "#size-cells", 0 }, + } + }) + } + + Device (I2C4) { + Name (_HID, "RKCP3001") + Name (_CID, "PRP0001") + Name (_UID, 4) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfeac0000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 353 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "i2c,clk-rate", 198000000 }, + Package (2) { "rockchip,bclk", 198000000 }, + Package (2) { "#address-cells", 1 }, + Package (2) { "#size-cells", 0 }, + } + }) + } + + Device (I2C5) { + Name (_HID, "RKCP3001") + Name (_CID, "PRP0001") + Name (_UID, 5) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfead0000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 354 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "i2c,clk-rate", 198000000 }, + Package (2) { "rockchip,bclk", 198000000 }, + Package (2) { "#address-cells", 1 }, + Package (2) { "#size-cells", 0 }, + } + }) + } + + Device (I2C6) { + Name (_HID, "RKCP3001") + Name (_CID, "PRP0001") + Name (_UID, 6) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfec80000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 355 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "i2c,clk-rate", 198000000 }, + Package (2) { "rockchip,bclk", 198000000 }, + Package (2) { "#address-cells", 1 }, + Package (2) { "#size-cells", 0 }, + } + }) + } + + Device (I2C7) { + Name (_HID, "RKCP3001") + Name (_CID, "PRP0001") + Name (_UID, 7) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfec90000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 356 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "i2c,clk-rate", 198000000 }, + Package (2) { "rockchip,bclk", 198000000 }, + Package (2) { "#address-cells", 1 }, + Package (2) { "#size-cells", 0 }, + } + }) + } + + Device (I2C8) { + Name (_HID, "RKCP3001") + Name (_CID, "PRP0001") + Name (_UID, 8) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfeca0000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 357 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "i2c,clk-rate", 198000000 }, + Package (2) { "rockchip,bclk", 198000000 }, + Package (2) { "#address-cells", 1 }, + Package (2) { "#size-cells", 0 }, + } + }) + } diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/I2s.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/I2s.asl new file mode 100644 index 0000000..64d2424 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/I2s.asl @@ -0,0 +1,240 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2024, CoolStar. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ +#include "AcpiTables.h" + +#define RK3588_PLL_AUPLL_RATE 786432000 +#define RK3588_PLL_CPLL_RATE 1500000000 + +#define I2S_INITIAL_CLOCK (256 * 48000) + +#define I2S_DSM_UUID ToUUID ("7056bfa1-af0b-48e5-b67f-139f2004a26a") + +#if FixedPcdGetBool(PcdI2S0Supported) + Device (I2S0) { + Name (_HID, "RKCP3003") + Name (_UID, 0) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe470000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 212 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "rockchip,dma", "DMA0" }, + Package (2) { "rockchip,tx", 0 }, + Package (2) { "rockchip,rx", 1 }, + Package (2) { "rockchip,tplg", BOARD_I2S0_TPLG }, + } + }) + Name (_DEP, Package () { \_SB.DMA0 }) + + Method (_INI, 0, Serialized) { + _DSM (I2S_DSM_UUID, 0, 1, Package () { I2S_INITIAL_CLOCK }) + } + + Method (_DSM, 4, Serialized) { + // CRU_CLKSEL_CON24 + OperationRegion (CRU, SystemMemory, 0xFD7C0360, 0x8) + Field (CRU, DWordAcc, NoLock, Preserve) { + C24, 32, + C25, 32 + } + + // Check the UUID + If (Arg0 == I2S_DSM_UUID) { + // Check the revision + If (Arg1 >= 0) { + // Check the function index + Switch (ToInteger (Arg2)) { + // + // Supported functions: + // Bit 0 - Indicates support for functions other than 0 + // Bit 1 - Indicates support for setting TX master clock + // Bit 2 - Indicates support for setting RX master clock + // + Case (0) { + Return (Buffer () { 0x03 }) + } + + // + // Function Index 1: Set TX master clock + // Takes the target clock rate in Hz, returns the actual set rate. + // + Case (1) { + // Source divided by clk_i2s0_8ch_tx_src_div + 1 + Local0 = RK3588_PLL_AUPLL_RATE / (((C24 >> 4) & 0xf) + 1) + + // Compute numerator/denumerator + Local1 = FRBA (DerefOf (Arg3[0]), Local0, 0xFFFF, 0xFFFF) + + // Set fractional register + C25 = (DerefOf (Local1[0])) << 16 | DerefOf (Local1[1]) + + Return ((Local0 * DerefOf (Local1[0])) / DerefOf (Local1[1])) + } + } // Function index check + } // Revision check + } // UUID check + Return (Buffer () { 0x0 }) + } // _DSM + } +#endif + +#if FixedPcdGetBool(PcdI2S1Supported) + Device (I2S1) { + Name (_HID, "RKCP3003") + Name (_UID, 1) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe480000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 213 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "rockchip,dma", "DMA0" }, + Package (2) { "rockchip,tx", 2 }, + Package (2) { "rockchip,rx", 3 }, + Package (2) { "rockchip,tplg", BOARD_I2S1_TPLG }, + // XXX: Currently I2S1 is only used by Orange Pi 5. + // The following properties should be board specific + Package (2) { "rockchip,i2s-tx-route", 0x3210 },, + Package (2) { "rockchip,i2s-rx-route", 0x1320 }, + } + }) + Name (_DEP, Package () { \_SB.DMA0 }) + + Method (_INI, 0, Serialized) { + _DSM (I2S_DSM_UUID, 0, 1, Package () { I2S_INITIAL_CLOCK }) + } + + Method (_DSM, 4, Serialized) { + // PMU1CRU_CLKSEL_CON05 + OperationRegion (CRU, SystemMemory, 0xFD7F0314, 0x8) + Field (CRU, DWordAcc, NoLock, Preserve) { + C05, 32, + C06, 32 + } + + // Check the UUID + If (Arg0 == I2S_DSM_UUID) { + // Check the revision + If (Arg1 >= 0) { + // Check the function index + Switch (ToInteger (Arg2)) { + // + // Supported functions: + // Bit 0 - Indicates support for functions other than 0 + // Bit 1 - Indicates support for setting TX master clock + // Bit 2 - Indicates support for setting RX master clock + // + Case (0) { + Return (Buffer () { 0x03 }) + } + + // + // Function Index 1: Set TX master clock + // Takes the target clock rate in Hz, returns the actual set rate. + // + Case (1) { + // Source divided by clk_i2s1_8ch_tx_src_div + 1 + Local0 = RK3588_PLL_CPLL_RATE / (((C05 >> 2) & 0xf) + 1) + + // Compute numerator/denumerator + Local1 = FRBA (DerefOf (Arg3[0]), Local0, 0xFFFF, 0xFFFF) + + // Set fractional register + C06 = (DerefOf (Local1[0])) << 16 | DerefOf (Local1[1]) + + Return ((Local0 * DerefOf (Local1[0])) / DerefOf (Local1[1])) + } + } // Function index check + } // Revision check + } // UUID check + Return (Buffer () { 0x0 }) + } // _DSM + } +#endif + + // + // FRBA - Find Rational Best Approximation + // + // Arguments: (4) + // Arg0 - Given numerator + // Arg1 - Given denominator + // Arg2 - Maximum numerator + // Arg3 - Maximum denominator + // + // Return: + // Package of two integers: best numerator, best denominator + // + Function (FRBA, PkgObj, { IntObj, IntObj, IntObj, IntObj }) { + // + // Variables used throughout this function: + // Local0, Local1 - Remaining numerator/denominator for Euclidean algorithm + // Local2, Local4 - Previous numerator/denominator convergent + // Local3, Local5 - Current numerator/denominator convergent + // Local6 - Temporary variable for swapping values around + // Local7 - Next term in the continued fraction + // + Local0 = Arg0 + Local1 = Arg1 + Local2 = 0 + Local3 = 1 + Local4 = 1 + Local5 = 0 + + While (1) { + // Reached limits? Fall back to previous convergent. + If (Local3 > Arg2 || Local5 > Arg3) { + Local3 = Local2 + Local5 = Local4 + Break + } + + // No remainder? We're done. + If (Local1 == 0) { + Break + } + + // Find next term for convergent + Local7 = Local0 / Local1 + + // Set remainder + Local6 = Local1 + Local1 = Local0 % Local1 + Local0 = Local6 + + // Calculate numerator and save previous one + Local6 = Local2 + Local7 * Local3 + Local2 = Local3 + Local3 = Local6 + + // Caculate denominator and save previous one + Local6 = Local4 + Local7 * Local5 + Local4 = Local5 + Local5 = Local6 + } + + // Prepare return object + Local0 = Package (2) { 0, 0 } + Local0[0] = Local3 + Local0[1] = Local5 + + Return (Local0) + } diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Madt.aslc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Madt.aslc new file mode 100644 index 0000000..05cd5d1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Madt.aslc @@ -0,0 +1,123 @@ +/** @file +* Multiple APIC Description Table (MADT) +* +* Copyright (c) 2021, Jared McNeill +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved. +* Copyright (c) 2018, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include + +#include "AcpiTables.h" + +// +// Multiple APIC Description Table +// +#pragma pack (1) + +typedef struct { + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header; + EFI_ACPI_6_0_GIC_STRUCTURE GicInterfaces[8]; + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE GicDistributor; + EFI_ACPI_6_0_GICR_STRUCTURE GicRedistributors; + // EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE GicMsiFrame; + // EFI_ACPI_6_0_GIC_ITS_STRUCTURE GicIts[2]; +} EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE; + +#pragma pack () + +EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = { + { + ACPI_HEADER ( + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE, + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION + ), + // + // MADT specific fields + // + 0, // LocalApicAddress + 0, // Flags + }, + { + // Format: EFI_ACPI_6_0_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, + // Flags, + // PmuIrq, GicBase, GicVBase, GicHBase, GsivId, GicRBase, Efficiency) + // Note: The GIC Structure of the primary CPU must be the first entry + // (see note in 5.2.12.14 GICC Structure of ACPI v6.0). + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A55-0 + 0, 0, GET_MPID(0, 0x000), + EFI_ACPI_6_0_GIC_ENABLED, + 23, 0, 0, 0, 25, 0, 0), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A55-1 + 0, 1, GET_MPID(0, 0x100), + EFI_ACPI_6_0_GIC_ENABLED, + 23, 0, 0, 0, 25, 0, 0), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A55-2 + 0, 2, GET_MPID(0, 0x200), + EFI_ACPI_6_0_GIC_ENABLED, + 23, 0, 0, 0, 25, 0, 0), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A55-3 + 0, 3, GET_MPID(0, 0x300), + EFI_ACPI_6_0_GIC_ENABLED, + 23, 0, 0, 0, 25, 0, 0), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A76-0 + 0, 4, GET_MPID(0, 0x400), + EFI_ACPI_6_0_GIC_ENABLED, + 23, 0, 0, 0, 25, 0, 1), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A76-1 + 0, 5, GET_MPID(0, 0x500), + EFI_ACPI_6_0_GIC_ENABLED, + 23, 0, 0, 0, 25, 0, 1), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A76-2 + 0, 6, GET_MPID(0, 0x600), + EFI_ACPI_6_0_GIC_ENABLED, + 23, 0, 0, 0, 25, 0, 1), + EFI_ACPI_6_0_GICC_STRUCTURE_INIT( // A76-3 + 0, 7, GET_MPID(0, 0x700), + EFI_ACPI_6_0_GIC_ENABLED, + 23, 0, 0, 0, 25, 0, 1), + }, + // GIC Distributor Entry + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (0, FixedPcdGet64 (PcdGicDistributorBase), + 0, EFI_ACPI_6_0_GIC_V3), + // GIC Redistributors Entry + EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT (FixedPcdGet64 (PcdGicRedistributorsBase), + 0x100000), + // GIC MSI Frame + // + // Disable for now, will need to put it behind a config option + // as some OSes are not happy about it (like Windows). + // + // { + // EFI_ACPI_6_0_GIC_MSI_FRAME, + // sizeof (EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE), + // EFI_ACPI_RESERVED_WORD, + // 0, + // FixedPcdGet64 (PcdGicDistributorBase) + 0x10000, + // EFI_ACPI_6_0_SPI_COUNT_BASE_SELECT, + // 56, + // 424 + // }, + + /* ITS is broken on RK35xx!*/ + // Linux has a workaround for the erratum, but no way to describe + // this in ACPI yet. + // + // { + // EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(0, 0xfe640000), + // EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(1, 0xfe660000) + // }, +}; + +// +// Reference the table being generated to prevent the optimizer +// from removing the data structure from the executable +// +VOID* CONST ReferenceAcpiTable = &Madt; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Mcfg.aslc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Mcfg.aslc new file mode 100644 index 0000000..ce84490 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Mcfg.aslc @@ -0,0 +1,102 @@ +/** @file + * + * PCI Express Memory-mapped Configuration Space base address description table (MCFG) + * + * Copyright (c) 2021, Jared McNeill + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +// +// MCFG is patched by AcpiPlatformDxe. +// + +RK3588_MCFG_TABLE Mcfg = { + { + ACPI_HEADER ( + EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + RK3588_MCFG_TABLE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION + ), + }, + { // Main config space + { + PCIE_CFG_BASE (0), + 0, // PciSegmentNumber + 1, // PciBusMin + 1, // PciBusMax + 0 // Reserved + }, + { + PCIE_CFG_BASE (1), + 1, // PciSegmentNumber + 1, // PciBusMin + 1, // PciBusMax + 0 // Reserved + }, + { + PCIE_CFG_BASE (2), + 2, // PciSegmentNumber + 1, // PciBusMin + 1, // PciBusMax + 0 // Reserved + }, + { + PCIE_CFG_BASE (3), + 3, // PciSegmentNumber + 1, // PciBusMin + 1, // PciBusMax + 0 // Reserved + }, + { + PCIE_CFG_BASE (4), + 4, // PciSegmentNumber + 1, // PciBusMin + 1, // PciBusMax + 0 // Reserved + } + }, + { // Root Port DBI config space (for Windows) + { + PCIE_DBI_BASE (0), + 0, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + }, + { + PCIE_DBI_BASE (1), + 1, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + }, + { + PCIE_DBI_BASE (2), + 2, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + }, + { + PCIE_DBI_BASE (3), + 3, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + }, + { + PCIE_DBI_BASE (4), + 4, // PciSegmentNumber + 0, // PciBusMin + 0, // PciBusMax + 0 // Reserved + } + } +}; + +VOID* CONST ReferenceAcpiTable = &Mcfg; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie.asl new file mode 100644 index 0000000..99418bc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pcie.asl @@ -0,0 +1,120 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define PCIE_ROOT_COMPLEX(Segment, LegacyIrq) \ + Device (PCI ## Segment) { \ + Name (_HID, "PNP0A08") \ + Name (_CID, "PNP0A03") \ + Name (_CCA, 0) \ + Name (_UID, Segment) \ + Name (_SEG, Segment) \ + Method (_BBN) { \ + Return (PBMI) \ + } \ + Name (_STA, 0xF) \ + \ + Name (_PRT, Package() { \ + Package (4) { 0x0FFFF, 0, 0, LegacyIrq }, \ + Package (4) { 0x0FFFF, 1, 0, LegacyIrq }, \ + Package (4) { 0x0FFFF, 2, 0, LegacyIrq }, \ + Package (4) { 0x0FFFF, 3, 0, LegacyIrq } \ + }) \ + \ + Method (_CRS, 0, Serialized) { \ + Name (RBUF, ResourceTemplate () { \ + WORDBUSNUMBER_BUF (00, ResourceProducer) \ + DWORDMEMORY_BUF (01, ResourceProducer) \ + QWORDMEMORY_BUF (02, ResourceProducer) \ + QWORDIO_BUF (03, ResourceProducer) \ + }) \ + WORD_SET (00, PBMI, PBMA - PBMI + 1, 0) \ + DWORD_SET (01, PCIE_MEM_BASE (Segment), PCIE_MEM_SIZE, 0) \ + QWORD_SET (02, PCIE_MEM64_BASE (Segment), PCIE_MEM64_SIZE, 0) \ + QWORD_SET (03, PCIE_IO_BASE, PCIE_IO_SIZE, PCIE_IO_XLATE (Segment)) \ + Return (RBUF) \ + } \ + \ + Device (RES0) { \ + Name (_HID, "AMZN0001") \ + Name (_CID, "PNP0C02") \ + Name (_UID, Segment) \ + Method (_CRS, 0, Serialized) { \ + Name (RBUF, ResourceTemplate () { \ + QWORDMEMORY_BUF (00, ResourceProducer) \ + }) \ + QWORD_SET (00, PCIE_DBI_BASE (Segment), PCIE_DBI_SIZE, 0) \ + Return (RBUF) \ + } \ + } \ + \ + Device (RES1) { \ + Name (_HID, "PNP0C02") \ + Name (_UID, Segment + 1) \ + Method (_CRS, 0, Serialized) { \ + Name (RBUF, ResourceTemplate () { \ + QWORDMEMORY_BUF (00, ResourceProducer) \ + }) \ + QWORD_SET (00, PCIE_CFG_BASE (Segment), SIZE_256MB, 0) \ + Return (RBUF) \ + } \ + } \ + \ + Name (SUPP, Zero) /* PCI _OSC Support Field value */ \ + Name (CTRL, Zero) /* PCI _OSC Control Field value */ \ + \ + Method (_OSC, 4) { \ + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { \ + /* Create DWord-adressable fields from the Capabilities Buffer */ \ + CreateDWordField (Arg3, 0, CDW1) \ + CreateDWordField (Arg3, 4, CDW2) \ + CreateDWordField (Arg3, 8, CDW3) \ + \ + /* Save Capabilities DWord2 & 3 */ \ + SUPP = CDW2 \ + CTRL = CDW3 \ + \ + /* Mask out native hot plug control */ \ + CTRL &= 0x1E \ + \ + /* Always allow native PME, AER and Capability Structure control */ \ + /* Never allow SHPC and LTR control */ \ + CTRL &= 0x1D \ + \ + /* Unknown revision */ \ + If (Arg1 != 1) { \ + Cdw1 |= 0x08 \ + } \ + \ + /* Capabilities bits were masked */ \ + If (CDW3 != CTRL) { \ + CDW1 |= 0x10 \ + } \ + \ + /* Update DWORD3 in the buffer */ \ + CDW3 = CTRL \ + Return (Arg3) \ + } Else { \ + /* Unrecognized UUID */ \ + CDW1 |= 4 \ + Return (Arg3) \ + } \ + } \ + } + +Scope (\_SB_) { + Name (PBMI, 0xABCD) // PCI Bus Minimum + Name (PBMA, 0xABCD) // PCI Bus Maximum + + PCIE_ROOT_COMPLEX (0, 292) + PCIE_ROOT_COMPLEX (1, 287) + PCIE_ROOT_COMPLEX (2, 272) + PCIE_ROOT_COMPLEX (3, 277) + PCIE_ROOT_COMPLEX (4, 282) +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pptt.aslc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pptt.aslc new file mode 100644 index 0000000..207b5d2 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Pptt.aslc @@ -0,0 +1,267 @@ +/** @file + * + * RK3588 SoC Processor Properties Topology Table + * + * This table is based on the ACPI 6.2 spec because Windows + * (tested with build 22621.1992) is not able to properly parse + * newer revisions: + * - ACPI 6.3 (rev 2) leads to doubled L3 cache size. + * - ACPI 6.4 (rev 3) leads to a 0x7E bug check due to the new + * Cache ID field in the Cache Type Structure (see Table 5.140). + * + * It also entirely ignores cache sizes described here, relying on + * CCSIDR instead. The info there is mostly correct, except for L3. + * + * Linux parses and displays all this data correctly. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#pragma pack(1) +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package; + UINT32 L3CacheRef; +} RK3588_PPTT_PACKAGE_NODE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster; +} RK3588_PPTT_CLUSTER_NODE; + +typedef struct { + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core; + UINT32 L1DCacheRef; + UINT32 L1ICacheRef; + UINT32 L2CacheRef; +} RK3588_PPTT_CORE_NODE; + +typedef struct { + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RK3588_PPTT_PACKAGE_NODE Package; + RK3588_PPTT_CLUSTER_NODE Clusters[3]; + RK3588_PPTT_CORE_NODE Cores[8]; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE PackageL3Cache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE A55L1DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE A55L1ICache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE A55L2Cache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE A76L1DCache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE A76L1ICache; + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE A76L2Cache; +} RK3588_PPTT; +#pragma pack() + +/// +/// For PPTT struct processor flags +/// +#define EFI_ACPI_6_2_PPTT_PACKAGE_NOT_PHYSICAL 0x0 +#define EFI_ACPI_6_2_PPTT_PACKAGE_PHYSICAL 0x1 +#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID 0x1 + +/// +/// For PPTT struct cache flags +/// +#define EFI_ACPI_6_2_PPTT_CACHE_SIZE_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_CACHE_SIZE_VALID 0x1 +#define EFI_ACPI_6_2_PPTT_NUMBER_OF_SETS_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_NUMBER_OF_SETS_VALID 0x1 +#define EFI_ACPI_6_2_PPTT_ASSOCIATIVITY_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_ASSOCIATIVITY_VALID 0x1 +#define EFI_ACPI_6_2_PPTT_ALLOCATION_TYPE_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_ALLOCATION_TYPE_VALID 0x1 +#define EFI_ACPI_6_2_PPTT_CACHE_TYPE_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_CACHE_TYPE_VALID 0x1 +#define EFI_ACPI_6_2_PPTT_WRITE_POLICY_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_WRITE_POLICY_VALID 0x1 +#define EFI_ACPI_6_2_PPTT_LINE_SIZE_INVALID 0x0 +#define EFI_ACPI_6_2_PPTT_LINE_SIZE_VALID 0x1 + +#define PPTT_DATA_CACHE_ATTRIBUTES \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \ + } + +#define PPTT_INST_CACHE_ATTRIBUTES \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \ + } + +#define PPTT_UNIFIED_CACHE_ATTRIBUTES \ + { \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \ + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \ + } + +#define RK3588_PPTT_CLUSTER_NODE_INIT(ClusterUid) { \ + { /* Cluster */ \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, /* Type */ \ + sizeof (RK3588_PPTT_CLUSTER_NODE), /* Length */ \ + { /* Reserved[2] */ \ + EFI_ACPI_RESERVED_BYTE, \ + EFI_ACPI_RESERVED_BYTE \ + }, \ + { /* Flags */ \ + EFI_ACPI_6_2_PPTT_PACKAGE_NOT_PHYSICAL, \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID \ + }, \ + OFFSET_OF (RK3588_PPTT, Package), /* Parent */ \ + ClusterUid, /* AcpiProcessorId */ \ + 0 /* NumberOfPrivateResources */ \ + } \ +} + +#define RK3588_PPTT_CORE_NODE_INIT(ClusterIndex, CoreUid, \ + L1DCacheField, L1ICacheField, L2CacheField) { \ + { /* Core */ \ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, /* Type */ \ + sizeof (RK3588_PPTT_CORE_NODE), /* Length */ \ + { /* Reserved[2] */ \ + EFI_ACPI_RESERVED_BYTE, \ + EFI_ACPI_RESERVED_BYTE \ + }, \ + { /* Flags */ \ + EFI_ACPI_6_2_PPTT_PACKAGE_NOT_PHYSICAL, \ + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID \ + }, \ + OFFSET_OF (RK3588_PPTT, \ + Clusters[ClusterIndex]), /* Parent */ \ + CoreUid, /* AcpiProcessorId */ \ + 3 /* NumberOfPrivateResources */ \ + }, \ + OFFSET_OF (RK3588_PPTT, L1DCacheField), /* L1DCacheRef */ \ + OFFSET_OF (RK3588_PPTT, L1ICacheField), /* L1ICacheRef */ \ + OFFSET_OF (RK3588_PPTT, L2CacheField) /* L2CacheRef */ \ +} + +#define RK3588_PPTT_A55_CORE_NODE_INIT(ClusterIndex, CoreUid) \ + RK3588_PPTT_CORE_NODE_INIT ( \ + ClusterIndex, CoreUid, \ + A55L1DCache, A55L1ICache, A55L2Cache \ + ) + +#define RK3588_PPTT_A76_CORE_NODE_INIT(ClusterIndex, CoreUid) \ + RK3588_PPTT_CORE_NODE_INIT ( \ + ClusterIndex, CoreUid, \ + A76L1DCache, A76L1ICache, A76L2Cache \ + ) + +#define RK3588_PPTT_CACHE_NODE_INIT(NextLevelOfCache, Size, \ + NumberOfSets, Attributes) { \ + EFI_ACPI_6_2_PPTT_TYPE_CACHE, /* Type */ \ + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), /* Length */ \ + { /* Reserved[2] */ \ + EFI_ACPI_RESERVED_BYTE, \ + EFI_ACPI_RESERVED_BYTE \ + }, \ + { /* Flags */ \ + EFI_ACPI_6_2_PPTT_CACHE_SIZE_VALID, \ + EFI_ACPI_6_2_PPTT_NUMBER_OF_SETS_VALID, \ + EFI_ACPI_6_2_PPTT_ASSOCIATIVITY_VALID, \ + EFI_ACPI_6_2_PPTT_ALLOCATION_TYPE_VALID, \ + EFI_ACPI_6_2_PPTT_CACHE_TYPE_VALID, \ + EFI_ACPI_6_2_PPTT_WRITE_POLICY_VALID, \ + EFI_ACPI_6_2_PPTT_LINE_SIZE_VALID \ + }, \ + NextLevelOfCache, /* NextLevelOfCache */ \ + Size, /* Size */ \ + NumberOfSets, /* NumberOfSets */ \ + Size / NumberOfSets / 64, /* Associativity */ \ + Attributes, /* Attributes */ \ + 64 /* LineSize */ \ +} + +STATIC RK3588_PPTT Pptt = { + { + ACPI_HEADER ( + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + RK3588_PPTT, + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ), + }, + { + { /* Package */ + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, /* Type */ + sizeof (RK3588_PPTT_PACKAGE_NODE), /* Length */ + { /* Reserved[2] */ + EFI_ACPI_RESERVED_BYTE, + EFI_ACPI_RESERVED_BYTE + }, + { /* Flags */ + EFI_ACPI_6_2_PPTT_PACKAGE_PHYSICAL, + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID + }, + 0, /* Parent */ + 8, /* AcpiProcessorId */ + 1 /* NumberOfPrivateResources */ + }, + OFFSET_OF (RK3588_PPTT, PackageL3Cache) + }, + { /* Clusters */ + RK3588_PPTT_CLUSTER_NODE_INIT (9), /* Little cluster */ + RK3588_PPTT_CLUSTER_NODE_INIT (10), /* Big cluster 0 */ + RK3588_PPTT_CLUSTER_NODE_INIT (11) /* Big cluster 1 */ + }, + { /* Cores */ + RK3588_PPTT_A55_CORE_NODE_INIT (0, 0), /* 4x Cortex-A55 (Little cluster) */ + RK3588_PPTT_A55_CORE_NODE_INIT (0, 1), + RK3588_PPTT_A55_CORE_NODE_INIT (0, 2), + RK3588_PPTT_A55_CORE_NODE_INIT (0, 3), + RK3588_PPTT_A76_CORE_NODE_INIT (1, 4), /* 2x Cortex-A76 (Big cluster 0) */ + RK3588_PPTT_A76_CORE_NODE_INIT (1, 5), + RK3588_PPTT_A76_CORE_NODE_INIT (2, 6), /* 2x Cortex-A76 (Big cluster 1) */ + RK3588_PPTT_A76_CORE_NODE_INIT (2, 7) + }, + RK3588_PPTT_CACHE_NODE_INIT ( /* PackageL3Cache */ + 0, /* NextLevelOfCache */ + SIZE_1MB * 3, /* Size */ + 4096, /* NumberOfSets */ + PPTT_UNIFIED_CACHE_ATTRIBUTES /* Attributes */ + ), + RK3588_PPTT_CACHE_NODE_INIT ( /* A55L1DCache */ + OFFSET_OF (RK3588_PPTT, A55L2Cache), /* NextLevelOfCache */ + SIZE_32KB, /* Size */ + 128, /* NumberOfSets */ + PPTT_DATA_CACHE_ATTRIBUTES /* Attributes */ + ), + RK3588_PPTT_CACHE_NODE_INIT ( /* A55L1ICache */ + OFFSET_OF (RK3588_PPTT, A55L2Cache), /* NextLevelOfCache */ + SIZE_32KB, /* Size */ + 128, /* NumberOfSets */ + PPTT_INST_CACHE_ATTRIBUTES /* Attributes */ + ), + RK3588_PPTT_CACHE_NODE_INIT ( /* A55L2Cache */ + 0, /* NextLevelOfCache */ + SIZE_128KB, /* Size */ + 512, /* NumberOfSets */ + PPTT_UNIFIED_CACHE_ATTRIBUTES /* Attributes */ + ), + RK3588_PPTT_CACHE_NODE_INIT ( /* A76L1DCache */ + OFFSET_OF (RK3588_PPTT, A76L2Cache), /* NextLevelOfCache */ + SIZE_64KB, /* Size */ + 256, /* NumberOfSets */ + PPTT_DATA_CACHE_ATTRIBUTES /* Attributes */ + ), + RK3588_PPTT_CACHE_NODE_INIT ( /* A76L1ICache */ + OFFSET_OF (RK3588_PPTT, A76L2Cache), /* NextLevelOfCache */ + SIZE_64KB, /* Size */ + 256, /* NumberOfSets */ + PPTT_INST_CACHE_ATTRIBUTES /* Attributes */ + ), + RK3588_PPTT_CACHE_NODE_INIT ( /* A76L2Cache */ + 0, /* NextLevelOfCache */ + SIZE_512KB, /* Size */ + 1024, /* NumberOfSets */ + PPTT_UNIFIED_CACHE_ATTRIBUTES /* Attributes */ + ) +}; + +VOID* CONST ReferenceAcpiTable = &Pptt; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/RK3588PcieIort.aslc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/RK3588PcieIort.aslc new file mode 100644 index 0000000..172ef9a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/RK3588PcieIort.aslc @@ -0,0 +1,121 @@ +/** @file +* I/O Remapping Table (Iort) +* +* Copyright (c) 2018, ARM Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include "AcpiTables.h" + +#pragma pack(1) + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; + UINT32 ItsIdentifiers; +} ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE; + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMap; +} ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE; + +typedef struct +{ + EFI_ACPI_6_0_IO_REMAPPING_TABLE Header; + ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Its0Node; + ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Its1Node; + ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Rc3x4Node; +} ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE; + +#pragma pack (1) + +ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort = +{ + // EFI_ACPI_6_0_IO_REMAPPING_TABLE + { + ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER + ( + EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE, + ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00 + ), + 3, // NumNodes + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset + 0, // Reserved + }, + + // ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_NODE + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type + sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length + 0, // Revision + 0, // Reserved + 0, // NumIdMappings + 0, // IdReference + }, + 1, // ITS count + }, + 0, // GIC ITS Identifiers + }, + + // ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_NODE + { + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type + sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length + 0, // Revision + 0, // Reserved + 0, // NumIdMappings + 0, // IdReference + }, + 1, // ITS count + }, + 1, // GIC ITS Identifiers + }, + // ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_RC_NODE + { + // EFI_ACPI_6_0_IO_REMAPPING_NODE + { + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type + sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE), // Length + 0, // Revision + 0, // Reserved + 1, // NumIdMappings + OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap) // IdReference + }, + 0, // CacheCoherent + 0, // AllocationHints + 0, // Reserved + 0, // MemoryAccessFlags + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED, // AtsAttribute + 0x0, // PciSegmentNumber + }, + // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE + { + 0x0000, // InputBase + 0xffff, // NumIds + 0x0000, // OutputBase + OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, Its1Node), // OutputReference + 0, // Flags + } + } +}; + +VOID* CONST ReferenceAcpiTable = &Iort; + diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata.asl new file mode 100644 index 0000000..d094c54 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sata.asl @@ -0,0 +1,77 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +Scope (\_SB_) { + Device (ATA0) { + Name (_HID, "RKCP0161") + Name (_UID, 0) + Name (_CLS, Package() { 0x01, 0x06, 0x01 }) + Name (_CCA, 0) + Name (_STA, 0xF) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe210000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 305 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk-ahci" }, + } + }) + } + + Device (ATA1) { + Name (_HID, "RKCP0161") + Name (_UID, 1) + Name (_CLS, Package() { 0x01, 0x06, 0x01 }) + Name (_CCA, 0) + Name (_STA, 0xF) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe220000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 306 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk-ahci" }, + } + }) + } + + Device (ATA2) { + Name (_HID, "RKCP0161") + Name (_UID, 2) + Name (_CLS, Package() { 0x01, 0x06, 0x01 }) + Name (_CCA, 0) + Name (_STA, 0xF) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe230000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 307 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk-ahci" }, + } + }) + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Scmi.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Scmi.asl new file mode 100644 index 0000000..f5d8965 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Scmi.asl @@ -0,0 +1,264 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#define SCMI_SHARED_MEM_BASE FixedPcdGet32(PcdRkMtlMailBoxBase) +#define SCMI_SHARED_MEM_SIZE FixedPcdGet32(PcdRkMtlMailBoxSize) + +// Mailbox 0, channel 0 +#define SCMI_DOORBELL_BASE 0xfec60030 +#define SCMI_DOORBELL_SIZE 0x8 + +#define SMT_MESSAGE_TYPE_COMMAND 0 + +#define SMT_CHANNEL_STATUS_ERROR (0x1 << 1) +#define SMT_CHANNEL_STATUS_FREE (0x1 << 0) +#define SMT_CHANNEL_STATUS_BUSY 0 + +#define SMT_CHANNEL_FLAGS_INTERRUPT (0x1 << 0) +#define SMT_CHANNEL_FLAGS_POLL 0 + +#define SMT_POLL_TIMEOUT_US 20000 + +#define SCMI_STATUS_SUCCESS 0 + +Device (SCMI) { + Name (_HID, "PNP0C02") + Name (_UID, 0) + + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, SCMI_SHARED_MEM_BASE, SCMI_SHARED_MEM_SIZE) + }) + Return (RBUF) + } + + // + // CLRG - Clock Rate Get + // + // Arguments: + // Arg0: Clock ID + // + // Return: + // Package of two integers: Status, Clock rate + // Values following Status are only valid on success. + // + Method (CLRG, 1, Serialized) { + Name(PBUF, Buffer (4) { }) // Parameters + CreateDWordField (PBUF, 0, PCID) // Clock ID + PCID = Arg0 + + Local0 = SMT (0x14, 0x6, PBUF) // Response + CreateDWordField (Local0, 0, RSTA) // Status + CreateDWordField (Local0, 4, RRTL) // Rate low part + CreateDWordField (Local0, 8, RRTH) // Rate high part + + // Prepare return package + Local1 = Package (2) { 0, 0 } + Local1[0] = RSTA + + If (RSTA == SCMI_STATUS_SUCCESS) { + Local1[1] = (RRTH << 32) | RRTL + } + + Return (Local1) + } + + // + // CLRS - Clock Rate Set + // + // Arguments: + // Arg0: Clock ID + // Arg1: Clock rate + // + // Return: + // Package of one integer: Status + // + Method (CLRS, 2, Serialized) { + Name(PBUF, Buffer (16) { }) // Parameters + CreateDWordField (PBUF, 0, PFLG) // Flags + CreateDWordField (PBUF, 4, PCID) // Clock ID + CreateDWordField (PBUF, 8, PRTL) // Rate low part + CreateDWordField (PBUF, 12, PRTH) // Rate high part + PFLG = 0 + PCID = Arg0 + PRTL = Arg1 + PRTH = Arg1 >> 32 + + Local0 = SMT (0x14, 0x5, PBUF) // Response + CreateDWordField (Local0, 0, RSTA) // Status + + // Prepare return package + Local1 = Package (1) { 0 } + Local1[0] = RSTA + + Return (Local1) + } + + // + // CLCS - Clock Config Set + // + // Arguments: + // Arg0: Clock ID + // Arg1: Attributes (1 -> enable, 0 -> disable) + // + // Return: + // Package of one integer: Status + // + Method (CLCS, 2, Serialized) { + Name(PBUF, Buffer (8) { }) // Parameters + CreateDWordField (PBUF, 0, PCID) // Clock ID + CreateDWordField (PBUF, 4, PATR) // Attributes + PCID = Arg0 + PATR = Arg1 + + Local0 = SMT (0x14, 0x7, PBUF) // Response + CreateDWordField (Local0, 0, RSTA) // Status + + // Prepare return package + Local1 = Package (1) { 0 } + Local1[0] = RSTA + + Return (Local1) + } + + // + // VDLG - Voltage Domain Level Get + // + // Arguments: + // Arg0: Domain ID + // + // Return: + // Package of two integers: Status, Voltage level + // Values following Status are only valid on success. + // + Method (VDLG, 1, Serialized) { + Name(PBUF, Buffer (4) { }) // Parameters + CreateDWordField (PBUF, 0, PDID) // Domain ID + PDID = Arg0 + + Local0 = SMT (0x17, 0x8, PBUF) // Response + CreateDWordField (Local0, 0, RSTA) // Status + CreateDWordField (Local0, 4, RVOL) // Voltage level + + // Prepare return package + Local1 = Package (2) { 0, 0 } + Local1[0] = RSTA + + If (RSTA == SCMI_STATUS_SUCCESS) { + Local1[1] = RVOL + } + + Return (Local1) + } + + // + // VDLS - Voltage Domain Level Set + // + // Arguments: + // Arg0: Domain ID + // Arg1: Voltage level + // + // Return: + // Package of one integer: Status + // + Method (VDLS, 2, Serialized) { + Name(PBUF, Buffer (12) { }) // Parameters + CreateDWordField (PBUF, 0, PDID) // Domain ID + CreateDWordField (PBUF, 4, PFLG) // Flags + CreateDWordField (PBUF, 8, PVOL) // Voltage level + PDID = Arg0 + PFLG = 0 + PVOL = Arg1 + + Local0 = SMT (0x17, 0x7, PBUF) // Response + CreateDWordField (Local0, 0, RSTA) // Status + + // Prepare return package + Local1 = Package (1) { 0 } + Local1[0] = RSTA + + Return (Local1) + } + + OperationRegion (SHM, SystemMemory, SCMI_SHARED_MEM_BASE, SCMI_SHARED_MEM_SIZE) + Field (SHM, ByteAcc, NoLock, Preserve) { + , 32, // Reserved + SCHS, 32, // Channel status + , 64, // Reserved + SCHF, 32, // Channel flags + SLEN, 32, // Length + SMSH, 32, // Message header + SPLD, 736 // Payload + } + + OperationRegion (DBEL, SystemMemory, SCMI_DOORBELL_BASE, SCMI_DOORBELL_SIZE) + Field (DBEL, DWordAcc, NoLock, Preserve) { + DCMD, 32, // Command + DDAT, 32 // Data + } + + Method (FREE, 0, Serialized) { + For (Local0 = SMT_POLL_TIMEOUT_US, Local0 > 0, Local0--) { + If ((SCHS & SMT_CHANNEL_STATUS_FREE) != 0) { + Return (1) + } + Sleep (1) + } + Return (0) + } + + // + // SMT - Shared Memory Transport + // + // Arguments: + // Arg0: SCMI Protocol ID + // Arg1: SCMI Message ID + // Arg2: SCMI Input Buffer + // + // Return: + // Buffer: SCMI Payload + // + Method (SMT, 3, Serialized) { + // Initial return value (transport error) + Local0 = Buffer (4) { 1 } + + // Wait for any previous message + If (FREE () == 0) { + Return (Local0) + } + + // Fill in the message header + Name (MSGH, Buffer (4) { }) + CreateField (MSGH, 10, 8, PRTI) // Protocol identifier + CreateField (MSGH, 8, 2, MSGT) // Message type + CreateField (MSGH, 0, 8, MSGI) // Message identifier + PRTI = Arg0 + MSGT = SMT_MESSAGE_TYPE_COMMAND + MSGI = Arg1 + SMSH = MSGH + + SCHS = SMT_CHANNEL_STATUS_BUSY + SCHF = SMT_CHANNEL_FLAGS_POLL + SLEN = 4 + SizeOf (Arg2) // Message header + Payload + SPLD = Arg2 + + // Ring the doorbell + DCMD = 0 + DDAT = 0 + + // Wait for completion + If ((FREE () == 0) || ((SCHS & SMT_CHANNEL_STATUS_ERROR) != 0)) { + Return (Local0) + } + + Local0 = SPLD + Return (Local0) + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sdhc.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sdhc.asl new file mode 100644 index 0000000..e66d479 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Sdhc.asl @@ -0,0 +1,72 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +#ifndef SDMMC_CAP_DDR50 +#define SDMMC_CAP_DDR50 1 +#endif +#ifndef SDMMC_CAP_SDR50 +#define SDMMC_CAP_SDR50 1 +#endif +#ifndef SDMMC_CAP_SDR104 +#define SDMMC_CAP_SDR104 1 +#endif + +Scope (\_SB_) { + Name (SDRM, 1) // SD slot is removable + + Device (SDHC) { + Name (_HID, "RKCPFE2C") + Name (_UID, 0x0) + Name (_CCA, 0x0) + Name (_S1D, 0x1) + Name (_S2D, 0x1) + Name (_S3D, 0x1) + Name (_S4D, 0x1) + Name (_STA, 0xf) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0xfe2c0000, 0x4000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 235 } + + // SDMMC_DET + GpioIO (Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPI0") { GPIO_PIN_PA4 } + GpioInt (Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPI0") { GPIO_PIN_PA4 } + }) + Return (RBUF) + } + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", Package () { "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc" } }, + Package () { "fifo-depth", 0x100 }, + Package () { "max-frequency", 200000000 }, + Package () { "bus-width", 4 }, + Package () { "cap-sd-highspeed", 1 }, + Package () { "sd-uhs-ddr50", SDMMC_CAP_DDR50 }, + Package () { "sd-uhs-sdr50", SDMMC_CAP_SDR50 }, + Package () { "sd-uhs-sdr104", SDMMC_CAP_SDR104 }, + Package () { "broken-cd", FixedPcdGetBool (PcdRkSdmmcCardDetectBroken) }, + } + }) + + // + // A child device that represents the SD card. + // + Device (SDMM) { + Name (_ADR, 0x0) + + Method (_RMV) { + Return (SDRM) + } + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Spcr.aslc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Spcr.aslc new file mode 100644 index 0000000..d834494 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Spcr.aslc @@ -0,0 +1,50 @@ +/** @file +* Serial Port Console Redirection Table (SPCR). +* +* Copyright (c) 2021, Jared McNeill +* Copyright (c) 2020 Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include + +#include "AcpiTables.h" + +#pragma pack(push, 1) + +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { + ACPI_HEADER ( + EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550_WITH_GAS, + { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, + ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)), + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, + 0, /* Irq */ + 365, /* GlobalSystemInterrupt */ + 0, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, + 0, /* Flow Control */ + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_VT_UTF8, + EFI_ACPI_RESERVED_BYTE, /* Language */ + 0xFFFF, /* PciDeviceId */ + 0xFFFF, /* PciVendorId */ + 0x00, /* PciBusNumber */ + 0x00, /* PciDeviceNumber */ + 0x00, /* PciFunctionNumber */ + 0, /* PciFlags */ + 0, /* PciSegment */ + EFI_ACPI_RESERVED_DWORD +}; + +#pragma pack(pop) + +// Reference the table being generated to prevent the optimizer from removing +// the data structure from the executable +VOID* CONST ReferenceAcpiTable = &Spcr; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Spi.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Spi.asl new file mode 100644 index 0000000..f9b5971 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Spi.asl @@ -0,0 +1,145 @@ +/** @file + * + * Copyright (c) 2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ +#include "AcpiTables.h" + +Device (SPI0) +{ + Name (_HID, "PRP0001") + Name (_UID, 3) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfeb00000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 358 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk3036-spi" }, + Package () { "clock-frequency", 200000000 }, + Package () { "num-cs", 2 }, + } + }) +} + +Device (SPI1) +{ + Name (_HID, "PRP0001") + Name (_UID, 3) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfeb10000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 359 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk3036-spi" }, + Package () { "clock-frequency", 200000000 }, + Package () { "num-cs", 2 }, + } + }) +} + +Device (SPI2) +{ + Name (_HID, "PRP0001") + Name (_UID, 3) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfeb20000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 360 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk3036-spi" }, + Package () { "clock-frequency", 200000000 }, + Package () { "num-cs", 2 }, + } + }) +} + +Device (SPI3) +{ + Name (_HID, "PRP0001") + Name (_UID, 3) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfeb30000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 361 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk3036-spi" }, + Package () { "clock-frequency", 200000000 }, + Package () { "num-cs", 2 }, + } + }) +} + +Device (SPI4) +{ + Name (_HID, "PRP0001") + Name (_UID, 3) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfecb0000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 362 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,rk3036-spi" }, + Package () { "clock-frequency", 200000000 }, + Package () { "num-cs", 2 }, + } + }) +} + +Device (SFC0) +{ + Name (_HID, "PRP0001") + Name (_UID, 3) + Name (_CCA, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfe2b0000, 0x4000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 238 } + }) + Return (RBUF) + } + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "compatible", "rockchip,sfc" }, + Package () { "clock-frequency", 100000000 }, + } + }) +} \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Uart.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Uart.asl new file mode 100644 index 0000000..8643c4a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Uart.asl @@ -0,0 +1,36 @@ +/** @file + * + * [DSDT] Serial devices (UART). + * + * Copyright (c) 2021, ARM Limited. All rights reserved. + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2018, Andrey Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +Device(UAR2) { + Name (_HID, "HISI0031") + Name (_UID, 2) + Name (_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xfeb50000, 0x1000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 365 } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "reg-shift", 2 }, + Package () { "reg-io-width", 4 }, + Package () { "clock-frequency", 24000000 }, + } + }) + + Method (_STA, 0, NotSerialized) { + Return(0x0F) + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb2Host.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb2Host.asl new file mode 100644 index 0000000..40a6df9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb2Host.asl @@ -0,0 +1,198 @@ +/** @file + * + * USB 2.0 (EHCI + OHCI) controllers. + * + * Copyright (c) 2022, Rockchip Electronics Co., Ltd + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "AcpiTables.h" + +Scope (\_SB_) { + Name (EHID, 1) // Expose EHCI PNP _CID + + Device (EHC0) { + Name (_HID, "RKCP0D20") + If (EHID == 1) { + Name (_CID, "PNP0D20") + } + Name (_UID, Zero) + Name (_CCA, Zero) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xFC800000, 0x40000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 247 } + }) + Return (RBUF) + } + + Device (RHUB) { + Name (_ADR, 0) + Device (PRT1) { + Name (_ADR, 1) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Connector type - Type 'A' + 0x00000000, // Reserved, must be zero + 0x00000000 // Reserved, must be zero + }) + Name (_PLD, Package (0x01) { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_UserVisible = 0x1, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "HORIZONTALRECTANGLE", + PLD_Ejectable = 0x1, + PLD_EjectRequired = 0x1, + ) + }) + } + } + } + + Device (EHC1) { + Name (_HID, "RKCP0D20") + If (EHID == 1) { + Name (_CID, "PNP0D20") + } + Name (_UID, One) + Name (_CCA, Zero) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xFC880000, 0x40000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 250 } + }) + Return (RBUF) + } + + Device (RHUB) { + Name (_ADR, 0) + Device (PRT1) { + Name (_ADR, 1) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Connector type - Type 'A' + 0x00000000, // Reserved, must be zero + 0x00000000 // Reserved, must be zero + }) + Name (_PLD, Package (0x01) { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_UserVisible = 0x1, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "LOWER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "HORIZONTALRECTANGLE", + PLD_Ejectable = 0x1, + PLD_EjectRequired = 0x1, + ) + }) + } + } + } + + Device (OHC0) { + Name (_HID, "PRP0001") + Name (_CLS, Package() { 0x0c, 0x03, 0x10 }) + Name (_UID, Zero) + Name (_CCA, Zero) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "generic-ohci" }, + } + }) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xFC840000, 0x40000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 248 } + }) + Return (RBUF) + } + + Device (RHUB) { + Name (_ADR, 0) + Device (PRT1) { + Name (_ADR, 1) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Connector type - Type 'A' + 0x00000000, // Reserved, must be zero + 0x00000000 // Reserved, must be zero + }) + Name (_PLD, Package (0x01) { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_UserVisible = 0x1, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "UPPER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "HORIZONTALRECTANGLE", + PLD_Ejectable = 0x1, + PLD_EjectRequired = 0x1, + ) + }) + } + } + } + + Device (OHC1) { + Name (_HID, "PRP0001") + Name (_CLS, Package() { 0x0c, 0x03, 0x10 }) + Name (_UID, One) + Name (_CCA, Zero) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", "generic-ohci" }, + } + }) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xFC8C0000, 0x40000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 251 } + }) + Return (RBUF) + } + + Device (RHUB) { + Name (_ADR, 0) + Device (PRT1) { + Name (_ADR, 1) + Name (_UPC, Package() { + 0xFF, // Port is connectable + 0x00, // Connector type - Type 'A' + 0x00000000, // Reserved, must be zero + 0x00000000 // Reserved, must be zero + }) + Name (_PLD, Package (0x01) { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_UserVisible = 0x1, + PLD_Panel = "UNKNOWN", + PLD_VerticalPosition = "LOWER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "HORIZONTALRECTANGLE", + PLD_Ejectable = 0x1, + PLD_EjectRequired = 0x1, + ) + }) + } + } + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host0.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host0.asl new file mode 100644 index 0000000..a83aaf8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host0.asl @@ -0,0 +1,23 @@ +/** @file +* DWC3 XHCI controller #0 in host mode. +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "AcpiTables.h" + +Device (XHC0) { + Name (_HID, "PNP0D10") + Name (_UID, Zero) + Name (_CCA, Zero) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfc000000, 0x400000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 252 } + }) + Return (RBUF) + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host1.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host1.asl new file mode 100644 index 0000000..ed758e0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host1.asl @@ -0,0 +1,23 @@ +/** @file +* DWC3 XHCI controller #1 in host mode. (only exposed on full RK3588) +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "AcpiTables.h" + +Device (XHC1) { + Name (_HID, "PNP0D10") + Name (_UID, One) + Name (_CCA, Zero) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfc400000, 0x400000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 253 } + }) + Return (RBUF) + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host2.asl b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host2.asl new file mode 100644 index 0000000..0325410 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/AcpiTables/Usb3Host2.asl @@ -0,0 +1,26 @@ +/** @file +* DWC3 XHCI controller #2 in host mode. +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "AcpiTables.h" + +// This only supports USB 3.0 devices. +// USB2 DP / DM are connected to one of the EHCI controllers instead (EHC1 usually). + +Device (XHC2) { + Name (_HID, "PNP0D10") + Name (_UID, 2) + Name (_CCA, Zero) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xfcd00000, 0x400000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 254 } + }) + Return (RBUF) + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c new file mode 100644 index 0000000..9287f74 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c @@ -0,0 +1,581 @@ +/** @file + * + * ACPI platform driver + * + * Copyright (c) 2020, Jeremy Linton + * Copyright (c) 2024, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC CONST EFI_GUID mAcpiTableFile = { + 0x7E374E25, 0x8E01, 0x4FEE, { 0x87, 0xf2, 0x39, 0x0C, 0x23, 0xC6, 0x06, 0xCD } +}; + +STATIC EFI_EXIT_BOOT_SERVICES mOriginalExitBootServices; + +STATIC EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol; +STATIC EFI_ACPI_DESCRIPTION_HEADER *mDsdtTable; + +STATIC BOOLEAN mIsSdmmcBoot = FALSE; + +typedef enum { + AcpiOsUnknown = 0, + AcpiOsWindows, +} ACPI_OS_BOOT_TYPE; + +#define SDT_PATTERN_LEN (AML_NAME_SEG_SIZE + 1) + +// +// Simple NameOp integer patcher. +// Does not allocate memory and can be safely used at ExitBootServices. +// +STATIC +EFI_STATUS +AcpiUpdateSdtNameInteger ( + IN EFI_ACPI_DESCRIPTION_HEADER *AcpiTable, + IN CHAR8 Name[AML_NAME_SEG_SIZE], + IN UINTN Value + ) +{ + UINTN Index; + CHAR8 Pattern[SDT_PATTERN_LEN]; + UINT8 *SdtPtr; + UINT32 DataSize; + UINT32 ValueOffset; + + if (AcpiTable->Length <= SDT_PATTERN_LEN) { + return EFI_INVALID_PARAMETER; + } + + SdtPtr = (UINT8 *)AcpiTable; + // + // Do a single NameOp variable replacement. These are of the + // form "08 XXXX SIZE VAL", where SIZE is: 0A=byte, 0B=word, 0C=dword, + // XXXX is the name and VAL is the value. + // + Pattern[0] = AML_NAME_OP; + CopyMem (Pattern + 1, Name, AML_NAME_SEG_SIZE); + + ValueOffset = SDT_PATTERN_LEN + 1; + + for (Index = 0; Index < (AcpiTable->Length - SDT_PATTERN_LEN); Index++) { + if (CompareMem (SdtPtr + Index, Pattern, SDT_PATTERN_LEN) == 0) { + switch (SdtPtr[Index + SDT_PATTERN_LEN]) { + case AML_QWORD_PREFIX: + DataSize = sizeof (UINT64); + break; + case AML_DWORD_PREFIX: + DataSize = sizeof (UINT32); + break; + case AML_WORD_PREFIX: + DataSize = sizeof (UINT16); + break; + case AML_ONE_OP: + case AML_ZERO_OP: + ValueOffset--; + // Fallthrough + case AML_BYTE_PREFIX: + DataSize = sizeof (UINT8); + break; + default: + return EFI_UNSUPPORTED; + } + CopyMem (SdtPtr + Index + ValueOffset, &Value, DataSize); + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; +} + +STATIC +VOID +EFIAPI +AcpiDsdtFixupStatus ( + IN EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol, + IN EFI_ACPI_HANDLE TableHandle + ) +{ + EFI_STATUS Status; + UINTN Index; + + struct { + CHAR8 *ObjectPath; + BOOLEAN Enabled; + } DevStatus[] = { + { "\\_SB.PCI0._STA", FixedPcdGetBool (PcdPcie30Supported) && + PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED }, + { "\\_SB.PCI1._STA", PcdGet8 (PcdPcie30PhyMode) != PCIE30_PHY_MODE_AGGREGATION }, + { "\\_SB.PCI2._STA", PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_PCIE }, + { "\\_SB.PCI3._STA", PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_PCIE }, + { "\\_SB.PCI4._STA", PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_PCIE }, + { "\\_SB.ATA0._STA", PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_SATA }, + { "\\_SB.ATA1._STA", PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_SATA }, + { "\\_SB.ATA2._STA", PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_SATA }, + }; + + for (Index = 0; Index < ARRAY_SIZE (DevStatus); Index++) { + if (DevStatus[Index].Enabled == FALSE) { + Status = AcpiAmlObjectUpdateInteger (AcpiSdtProtocol, TableHandle, + DevStatus[Index].ObjectPath, 0x0); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Failed to patch %a. Status=%r\n", + DevStatus[Index].ObjectPath, Status)); + } + } + } +} + +STATIC +VOID +EFIAPI +NotifyEndOfDxeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + UINTN TableKey; + UINTN TableIndex; + EFI_ACPI_HANDLE TableHandle; + + Status = gBS->LocateProtocol ( + &gEfiAcpiSdtProtocolGuid, + NULL, + (VOID **)&mAcpiSdtProtocol); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't locate gEfiAcpiSdtProtocolGuid! Status=%r\n", Status)); + return; + } + + Status = LocateAndInstallAcpiFromFvConditional (&mAcpiTableFile, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "AcpiPlatform: Failed to install firmware ACPI as config table. Status=%r\n", + Status)); + } + + TableIndex = 0; + Status = AcpiLocateTableBySignature ( + mAcpiSdtProtocol, + EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + &TableIndex, + &mDsdtTable, + &TableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't locate ACPI DSDT table!\n", __func__)); + return; + } + + Status = mAcpiSdtProtocol->OpenSdt (TableKey, &TableHandle); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't open ACPI DSDT table!\n", __func__)); + mAcpiSdtProtocol->Close (TableHandle); + return; + } + + AcpiDsdtFixupStatus (mAcpiSdtProtocol, TableHandle); + + mAcpiSdtProtocol->Close (TableHandle); +} + +STATIC +EFI_STATUS +EFIAPI +AcpiFixupPcieEcam ( + IN ACPI_OS_BOOT_TYPE OsType + ) +{ + EFI_STATUS Status; + UINTN Index; + RK3588_MCFG_TABLE *McfgTable; + EFI_ACPI_DESCRIPTION_HEADER *FadtTable; + UINTN TableKey; + UINT32 PcieEcamMode; + UINT8 PcieBusMin; + UINT8 PcieBusMax; + UINT8 McfgMainBusMin; + BOOLEAN McfgSplitRootPort; + BOOLEAN McfgSingleDevQuirk; + + Index = 0; + Status = AcpiLocateTableBySignature ( + mAcpiSdtProtocol, + EFI_ACPI_6_4_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, + &Index, + (EFI_ACPI_DESCRIPTION_HEADER **)&McfgTable, + &TableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't locate ACPI MCFG table! Status=%r\n", + Status)); + return Status; + } + + PcieEcamMode = PcdGet32 (PcdAcpiPcieEcamCompatMode); + + if (PcieEcamMode == ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV || + PcieEcamMode == ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON) { + if (OsType == AcpiOsWindows) { + PcieEcamMode = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6; + } else { + PcieEcamMode &= ~ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6; + } + } + + switch (PcieEcamMode) { + case ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6: + PcieBusMin = 0; + PcieBusMax = PCIE_BUS_LIMIT; + McfgMainBusMin = 1; + McfgSplitRootPort = TRUE; + McfgSingleDevQuirk = FALSE; + + Index = 0; + Status = AcpiLocateTableBySignature ( + mAcpiSdtProtocol, + EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, + &Index, + &FadtTable, + &TableKey); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Couldn't locate ACPI FADT table! Status=%r\n", + Status)); + return Status; + } + + CopyMem (FadtTable->OemId, "NXPMX6", sizeof (FadtTable->OemId)); + AcpiUpdateChecksum ((UINT8 *)FadtTable, FadtTable->Length); + break; + + case ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON: + PcieBusMin = 0; + PcieBusMax = PCIE_BUS_LIMIT; + McfgMainBusMin = 0; + McfgSplitRootPort = FALSE; + McfgSingleDevQuirk = FALSE; + + CopyMem (McfgTable->Header.Header.OemId, "AMAZON", sizeof (McfgTable->Header.Header.OemId)); + McfgTable->Header.Header.OemTableId = SIGNATURE_64 ('G','R','A','V','I','T','O','N'); + break; + + default: // ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV + PcieBusMin = 1; + PcieBusMax = 1; + McfgMainBusMin = 1; + McfgSplitRootPort = FALSE; + McfgSingleDevQuirk = TRUE; + break; + } + + for (Index = 0; Index < ARRAY_SIZE (McfgTable->MainEntries); Index++) { + if (McfgSingleDevQuirk) { + if ((PcdGet32 (PcdPcieEcamCompliantSegmentsMask) & (1 << Index)) == 0) { + McfgTable->MainEntries[Index].BaseAddress += 0x8000; + } + } + McfgTable->MainEntries[Index].StartBusNumber = McfgMainBusMin; + McfgTable->MainEntries[Index].EndBusNumber = PcieBusMax; + } + + if (McfgSplitRootPort == FALSE) { + McfgTable->Header.Header.Length -= sizeof (McfgTable->RootPortEntries); + } + + AcpiUpdateChecksum ((UINT8 *)McfgTable, McfgTable->Header.Header.Length); + + AcpiUpdateSdtNameInteger (mDsdtTable, "PBMI", PcieBusMin); + AcpiUpdateSdtNameInteger (mDsdtTable, "PBMA", PcieBusMax); + + return EFI_SUCCESS; +} + +STATIC +VOID +EFIAPI +AcpiPlatformOsBootHandler ( + IN ACPI_OS_BOOT_TYPE OsType + ) +{ + if (mAcpiSdtProtocol == NULL || mDsdtTable == NULL) { + return; + } + + // + // Hide EHCI PNP ID for Windows to avoid binding to the inbox driver, + // which by default uses atomics on uncached memory and would crash + // the system. + // + if (OsType == AcpiOsWindows) { + AcpiUpdateSdtNameInteger (mDsdtTable, "EHID", 0); + } + + // + // If the boot device is SDMMC, mark the slot as non-removable. + // This allows Windows to create a page file on it. + // + if (mIsSdmmcBoot) { + AcpiUpdateSdtNameInteger (mDsdtTable, "SDRM", 0); + } + + AcpiFixupPcieEcam (OsType); + + AcpiUpdateChecksum ((UINT8 *)mDsdtTable, mDsdtTable->Length); +} + +STATIC +UINTN +EFIAPI +FindPeImageBase ( + EFI_PHYSICAL_ADDRESS Base + ) +{ + EFI_IMAGE_DOS_HEADER *DosHdr; + EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr; + + Base &= ~(EFI_PAGE_SIZE - 1); + + while (Base != 0) { + DosHdr = (EFI_IMAGE_DOS_HEADER *)Base; + if (DosHdr->e_magic == EFI_IMAGE_DOS_SIGNATURE) { + Hdr.Pe32 = (EFI_IMAGE_NT_HEADERS32 *)(Base + DosHdr->e_lfanew); + if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE) { + break; + } + } + + Base -= EFI_PAGE_SIZE; + } + + return Base; +} + +STATIC CHAR8 mWinLoadNameStr[] = "winload"; +#define PDB_NAME_MAX_LENGTH 256 + +STATIC +BOOLEAN +IsPeImageWinLoader ( + IN VOID *PeImage + ) +{ + CHAR8 *PdbStr; + UINTN Index; + + PdbStr = (CHAR8 *)PeCoffLoaderGetPdbPointer (PeImage); + if (PdbStr == NULL) { + return FALSE; + } + + for (Index = 0; Index < PDB_NAME_MAX_LENGTH && PdbStr[Index] != '\0'; Index++) { + if (AsciiStrnCmp (PdbStr + Index, mWinLoadNameStr, sizeof (mWinLoadNameStr) - sizeof (CHAR8)) == 0) { + return TRUE; + } + } + + return FALSE; +} + +STATIC +EFI_STATUS +EFIAPI +AcpiPlatformExitBootServicesHook ( + IN EFI_HANDLE ImageHandle, + IN UINTN MapKey + ) +{ + UINTN ReturnAddress; + UINTN OsLoaderAddress; + ACPI_OS_BOOT_TYPE OsType; + + ReturnAddress = (UINTN)RETURN_ADDRESS (0); + + gBS->ExitBootServices = mOriginalExitBootServices; + + OsType = AcpiOsUnknown; + + OsLoaderAddress = FindPeImageBase (ReturnAddress); + if (OsLoaderAddress > 0) { + if (IsPeImageWinLoader ((VOID *)OsLoaderAddress)) { + OsType = AcpiOsWindows; + } + } + + AcpiPlatformOsBootHandler (OsType); + + return gBS->ExitBootServices (ImageHandle, MapKey); +} + +STATIC +BOOLEAN +IsDeviceSdmmc ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_HANDLE DeviceHandle; + NON_DISCOVERABLE_DEVICE *Device; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + + DevicePath = DevicePathFromHandle (Handle); + + if (DevicePath == NULL + || DevicePath->Type != HARDWARE_DEVICE_PATH + || DevicePath->SubType != HW_VENDOR_DP) { + return FALSE; + } + + Status = gBS->LocateDevicePath (&gEdkiiNonDiscoverableDeviceProtocolGuid, + &DevicePath, &DeviceHandle); + if (EFI_ERROR (Status)) { + return FALSE; + } + + Status = gBS->HandleProtocol (DeviceHandle, + &gEdkiiNonDiscoverableDeviceProtocolGuid, (VOID **) &Device); + if (EFI_ERROR (Status)) { + return FALSE; + } + + Descriptor = &Device->Resources[0]; + + if (Descriptor->Desc != ACPI_ADDRESS_SPACE_DESCRIPTOR || + Descriptor->ResType != ACPI_ADDRESS_SPACE_TYPE_MEM) { + return FALSE; + } + + return Descriptor->AddrRangeMin == PcdGet32 (PcdRkSdmmcBaseAddress); +} + + +STATIC VOID *mLoadedImageEventRegistration; + +STATIC +VOID +EFIAPI +NotifyLoadedImage ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN HandleCount; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + + while (TRUE) { + Status = gBS->LocateHandleBuffer ( + ByRegisterNotify, + NULL, + mLoadedImageEventRegistration, + &HandleCount, + &Handles + ); + if (EFI_ERROR (Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Failed to locate gEfiLoadedImageProtocolGuid. Status=%r\n", + Status)); + } + break; + } + ASSERT (HandleCount == 1); + + Status = gBS->HandleProtocol ( + Handles[0], + &gEfiLoadedImageProtocolGuid, + (VOID **)&LoadedImage + ); + FreePool (Handles); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "AcpiPlatform: Failed to get gEfiLoadedImageProtocolGuid. Status=%r\n", + Status)); + break; + } + + if (LoadedImage->DeviceHandle == NULL) { + continue; + } + + // + // If the last image was loaded from SDMMC, then assume that's + // the boot device. + // + mIsSdmmcBoot = IsDeviceSdmmc (LoadedImage->DeviceHandle); + } +} + +STATIC +VOID +EFIAPI +NotifyReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gBS->CloseEvent (Event); + + EfiCreateProtocolNotifyEvent ( + &gEfiLoadedImageProtocolGuid, + TPL_CALLBACK, + NotifyLoadedImage, + NULL, + &mLoadedImageEventRegistration + ); +} + +EFI_STATUS +EFIAPI +AcpiPlatformDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + if ((PcdGet32 (PcdConfigTableMode) & CONFIG_TABLE_MODE_ACPI) == 0) { + DEBUG ((DEBUG_WARN, "AcpiPlatform: ACPI support is disabled by the settings.\n")); + return EFI_UNSUPPORTED; + } + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, // Type + TPL_CALLBACK, // NotifyTpl + NotifyEndOfDxeEvent, // NotifyFunction + NULL, // NotifyContext + &gEfiEndOfDxeEventGroupGuid, // EventGroup + &Event // Event + ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, // Type + TPL_CALLBACK, // NotifyTpl + NotifyReadyToBoot, // NotifyFunction + NULL, // NotifyContext + &gEfiEventReadyToBootGuid, // EventGroup + &Event // Event + ); + ASSERT_EFI_ERROR (Status); + + mOriginalExitBootServices = gBS->ExitBootServices; + gBS->ExitBootServices = AcpiPlatformExitBootServicesHook; + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf new file mode 100644 index 0000000..a3ddbc6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf @@ -0,0 +1,63 @@ +#/** @file +# +# ACPI platform driver +# +# Copyright (c) 2024, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = AcpiPlatformDxe + FILE_GUID = 1f7decf3-c2dc-49ee-a932-8074718cdc6d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = AcpiPlatformDxeInitialize + +[Sources] + AcpiPlatformDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + AcpiLib + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + MemoryAllocationLib + PeCoffGetEntryPointLib + UefiBootServicesTableLib + UefiLib + UefiDriverEntryPoint + +[Guids] + gEfiEndOfDxeEventGroupGuid + gEfiEventReadyToBootGuid + +[Protocols] + gEdkiiNonDiscoverableDeviceProtocolGuid + gEfiAcpiSdtProtocolGuid + gEfiLoadedImageProtocolGuid + +[Pcd] + gRK3588TokenSpaceGuid.PcdConfigTableMode + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatMode + gRK3588TokenSpaceGuid.PcdComboPhy0Mode + gRK3588TokenSpaceGuid.PcdComboPhy1Mode + gRK3588TokenSpaceGuid.PcdComboPhy2Mode + gRK3588TokenSpaceGuid.PcdPcie30Supported + gRK3588TokenSpaceGuid.PcdPcie30State + gRK3588TokenSpaceGuid.PcdPcie30PhyMode + gRK3588TokenSpaceGuid.PcdPcieEcamCompliantSegmentsMask + gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress + +[Depex] + gRockchipPlatformConfigAppliedProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.c new file mode 100644 index 0000000..04cb8a8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.c @@ -0,0 +1,717 @@ +/** @file + * + * Flattened Device Tree platform driver + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define MAX_PATH_LENGTH 512 + +STATIC VOID *mPlatformFdt; +STATIC VOID *mLoadedImageEventRegistration; + +STATIC +INTN +EFIAPI +StriCmp ( + IN CONST CHAR16 *String1, + IN CONST CHAR16 *String2 + ) +{ + while ((*String1 != L'\0') && + (CharToUpper (*String1) == CharToUpper (*String2))) { + String1++; + String2++; + } + + return CharToUpper (*String1) - CharToUpper (*String2); +} + +STATIC +BOOLEAN +EFIAPI +StrEndsWith ( + IN CONST CHAR16 *String, + IN CONST CHAR16 *Extension + ) +{ + UINTN StringLength = StrLen (String); + UINTN ExtensionLength = StrLen (Extension); + + if (StringLength < ExtensionLength) { + return FALSE; + } + + return StriCmp (String + StringLength - ExtensionLength, Extension) == 0; +} + +STATIC +EFI_STATUS +EFIAPI +FdtOpenIntoAlloc ( + IN OUT VOID **Fdt, + IN OUT VOID **DestinationFdt, OPTIONAL + IN UINTN Size + ) +{ + VOID *NewFdt; + INTN Ret; + + NewFdt = AllocatePool (Size); + if (NewFdt == NULL) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Not enough resources to reallocate FDT (%d bytes).\n", + Size)); + return EFI_OUT_OF_RESOURCES; + } + + Ret = fdt_open_into (*Fdt, NewFdt, Size); + if (Ret) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to copy FDT. Ret=%a\n", fdt_strerror (Ret))); + FreePool (NewFdt); + return EFI_LOAD_ERROR; + } + + if (DestinationFdt != NULL) { + *DestinationFdt = NewFdt; + } else { + FreePool (*Fdt); + *Fdt = NewFdt; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +ReadFdtFromFilePath ( + IN EFI_FILE_PROTOCOL *Root, + IN CHAR16 *Path, + IN OUT UINTN *FileSize, OPTIONAL + IN OUT VOID **Fdt + ) +{ + EFI_STATUS Status; + EFI_FILE_PROTOCOL *File; + UINTN FileBufferSize; + UINTN FileInfoSize; + EFI_FILE_INFO *FileInfo = NULL; + INT32 Ret; + + Status = Root->Open (Root, &File, Path, EFI_FILE_MODE_READ, 0); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Couldn't open '%s'. Status=%r\n", Path, Status)); + return Status; + } + + if (FileSize == NULL) { + FileInfoSize = 0; + Status = File->GetInfo (File, &gEfiFileInfoGuid, &FileInfoSize, NULL); + if (EFI_ERROR (Status) && FileInfoSize == 0) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to get '%s' file info size. Status=%r\n", + Path, Status)); + goto Exit; + } + + FileInfo = AllocatePool (FileInfoSize); + if (FileInfo == NULL) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Not enough resources for '%s' file info (%d bytes).\n", + Path, FileInfoSize)); + Status = EFI_OUT_OF_RESOURCES; + goto Exit; + } + + Status = File->GetInfo (File, &gEfiFileInfoGuid, &FileInfoSize, FileInfo); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to get '%s' file info. Status=%r\n", + Path, Status)); + goto Exit; + } + FileBufferSize = FileInfo->FileSize; + } else { + FileBufferSize = *FileSize; + } + + *Fdt = AllocatePool (FileBufferSize); + if (*Fdt == NULL) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Not enough resources for '%s' file buffer (%d bytes).\n", + Path, FileBufferSize)); + Status = EFI_OUT_OF_RESOURCES; + goto Exit; + } + + Status = File->Read (File, &FileBufferSize, *Fdt); + if (EFI_ERROR (Status)) { + if (FileSize != NULL) { + *FileSize = FileBufferSize; + } + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to read '%s' (%d bytes). Status=%r\n", + Path, FileBufferSize, Status)); + goto Exit; + } + + Ret = fdt_check_header (*Fdt); + if (Ret) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: '%s' has an invalid header! Ret=%a\n", + Path, fdt_strerror (Ret))); + Status = EFI_NOT_FOUND; + goto Exit; + } + +Exit: + Root->Close (File); + if (FileInfo != NULL) { + FreePool (FileInfo); + } + if (EFI_ERROR (Status) && *Fdt != NULL) { + FreePool (*Fdt); + *Fdt = NULL; + } + return Status; +} + +#define FDT_GET_USED_SIZE(Fdt) (fdt_off_dt_struct (Fdt) \ + + fdt_size_dt_struct (Fdt) \ + + fdt_size_dt_strings (Fdt)) + +STATIC +EFI_STATUS +EFIAPI +InstallOverlaysFromDirectoryPath ( + IN EFI_FILE_PROTOCOL *Root, + IN CHAR16 *Path, + IN OUT VOID **Fdt, + IN OUT UINTN *OverlaysCount + ) +{ + EFI_STATUS Status; + EFI_FILE_PROTOCOL *Dir; + UINTN DirEntryInfoSize; + UINTN CurrentInfoSize; + EFI_FILE_INFO *DirEntryInfo; + VOID *FdtOverlay; + UINTN FdtSize; + INT32 Ret; + + Status = Root->Open (Root, &Dir, Path, EFI_FILE_MODE_READ, 0); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Couldn't open directory '%s'. Status=%r\n", + Path, Status)); + return Status; + } + + DirEntryInfoSize = sizeof (EFI_FILE_INFO) + MAX_PATH_LENGTH; + DirEntryInfo = AllocatePool (DirEntryInfoSize); + if (DirEntryInfo == NULL) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Not enough resources for '%s' directory entry info.\n", + Path)); + Root->Close (Dir); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "FdtPlatform: Processing overlays in sub-directory '%s'\n", Path)); + + while (TRUE) { + CurrentInfoSize = DirEntryInfoSize; + Status = Dir->Read (Dir, &CurrentInfoSize, (VOID *) DirEntryInfo); + if (EFI_ERROR (Status) || CurrentInfoSize == 0) { + // Reached end of directory? + ASSERT (CurrentInfoSize <= DirEntryInfoSize); + ASSERT_EFI_ERROR (Status); + break; + } + + if (DirEntryInfo->Attribute & EFI_FILE_DIRECTORY) { + continue; + } + + if (!StrEndsWith (DirEntryInfo->FileName, L".dtbo")) { + continue; + } + + DEBUG ((DEBUG_INFO, "FdtPlatform: Installing overlay '%s'\n", + DirEntryInfo->FileName)); + + Status = ReadFdtFromFilePath (Dir, DirEntryInfo->FileName, + &DirEntryInfo->FileSize, &FdtOverlay); + if (EFI_ERROR (Status)) { + if (Status == EFI_OUT_OF_RESOURCES) { + break; + } + continue; + } + + FdtSize = FDT_GET_USED_SIZE (*Fdt); + if (FdtSize + DirEntryInfo->FileSize >= fdt_totalsize (*Fdt)) { + // + // Expand the buffer by at least 8 KB, so we don't end up + // reallocating for every small overlay. + // + FdtSize = fdt_totalsize (*Fdt) + MAX (DirEntryInfo->FileSize, SIZE_8KB); + Status = FdtOpenIntoAlloc (Fdt, NULL, FdtSize); + if (EFI_ERROR (Status)) { + FreePool (FdtOverlay); + break; + } + } + + Ret = fdt_overlay_apply (*Fdt, FdtOverlay); + FreePool (FdtOverlay); + if (Ret) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to apply overlay '%s' (%d bytes). Ret=%a\n", + DirEntryInfo->FileName, DirEntryInfo->FileSize, fdt_strerror (Ret))); + + if (Ret == -FDT_ERR_NOSPACE) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: FDT bytes used: %d, total: %d\n", + FDT_GET_USED_SIZE (*Fdt), fdt_totalsize (*Fdt))); + } + // + // The FDT is damaged at this point, we can't continue. + // + Status = EFI_LOAD_ERROR; + break; + } + + *OverlaysCount += 1; + } + + FreePool (DirEntryInfo); + Root->Close (Dir); + + return Status; +} + +STATIC CHAR16 mDtbOverrideRootPath[] = L"\\dtb"; + +STATIC +EFI_STATUS +EFIAPI +FdtPlatformProcessFileSystem ( + IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *FileSystem + ) +{ + EFI_STATUS Status; + EFI_FILE_PROTOCOL *Root; + EFI_FILE_PROTOCOL *DtbDir; + UINTN PathSize; + CHAR16 *Path; + CHAR8 *FdtName; + VOID *Fdt = NULL; + VOID *NewFdt = NULL; + VOID *FdtToInstall = NULL; + UINTN OverlaysCount = 0; + + Status = FileSystem->OpenVolume (FileSystem, &Root); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to open volume. Status=%r\n", Status)); + return Status; + } + + Status = Root->Open (Root, &DtbDir, mDtbOverrideRootPath, EFI_FILE_MODE_READ, 0); + if (EFI_ERROR (Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to open directory '%s'. Status=%r\n", + mDtbOverrideRootPath, Status)); + } + return Status; + } else { + DEBUG ((DEBUG_INFO, "FdtPlatform: Found override directory '%s'.\n", + mDtbOverrideRootPath)); + } + + PathSize = MAX_PATH_LENGTH * sizeof (CHAR16); + Path = AllocatePool (PathSize); + if (Path == NULL) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Not enough resources for '%s' access path.\n", + mDtbOverrideRootPath)); + Root->Close (DtbDir); + return EFI_OUT_OF_RESOURCES; + } + + FdtName = FixedPcdGetPtr (PcdDeviceTreeName); + + // + // Try to open the FDT override. + // + UnicodeSPrint (Path, PathSize, L"base\\%a.dtb", FdtName); + Status = ReadFdtFromFilePath (DtbDir, Path, NULL, &Fdt); + if (EFI_ERROR (Status)) { + if (mPlatformFdt == NULL) { + goto Exit; + } + Fdt = mPlatformFdt; + } else { + DEBUG ((DEBUG_INFO, "FdtPlatform: Loaded FDT override '%s'.\n", Path)); + } + + // + // Clone the FDT so that we can restore the original one + // in case it gets damaged. + // + Status = FdtOpenIntoAlloc (&Fdt, &NewFdt, fdt_totalsize (Fdt)); + if (EFI_ERROR (Status)) { + goto Exit; + } + + // + // Process the overlays common to all platforms. + // + Status = InstallOverlaysFromDirectoryPath (DtbDir, L"overlays", &NewFdt, &OverlaysCount); + if (Status == EFI_LOAD_ERROR || Status == EFI_OUT_OF_RESOURCES) { + goto Exit; + } + + // + // Process the platform-specific overlays. + // + UnicodeSPrint (Path, PathSize, L"overlays\\%a", FdtName); + Status = InstallOverlaysFromDirectoryPath (DtbDir, Path, &NewFdt, &OverlaysCount); + if (Status == EFI_LOAD_ERROR || Status == EFI_OUT_OF_RESOURCES) { + goto Exit; + } + +Exit: + Root->Close (DtbDir); + FreePool (Path); + + if (NewFdt != NULL) { + if (fdt_check_header (NewFdt) == 0) { + FdtToInstall = NewFdt; + DEBUG ((DEBUG_INFO, "FdtPlatform: Using FDT with %d overlays merged.\n", OverlaysCount)); + } else { + FreePool (NewFdt); + } + } + if (Fdt != NULL && Fdt != mPlatformFdt) { + if (FdtToInstall == NULL && fdt_check_header (Fdt) == 0) { + FdtToInstall = Fdt; + DEBUG ((DEBUG_INFO, "FdtPlatform: Using original FDT without overlays.\n")); + } else { + FreePool (Fdt); + } + } + + if (FdtToInstall != NULL) { + Status = gBS->InstallConfigurationTable (&gFdtTableGuid, FdtToInstall); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to install the new FDT as config table. Status=%r\n", + Status)); + } + } + + return Status; +} + +STATIC +VOID +EFIAPI +NotifyLoadedImage ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN HandleCount; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *FileSystem; + + while (TRUE) { + Status = gBS->LocateHandleBuffer ( + ByRegisterNotify, + NULL, + mLoadedImageEventRegistration, + &HandleCount, + &Handles + ); + if (EFI_ERROR (Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to locate gEfiLoadedImageProtocolGuid. Status=%r\n", + Status)); + } + break; + } + ASSERT (HandleCount == 1); + + Status = gBS->HandleProtocol ( + Handles[0], + &gEfiLoadedImageProtocolGuid, + (VOID **)&LoadedImage + ); + FreePool (Handles); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to get gEfiLoadedImageProtocolGuid. Status=%r\n", + Status)); + break; + } + + if (LoadedImage->DeviceHandle == NULL) { + continue; + } + + Status = gBS->HandleProtocol ( + LoadedImage->DeviceHandle, + &gEfiSimpleFileSystemProtocolGuid, + (VOID **)&FileSystem + ); + if (EFI_ERROR (Status)) { + if (Status != EFI_UNSUPPORTED) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to get gEfiSimpleFileSystemProtocolGuid. Status=%r\n", + Status)); + } + continue; + } + + Status = FdtPlatformProcessFileSystem (FileSystem); + if (EFI_ERROR (Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to process the file system. Status=%r\n", Status)); + } + continue; + } + } +} + +STATIC +VOID +EFIAPI +NotifyReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gBS->CloseEvent (Event); + + EfiCreateProtocolNotifyEvent ( + &gEfiLoadedImageProtocolGuid, + TPL_CALLBACK, + NotifyLoadedImage, + NULL, + &mLoadedImageEventRegistration + ); +} + +STATIC +VOID +EFIAPI +NotifyExitBootServices ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + VOID *Dtb; + + Status = EfiGetSystemConfigurationTable (&gFdtTableGuid, &Dtb); + if (EFI_ERROR (Status) || Dtb == NULL) { + DEBUG ((DEBUG_WARN, "FdtPlatform: No FDT installed!\n")); + } else if (fdt_totalsize (Dtb) <= SIZE_4KB) { + // Some loaders may install a dummy table, warn in this case too. + DEBUG ((DEBUG_WARN, "FdtPlatform: No usable FDT installed!\n")); + } +} + +STATIC +EFI_STATUS +EFIAPI +FdtEnableNode ( + IN VOID *Fdt, + IN CONST CHAR8 *NodePath, + IN BOOLEAN Enable + ) +{ + INT32 Node; + INT32 Ret; + CHAR8 *NodeStatus; + + Node = fdt_path_offset (Fdt, NodePath); + if (Node < 0) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Couldn't locate FDT node path '%a'. Ret=%a\n", + NodePath, fdt_strerror (Node))); + return EFI_NOT_FOUND; + } + + NodeStatus = Enable ? "okay" : "disabled"; + Ret = fdt_setprop_string (Fdt, Node, "status", NodeStatus); + if (Ret) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Failed to set '%a' status to '%a'. Ret=%a\n", + NodePath, NodeStatus, fdt_strerror (Ret))); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +STATIC +VOID +EFIAPI +FdtFixupComboPhyDevices ( + IN VOID *Fdt + ) +{ + DEBUG ((DEBUG_INFO, "FdtPlatform: Fixing up Combo PHY devices (PCIe, SATA, USB)\n")); + + FdtEnableNode (Fdt, "/pcie@fe170000", + PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_PCIE); + FdtEnableNode (Fdt, "/pcie@fe180000", + PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_PCIE); + FdtEnableNode (Fdt, "/pcie@fe190000", + PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_PCIE); + + FdtEnableNode (Fdt, "/sata@fe210000", + PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_SATA); + FdtEnableNode (Fdt, "/sata@fe220000", + PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_SATA); + FdtEnableNode (Fdt, "/sata@fe230000", + PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_SATA); + + FdtEnableNode (Fdt, "/usbhost3_0", + PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_USB3); +} + +STATIC +VOID +EFIAPI +FdtFixupPcie3Devices ( + IN VOID *Fdt + ) +{ + if (!FixedPcdGetBool (PcdPcie30Supported)) { + return; + } + + DEBUG ((DEBUG_INFO, "FdtPlatform: Fixing up PCIe 3 devices\n")); + + FdtEnableNode (Fdt, "/pcie@fe150000", + PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED); + if (PcdGet8 (PcdPcie30PhyMode) != PCIE30_PHY_MODE_AGGREGATION) { + FdtEnableNode (Fdt, "/pcie@fe160000", + PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED); + } +} + +STATIC +VOID +EFIAPI +ApplyPlatformFdtFixups ( + IN VOID *Fdt + ) +{ + FdtFixupComboPhyDevices (Fdt); + FdtFixupPcie3Devices (Fdt); +} + +STATIC +EFI_STATUS +EFIAPI +LoadPlatformFdt ( + OUT VOID **PlatformFdt + ) +{ + EFI_STATUS Status; + VOID *Fdt; + UINTN FdtSize; + INT32 Ret; + + Status = GetSectionFromAnyFv ( + &gDtPlatformDefaultDtbFileGuid, + EFI_SECTION_RAW, + 0, + &Fdt, + &FdtSize + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Ret = fdt_check_header (Fdt); + if (Ret) { + DEBUG ((DEBUG_ERROR, "FdtPlatform: Firmware FDT has an invalid header! Ret=%a\n", + fdt_strerror (Ret))); + return EFI_NOT_FOUND; + } + + // Expand the FDT a bit to give room for any additions. + Status = FdtOpenIntoAlloc (&Fdt, NULL, fdt_totalsize (Fdt) + SIZE_1KB); + if (EFI_ERROR (Status)) { + return Status; + } + + *PlatformFdt = Fdt; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FdtPlatformDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + if ((PcdGet32 (PcdConfigTableMode) & CONFIG_TABLE_MODE_FDT) == 0) { + DEBUG ((DEBUG_WARN, "FdtPlatform: FDT support is disabled by the settings.\n")); + return EFI_UNSUPPORTED; + } + + if (PcdGet8 (PcdFdtSupportOverrides)) { + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, // Type + TPL_CALLBACK, // NotifyTpl + NotifyReadyToBoot, // NotifyFunction + NULL, // NotifyContext + &gEfiEventReadyToBootGuid, // EventGroup + &Event // Event + ); + ASSERT_EFI_ERROR (Status); + } + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, // Type + TPL_CALLBACK, // NotifyTpl + NotifyExitBootServices, // NotifyFunction + NULL, // NotifyContext + &gEfiEventExitBootServicesGuid, // EventGroup + &Event // Event + ); + ASSERT_EFI_ERROR (Status); + + Status = LoadPlatformFdt (&mPlatformFdt); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "FdtPlatform: Failed to load firmware FDT. Status=%r\n", Status)); + return EFI_SUCCESS; + } + + ApplyPlatformFdtFixups (mPlatformFdt); + + Status = gBS->InstallConfigurationTable (&gFdtTableGuid, mPlatformFdt); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "FdtPlatform: Failed to install firmware DTB as config table. Status=%r\n", + Status)); + } + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf new file mode 100644 index 0000000..2d2cae6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf @@ -0,0 +1,62 @@ +#/** @file +# +# Flattened Device Tree platform driver +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = FdtPlatformDxe + FILE_GUID = 5d028f9c-bb17-4ff5-8c61-dbb4474e4a13 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = FdtPlatformDxeInitialize + +[Sources] + FdtPlatformDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + BaseLib + DebugLib + PrintLib + DxeServicesLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + FdtLib + +[Guids] + gFdtTableGuid + gDtPlatformDefaultDtbFileGuid + gEfiEventReadyToBootGuid + gEfiEventExitBootServicesGuid + +[Protocols] + gEfiLoadedImageProtocolGuid + gEfiSimpleFileSystemProtocolGuid + +[Pcd] + gRockchipTokenSpaceGuid.PcdDeviceTreeName + gRK3588TokenSpaceGuid.PcdConfigTableMode + gRK3588TokenSpaceGuid.PcdFdtSupportOverrides + gRK3588TokenSpaceGuid.PcdComboPhy0Mode + gRK3588TokenSpaceGuid.PcdComboPhy1Mode + gRK3588TokenSpaceGuid.PcdComboPhy2Mode + gRK3588TokenSpaceGuid.PcdPcie30Supported + gRK3588TokenSpaceGuid.PcdPcie30State + gRK3588TokenSpaceGuid.PcdPcie30PhyMode + +[Depex] + gRockchipPlatformConfigAppliedProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/EthernetPhy.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/EthernetPhy.h new file mode 100644 index 0000000..367b105 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/EthernetPhy.h @@ -0,0 +1,50 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef ETHERNETPHY_H__ +#define ETHERNETPHY_H__ + +typedef +EFI_STATUS +(EFIAPI *ETHERNET_PHY_INIT) ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT32 PhyId + ); + +VOID +PhyRead ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT8 Phy, + IN UINT16 Reg, + OUT UINT16 *Value + ); + +VOID +PhyWrite ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT8 Phy, + IN UINT16 Reg, + IN UINT16 Value + ); + +EFI_STATUS +EFIAPI +RealtekPhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT32 PhyId + ); + +EFI_STATUS +EFIAPI +MotorcommPhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT32 PhyId + ); + +#endif /* ETHERNETPHY_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.c new file mode 100644 index 0000000..a3f2307 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.c @@ -0,0 +1,309 @@ +/** @file + * + * RK3588 GMAC initializer + * + * Copyright (c) 2021-2022, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#define CRU_SOFTRST_CON32 (CRU_BASE + 0x0A80) + +#define PHP_GRF_BASE 0xFD5B0000 +#define PHP_GRF_CLK_CON1 (PHP_GRF_BASE + 0x0070) +#define PHP_GRF_GMAC_CON0 (PHP_GRF_BASE + 0x0008) + +#define SYS_GRF_BASE 0xFD58C000 +#define SYS_GRF_SOC_CON7 (SYS_GRF_BASE + 0x031C) +#define SYS_GRF_SOC_CON8 (SYS_GRF_BASE + 0x0320) +#define SYS_GRF_SOC_CON9 (SYS_GRF_BASE + 0x0324) +#define CLK_RX_DL_CFG_SHIFT 8 +#define CLK_TX_DL_CFG_SHIFT 0 + +#define TX_DELAY_GMAC0 FixedPcdGet8 (PcdGmac0TxDelay) +#define RX_DELAY_GMAC0 FixedPcdGet8 (PcdGmac0RxDelay) +#define TX_DELAY_GMAC1 FixedPcdGet8 (PcdGmac1TxDelay) +#define RX_DELAY_GMAC1 FixedPcdGet8 (PcdGmac1RxDelay) + +#define GMAC0_BASE 0xfe1b0000 +#define GMAC1_BASE 0xfe1c0000 + +/* GMAC registers */ +#define GMAC_MAC_MDIO_ADDRESS 0x0200 +#define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21 +#define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16 +#define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT 8 +#define GMAC_MAC_MDIO_ADDRESS_CR_100_150 (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) +#define GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT 2 +#define GMAC_MAC_MDIO_ADDRESS_GOC_READ (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) +#define GMAC_MAC_MDIO_ADDRESS_GOC_WRITE (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) +#define GMAC_MAC_MDIO_ADDRESS_GB BIT0 +#define GMAC_MAC_MDIO_DATA 0x0204 + +#define GMAC_MAC_ADDRESS0_LOW 0x0304 +#define GMAC_MAC_ADDRESS0_HIGH 0x0300 + +/* MII registers */ +#define MII_PHYIDR1 0x02 +#define MII_PHYIDR2 0x03 + +STATIC ETHERNET_PHY_INIT mPhyInitList[] = { + RealtekPhyInit, + MotorcommPhyInit +}; + +VOID +PhyRead ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT8 Phy, + IN UINT16 Reg, + OUT UINT16 *Value + ) +{ + UINT32 Addr; + UINTN Retry; + + Addr = GMAC_MAC_MDIO_ADDRESS_CR_100_150 | + (Phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | + (Reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | + GMAC_MAC_MDIO_ADDRESS_GOC_READ | + GMAC_MAC_MDIO_ADDRESS_GB; + MmioWrite32 (GmacBase + GMAC_MAC_MDIO_ADDRESS, Addr); + + MicroSecondDelay (10000); + + for (Retry = 1000; Retry > 0; Retry--) { + Addr = MmioRead32 (GmacBase + GMAC_MAC_MDIO_ADDRESS); + if ((Addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { + *Value = MmioRead32 (GmacBase + GMAC_MAC_MDIO_DATA) & 0xFFFFu; + break; + } + MicroSecondDelay (10); + } + if (Retry == 0) { + DEBUG ((DEBUG_WARN, "MDIO: PHY read timeout!\n")); + *Value = 0xFFFFU; + ASSERT (FALSE); + } +} + +VOID +PhyWrite ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT8 Phy, + IN UINT16 Reg, + IN UINT16 Value + ) +{ + UINT32 Addr; + UINTN Retry; + + MmioWrite32 (GmacBase + GMAC_MAC_MDIO_DATA, Value); + + Addr = GMAC_MAC_MDIO_ADDRESS_CR_100_150 | + (Phy << GMAC_MAC_MDIO_ADDRESS_PA_SHIFT) | + (Reg << GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) | + GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | + GMAC_MAC_MDIO_ADDRESS_GB; + MmioWrite32 (GmacBase + GMAC_MAC_MDIO_ADDRESS, Addr); + + MicroSecondDelay (10000); + + for (Retry = 1000; Retry > 0; Retry--) { + Addr = MmioRead32 (GmacBase + GMAC_MAC_MDIO_ADDRESS); + if ((Addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { + break; + } + MicroSecondDelay (10); + } + if (Retry == 0) { + DEBUG ((DEBUG_WARN, "MDIO: PHY write timeout!\n")); + ASSERT (FALSE); + } +} + +STATIC +VOID +EFIAPI +PhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase + ) +{ + EFI_STATUS Status; + UINT16 PhyIdReg; + UINT32 PhyId; + UINT32 Index; + + PhyRead (GmacBase, 0, MII_PHYIDR1, &PhyIdReg); + PhyId = PhyIdReg << 16; + PhyRead (GmacBase, 0, MII_PHYIDR2, &PhyIdReg); + PhyId |= PhyIdReg; + + for (Index = 0; Index < ARRAY_SIZE (mPhyInitList); Index++) { + Status = mPhyInitList[Index] (GmacBase, PhyId); + if (Status == EFI_UNSUPPORTED) { + continue; + } else if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: mPhyInitList[%d]() failed: %r\n", __func__, Index, Status)); + } + return; + } + + DEBUG ((DEBUG_ERROR, "%a: Unknown PHY ID %08X\n", __func__, PhyId)); +} + +STATIC +VOID +EFIAPI +InitGmac0 ( + VOID + ) +{ + /* Assert reset */ + MmioWrite32 (CRU_SOFTRST_CON32, 0x04000400); // aresetn_gmac0 = 1 + + /* Configure pins */ + GmacIomux (0); + + /* Setup clocks */ + MmioWrite32 (PHP_GRF_CLK_CON1, 0x001d0000); // io_clksel_gmac0 = io + // mii_tx_clk_sel_gamc0 = 125 MHz + // rmii_mode_gmac0 = RGMII mode + + MmioWrite32 (PHP_GRF_GMAC_CON0, 0x00380008); // gmac0_phy_intf_sel = RGMII + + /* Setup DLLs */ + if (TX_DELAY_GMAC0) { + MmioWrite32 (SYS_GRF_SOC_CON7, 0x00040004); // gmac0_txclk_dly_ena = 1 + MmioWrite32 (SYS_GRF_SOC_CON8, 0x007F0000U | + (TX_DELAY_GMAC0 << CLK_TX_DL_CFG_SHIFT)); + } + + if (RX_DELAY_GMAC0) { + MmioWrite32 (SYS_GRF_SOC_CON7, 0x00080008); // gmac0_rxclk_dly_ena = 1 + MmioWrite32 (SYS_GRF_SOC_CON8, 0x7F000000U | + (RX_DELAY_GMAC0 << CLK_RX_DL_CFG_SHIFT)); + } + + /* Reset PHY */ + GmacIoPhyReset (0, TRUE); + MicroSecondDelay (20000); + GmacIoPhyReset (0, FALSE); + MicroSecondDelay (200000); + + /* Deassert reset */ + MmioWrite32 (CRU_SOFTRST_CON32, 0x04000000); // aresetn_gmac0 = 0 + + PhyInit (GMAC0_BASE); +} + +STATIC +VOID +EFIAPI +InitGmac1 ( + VOID + ) +{ + /* Assert reset */ + MmioWrite32 (CRU_SOFTRST_CON32, 0x08000800); // aresetn_gmac1 = 1 + + /* Configure pins */ + GmacIomux (1); + + /* Setup clocks */ + MmioWrite32 (PHP_GRF_CLK_CON1, 0x03a00000); // io_clksel_gmac1 = io + // mii_tx_clk_sel_gamc1 = 125 MHz + // rmii_mode_gmac1 = RGMII mode + + MmioWrite32 (PHP_GRF_GMAC_CON0, 0x0e000200); // gmac1_phy_intf_sel = RGMII + + /* Setup DLLs */ + if (TX_DELAY_GMAC1) { + MmioWrite32 (SYS_GRF_SOC_CON7, 0x00100010); // gmac1_txclk_dly_ena = 1 + MmioWrite32 (SYS_GRF_SOC_CON9, 0x007F0000U | + (TX_DELAY_GMAC1 << CLK_TX_DL_CFG_SHIFT)); + } + + if (RX_DELAY_GMAC1) { + MmioWrite32 (SYS_GRF_SOC_CON7, 0x00200020); // gmac1_rxclk_dly_ena = 1 + MmioWrite32 (SYS_GRF_SOC_CON9, 0x7F000000U | + (RX_DELAY_GMAC1 << CLK_RX_DL_CFG_SHIFT)); + } + + /* Reset PHY */ + GmacIoPhyReset (1, TRUE); + MicroSecondDelay (20000); + GmacIoPhyReset (1, FALSE); + MicroSecondDelay (200000); + + /* Deassert reset */ + MmioWrite32 (CRU_SOFTRST_CON32, 0x08000000); // aresetn_gmac1 = 0 + + PhyInit (GMAC1_BASE); +} + +EFI_STATUS +EFIAPI +GmacPlatformDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT8 OtpData[32]; + UINT8 Hash[SHA256_DIGEST_SIZE]; + UINT32 MacLo, MacHi; + + if (!FixedPcdGetBool (PcdGmac0Supported) + && !FixedPcdGetBool (PcdGmac1Supported)) { + return EFI_SUCCESS; + } + + /* Generate MAC addresses from the first 32 bytes in the OTP and write it to GMAC0 and GMAC1 */ + /* Use sequential MAC addresses. Last byte is even for GMAC0, and odd for GMAC1. */ + OtpRead (0x00, sizeof (OtpData), OtpData); + Sha256HashAll (OtpData, sizeof (OtpData), Hash); + Hash[0] &= 0xFE; + Hash[0] |= 0x02; + + if (FixedPcdGetBool (PcdGmac0Supported)) { + InitGmac0 (); + + Hash[5] &= ~1; + DEBUG ((DEBUG_INFO, "%a: GMAC0 MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", + __func__, + Hash[0], Hash[1], Hash[2], + Hash[3], Hash[4], Hash[5])); + MacLo = Hash[3] | (Hash[2] << 8) | (Hash[1] << 16) | (Hash[0] << 24); + MacHi = Hash[5] | (Hash[4] << 8); + MmioWrite32 (GMAC0_BASE + GMAC_MAC_ADDRESS0_LOW, MacLo); + MmioWrite32 (GMAC0_BASE + GMAC_MAC_ADDRESS0_HIGH, MacHi); + } + + if (FixedPcdGetBool (PcdGmac1Supported)) { + InitGmac1 (); + + Hash[5] |= 1; + DEBUG ((DEBUG_INFO, "%a: GMAC1 MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", + __func__, + Hash[0], Hash[1], Hash[2], + Hash[3], Hash[4], Hash[5])); + MacLo = Hash[3] | (Hash[2] << 8) | (Hash[1] << 16) | (Hash[0] << 24); + MacHi = Hash[5] | (Hash[4] << 8); + MmioWrite32 (GMAC1_BASE + GMAC_MAC_ADDRESS0_LOW, MacLo); + MmioWrite32 (GMAC1_BASE + GMAC_MAC_ADDRESS0_HIGH, MacHi); + } + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf new file mode 100644 index 0000000..808e3e1 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf @@ -0,0 +1,51 @@ +#/** @file +# +# RK3588 GMAC initializer +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = GmacPlatformDxe + FILE_GUID = e08592c7-55f6-4f90-be56-327356aa1462 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = GmacPlatformDxeInitialize + +[Sources.common] + GmacPlatformDxe.c + RealtekPhy.c + MotorcommPhy.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CryptoPkg/CryptoPkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + UefiDriverEntryPoint + DebugLib + IoLib + TimerLib + BaseCryptLib + OtpLib + RockchipPlatformLib + +[Protocols] + +[Pcd] + gRK3588TokenSpaceGuid.PcdGmac0Supported + gRK3588TokenSpaceGuid.PcdGmac1Supported + gRK3588TokenSpaceGuid.PcdGmac0TxDelay + gRK3588TokenSpaceGuid.PcdGmac0RxDelay + gRK3588TokenSpaceGuid.PcdGmac1TxDelay + gRK3588TokenSpaceGuid.PcdGmac1RxDelay + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/MotorcommPhy.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/MotorcommPhy.c new file mode 100644 index 0000000..cbb5ab0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/MotorcommPhy.c @@ -0,0 +1,97 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "EthernetPhy.h" + +/* Motorcomm PHY registers */ +#define EXT_REG_ADDR 0x1E +#define EXT_REG_DATA 0x1F +#define PHY_CLOCK_GATING_REG 0x0C +#define RX_CLK_EN BIT12 +#define TX_CLK_DELAY_SEL_SHIFT 4 +#define TX_CLK_DELAY_SEL (0xFU << TX_CLK_DELAY_SEL_SHIFT) +#define CLK_25M_SEL_SHIFT 1 +#define CLK_25M_SEL_MASK (0x3U << CLK_25M_SEL_SHIFT) +#define CLK_25M_SEL_125M (3U << CLK_25M_SEL_SHIFT) +#define RX_CLK_DELAY_EN BIT0 +#define PHY_SLEEP_CONTROL1_REG 0x27 +#define SLEEP_SW BIT15 +#define PLLON_IN_SLP BIT14 + +#define YTPHY_SYNCE_CFG_REG 0xA012 +#define YT8531_SCR_SYNCE_ENABLE BIT6 +#define YT8531_SCR_CLK_FRE_SEL_125M BIT4 +#define YT8531_SCR_CLK_SRC_SEL_SHIFT 1 +#define YT8531_SCR_CLK_SRC_SEL_PLL_125M (0 << YT8531_SCR_CLK_SRC_SEL_SHIFT) + +#define LED1_CFG_REG 0xA00D +#define LED2_CFG_REG 0xA00E +#define LED_BLINK_CFG_REG 0xA00F + +STATIC +VOID +YT8531PhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase + ) +{ + UINT16 OldAddr; + UINT16 Data; + + PhyRead (GmacBase, 0, EXT_REG_ADDR, &OldAddr); + + PhyWrite (GmacBase, 0, EXT_REG_ADDR, YTPHY_SYNCE_CFG_REG); + PhyWrite (GmacBase, 0, EXT_REG_DATA, YT8531_SCR_SYNCE_ENABLE | + YT8531_SCR_CLK_FRE_SEL_125M | + YT8531_SCR_CLK_SRC_SEL_PLL_125M); + + PhyWrite (GmacBase, 0, EXT_REG_ADDR, PHY_CLOCK_GATING_REG); + PhyRead (GmacBase, 0, EXT_REG_DATA, &Data); + Data &= ~RX_CLK_EN; + Data &= ~CLK_25M_SEL_MASK; + Data |= CLK_25M_SEL_125M; + PhyWrite (GmacBase, 0, EXT_REG_DATA, Data); + + PhyWrite (GmacBase, 0, EXT_REG_ADDR, PHY_SLEEP_CONTROL1_REG); + PhyRead (GmacBase, 0, EXT_REG_DATA, &Data); + Data &= ~SLEEP_SW; + PhyWrite (GmacBase, 0, EXT_REG_DATA, Data); + + PhyWrite (GmacBase, 0, EXT_REG_ADDR, LED1_CFG_REG); + PhyWrite (GmacBase, 0, EXT_REG_DATA, 0x0670); + + PhyWrite (GmacBase, 0, EXT_REG_ADDR, LED2_CFG_REG); + PhyWrite (GmacBase, 0, EXT_REG_DATA, 0x2070); + + PhyWrite (GmacBase, 0, EXT_REG_ADDR, LED_BLINK_CFG_REG); + PhyWrite (GmacBase, 0, EXT_REG_DATA, 0x007e); + + PhyWrite (GmacBase, 0, EXT_REG_ADDR, OldAddr); +} + +EFI_STATUS +EFIAPI +MotorcommPhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT32 PhyId + ) +{ + switch (PhyId) { + case 0x4F51E91B: + DEBUG ((DEBUG_INFO, "%a: Found Motorcomm YT8531 GbE PHY\n", __func__)); + YT8531PhyInit (GmacBase); + break; + default: + return EFI_UNSUPPORTED; + } + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/RealtekPhy.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/RealtekPhy.c new file mode 100644 index 0000000..da4d96e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/RealtekPhy.c @@ -0,0 +1,54 @@ +/** @file + * + * Copyright (c) 2022, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "EthernetPhy.h" + +/* Realtek RTL8211F PHY registers */ +#define PAGSR 0x1F +#define LCR 0x10 +#define LCR_VALUE 0x6940 + +STATIC +VOID +RTL8211FPhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase + ) +{ + PhyWrite (GmacBase, 0, PAGSR, 0xD04); + MicroSecondDelay (10000); + PhyWrite (GmacBase, 0, LCR, LCR_VALUE); + MicroSecondDelay (10000); + PhyWrite (GmacBase, 0, PAGSR, 0); +} + +EFI_STATUS +EFIAPI +RealtekPhyInit ( + IN EFI_PHYSICAL_ADDRESS GmacBase, + IN UINT32 PhyId + ) +{ + switch (PhyId) { + case 0x001CC916: + DEBUG ((DEBUG_INFO, "%a: Found Realtek RTL8211F GbE PHY\n", __func__)); + RTL8211FPhyInit (GmacBase); + break; + case 0x001CC878: + DEBUG ((DEBUG_INFO, "%a: Found Realtek RTL8211F-VD GbE PHY\n", __func__)); + RTL8211FPhyInit (GmacBase); + break; + default: + return EFI_UNSUPPORTED; + } + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ComboPhy.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ComboPhy.c new file mode 100644 index 0000000..c8ce318 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ComboPhy.c @@ -0,0 +1,216 @@ +/** @file + * + * Copyright (c) 2021, Rockchip Limited. All rights reserved. + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include + +#include "RK3588DxeFormSetGuid.h" +#include "ComboPhy.h" + +#define COMBO_PIPE_PHY0 0xFEE00000 +#define COMBO_PIPE_PHY1 0xFEE10000 +#define COMBO_PIPE_PHY2 0xFEE20000 + +#define PHP_GRF_BASE 0xFD5B0000 +#define PHP_GRF_PCIESEL_CON 0x100 + +#define PIPE_PHY0_GRF 0xFD5BC000 +#define PIPE_PHY1_GRF 0xFD5C0000 +#define PIPE_PHY2_GRF 0xFD5C4000 + +static UINTN ComPhyReg[3][2] = { + { COMBO_PIPE_PHY0, PIPE_PHY0_GRF }, + { COMBO_PIPE_PHY1, PIPE_PHY1_GRF }, + { COMBO_PIPE_PHY2, PIPE_PHY2_GRF }, +}; + +STATIC +VOID +EFIAPI +InitComPhyConfig ( + UINTN PhyBaseAddr, + UINTN PhpBaseAddr, + UINT32 PhyMode + ) +{ + UINT32 Val; + DEBUG ((DEBUG_INIT, "%a reg=%x %x mode = %d\n", __func__, PhyBaseAddr, PhpBaseAddr, PhyMode)); + + switch (PhyMode) { + case COMBO_PHY_MODE_PCIE: + MmioWrite32 (PhpBaseAddr + 0x0, 0xFFFF1000); + MmioWrite32 (PhpBaseAddr + 0x4, 0xFFFF4000); + MmioWrite32 (PhpBaseAddr + 0x8, 0xFFFF0101); + MmioWrite32 (PhpBaseAddr + 0xc, 0xFFFF0200); + + /* gate_tx_pck_sel length select work for L1SS */ + MmioWrite32 (PhyBaseAddr + 0x74, 0xc0); + + /* PLL KVCO tuning fine */ + Val = MmioRead32 (PhyBaseAddr + (0x20 << 2)); + Val &= ~(0x7 << 2); + Val |= 0x4 << 2; + MmioWrite32 (PhyBaseAddr + (0x20 << 2), Val); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ + MmioWrite32 (PhyBaseAddr + (0x1b << 2), 0x4c); + + /* Set up su_trim: T3 */ + MmioWrite32 (PhyBaseAddr + (0xa << 2), 0xb0); + MmioWrite32 (PhyBaseAddr + (0xb << 2), 0x47); + MmioWrite32 (PhyBaseAddr + (0xd << 2), 0x57); + + if (PhyBaseAddr == COMBO_PIPE_PHY0) { + MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, BIT1 << 16); + } + + if (PhyBaseAddr == COMBO_PIPE_PHY1) { + MmioWrite32 (PHP_GRF_BASE + PHP_GRF_PCIESEL_CON, BIT0 << 16); + } + break; + + case COMBO_PHY_MODE_SATA: + MmioWrite32 (PhyBaseAddr + 0x38, 0x41); + MmioWrite32 (PhyBaseAddr + 0x18, 0x8F); + MmioWrite32 (PhyBaseAddr + 0x7C, 0x50); + MmioWrite32 (PhyBaseAddr + 0x24, 0x07); + + MmioWrite32 (PhpBaseAddr + 0x0, 0xFFFF0129); + MmioWrite32 (PhpBaseAddr + 0x4, 0xFFFF4000); + MmioWrite32 (PhpBaseAddr + 0x8, 0xFFFF80c1); + MmioWrite32 (PhpBaseAddr + 0xc, 0xFFFF4007); + + /* Should we tune the rest of the parameters too? */ + + break; + + case COMBO_PHY_MODE_USB3: + /* Set SSC downward spread spectrum */ + Val = MmioRead32 (PhyBaseAddr + (0x1f << 2)); + Val &= ~(0x3 << 4); + Val |= 0x01 << 4; + MmioWrite32 (PhyBaseAddr + 0x7c, Val); + + /* Enable adaptive CTLE for USB3.0 Rx */ + Val = MmioRead32 (PhyBaseAddr + (0x0e << 2)); + Val &= ~(0x1 << 0); + Val |= 0x01; + MmioWrite32 (PhyBaseAddr + (0x0e << 2), Val); + + /* Set PLL KVCO fine tuning signals */ + Val = MmioRead32 (PhyBaseAddr + (0x20 << 2)); + Val &= ~(0x7 << 2); + Val |= 0x2 << 2; + MmioWrite32 (PhyBaseAddr + (0x20 << 2), Val); + + /* Set PLL LPF R1 to su_trim[10:7]=1001 */ + MmioWrite32 (PhyBaseAddr + (0xb << 2), 0x4); + + /* Set PLL input clock divider 1/2 */ + Val = MmioRead32 (PhyBaseAddr + (0x5 << 2)); + Val &= ~(0x3 << 6); + Val |= 0x1 << 6; + MmioWrite32 (PhyBaseAddr + (0x5 << 2), Val); + + /* Set PLL loop divider */ + MmioWrite32 (PhyBaseAddr + (0x11 << 2), 0x32); + + /* Set PLL KVCO to min and set PLL charge pump current to max */ + MmioWrite32 (PhyBaseAddr + (0xa << 2), 0xf0); + + /* Set Rx squelch input filler bandwidth */ + MmioWrite32 (PhyBaseAddr + (0x14 << 2), 0x0d); + + /* Set txcomp_sel[15] to 1b'0 */ + MmioWrite32 (PhpBaseAddr + 0x8, 0x80000000); + /* Set txelec_sel[12] to 1b'0 */ + MmioWrite32 (PhpBaseAddr + 0x8, 0x10000000); + /* Set usb_mode_set[5:0]=6b'000100 */ + MmioWrite32 (PhpBaseAddr + 0x0, 0x003F0004); + + /* phy_clk_sel to 100MHz */ + MmioWrite32 (PhpBaseAddr + 0x4, 0x60004000); + break; + + default: + break; + } +} + +VOID +EFIAPI +ApplyComboPhyVariables ( + VOID + ) +{ + UINTN Index; + + UINT32 ComPhyMode[] = { PcdGet32 (PcdComboPhy0Mode), + PcdGet32 (PcdComboPhy1Mode), + PcdGet32 (PcdComboPhy2Mode) }; + + /* config phy clock to 100Mhz */ + HAL_CRU_ClkSetFreq (PLL_PPLL, 100 * 1000000); + HAL_CRU_ClkSetFreq (CLK_REF_PIPE_PHY0, 100 * 1000000); + HAL_CRU_ClkSetFreq (CLK_REF_PIPE_PHY1, 100 * 1000000); + HAL_CRU_ClkSetFreq (CLK_REF_PIPE_PHY2, 100 * 1000000); + + /* Initialize echo combo phy */ + for (Index = 0; Index < ARRAY_SIZE (ComPhyMode); Index++) { + InitComPhyConfig (ComPhyReg[Index][0], ComPhyReg[Index][1], ComPhyMode[Index]); + } + + MmioWrite32 (PHP_GRF_BASE + 0x0, 0x07E00440); + MmioWrite32 (PHP_GRF_BASE + 0x4, 0x00070002); + + /* reset deassert */ + MmioWrite32 (0xfd7c0000 + 0x0b34, 0x01c00000); +} + +VOID +EFIAPI +SetupComboPhyVariables ( + VOID + ) +{ + UINTN Size; + UINT32 Var32; + EFI_STATUS Status; + + Size = sizeof (UINT32); + + Status = gRT->GetVariable (L"ComboPhy0Mode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status) || !FixedPcdGetBool (PcdComboPhy0Switchable)) { + Status = PcdSet32S (PcdComboPhy0Mode, FixedPcdGet32 (PcdComboPhy0ModeDefault)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"ComboPhy1Mode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status) || !FixedPcdGetBool (PcdComboPhy1Switchable)) { + Status = PcdSet32S (PcdComboPhy1Mode, FixedPcdGet32 (PcdComboPhy1ModeDefault)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"ComboPhy2Mode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status) || !FixedPcdGetBool (PcdComboPhy2Switchable)) { + Status = PcdSet32S (PcdComboPhy2Mode, FixedPcdGet32 (PcdComboPhy2ModeDefault)); + ASSERT_EFI_ERROR (Status); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ComboPhy.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ComboPhy.h new file mode 100644 index 0000000..dd1e6f7 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ComboPhy.h @@ -0,0 +1,29 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK3588DXE_COMBO_PHY_H__ +#define __RK3588DXE_COMBO_PHY_H__ + +// +// Don't declare these in the VFR file. +// +#ifndef VFR_FILE_INCLUDE +VOID +EFIAPI +ApplyComboPhyVariables ( + VOID + ); + +VOID +EFIAPI +SetupComboPhyVariables ( + VOID + ); +#endif // VFR_FILE_INCLUDE + +#endif // __RK3588DXE_COMBO_PHY_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c new file mode 100644 index 0000000..97dff95 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.c @@ -0,0 +1,63 @@ +/** @file + * + * Copyright (c) 2020, Jeremy Linton + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "RK3588DxeFormSetGuid.h" +#include "ConfigTable.h" + +VOID +EFIAPI +ApplyConfigTableVariables ( + VOID + ) +{ + /* nothing to do here, the PCDs are read by AcpiPlatformDxe and FdtPlatformDxe */ +} + +VOID +EFIAPI +SetupConfigTableVariables ( + VOID + ) +{ + UINTN Size; + UINT32 Var32; + UINT8 Var8; + EFI_STATUS Status; + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"ConfigTableMode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdConfigTableMode, PcdGet32 (PcdConfigTableMode)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"AcpiPcieEcamCompatMode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdAcpiPcieEcamCompatMode, FixedPcdGet32 (PcdAcpiPcieEcamCompatModeDefault)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT8); + Status = gRT->GetVariable (L"FdtSupportOverrides", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var8); + if (EFI_ERROR (Status)) { + Status = PcdSet8S (PcdFdtSupportOverrides, PcdGet8 (PcdFdtSupportOverrides)); + ASSERT_EFI_ERROR (Status); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.h new file mode 100644 index 0000000..6c3f8dd --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/ConfigTable.h @@ -0,0 +1,29 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK3588DXE_CONFIG_TABLE_H__ +#define __RK3588DXE_CONFIG_TABLE_H__ + +// +// Don't declare these in the VFR file. +// +#ifndef VFR_FILE_INCLUDE +VOID +EFIAPI +ApplyConfigTableVariables ( + VOID + ); + +VOID +EFIAPI +SetupConfigTableVariables ( + VOID + ); +#endif // VFR_FILE_INCLUDE + +#endif // __RK3588DXE_CONFIG_TABLE_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/CpuPerformance.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/CpuPerformance.c new file mode 100644 index 0000000..cba6e9b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/CpuPerformance.c @@ -0,0 +1,498 @@ +/** @file +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "RK3588DxeFormSetGuid.h" +#include "CpuPerformance.h" + +#define SCMI_CLK_CPUL 0 +#define SCMI_CLK_CPUB01 2 +#define SCMI_CLK_CPUB23 3 + +#define FREQ_1_MHZ 1000000 + +typedef struct { + UINT64 Hz; + UINT32 Microvolts; +} OPERATING_PERFORMANCE_POINT; + +STATIC CONST OPERATING_PERFORMANCE_POINT mCPULOppTable[] = { + { 408000000, 675000 }, + { 600000000, 675000 }, + { 816000000, 675000 }, + { 1008000000, 675000 }, + { 1200000000, 712500 }, + { 1416000000, 762500 }, + { 1608000000, 850000 }, + { 1800000000, 950000 } +}; + +STATIC CONST OPERATING_PERFORMANCE_POINT mCPUBOppTable[] = { + { 408000000, 675000 }, + { 600000000, 675000 }, + { 816000000, 675000 }, + { 1008000000, 675000 }, + { 1200000000, 675000 }, + { 1416000000, 725000 }, + { 1608000000, 762500 }, + { 1800000000, 850000 }, + { 2016000000, 925000 }, + { 2208000000, 987500 }, + { 2256000000, 1000000 }, + { 2304000000, 1000000 }, + { 2352000000, 1000000 }, + { 2400000000, 1000000 } +}; + +typedef struct { + UINT32 ClockId; + CONST OPERATING_PERFORMANCE_POINT *Opp; + UINT32 OppCount; +} SCMI_OPP_TABLE; + +STATIC CONST SCMI_OPP_TABLE mScmiOppTable[] = { + { SCMI_CLK_CPUL, mCPULOppTable, ARRAY_SIZE (mCPULOppTable) }, + { SCMI_CLK_CPUB01, mCPUBOppTable, ARRAY_SIZE (mCPUBOppTable) }, + { SCMI_CLK_CPUB23, mCPUBOppTable, ARRAY_SIZE (mCPUBOppTable) } +}; + +STATIC +EFI_STATUS +EFIAPI +ScmiSetClockRate ( + IN UINT32 ClockId, + IN UINT64 Hz + ) +{ + EFI_STATUS Status; + SCMI_CLOCK_PROTOCOL *ClockProtocol; + EFI_GUID ClockProtocolGuid = ARM_SCMI_CLOCK_PROTOCOL_GUID; + UINT64 ClockRate; + BOOLEAN Enabled; + CHAR8 ClockName[SCMI_MAX_STR_LEN]; + + Status = gBS->LocateProtocol ( + &ClockProtocolGuid, + NULL, + (VOID**)&ClockProtocol + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = ClockProtocol->GetClockAttributes ( + ClockProtocol, + ClockId, + &Enabled, + ClockName + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = ClockProtocol->RateGet (ClockProtocol, ClockId, &ClockRate); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DEBUG ((DEBUG_INFO, "SCMI: %a: Current rate is %uHz\n", ClockName, ClockRate)); + + ClockRate = Hz; + + DEBUG ((DEBUG_INFO, "SCMI: %a: New rate is %uHz\n", ClockName, ClockRate)); + + Status = ClockProtocol->RateSet ( + ClockProtocol, + ClockId, + ClockRate + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + Status = ClockProtocol->RateGet (ClockProtocol, ClockId, &ClockRate); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DEBUG ((DEBUG_INFO, "SCMI: %a: Current rate is %uHz\n", ClockName, ClockRate)); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +ScmiGetClockRate ( + IN UINT32 ClockId, + OUT UINT64 *Hz + ) +{ + EFI_STATUS Status; + SCMI_CLOCK_PROTOCOL *ClockProtocol; + EFI_GUID ClockProtocolGuid = ARM_SCMI_CLOCK_PROTOCOL_GUID; + + Status = gBS->LocateProtocol ( + &ClockProtocolGuid, + NULL, + (VOID**)&ClockProtocol + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + return ClockProtocol->RateGet (ClockProtocol, ClockId, Hz); +} + +STATIC +EFI_STATUS +EFIAPI +GetOppVoltage ( + IN CONST OPERATING_PERFORMANCE_POINT *OppTable, + IN UINT32 OppCount, + IN UINT64 Hz, + OUT UINT32 *Microvolts + ) +{ + for (UINTN Index = 0; Index < OppCount; Index++) { + if (Hz <= OppTable[Index].Hz) { + *Microvolts = OppTable[Index].Microvolts; + return EFI_SUCCESS; + } + } + return EFI_NOT_FOUND; +} + +STATIC +VOID +EFIAPI +SetRk860xRegulatorByTag ( + IN UINT32 Tag, + OUT UINT32 Microvolts + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + RK860X_REGULATOR_PROTOCOL *Rk860xRegulator; + UINTN NumRegulators; + UINT32 Index; + UINT32 Voltage; + BOOLEAN FoundReg; + + Status = gBS->LocateHandleBuffer (ByProtocol, + &gRk860xRegulatorProtocolGuid, + NULL, + &NumRegulators, + &HandleBuffer); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_WARN, "Couldn't locate gRk860xRegulatorProtocolGuid. Status=%r\n", Status)); + return; + } + + FoundReg = FALSE; + for (Index = 0; Index < NumRegulators; Index++) { + Status = gBS->OpenProtocol (HandleBuffer[Index], + &gRk860xRegulatorProtocolGuid, + (VOID **) &Rk860xRegulator, + gImageHandle, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Failed to open protocol for reg %d. Status=%r\n", Index)); + return; + } + + if (Rk860xRegulator->Tag != Tag) { + goto CloseProtocol; + } + + FoundReg = TRUE; + DEBUG((DEBUG_INFO, "Found 0x%x on I2C bus %d for tag %u\n", + I2C_DEVICE_ADDRESS(Rk860xRegulator->Identifier), + I2C_DEVICE_BUS(Rk860xRegulator->Identifier), + Tag)); + + Status = Rk860xRegulator->GetVoltage (Rk860xRegulator, &Voltage, FALSE); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Failed to get voltage. Status=%r\n", Status)); + goto CloseProtocol; + } + DEBUG((DEBUG_INFO, "Current voltage: %d uV\n", Voltage)); + + Voltage = Microvolts; + + DEBUG((DEBUG_INFO, "Setting voltage to: %d uV\n", Voltage)); + Status = Rk860xRegulator->SetVoltage (Rk860xRegulator, Voltage, FALSE); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Failed to set voltage. Status=%r\n", Status)); + goto CloseProtocol; + } + + Status = Rk860xRegulator->GetVoltage (Rk860xRegulator, &Voltage, FALSE); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Failed to get voltage. Status=%r\n", Status)); + goto CloseProtocol; + } + DEBUG((DEBUG_INFO, "Current voltage: %d uV\n", Voltage)); + +CloseProtocol: + gBS->CloseProtocol (HandleBuffer[Index], + &gRk860xRegulatorProtocolGuid, + gImageHandle, + NULL); + + if (FoundReg) { + break; + } + } +} + +STATIC +VOID +EFIAPI +SetCpuVoltage ( + IN UINT32 ClockId, + OUT UINT32 Microvolts + ) +{ + if (Microvolts > CLUSTER_MICROVOLTS_MAX) { + Microvolts = CLUSTER_MICROVOLTS_MAX; + } + if (Microvolts < CLUSTER_MICROVOLTS_MIN) { + Microvolts = CLUSTER_MICROVOLTS_MIN; + } + + if (ClockId == SCMI_CLK_CPUL) { + SetCPULittleVoltage (Microvolts); + } else { + SetRk860xRegulatorByTag (ClockId, Microvolts); + } +} + +VOID +EFIAPI +ApplyCpuClockVariables ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 Index; + UINT64 ClockRate; + SCMI_OPP_TABLE ScmiOppTable; + UINT32 CPUClusterClockPreset[] = { PcdGet32 (PcdCPULClusterClockPreset), + PcdGet32 (PcdCPUB01ClusterClockPreset), + PcdGet32 (PcdCPUB23ClusterClockPreset) }; + UINT32 CPUClusterClockCustom[] = { PcdGet32 (PcdCPULClusterClockCustom), + PcdGet32 (PcdCPUB01ClusterClockCustom), + PcdGet32 (PcdCPUB23ClusterClockCustom) }; + + for (Index = 0; Index < ARRAY_SIZE(CPUClusterClockPreset); Index++) { + ScmiOppTable = mScmiOppTable[Index]; + + switch (CPUClusterClockPreset[Index]) { + case CPU_PERF_CLUSTER_CLOCK_PRESET_MIN: + ClockRate = ScmiOppTable.Opp[0].Hz; + break; + case CPU_PERF_CLUSTER_CLOCK_PRESET_MAX: + ClockRate = ScmiOppTable.Opp[ScmiOppTable.OppCount - 1].Hz; + break; + case CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM: + ClockRate = CPUClusterClockCustom[Index] * FREQ_1_MHZ; + break; + default: + continue; + } + + Status = ScmiSetClockRate (ScmiOppTable.ClockId, ClockRate); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_WARN, "%a: ScmiSetClockRate failed. Status=%r\n", __FUNCTION__, Status)); + } + } +} + +VOID +EFIAPI +ApplyCpuVoltageVariables ( + VOID + ) +{ + EFI_STATUS Status; + UINT64 ClockRate; + UINT32 Index; + SCMI_OPP_TABLE ScmiOppTable; + UINT32 Microvolts; + UINT32 CPUClusterVoltageMode[] = { PcdGet32 (PcdCPULClusterVoltageMode), + PcdGet32 (PcdCPUB01ClusterVoltageMode), + PcdGet32 (PcdCPUB23ClusterVoltageMode) }; + UINT32 CPUClusterVoltageCustom[] = { PcdGet32 (PcdCPULClusterVoltageCustom), + PcdGet32 (PcdCPUB01ClusterVoltageCustom), + PcdGet32 (PcdCPUB23ClusterVoltageCustom) }; + + for (Index = 0; Index < ARRAY_SIZE (CPUClusterVoltageMode); Index++) { + ScmiOppTable = mScmiOppTable[Index]; + + switch (CPUClusterVoltageMode[Index]) { + case CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO: + Status = ScmiGetClockRate (ScmiOppTable.ClockId, &ClockRate); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: ScmiGetClockRate failed. Status=%r\n", __FUNCTION__, Status)); + continue; + } + + Status = GetOppVoltage (ScmiOppTable.Opp, ScmiOppTable.OppCount, + ClockRate, &Microvolts); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: GetOppVoltage failed. Status=%r\n", __FUNCTION__, Status)); + continue; + } + break; + case CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM: + Microvolts = CPUClusterVoltageCustom[Index]; + break; + default: + continue; + } + + SetCpuVoltage (ScmiOppTable.ClockId, Microvolts); + } +} + +VOID +EFIAPI +SetupCpuPerfVariables ( + VOID + ) +{ + UINTN Size; + UINT32 Var32; + EFI_STATUS Status; + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPULClusterClockPreset", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPULClusterClockPreset, PcdGet32 (PcdCPULClusterClockPresetDefault)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPULClusterClockCustom", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPULClusterClockCustom, PcdGet32 (PcdCPULClusterClockCustom)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPUB01ClusterClockPreset", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPUB01ClusterClockPreset, PcdGet32 (PcdCPUB01ClusterClockPresetDefault)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPUB01ClusterClockCustom", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPUB01ClusterClockCustom, PcdGet32 (PcdCPUB01ClusterClockCustom)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPUB23ClusterClockPreset", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPUB23ClusterClockPreset, PcdGet32 (PcdCPUB23ClusterClockPresetDefault)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPUB23ClusterClockCustom", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPUB23ClusterClockCustom, PcdGet32 (PcdCPUB23ClusterClockCustom)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPULClusterVoltageMode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPULClusterVoltageMode, PcdGet32 (PcdCPULClusterVoltageMode)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPULClusterVoltageCustom", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPULClusterVoltageCustom, PcdGet32 (PcdCPULClusterVoltageCustom)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPUB01ClusterVoltageMode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPUB01ClusterVoltageMode, PcdGet32 (PcdCPUB01ClusterVoltageMode)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPUB01ClusterVoltageCustom", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPUB01ClusterVoltageCustom, PcdGet32 (PcdCPUB01ClusterVoltageCustom)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPUB23ClusterVoltageMode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPUB23ClusterVoltageMode, PcdGet32 (PcdCPUB23ClusterVoltageMode)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT32); + Status = gRT->GetVariable (L"CpuPerf_CPUB23ClusterVoltageCustom", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCPUB23ClusterVoltageCustom, PcdGet32 (PcdCPUB23ClusterVoltageCustom)); + ASSERT_EFI_ERROR (Status); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/CpuPerformance.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/CpuPerformance.h new file mode 100644 index 0000000..d01b103 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/CpuPerformance.h @@ -0,0 +1,40 @@ +/** @file +* +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ +#ifndef __RK3588DXE_CPU_PERF_H__ +#define __RK3588DXE_CPU_PERF_H__ + +#define CLUSTER_MICROVOLTS_MIN 500000 +#define CLUSTER_MICROVOLTS_MAX 1500000 +#define CLUSTER_MICROVOLTS_STEP 6250 +#define CPUL_CLUSTER_MICROVOLTS_DEFAULT 950000 +#define CPUB_CLUSTER_MICROVOLTS_DEFAULT 1000000 + +// +// Don't declare these in the VFR file. +// +#ifndef VFR_FILE_INCLUDE +VOID +EFIAPI +ApplyCpuClockVariables ( + VOID + ); + +VOID +EFIAPI +ApplyCpuVoltageVariables ( + VOID + ); + +VOID +EFIAPI +SetupCpuPerfVariables ( + VOID + ); +#endif + +#endif // __RK3588DXE_CPU_PERF_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/DebugSerialPort.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/DebugSerialPort.c new file mode 100644 index 0000000..19855d6 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/DebugSerialPort.c @@ -0,0 +1,50 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "RK3588DxeFormSetGuid.h" +#include "DebugSerialPort.h" + +VOID +EFIAPI +ApplyDebugSerialPortVariables ( + VOID + ) +{ + /* nothing to do here */ +} + +VOID +EFIAPI +SetupDebugSerialPortVariables ( + VOID + ) +{ + UINTN Size; + UINT64 Var64; + EFI_STATUS Status; + + Size = sizeof (UINT64); + + Status = gRT->GetVariable (L"DebugSerialPortBaudRate", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var64); + if (EFI_ERROR (Status)) { + Var64 = DEBUG_SERIAL_PORT_BAUD_RATE_DEFAULT; + Status = gRT->SetVariable ( + L"DebugSerialPortBaudRate", + &gRK3588DxeFormSetGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + Size, + &Var64); + ASSERT_EFI_ERROR (Status); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/DebugSerialPort.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/DebugSerialPort.h new file mode 100644 index 0000000..0ffeaeb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/DebugSerialPort.h @@ -0,0 +1,33 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK3588DXE_DEBUG_SERIAL_PORT_H__ +#define __RK3588DXE_DEBUG_SERIAL_PORT_H__ + +#define DEBUG_SERIAL_PORT_BAUD_RATE_MIN 0 +#define DEBUG_SERIAL_PORT_BAUD_RATE_MAX 1500000 +#define DEBUG_SERIAL_PORT_BAUD_RATE_DEFAULT 1500000 + +// +// Don't declare these in the VFR file. +// +#ifndef VFR_FILE_INCLUDE +VOID +EFIAPI +ApplyDebugSerialPortVariables ( + VOID + ); + +VOID +EFIAPI +SetupDebugSerialPortVariables ( + VOID + ); +#endif // VFR_FILE_INCLUDE + +#endif // __RK3588DXE_DEBUG_SERIAL_PORT_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/FanControl.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/FanControl.c new file mode 100644 index 0000000..8679758 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/FanControl.c @@ -0,0 +1,58 @@ +/** @file + * + * Copyright (c) 2023, Molly Sophia + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include +#include "RK3588DxeFormSetGuid.h" +#include "FanControl.h" + +VOID +EFIAPI +ApplyCoolingFanVariables ( + VOID + ) +{ + UINT32 Var32 = PcdGet32 (PcdCoolingFanState); + if (Var32 == COOLING_FAN_STATE_ENABLED) { + Var32 = PcdGet32 (PcdCoolingFanSpeed); + PwmFanIoSetup(); + PwmFanSetSpeed(Var32); + } +} + +VOID +EFIAPI +SetupCoolingFanVariables ( + VOID + ) +{ + UINTN Size; + UINT32 Var32; + EFI_STATUS Status; + + Size = sizeof (UINT32); + + Status = gRT->GetVariable (L"CoolingFanState", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCoolingFanState, 1); + ASSERT_EFI_ERROR (Status); + } + + Status = gRT->GetVariable (L"CoolingFanSpeed", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdCoolingFanSpeed, FAN_PERCENTAGE_DEFAULT); + ASSERT_EFI_ERROR (Status); + } +} \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/FanControl.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/FanControl.h new file mode 100644 index 0000000..d493405 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/FanControl.h @@ -0,0 +1,34 @@ +/** @file + * + * Copyright (c) 2023, Molly Sophia + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK3588DXE_FANCONTROL_H__ +#define __RK3588DXE_FANCONTROL_H__ + +#define FAN_PERCENTAGE_MIN 0 +#define FAN_PERCENTAGE_MAX 100 +#define FAN_PERCENTAGE_STEP 1 +#define FAN_PERCENTAGE_DEFAULT 50 + +// +// Don't declare these in the VFR file. +// +#ifndef VFR_FILE_INCLUDE +VOID +EFIAPI +ApplyCoolingFanVariables ( + VOID + ); + +VOID +EFIAPI +SetupCoolingFanVariables ( + VOID + ); +#endif // VFR_FILE_INCLUDE + +#endif // __RK3588DXE_FANCONTROL_H__ \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/PciExpress30.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/PciExpress30.c new file mode 100644 index 0000000..ccacadf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/PciExpress30.c @@ -0,0 +1,56 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "RK3588DxeFormSetGuid.h" +#include "PciExpress30.h" + +VOID +EFIAPI +ApplyPcie30Variables ( + VOID + ) +{ + /* nothing to do yet */ +} + +VOID +EFIAPI +SetupPcie30Variables ( + VOID + ) +{ + UINTN Size; + UINT32 Var32; + UINT8 Var8; + + EFI_STATUS Status; + + Size = sizeof (UINT32); + + Status = gRT->GetVariable (L"Pcie30State", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status) || !FixedPcdGetBool (PcdPcie30Supported)) { + Status = PcdSet32S (PcdPcie30State, FixedPcdGet32 (PcdPcie30Supported)); + ASSERT_EFI_ERROR (Status); + } + + Size = sizeof (UINT8); + + Status = gRT->GetVariable (L"Pcie30PhyMode", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var8); + if (EFI_ERROR (Status) || !FixedPcdGetBool (PcdPcie30Supported)) { + Status = PcdSet8S (PcdPcie30PhyMode, FixedPcdGet8 (PcdPcie30PhyModeDefault)); + ASSERT_EFI_ERROR (Status); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/PciExpress30.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/PciExpress30.h new file mode 100644 index 0000000..7d3deec --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/PciExpress30.h @@ -0,0 +1,29 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK3588DXE_PCIE30_H__ +#define __RK3588DXE_PCIE30_H__ + +// +// Don't declare these in the VFR file. +// +#ifndef VFR_FILE_INCLUDE +VOID +EFIAPI +ApplyPcie30Variables ( + VOID + ); + +VOID +EFIAPI +SetupPcie30Variables ( + VOID + ); +#endif // VFR_FILE_INCLUDE + +#endif // __RK3588DXE_PCIE30_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c new file mode 100644 index 0000000..9c1bd07 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.c @@ -0,0 +1,520 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Limited. All rights reserved. +* Copyright (c) 2023, Mario Bălănică +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "RK3588Dxe.h" +#include "RK3588DxeFormSetGuid.h" +#include "CpuPerformance.h" +#include "ComboPhy.h" +#include "PciExpress30.h" +#include "ConfigTable.h" +#include "FanControl.h" +#include "UsbDpPhy.h" +#include "DebugSerialPort.h" + +extern UINT8 RK3588DxeHiiBin[]; +extern UINT8 RK3588DxeStrings[]; + +typedef struct { + VENDOR_DEVICE_PATH VendorDevicePath; + EFI_DEVICE_PATH_PROTOCOL End; +} HII_VENDOR_DEVICE_PATH; + +STATIC HII_VENDOR_DEVICE_PATH mVendorDevicePath = { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(sizeof (VENDOR_DEVICE_PATH)), + (UINT8)((sizeof (VENDOR_DEVICE_PATH)) >> 8) + } + }, + RK3588DXE_FORMSET_GUID + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + (UINT8)(END_DEVICE_PATH_LENGTH), + (UINT8)((END_DEVICE_PATH_LENGTH) >> 8) + } + } +}; + +#define SATA_CAP 0x0000 +#define SATA_CAP_SSS BIT27 +#define SATA_PI 0x000C +#define SATA_CMD 0x0118 +#define SATA_CMD_FBSCP BIT22 + +static UINTN AhciReg[3] = { + 0xFE210000, + 0xFE220000, + 0xFE230000, +}; + +STATIC +VOID +InstallSataDevices ( + VOID + ) +{ + UINT32 Index; + UINT32 PcieSlotIndex; + UINT32 ComPhyMode[] = { PcdGet32 (PcdComboPhy0Mode), + PcdGet32 (PcdComboPhy1Mode), + PcdGet32 (PcdComboPhy2Mode) }; + + for (Index = 0; Index < ARRAY_SIZE (ComPhyMode); Index++) { + if (ComPhyMode[Index] == COMBO_PHY_MODE_SATA) { + /* Enable power at the M.2 PCIe/SATA slots */ + switch (Index) { + case 0: + PcieSlotIndex = PCIE_SEGMENT_PCIE20L2; + break; + case 1: + PcieSlotIndex = PCIE_SEGMENT_PCIE20L0; + break; + case 2: + PcieSlotIndex = PCIE_SEGMENT_PCIE20L1; + break; + default: + ASSERT (FALSE); + continue; + } + PcieIoInit(PcieSlotIndex); + PciePowerEn(PcieSlotIndex, TRUE); + + /* Set port implemented flag */ + MmioWrite32 (AhciReg[Index] + SATA_PI, 0x1); + + /* Supports staggered spin-up */ + /* Disable for now, otherwise NetBSD seems to not pick up any drive? */ + MmioAndThenOr32 (AhciReg[Index] + SATA_CAP, ~SATA_CAP_SSS, 0); + + /* Supports FIS-based switching */ + MmioOr32 (AhciReg[Index] + SATA_CMD, SATA_CMD_FBSCP); + + RegisterNonDiscoverableMmioDevice (NonDiscoverableDeviceTypeAhci, + NonDiscoverableDeviceDmaTypeNonCoherent, + NULL, + NULL, + 1, + AhciReg[Index], SIZE_4KB); + } + } +} + +STATIC +EFI_STATUS +EFIAPI +InstallHiiPages ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HII_HANDLE HiiHandle; + EFI_HANDLE DriverHandle; + + DriverHandle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces (&DriverHandle, + &gEfiDevicePathProtocolGuid, + &mVendorDevicePath, + NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + HiiHandle = HiiAddPackages (&gRK3588DxeFormSetGuid, + DriverHandle, + RK3588DxeStrings, + RK3588DxeHiiBin, + NULL); + + if (HiiHandle == NULL) { + gBS->UninstallMultipleProtocolInterfaces (DriverHandle, + &gEfiDevicePathProtocolGuid, + &mVendorDevicePath, + NULL); + return EFI_OUT_OF_RESOURCES; + } + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +EFIAPI +SetupVariables ( + VOID + ) +{ + SetupCpuPerfVariables (); + SetupComboPhyVariables (); + SetupPcie30Variables (); + SetupConfigTableVariables (); + SetupCoolingFanVariables (); + SetupUsbDpPhyVariables (); + SetupDebugSerialPortVariables (); + + return EFI_SUCCESS; +} + +STATIC +VOID +EFIAPI +AfterApplyVariablesInit ( + VOID + ) +{ + InstallSataDevices (); +} + +STATIC +VOID +EFIAPI +InstallConfigAppliedProtocol ( + VOID + ) +{ + EFI_HANDLE Handle = NULL; + EFI_STATUS Status; + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gRockchipPlatformConfigAppliedProtocolGuid, + NULL, + NULL); + ASSERT_EFI_ERROR (Status); +} + +STATIC +VOID +EFIAPI +ApplyVariables ( + VOID + ) +{ + ApplyCpuClockVariables (); + ApplyComboPhyVariables (); + ApplyPcie30Variables (); + ApplyConfigTableVariables (); + ApplyCoolingFanVariables (); + ApplyUsbDpPhyVariables (); + ApplyDebugSerialPortVariables (); + + InstallConfigAppliedProtocol (); + + AfterApplyVariablesInit (); +} + +STATIC +VOID +RK3588SetupAudio ( + IN VOID + ) +{ + // Source PLL, ACPI expects this exact rate. + HAL_CRU_ClkSetFreq (PLL_AUPLL, 786432000); + + // Warning: Only enable I2S if present. + // E.g. Enabling I2S1 on OPI5+ causes PCIe devices to disappear + if (FixedPcdGetBool(PcdI2S0Supported)){ + //Configure I2S0 (e.g. Orange Pi 5 Plus) + GpioPinSetFunction(1, GPIO_PIN_PD4, 2); //i2s0_sdi0 + GpioPinSetFunction(1, GPIO_PIN_PC7, 1); //i2s0_sdo0 + + GpioPinSetFunction(1, GPIO_PIN_PC5, 1); //i2s0_lrck + GpioPinSetFunction(1, GPIO_PIN_PC3, 1); //i2s0_sclk + GpioPinSetFunction(1, GPIO_PIN_PC2, 1); //i2s0_mclk + + HAL_CRU_ClkSetMux (CLK_I2S0_8CH_TX_SRC, 0x1); // clk_aupll_mux + HAL_CRU_ClkSetMux (MCLK_I2S0_8CH_TX, 0x1); // clk_i2s0_8ch_tx_frac + } + + if (FixedPcdGetBool(PcdI2S1Supported)){ + //Configure I2S1 (e.g. Orange Pi 5) + GpioPinSetFunction(4, GPIO_PIN_PA6, 3); //i2s1m0_sdi1 + GpioPinSetFunction(4, GPIO_PIN_PB4, 3); //i2s1m0_sdo3 + + GpioPinSetFunction(4, GPIO_PIN_PA2, 3); //i2s1m0_lrck + GpioPinSetFunction(4, GPIO_PIN_PA1, 3); //i2s1m0_sclk + GpioPinSetFunction(4, GPIO_PIN_PA0, 3); //i2s1m0_mclk + + // CLK_I2S1_8CH_TX_SRC fixed parent: PLL_CPLL + HAL_CRU_ClkSetMux (MCLK_I2S1_8CH_TX, 0x1); // clk_i2s1_8ch_tx_frac + } +} + +EFI_STATUS +RK3588InitPeripherals ( + IN VOID + ) +{ + DEBUG((DEBUG_INIT, "RK3588InitPeripherals: Entry\n")); + + RK3588SetupAudio (); + + Rk806Configure(); + + return EFI_SUCCESS; +} + +STATIC VOID SetFlashAttributeToUncache(VOID) +{ + EFI_STATUS Status; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR desp = {0}; + + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + PcdGet64(FspiBaseAddr), + SIZE_64KB, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC: Failed to add memory space Status = %r\n", Status)); + return; + } + + Status = gDS->GetMemorySpaceDescriptor(PcdGet64(FspiBaseAddr),&desp); + if(EFI_ERROR(Status)){ + DEBUG ((DEBUG_ERROR, "%a: GetMemorySpaceDescriptor failed = %x\n", __FUNCTION__, Status)); + return; + } + + Status = gDS->SetMemorySpaceAttributes ( + PcdGet64(FspiBaseAddr), + SIZE_64KB, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes Status = %x\n",__FUNCTION__, Status)); + } + + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + PcdGet64(CruBaseAddr), + SIZE_64KB, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "RTC: Failed to add memory space Status = %r\n", Status)); + return; + } + + Status = gDS->GetMemorySpaceDescriptor(PcdGet64(CruBaseAddr),&desp); + if(EFI_ERROR(Status)){ + DEBUG ((DEBUG_ERROR, "%a: GetMemorySpaceDescriptor failed = %x\n", __FUNCTION__, Status)); + return; + } + + Status = gDS->SetMemorySpaceAttributes ( + PcdGet64(CruBaseAddr), + SIZE_64KB, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes Status = %x\n",__FUNCTION__, Status)); + } +} + +STATIC +VOID +EFIAPI +OnEfiVariableWriteArchRegistrationEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumProtocols; + + Status = gBS->LocateHandleBuffer (ByProtocol, + &gEfiVariableWriteArchProtocolGuid, + NULL, + &NumProtocols, + &HandleBuffer); + if (EFI_ERROR(Status)) { + if (Status != EFI_NOT_FOUND) { + DEBUG((DEBUG_WARN, "Couldn't locate gEfiVariableWriteArchProtocolGuid. Status=%r\n", Status)); + } + return; + } + + gBS->CloseEvent (Event); + + Status = SetupVariables (); + if (Status != EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "Couldn't setup NV vars. Status=%r\n", Status)); + } + + ApplyVariables (); + + Status = InstallHiiPages (); + if (Status != EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "Couldn't install RK3588Dxe HII pages. Status=%r\n", Status)); + } +} + +VOID +EFIAPI +RK3588NotifyReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // We set CPU voltages late on first notification of the ReadyToBoot event because + // the user should have a chance to dial settings back in case they've set values that are + // too high and/or the power supply is insufficient. Setting them earlier may prevent this. + // The default values provide enough performance for the UEFI environment, so there's + // really no need to set them early. + // + + DEBUG ((DEBUG_INFO, "%a: called. Configure CPU voltages once.\n", __FUNCTION__)); + + ApplyCpuVoltageVariables (); + + gBS->CloseEvent (Event); +} + + +/** + This function uninstalls the recently added EFI_MEMORY_ATTRIBUTE_PROTOCOL + to workaround older versions of OS loaders/shims using it incorrectly and + throwing a Synchronous Exception. + + See: + - https://github.com/microsoft/mu_silicon_arm_tiano/issues/124 + - https://edk2.groups.io/g/devel/topic/99631663 +**/ +STATIC +VOID +EFIAPI +UninstallMemoryAttributeProtocol ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HANDLE *Handles; + UINTN HandleCount; + EFI_MEMORY_ATTRIBUTE_PROTOCOL *MemoryAttributeProtocol; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiMemoryAttributeProtocolGuid, + NULL, + &HandleCount, + &Handles + ); + ASSERT_EFI_ERROR (Status); + ASSERT (HandleCount == 1); + + Status = gBS->HandleProtocol ( + Handles[0], + &gEfiMemoryAttributeProtocolGuid, + (VOID **)&MemoryAttributeProtocol + ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->UninstallMultipleProtocolInterfaces ( + Handles[0], + &gEfiMemoryAttributeProtocolGuid, + MemoryAttributeProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + + gBS->FreePool (Handles); +} + +STATIC +VOID +EFIAPI +RK3588NotifyEndOfDxe ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gBS->CloseEvent (Event); + + UninstallMemoryAttributeProtocol (); +} + +EFI_STATUS +EFIAPI +RK3588EntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + VOID *EfiVariableArchRegistrationEvent; + EFI_EVENT Event; + + PlatformEarlyInit(); + + // + // We actually depend on gEfiVariableWriteArchProtocolGuid but don't want to + // delay the entire driver, so we create a notify event on protocol arrival instead + // and set up the variables & HII data in the callback. + // + EfiCreateProtocolNotifyEvent (&gEfiVariableWriteArchProtocolGuid, + TPL_CALLBACK, + OnEfiVariableWriteArchRegistrationEvent, + NULL, + &EfiVariableArchRegistrationEvent); + + Status = EfiCreateEventReadyToBootEx (TPL_CALLBACK, + RK3588NotifyReadyToBoot, + NULL, + &Event); + ASSERT_EFI_ERROR (Status); + + Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + RK3588NotifyEndOfDxe, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &Event); + ASSERT_EFI_ERROR (Status); + + Status = RK3588InitPeripherals (); + if (EFI_ERROR (Status)) { + return Status; + } + + SetFlashAttributeToUncache(); + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.h new file mode 100644 index 0000000..1aa55e5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.h @@ -0,0 +1,12 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __RK3588DXE_H__ +#define __RK3588DXE_H__ + +#endif /* __RK3588DXE_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf new file mode 100644 index 0000000..93d266f --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf @@ -0,0 +1,119 @@ +# +# Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2018, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = RK3588Dxe + FILE_GUID = f6c64348-45ec-11ec-9726-f42a7dcb925d + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = RK3588EntryPoint + +[Sources.common] + RK3588Dxe.c + RK3588DxeHii.uni + RK3588DxeHii.vfr + CpuPerformance.c + ComboPhy.c + PciExpress30.c + ConfigTable.c + FanControl.c + UsbDpPhy.c + DebugSerialPort.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + CacheMaintenanceLib + DebugLib + IoLib + BaseMemoryLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiLib + UefiDriverEntryPoint + DxeServicesTableLib + SpiLib + RK806 + CruLib + ArmLib + NonDiscoverableDeviceRegistrationLib + HiiLib + PcdLib + RockchipPlatformLib + +[Protocols] + gEfiVariableWriteArchProtocolGuid ## CONSUMES + gEfiMemoryAttributeProtocolGuid ## CONSUMES + gRk860xRegulatorProtocolGuid ## CONSUMES + gRockchipPlatformConfigAppliedProtocolGuid ## PRODUCES + +[Pcd] + gRockchipTokenSpaceGuid.CruBaseAddr + gRockchipTokenSpaceGuid.FspiBaseAddr + + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault + gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset + gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom + gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode + gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom + gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode + gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom + gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode + gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom + + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault + gRK3588TokenSpaceGuid.PcdComboPhy0Mode + gRK3588TokenSpaceGuid.PcdComboPhy1Mode + gRK3588TokenSpaceGuid.PcdComboPhy2Mode + + gRK3588TokenSpaceGuid.PcdPcie30Supported + gRK3588TokenSpaceGuid.PcdPcie30State + gRK3588TokenSpaceGuid.PcdPcie30PhyMode + gRK3588TokenSpaceGuid.PcdPcie30PhyModeDefault + + gRK3588TokenSpaceGuid.PcdConfigTableMode + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatMode + gRK3588TokenSpaceGuid.PcdFdtSupportOverrides + + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput + gRK3588TokenSpaceGuid.PcdCoolingFanState + gRK3588TokenSpaceGuid.PcdCoolingFanSpeed + + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Usb3State + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Usb3State + + gRK3588TokenSpaceGuid.PcdI2S0Supported + gRK3588TokenSpaceGuid.PcdI2S1Supported + +[Guids] + gRK3588DxeFormSetGuid + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeFormSetGuid.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeFormSetGuid.h new file mode 100644 index 0000000..ca10926 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeFormSetGuid.h @@ -0,0 +1,17 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK3588DXE_FORMSET_GUID_H__ +#define __RK3588DXE_FORMSET_GUID_H__ + +#define RK3588DXE_FORMSET_GUID \ + { 0x10f41c33, 0xa468, 0x42cd, { 0x85, 0xee, 0x70, 0x43, 0x21, 0x3f, 0x73, 0xa3 } } + +extern EFI_GUID gRK3588DxeFormSetGuid; + +#endif // __RK3588DXE_FORMSET_GUID_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni new file mode 100644 index 0000000..112a705 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni @@ -0,0 +1,183 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#langdef en-US "English" + +#string STR_NULL_STRING #language en-US "" + +#string STR_FORM_SET_TITLE #language en-US "Rockchip Platform Configuration" +#string STR_FORM_SET_TITLE_HELP #language en-US "Configure various platform settings." +#string STR_FORM_SET_TITLE_SUBTITLE #language en-US "Configuration Options" + +/* + * Common strings + */ +#string STR_DISABLED #language en-US "Disabled" +#string STR_ENABLED #language en-US "Enabled" + +/* + * CPU Performance configuration + */ +#string STR_CPU_PERF_FORM_TITLE #language en-US "CPU Performance" +#string STR_CPU_PERF_FORM_HELP #language en-US "Adjust CPU clocks and voltages." +#string STR_CPU_PERF_FORM_SUBTITLE #language en-US "Note: All these settings may be overridden by the OS if supported." + +#string STR_CPU_PERF_CLUSTER_CLOCKS_SUBTITLE #language en-US "Cluster Clocks" + +#string STR_CPU_PERF_CPUL_CLUSTER_CLOCK_PRESET_PROMPT #language en-US "CPUL Clock Preset" +#string STR_CPU_PERF_CPUL_CLUSTER_CLOCK_PRESET_HELP #language en-US "Clock preset for the Arm LITTLE cores (Cortex-A55) cluster.\n\nBoot default will retain the frequency set by earlier boot stages.\n\nWARNING! Setting Maximum clock rate is NOT recommended without adequate cooling and power supply." +#string STR_CPU_PERF_CPUL_CLUSTER_CLOCK_CUSTOM_PROMPT #language en-US "CPUL Custom Clock (MHz)" +#string STR_CPU_PERF_CPUL_CLUSTER_CLOCK_CUSTOM_HELP #language en-US "Custom target clock for the Arm LITTLE cores (Cortex-A55) cluster.\n\nNote that the actual frequency will vary with voltage starting from 816 MHz." + +#string STR_CPU_PERF_CPUB01_CLUSTER_CLOCK_PRESET_PROMPT #language en-US "CPUB01 Clock Preset" +#string STR_CPU_PERF_CPUB01_CLUSTER_CLOCK_CUSTOM_PROMPT #language en-US "CPUB01 Custom Clock (MHz)" + +#string STR_CPU_PERF_CPUB23_CLUSTER_CLOCK_PRESET_PROMPT #language en-US "CPUB23 Clock Preset" +#string STR_CPU_PERF_CPUB23_CLUSTER_CLOCK_CUSTOM_PROMPT #language en-US "CPUB23 Custom Clock (MHz)" + +#string STR_CPU_PERF_CPUB_CLUSTER_CLOCK_PRESET_HELP #language en-US "Clock preset for the selected Arm big cores (Cortex-A76) cluster.\n\nBoot default will retain the frequency set by earlier boot stages.\n\nWARNING! Setting Maximum clock rate is NOT recommended without adequate cooling and power supply." +#string STR_CPU_PERF_CPUB_CLUSTER_CLOCK_CUSTOM_HELP #language en-US "Custom target clock for the selected Arm big cores (Cortex-A76) cluster.\n\nNote that the actual frequency will vary with voltage starting from 816 MHz." + +#string STR_CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEF #language en-US "Boot default" +#string STR_CPU_PERF_CLUSTER_CLOCK_PRESET_MIN #language en-US "Minimum" +#string STR_CPU_PERF_CLUSTER_CLOCK_PRESET_MAX #language en-US "Maximum" +#string STR_CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM #language en-US "Custom" + +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_408 #language en-US "408" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_600 #language en-US "600" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_816 #language en-US "816" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1008 #language en-US "1008" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1200 #language en-US "1200" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1416 #language en-US "1416" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1608 #language en-US "1608" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1800 #language en-US "1800" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2016 #language en-US "2016" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2208 #language en-US "2208" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2256 #language en-US "2256" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2304 #language en-US "2304" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2352 #language en-US "2352" +#string STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2400 #language en-US "2400" + +#string STR_CPU_PERF_CLUSTER_VOLTAGES_SUBTITLE #language en-US "Cluster Voltages" + +#string STR_CPU_PERF_CPUL_CLUSTER_VOLTAGE_MODE_PROMPT #language en-US "CPUL Voltage Mode" +#string STR_CPU_PERF_CPUL_CLUSTER_VOLTAGE_MODE_HELP #language en-US "Voltage mode for the Arm LITTLE cores (Cortex-A55) cluster.\n\n Automatic = voltage is set according to predefined OPP table.\n Custom = voltage is user-controlled, affecting clock rate too due to PVTPLL." +#string STR_CPU_PERF_CPUL_CLUSTER_VOLTAGE_CUSTOM_PROMPT #language en-US "CPUL Custom Volt (uV)" +#string STR_CPU_PERF_CPUL_CLUSTER_VOLTAGE_CUSTOM_HELP #language en-US "Custom regulator voltage for the Arm LITTLE cores (Cortex-A55) cluster.\n\nUse +/- keys to increment/decrement value by the predefined step.\n\nWARNING! Higher custom voltage may cause system instability and excessive heat." + +#string STR_CPU_PERF_CPUB01_CLUSTER_VOLTAGE_MODE_PROMPT #language en-US "CPUB01 Voltage Mode" +#string STR_CPU_PERF_CPUB01_CLUSTER_VOLTAGE_CUSTOM_PROMPT #language en-US "CPUB01 Custom Volt (uV)" + +#string STR_CPU_PERF_CPUB23_CLUSTER_VOLTAGE_MODE_PROMPT #language en-US "CPUB23 Voltage Mode" +#string STR_CPU_PERF_CPUB23_CLUSTER_VOLTAGE_CUSTOM_PROMPT #language en-US "CPUB23 Custom Volt (uV)" + +#string STR_CPU_PERF_CPUB_CLUSTER_VOLTAGE_MODE_HELP #language en-US "Voltage mode for the selected Arm big cores (Cortex-A76) cluster.\n\n Automatic = voltage is set according to predefined OPP table.\n Custom = voltage is user-controlled, affecting clock rate too due to PVTPLL." +#string STR_CPU_PERF_CPUB_CLUSTER_VOLTAGE_CUSTOM_HELP #language en-US "Custom regulator voltage for the selected Arm big cores (Cortex-A76) cluster.\n\nUse +/- keys to increment/decrement value by the predefined step.\n\nWARNING! Higher custom voltage may cause system instability and excessive heat." + +#string STR_CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO #language en-US "Automatic" +#string STR_CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM #language en-US "Custom" + +/* + * PCIe/SATA/USB Combo PIPE PHY configuration + */ +#string STR_COMBO_PHY_FORM_TITLE #language en-US "PCIe/SATA/USB Combo PIPE PHY" +#string STR_COMBO_PHY_FORM_HELP #language en-US "Configure the Combo PIPE PHY operation modes." +#string STR_COMBO_PHY_FORM_SUBTITLE #language en-US "Note: the selected mode must match the interface of the connected device." + +#string STR_COMBO_PHY0_MODE_PROMPT #language en-US "PHY #0 Mode" +#string STR_COMBO_PHY1_MODE_PROMPT #language en-US "PHY #1 Mode" +#string STR_COMBO_PHY2_MODE_PROMPT #language en-US "PHY #2 Mode" + +#string STR_COMBO_PHY_MODE_UNCONNECTED #language en-US "Unconnected" +#string STR_COMBO_PHY_MODE_PCIE #language en-US "PCIe 2.1 x1" +#string STR_COMBO_PHY_MODE_SATA #language en-US "SATA 3.1" +#string STR_COMBO_PHY_MODE_USB3 #language en-US "USB 3.1 Gen 1" + +#string STR_COMBO_PHY_MODE_DEFAULT_UNCONNECTED_HELP #language en-US "This PHY may not be wired to any slot or device." +#string STR_COMBO_PHY_MODE_DEFAULT_PCIE_HELP #language en-US "This PHY may be wired to an M.2 or Mini PCIe slot.\n\nConsult your platform's documentation for details on potential alternate modes, such as SATA or USB." +#string STR_COMBO_PHY_MODE_DEFAULT_SATA_HELP #language en-US "This PHY may be wired to a SATA or M.2 slot.\n\nConsult your platform's documentation for details on potential alternate modes, such as PCIe or USB." +#string STR_COMBO_PHY_MODE_DEFAULT_USB3_HELP #language en-US "This PHY is wired to an USB 3.1 Gen 1 Type-A port.\n\nConsult your platform's documentation for details on potential alternate modes, such as PCIe or SATA (via non-standard adapters)." + +/* + * USB/DP Combo PHY configuration + */ +#string STR_USBDP_PHY_FORM_TITLE #language en-US "USB/DP Combo PHY" +#string STR_USBDP_PHY_FORM_HELP #language en-US "Configure the USB/DP Combo PHY operation modes." + +#string STR_USBDP_PHY0_USB3_STATE_PROMPT #language en-US "PHY #0 USB 3 SuperSpeed State" +#string STR_USBDP_PHY1_USB3_STATE_PROMPT #language en-US "PHY #1 USB 3 SuperSpeed State" +#string STR_USBDP_PHY_USB3_STATE_PROMPT #language en-US "Enable or disable SuperSpeed signaling on the selected PHY.\n\nIf USB 3.0 devices connected to the associated Type-C or Type-A port malfunction, disabling this option may help." + +/* + * PCI Express 3.0 configuration + */ +#string STR_PCIE30_FORM_TITLE #language en-US "PCI Express 3.0" +#string STR_PCIE30_FORM_HELP #language en-US "Configure the PCIe 3.0 operation modes." + +#string STR_PCIE30_STATE_PROMPT #language en-US "Support State" +#string STR_PCIE30_STATE_HELP #language en-US "Enable or disable PCIe 3.0 support." + +#string STR_PCIE30_PHY_MODE_PROMPT #language en-US "PHY Mode" +#string STR_PCIE30_PHY_MODE_HELP #language en-US "Choose PHY Mode\n\nx4:\n 4l -> PCIe3 PHY lane 0123\n 2l -> Not connected\n 1l0 -> Combo PHY #1\n 1l1 -> Combo PHY #2\n 1l2 -> Combo PHY #0\n\nx2 x2:\n 4l -> PCIe3 PHY lane 01\n 2l -> PCIe3 PHY lane 23\n 1l0 -> Combo PHY #1\n 1l1 -> Combo PHY #2\n 1l2 -> Combo PHY #0\n\nx1x1 x2:\n 4l -> PCIe3 PHY lane 0\n 2l -> PCIe3 PHY lane 23\n 1l0 -> PCIe3 PHY lane 1\n 1l1 -> Combo PHY #2\n 1l2 -> Combo PHY #0\n\nx2 x1x1:\n 4l -> PCIe3 PHY lane 01\n 2l -> PCIe3 PHY lane 2\n 1l0 -> Combo PHY #1\n 1l1 -> PCIe3 PHY lane 3\n 1l2 -> Combo PHY #0\n\nx1x1 x1x1:\n 4l -> PCIe3 PHY lane 0\n 2l -> PCIe3 PHY lane 2\n 1l0 -> PCIe3 PHY lane 1\n 1l1 -> PCIe3 PHY lane 3\n 1l2 -> Combo PHY #0\n" +#string STR_PCIE30_PHY_MODE_AGGREGATION #language en-US "x4" +#string STR_PCIE30_PHY_MODE_NANBNB #language en-US "x2 x2" +#string STR_PCIE30_PHY_MODE_NANBBI #language en-US "x1x1 x2" +#string STR_PCIE30_PHY_MODE_NABINB #language en-US "x2 x1x1" +#string STR_PCIE30_PHY_MODE_NABIBI #language en-US "x1x1 x1x1" + +/* + * ACPI / Device Tree configuration + */ +#string STR_CONFIG_TABLE_FORM_TITLE #language en-US "ACPI / Device Tree" +#string STR_CONFIG_TABLE_FORM_HELP #language en-US "Configure the ACPI and Device Tree system tables support." + +#string STR_CONFIG_TABLE_MODE_PROMPT #language en-US "Config Table Mode" +#string STR_CONFIG_TABLE_MODE_HELP #language en-US "Choose what config tables to expose to the OS.\n\nACPI - provides basic hardware support (USB, PCIe, SATA) for most OS/kernel versions.\n\nDevice Tree - provides extensive hardware support specific to a kernel version.\nThe firmware includes a DTB compatible with Rockchip SDK Linux 5.10 legacy kernel.\n\nIf both are exposed, the OS will decide which one to use." +#string STR_CONFIG_TABLE_MODE_ACPI #language en-US "ACPI" +#string STR_CONFIG_TABLE_MODE_FDT #language en-US "Device Tree" +#string STR_CONFIG_TABLE_MODE_ACPI_FDT #language en-US "Both" + +#string STR_CONFIG_TABLE_ACPI_SUBTITLE #language en-US "ACPI Configuration" + +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_PROMPT #language en-US "PCIe ECAM Compatibility Mode" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_HELP #language en-US "Choose how to expose the non-standard PCIe configuration space to the OS.\n\n" + "Single Device - compatible with all OSes. Allows usage of a single or multi-function device. Switches are not supported.\n\n" + "NXPMX6 - compatible with Windows. Exposes the full bus topology and supports switches.\n\n" + "AMAZON GRAVITON - compatible with Linux. Exposes the full bus topology and supports switches.\n\n" + "The Auto modes select NXPMX6 for Windows and fall back to the second option when booting other OSes." +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV #language en-US "Auto (NXPMX6 + Single Device)" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON #language en-US "Auto (NXPMX6 + AMAZON GRAVITON)" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV #language en-US "Single Device" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6 #language en-US "NXPMX6" +#string STR_ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON #language en-US "AMAZON GRAVITON" + +#string STR_CONFIG_TABLE_FDT_SUBTITLE #language en-US "Device Tree Configuration" +#string STR_FDT_SUPPORT_OVERRIDES_PROMPT #language en-US "Support DTB override & overlays" +#string STR_FDT_SUPPORT_OVERRIDES_HELP #language en-US "Enable or disable support for overriding the firmware-provided DTB and installing overlays.\n\nCheck firmware documentation for more details." + +/* + * Cooling fan configuration + */ + +#string STR_COOLING_FAN_FORM_TITLE #language en-US "Cooling Fan" +#string STR_COOLING_FAN_FORM_HELP #language en-US "Configure the on-board cooling fan." + +#string STR_COOLING_FAN_STATE_PROMPT #language en-US "On-board Fan" +#string STR_COOLING_FAN_STATE_HELP #language en-US "Enable or disable the on-board fan output." + +#string STR_COOLING_FAN_SPEED_PROMPT #language en-US "Fan Speed (%)" +#string STR_COOLING_FAN_SPEED_HELP #language en-US "PWM duty cycle of on-board fan output." + +/* + * Debug Serial Port configuration + */ +#string STR_DEBUG_SERIAL_PORT_FORM_TITLE #language en-US "Debug Serial Port" +#string STR_DEBUG_SERIAL_PORT_FORM_HELP #language en-US "Configure the debug (UART) serial port." +#string STR_DEBUG_SERIAL_PORT_SUBTITLE #language en-US "Note: These settings only take effect in UEFI and might be overridden by the OS. Earlier boot messages will be printed at the default settings." + +#string STR_DEBUG_SERIAL_PORT_BAUD_RATE_PROMPT #language en-US "Baud Rate" diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr new file mode 100644 index 0000000..3ce4b4c --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr @@ -0,0 +1,576 @@ +/** @file + * + * Copyright (c) 2018 Andrei Warkentin + * Copyright (c) 2020, ARM Limited. All rights reserved. + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include + +#include "RK3588DxeFormSetGuid.h" + +#define VFR_FILE_INCLUDE +#include "CpuPerformance.h" +#include "FanControl.h" +#include "DebugSerialPort.h" + +// +// EFI Variable attributes +// +#define EFI_VARIABLE_NON_VOLATILE 0x00000001 +#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 +#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004 +#define EFI_VARIABLE_READ_ONLY 0x00000008 + +formset + guid = RK3588DXE_FORMSET_GUID, + title = STRING_TOKEN(STR_FORM_SET_TITLE), + help = STRING_TOKEN(STR_FORM_SET_TITLE_HELP), + classguid = EFI_HII_PLATFORM_SETUP_FORMSET_GUID, + + efivarstore CPU_PERF_CLUSTER_CLOCK_PRESET_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPULClusterClockPreset, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_CLOCK_CUSTOM_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPULClusterClockCustom, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_CLOCK_PRESET_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPUB01ClusterClockPreset, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_CLOCK_CUSTOM_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPUB01ClusterClockCustom, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_CLOCK_PRESET_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPUB23ClusterClockPreset, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_CLOCK_CUSTOM_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPUB23ClusterClockCustom, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_VOLTAGE_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPULClusterVoltageMode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_VOLTAGE_CUSTOM_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPULClusterVoltageCustom, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_VOLTAGE_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPUB01ClusterVoltageMode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_VOLTAGE_CUSTOM_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPUB01ClusterVoltageCustom, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_VOLTAGE_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPUB23ClusterVoltageMode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CPU_PERF_CLUSTER_VOLTAGE_CUSTOM_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CpuPerf_CPUB23ClusterVoltageCustom, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore COMBO_PHY_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = ComboPhy0Mode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore COMBO_PHY_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = ComboPhy1Mode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore COMBO_PHY_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = ComboPhy2Mode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore USBDP_PHY_USB3_STATE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = UsbDpPhy0Usb3State, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore USBDP_PHY_USB3_STATE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = UsbDpPhy1Usb3State, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore PCIE30_STATE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = Pcie30State, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore PCIE30_PHY_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = Pcie30PhyMode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore CONFIG_TABLE_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = ConfigTableMode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore ACPI_PCIE_ECAM_COMPAT_MODE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = AcpiPcieEcamCompatMode, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore FDT_SUPPORT_OVERRIDES_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = FdtSupportOverrides, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore COOLING_FAN_STATE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CoolingFanState, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore COOLING_FAN_SPEED_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = CoolingFanSpeed, + guid = RK3588DXE_FORMSET_GUID; + + efivarstore DEBUG_SERIAL_PORT_BAUD_RATE_VARSTORE_DATA, + attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE, + name = DebugSerialPortBaudRate, + guid = RK3588DXE_FORMSET_GUID; + + form formid = 1, + title = STRING_TOKEN(STR_FORM_SET_TITLE); + subtitle text = STRING_TOKEN(STR_FORM_SET_TITLE_SUBTITLE); + + subtitle text = STRING_TOKEN(STR_NULL_STRING); + + goto 0x1000, + prompt = STRING_TOKEN(STR_CPU_PERF_FORM_TITLE), + help = STRING_TOKEN(STR_CPU_PERF_FORM_HELP); + + goto 0x1001, + prompt = STRING_TOKEN(STR_COMBO_PHY_FORM_TITLE), + help = STRING_TOKEN(STR_COMBO_PHY_FORM_HELP); + +#if FixedPcdGetBool (PcdUsbDpPhy0Supported) || FixedPcdGetBool (PcdUsbDpPhy1Supported) + goto 0x1002, + prompt = STRING_TOKEN(STR_USBDP_PHY_FORM_TITLE), + help = STRING_TOKEN(STR_USBDP_PHY_FORM_HELP); +#endif + +#if FixedPcdGetBool (PcdPcie30Supported) + goto 0x1003, + prompt = STRING_TOKEN(STR_PCIE30_FORM_TITLE), + help = STRING_TOKEN(STR_PCIE30_FORM_HELP); +#endif + + goto 0x1004, + prompt = STRING_TOKEN(STR_CONFIG_TABLE_FORM_TITLE), + help = STRING_TOKEN(STR_CONFIG_TABLE_FORM_HELP); + +#if FixedPcdGetBool (PcdHasOnBoardFanOutput) + goto 0x1005, + prompt = STRING_TOKEN(STR_COOLING_FAN_FORM_TITLE), + help = STRING_TOKEN(STR_COOLING_FAN_FORM_HELP); +#endif + + goto 0x1006, + prompt = STRING_TOKEN(STR_DEBUG_SERIAL_PORT_FORM_TITLE), + help = STRING_TOKEN(STR_DEBUG_SERIAL_PORT_FORM_HELP); + endform; + + form formid = 0x1000, + title = STRING_TOKEN(STR_CPU_PERF_FORM_TITLE); + subtitle text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCKS_SUBTITLE); + + oneof varid = CpuPerf_CPULClusterClockPreset.Preset, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUL_CLUSTER_CLOCK_PRESET_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUL_CLUSTER_CLOCK_PRESET_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet32 (PcdCPULClusterClockPresetDefault), + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEF), value = CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_MIN), value = CPU_PERF_CLUSTER_CLOCK_PRESET_MIN, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_MAX), value = CPU_PERF_CLUSTER_CLOCK_PRESET_MAX, flags = DEFAULT; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM), value = CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM, flags = 0; + endoneof; + + grayoutif NOT ideqval CpuPerf_CPULClusterClockPreset.Preset == CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM; + oneof varid = CpuPerf_CPULClusterClockCustom.Mhz, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUL_CLUSTER_CLOCK_CUSTOM_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUL_CLUSTER_CLOCK_CUSTOM_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_408), value = 408, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_600), value = 600, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_816), value = 816, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1008), value = 1008, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1200), value = 1200, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1416), value = 1416, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1608), value = 1608, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1800), value = 1800, flags = DEFAULT; + endoneof; + endif; + + oneof varid = CpuPerf_CPUB01ClusterClockPreset.Preset, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUB01_CLUSTER_CLOCK_PRESET_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUB_CLUSTER_CLOCK_PRESET_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet32 (PcdCPUB01ClusterClockPresetDefault), + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEF), value = CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_MIN), value = CPU_PERF_CLUSTER_CLOCK_PRESET_MIN, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_MAX), value = CPU_PERF_CLUSTER_CLOCK_PRESET_MAX, flags = DEFAULT; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM), value = CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM, flags = 0; + endoneof; + + grayoutif NOT ideqval CpuPerf_CPUB01ClusterClockPreset.Preset == CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM; + oneof varid = CpuPerf_CPUB01ClusterClockCustom.Mhz, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUB01_CLUSTER_CLOCK_CUSTOM_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUB_CLUSTER_CLOCK_CUSTOM_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_408), value = 408, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_600), value = 600, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_816), value = 816, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1008), value = 1008, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1200), value = 1200, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1416), value = 1416, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1608), value = 1608, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1800), value = 1800, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2016), value = 2016, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2208), value = 2208, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2256), value = 2256, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2304), value = 2304, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2352), value = 2352, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2400), value = 2400, flags = DEFAULT; + endoneof; + endif; + + oneof varid = CpuPerf_CPUB23ClusterClockPreset.Preset, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUB23_CLUSTER_CLOCK_PRESET_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUB_CLUSTER_CLOCK_PRESET_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet32 (PcdCPUB23ClusterClockPresetDefault), + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEF), value = CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_MIN), value = CPU_PERF_CLUSTER_CLOCK_PRESET_MIN, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_MAX), value = CPU_PERF_CLUSTER_CLOCK_PRESET_MAX, flags = DEFAULT; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM), value = CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM, flags = 0; + endoneof; + + grayoutif NOT ideqval CpuPerf_CPUB23ClusterClockPreset.Preset == CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM; + oneof varid = CpuPerf_CPUB23ClusterClockCustom.Mhz, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUB23_CLUSTER_CLOCK_CUSTOM_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUB_CLUSTER_CLOCK_CUSTOM_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_408), value = 408, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_600), value = 600, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_816), value = 816, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1008), value = 1008, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1200), value = 1200, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1416), value = 1416, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1608), value = 1608, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_1800), value = 1800, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2016), value = 2016, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2208), value = 2208, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2256), value = 2256, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2304), value = 2304, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2352), value = 2352, flags = 0; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_CLOCK_CUSTOM_2400), value = 2400, flags = DEFAULT; + endoneof; + endif; + + subtitle text = STRING_TOKEN(STR_NULL_STRING); + subtitle text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_VOLTAGES_SUBTITLE); + + oneof varid = CpuPerf_CPULClusterVoltageMode.Mode, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUL_CLUSTER_VOLTAGE_MODE_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUL_CLUSTER_VOLTAGE_MODE_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO), value = CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO, flags = DEFAULT; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM), value = CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM, flags = 0; + endoneof; + + grayoutif NOT ideqval CpuPerf_CPULClusterVoltageMode.Mode == CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM; + numeric varid = CpuPerf_CPULClusterVoltageCustom.Microvolts, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUL_CLUSTER_VOLTAGE_CUSTOM_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUL_CLUSTER_VOLTAGE_CUSTOM_HELP), + flags = DISPLAY_UINT_DEC | NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + minimum = CLUSTER_MICROVOLTS_MIN, + maximum = CLUSTER_MICROVOLTS_MAX, + step = CLUSTER_MICROVOLTS_STEP, + default = CPUL_CLUSTER_MICROVOLTS_DEFAULT, + endnumeric; + endif; + + oneof varid = CpuPerf_CPUB01ClusterVoltageMode.Mode, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUB01_CLUSTER_VOLTAGE_MODE_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUB_CLUSTER_VOLTAGE_MODE_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO), value = CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO, flags = DEFAULT; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM), value = CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM, flags = 0; + endoneof; + + grayoutif NOT ideqval CpuPerf_CPUB01ClusterVoltageMode.Mode == CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM; + numeric varid = CpuPerf_CPUB01ClusterVoltageCustom.Microvolts, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUB01_CLUSTER_VOLTAGE_CUSTOM_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUB_CLUSTER_VOLTAGE_CUSTOM_HELP), + flags = DISPLAY_UINT_DEC | NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + minimum = CLUSTER_MICROVOLTS_MIN, + maximum = CLUSTER_MICROVOLTS_MAX, + step = CLUSTER_MICROVOLTS_STEP, + default = CPUB_CLUSTER_MICROVOLTS_DEFAULT, + endnumeric; + endif; + + oneof varid = CpuPerf_CPUB23ClusterVoltageMode.Mode, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUB23_CLUSTER_VOLTAGE_MODE_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUB_CLUSTER_VOLTAGE_MODE_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO), value = CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO, flags = DEFAULT; + option text = STRING_TOKEN(STR_CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM), value = CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM, flags = 0; + endoneof; + + grayoutif NOT ideqval CpuPerf_CPUB23ClusterVoltageMode.Mode == CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM; + numeric varid = CpuPerf_CPUB23ClusterVoltageCustom.Microvolts, + prompt = STRING_TOKEN(STR_CPU_PERF_CPUB23_CLUSTER_VOLTAGE_CUSTOM_PROMPT), + help = STRING_TOKEN(STR_CPU_PERF_CPUB_CLUSTER_VOLTAGE_CUSTOM_HELP), + flags = DISPLAY_UINT_DEC | NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + minimum = CLUSTER_MICROVOLTS_MIN, + maximum = CLUSTER_MICROVOLTS_MAX, + step = CLUSTER_MICROVOLTS_STEP, + default = CPUB_CLUSTER_MICROVOLTS_DEFAULT, + endnumeric; + endif; + + subtitle text = STRING_TOKEN(STR_NULL_STRING); + subtitle text = STRING_TOKEN(STR_CPU_PERF_FORM_SUBTITLE); + endform; + + form formid = 0x1001, + title = STRING_TOKEN(STR_COMBO_PHY_FORM_TITLE); + + grayoutif FixedPcdGetBool (PcdComboPhy0Switchable) == 0; + oneof varid = ComboPhy0Mode.Mode, + prompt = STRING_TOKEN(STR_COMBO_PHY0_MODE_PROMPT), +#if FixedPcdGet32 (PcdComboPhy0ModeDefault) == COMBO_PHY_MODE_PCIE + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_PCIE_HELP), +#elif FixedPcdGet32 (PcdComboPhy0ModeDefault) == COMBO_PHY_MODE_SATA + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_SATA_HELP), +#elif FixedPcdGet32 (PcdComboPhy0ModeDefault) == COMBO_PHY_MODE_USB3 + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_USB3_HELP), +#else + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_UNCONNECTED_HELP), +#endif + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet32 (PcdComboPhy0ModeDefault), + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_UNCONNECTED), value = COMBO_PHY_MODE_UNCONNECTED, flags = 0; + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_PCIE), value = COMBO_PHY_MODE_PCIE, flags = 0; + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_SATA), value = COMBO_PHY_MODE_SATA, flags = 0; + endoneof; + endif; + + grayoutif FixedPcdGetBool (PcdComboPhy1Switchable) == 0; + oneof varid = ComboPhy1Mode.Mode, + prompt = STRING_TOKEN(STR_COMBO_PHY1_MODE_PROMPT), +#if FixedPcdGet32 (PcdComboPhy1ModeDefault) == COMBO_PHY_MODE_PCIE + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_PCIE_HELP), +#elif FixedPcdGet32 (PcdComboPhy1ModeDefault) == COMBO_PHY_MODE_SATA + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_SATA_HELP), +#elif FixedPcdGet32 (PcdComboPhy1ModeDefault) == COMBO_PHY_MODE_USB3 + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_USB3_HELP), +#else + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_UNCONNECTED_HELP), +#endif + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet32 (PcdComboPhy1ModeDefault), + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_UNCONNECTED), value = COMBO_PHY_MODE_UNCONNECTED, flags = 0; + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_PCIE), value = COMBO_PHY_MODE_PCIE, flags = 0; + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_SATA), value = COMBO_PHY_MODE_SATA, flags = 0; + endoneof; + endif; + + grayoutif FixedPcdGetBool (PcdComboPhy2Switchable) == 0; + oneof varid = ComboPhy2Mode.Mode, + prompt = STRING_TOKEN(STR_COMBO_PHY2_MODE_PROMPT), +#if FixedPcdGet32 (PcdComboPhy2ModeDefault) == COMBO_PHY_MODE_PCIE + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_PCIE_HELP), +#elif FixedPcdGet32 (PcdComboPhy2ModeDefault) == COMBO_PHY_MODE_SATA + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_SATA_HELP), +#elif FixedPcdGet32 (PcdComboPhy2ModeDefault) == COMBO_PHY_MODE_USB3 + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_USB3_HELP), +#else + help = STRING_TOKEN(STR_COMBO_PHY_MODE_DEFAULT_UNCONNECTED_HELP), +#endif + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet32 (PcdComboPhy2ModeDefault), + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_UNCONNECTED), value = COMBO_PHY_MODE_UNCONNECTED, flags = 0; + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_PCIE), value = COMBO_PHY_MODE_PCIE, flags = 0; + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_SATA), value = COMBO_PHY_MODE_SATA, flags = 0; + option text = STRING_TOKEN(STR_COMBO_PHY_MODE_USB3), value = COMBO_PHY_MODE_USB3, flags = 0; + endoneof; + endif; + + subtitle text = STRING_TOKEN(STR_NULL_STRING); + subtitle text = STRING_TOKEN(STR_COMBO_PHY_FORM_SUBTITLE); + endform; + + form formid = 0x1002, + title = STRING_TOKEN(STR_USBDP_PHY_FORM_TITLE); + +#if FixedPcdGetBool (PcdUsbDpPhy0Supported) + oneof varid = UsbDpPhy0Usb3State.State, + prompt = STRING_TOKEN(STR_USBDP_PHY0_USB3_STATE_PROMPT), + help = STRING_TOKEN(STR_USBDP_PHY_USB3_STATE_PROMPT), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = USBDP_PHY_USB3_STATE_ENABLED, + option text = STRING_TOKEN(STR_ENABLED), value = USBDP_PHY_USB3_STATE_ENABLED, flags = 0; + option text = STRING_TOKEN(STR_DISABLED), value = USBDP_PHY_USB3_STATE_DISABLED, flags = 0; + endoneof; +#endif + +#if FixedPcdGetBool (PcdUsbDpPhy1Supported) + oneof varid = UsbDpPhy1Usb3State.State, + prompt = STRING_TOKEN(STR_USBDP_PHY1_USB3_STATE_PROMPT), + help = STRING_TOKEN(STR_USBDP_PHY_USB3_STATE_PROMPT), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = USBDP_PHY_USB3_STATE_ENABLED, + option text = STRING_TOKEN(STR_ENABLED), value = USBDP_PHY_USB3_STATE_ENABLED, flags = 0; + option text = STRING_TOKEN(STR_DISABLED), value = USBDP_PHY_USB3_STATE_DISABLED, flags = 0; + endoneof; +#endif + endform; + +#if FixedPcdGetBool (PcdPcie30Supported) + form formid = 0x1003, + title = STRING_TOKEN(STR_PCIE30_FORM_TITLE); + + oneof varid = Pcie30State.State, + prompt = STRING_TOKEN(STR_PCIE30_STATE_PROMPT), + help = STRING_TOKEN(STR_PCIE30_STATE_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = PCIE30_STATE_ENABLED, + option text = STRING_TOKEN(STR_DISABLED), value = PCIE30_STATE_DISABLED, flags = 0; + option text = STRING_TOKEN(STR_ENABLED), value = PCIE30_STATE_ENABLED, flags = 0; + endoneof; + + /* shoule we move this to single PHY settings form */ + oneof varid = Pcie30PhyMode.Mode, + prompt = STRING_TOKEN(STR_PCIE30_PHY_MODE_PROMPT), + help = STRING_TOKEN(STR_PCIE30_PHY_MODE_HELP), + flags = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet8 (PcdPcie30PhyModeDefault), + option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_AGGREGATION), value = PCIE30_PHY_MODE_AGGREGATION, flags = 0; + option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_NANBNB), value = PCIE30_PHY_MODE_NANBNB, flags = 0; + option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_NANBBI), value = PCIE30_PHY_MODE_NANBBI, flags = 0; + option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_NABINB), value = PCIE30_PHY_MODE_NABINB, flags = 0; + option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_NABIBI), value = PCIE30_PHY_MODE_NABIBI, flags = 0; + endoneof; + endform; +#endif + + form formid = 0x1004, + title = STRING_TOKEN(STR_CONFIG_TABLE_FORM_TITLE); + + oneof varid = ConfigTableMode.Mode, + prompt = STRING_TOKEN(STR_CONFIG_TABLE_MODE_PROMPT), + help = STRING_TOKEN(STR_CONFIG_TABLE_MODE_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = CONFIG_TABLE_MODE_ACPI, + option text = STRING_TOKEN(STR_CONFIG_TABLE_MODE_ACPI), value = CONFIG_TABLE_MODE_ACPI, flags = 0; + option text = STRING_TOKEN(STR_CONFIG_TABLE_MODE_FDT), value = CONFIG_TABLE_MODE_FDT, flags = 0; + option text = STRING_TOKEN(STR_CONFIG_TABLE_MODE_ACPI_FDT), value = CONFIG_TABLE_MODE_ACPI_FDT, flags = 0; + endoneof; + + suppressif (get(ConfigTableMode.Mode) & CONFIG_TABLE_MODE_ACPI) == 0; + subtitle text = STRING_TOKEN(STR_NULL_STRING); + subtitle text = STRING_TOKEN(STR_CONFIG_TABLE_ACPI_SUBTITLE); + + oneof varid = AcpiPcieEcamCompatMode.Mode, + prompt = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_PROMPT), + help = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_HELP), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = FixedPcdGet32 (PcdAcpiPcieEcamCompatModeDefault), + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV, flags = 0; + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON, flags = 0; + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV), value = ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV, flags = 0; + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6), value = ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6, flags = 0; + option text = STRING_TOKEN(STR_ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON), value = ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON, flags = 0; + endoneof; + endif; + + suppressif (get(ConfigTableMode.Mode) & CONFIG_TABLE_MODE_FDT) == 0; + subtitle text = STRING_TOKEN(STR_NULL_STRING); + subtitle text = STRING_TOKEN(STR_CONFIG_TABLE_FDT_SUBTITLE); + + oneof varid = FdtSupportOverrides.State, + prompt = STRING_TOKEN(STR_FDT_SUPPORT_OVERRIDES_PROMPT), + help = STRING_TOKEN(STR_FDT_SUPPORT_OVERRIDES_HELP), + flags = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + default = FALSE, + option text = STRING_TOKEN(STR_DISABLED), value = FALSE, flags = 0; + option text = STRING_TOKEN(STR_ENABLED), value = TRUE, flags = 0; + endoneof; + endif; + endform; + +#if FixedPcdGetBool (PcdHasOnBoardFanOutput) + form formid = 0x1005, + title = STRING_TOKEN(STR_COOLING_FAN_FORM_TITLE); + + oneof varid = CoolingFanState.State, + prompt = STRING_TOKEN(STR_COOLING_FAN_STATE_PROMPT), + help = STRING_TOKEN(STR_COOLING_FAN_STATE_PROMPT), + flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + default = COOLING_FAN_STATE_ENABLED, + option text = STRING_TOKEN(STR_DISABLED), value = COOLING_FAN_STATE_DISABLED, flags = 0; + option text = STRING_TOKEN(STR_ENABLED), value = COOLING_FAN_STATE_ENABLED, flags = 0; + endoneof; + + grayoutif NOT ideqval CoolingFanState.State == COOLING_FAN_STATE_ENABLED; + numeric varid = CoolingFanSpeed.Percentage, + prompt = STRING_TOKEN(STR_COOLING_FAN_SPEED_PROMPT), + help = STRING_TOKEN(STR_COOLING_FAN_SPEED_PROMPT), + flags = DISPLAY_UINT_DEC | NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED, + minimum = FAN_PERCENTAGE_MIN, + maximum = FAN_PERCENTAGE_MAX, + step = FAN_PERCENTAGE_STEP, + default = FAN_PERCENTAGE_DEFAULT, + endnumeric; + endif; + endform; +#endif + + form formid = 0x1006, + title = STRING_TOKEN(STR_DEBUG_SERIAL_PORT_FORM_TITLE); + + numeric varid = DebugSerialPortBaudRate.Value, + prompt = STRING_TOKEN(STR_DEBUG_SERIAL_PORT_BAUD_RATE_PROMPT), + help = STRING_TOKEN(STR_NULL_STRING), + flags = DISPLAY_UINT_DEC | NUMERIC_SIZE_8 | INTERACTIVE | RESET_REQUIRED, + minimum = DEBUG_SERIAL_PORT_BAUD_RATE_MIN, + maximum = DEBUG_SERIAL_PORT_BAUD_RATE_MAX, + step = 0, + default = DEBUG_SERIAL_PORT_BAUD_RATE_DEFAULT, + endnumeric; + + subtitle text = STRING_TOKEN(STR_NULL_STRING); + subtitle text = STRING_TOKEN(STR_DEBUG_SERIAL_PORT_SUBTITLE); + endform; + +endformset; diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/UsbDpPhy.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/UsbDpPhy.c new file mode 100644 index 0000000..b2cb799 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/UsbDpPhy.c @@ -0,0 +1,52 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include + +#include "RK3588DxeFormSetGuid.h" +#include "UsbDpPhy.h" + +VOID +EFIAPI +ApplyUsbDpPhyVariables ( + VOID + ) +{ + /* nothing to do here, the PCDs are read by UsbDpPhyDxe */ +} + +VOID +EFIAPI +SetupUsbDpPhyVariables ( + VOID + ) +{ + UINTN Size; + UINT32 Var32; + EFI_STATUS Status; + + Size = sizeof (UINT32); + + Status = gRT->GetVariable (L"UsbDpPhy0Usb3State", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdUsbDpPhy0Usb3State, USBDP_PHY_USB3_STATE_ENABLED); + ASSERT_EFI_ERROR (Status); + } + + Status = gRT->GetVariable (L"UsbDpPhy1Usb3State", + &gRK3588DxeFormSetGuid, + NULL, &Size, &Var32); + if (EFI_ERROR (Status)) { + Status = PcdSet32S (PcdUsbDpPhy1Usb3State, USBDP_PHY_USB3_STATE_ENABLED); + ASSERT_EFI_ERROR (Status); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/UsbDpPhy.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/UsbDpPhy.h new file mode 100644 index 0000000..7ae4364 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/UsbDpPhy.h @@ -0,0 +1,29 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK3588DXE_USBDP_PHY_H__ +#define __RK3588DXE_USBDP_PHY_H__ + +// +// Don't declare these in the VFR file. +// +#ifndef VFR_FILE_INCLUDE +VOID +EFIAPI +ApplyUsbDpPhyVariables ( + VOID + ); + +VOID +EFIAPI +SetupUsbDpPhyVariables ( + VOID + ); +#endif // VFR_FILE_INCLUDE + +#endif // __RK3588DXE_USBDP_PHY_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhy.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhy.h new file mode 100644 index 0000000..733bccc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhy.h @@ -0,0 +1,79 @@ +/** @file + * + * Rockchip USBDP Combo PHY with Samsung IP block driver + * + * U-Boot file: include/linux/usb/phy-rockchip-usbdp.h + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code can be relicensed as BSD-2-Clause-Patent if permission + * is granted by the original authors. + * + **/ + +#ifndef __PHY_ROCKCHIP_USBDP_H_ +#define __PHY_ROCKCHIP_USBDP_H_ + +#include "uboot-env.h" + +/* RK3588 USBDP PHY Register Definitions */ + +#define UDPHY_PCS 0x4000 +#define UDPHY_PMA 0x8000 + +/* VO0 GRF Registers */ +#define RK3588_GRF_VO0_CON0 0x0000 +#define RK3588_GRF_VO0_CON2 0x0008 +#define DP_SINK_HPD_CFG BIT(11) +#define DP_SINK_HPD_SEL BIT(10) +#define DP_AUX_DIN_SEL BIT(9) +#define DP_AUX_DOUT_SEL BIT(8) +#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) +#define DP_LANE_SEL_ALL GENMASK(7, 0) +#define PHY_AUX_DP_DATA_POL_NORMAL 0 +#define PHY_AUX_DP_DATA_POL_INVERT 1 + +/* PMA CMN Registers */ +#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ +#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) +#define CMN_DP_LANE_EN_N(n) BIT(n) +#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) +#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) +#define PHY_LANE_MUX_USB 0 +#define PHY_LANE_MUX_DP 1 + +#define CMN_DP_LINK_OFFSET 0x28c /*cmn_reg00A3 */ +#define CMN_DP_TX_LINK_BW GENMASK(6, 5) +#define CMN_DP_TX_LANE_SWAP_EN BIT(2) + +#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ +#define CMN_ROPLL_SSC_EN BIT(1) +#define CMN_LCPLL_SSC_EN BIT(0) + +#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ +#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) +#define CMN_ANA_LCPLL_AFC_DONE BIT(6) + +#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ +#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) +#define CMN_ANA_ROPLL_AFC_DONE BIT(0) + +#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ +#define CMN_DP_INIT_RSTN BIT(3) +#define CMN_DP_CMN_RSTN BIT(2) +#define CMN_CDR_WTCHDG_EN BIT(1) +#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) + +#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ +#define LN_ANA_TX_SER_TXCLK_INV BIT(1) + +#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ +#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) + +#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ +#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.c new file mode 100644 index 0000000..81d0ed9 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.c @@ -0,0 +1,1253 @@ +/** @file + * + * Rockchip USBDP Combo PHY with Samsung IP block driver + * + * This was ported from U-Boot upstream/downstream. It currently lacks: + * - lane orientation flip binding, exposed via a protocol to the TCPM driver. + * + * After all features are merged in and tested, the code should ideally + * be refactored to meet EDK II conventions. + * + * U-Boot file: drivers/phy/rockchip/phy-rockchip-usbdp.c + * + * Copyright (C) 2021 Rockchip Electronics Co., Ltd + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This code can be relicensed as BSD-2-Clause-Patent if permission + * is granted by the original authors. + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "uboot-env.h" + +#include "UsbDpPhy.h" + +#define BIT_WRITEABLE_SHIFT 16 + +enum { + DP_BW_RBR, + DP_BW_HBR, + DP_BW_HBR2, + DP_BW_HBR3, +}; + +enum { + UDPHY_MODE_NONE = 0, + UDPHY_MODE_USB = BIT(0), + UDPHY_MODE_DP = BIT(1), + UDPHY_MODE_DP_USB = BIT(1) | BIT(0), +}; + +struct udphy_grf_reg { + unsigned int offset; + unsigned int bitend; + unsigned int bitstart; + unsigned int disable; + unsigned int enable; +}; + +/** + * struct reg_sequence - An individual write from a sequence of writes. + * + * @reg: Register address. + * @def: Register value. + * @delay_us: Delay to be applied after the register write in microseconds + * + * Register/value pairs for sequences of writes with an optional delay in + * microseconds to be applied after each write. + */ +struct reg_sequence { + unsigned int reg; + unsigned int def; + unsigned int delay_us; +}; + +struct udphy_grf_cfg { + /* u2phy-grf */ + struct udphy_grf_reg bvalid_phy_con; + struct udphy_grf_reg bvalid_grf_con; + + /* usb-grf */ + struct udphy_grf_reg usb3otg0_cfg; + struct udphy_grf_reg usb3otg1_cfg; + + /* usbdpphy-grf */ + struct udphy_grf_reg low_pwrn; + struct udphy_grf_reg rx_lfps; +}; + +struct dp_tx_drv_ctrl { + u32 trsv_reg0204; + u32 trsv_reg0205; + u32 trsv_reg0206; + u32 trsv_reg0207; +}; + +struct rockchip_udphy; + +struct rockchip_udphy_cfg { + struct udphy_grf_cfg grfcfg; + const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; + int (*combophy_init)(struct rockchip_udphy *udphy); + int (*dp_phy_set_rate)(struct rockchip_udphy *udphy, + DP_PHY_CONFIGURATION *dp); + int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy, + DP_PHY_CONFIGURATION *dp); + int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes); + int (*dplane_select)(struct rockchip_udphy *udphy); +}; + +struct cru_reset_reg { + unsigned int offset; + unsigned int bit; +}; + +struct rockchip_udphy { + UINT32 Signature; + EFI_HANDLE Handle; + DP_PHY_PROTOCOL DpPhyProtocol; + + UINTN pma_regmap; + UINTN u2phygrf; + UINTN udphygrf; + UINTN usbgrf; + UINTN vogrf; + + /* clocks and rests */ + struct cru_reset_reg rst_init; + struct cru_reset_reg rst_cmn; + struct cru_reset_reg rst_lane; + struct cru_reset_reg rst_pcs_apb; + struct cru_reset_reg rst_pma_apb; + + /* PHY status management */ + bool flip; + bool mode_change; + u8 mode; + u8 status; + + /* utilized for USB */ + bool hs; /* flag for high-speed */ + + /* utilized for DP */ + //struct gpio_desc *sbu1_dc_gpio; + //struct gpio_desc *sbu2_dc_gpio; + u32 lane_mux_sel[4]; + u32 dp_lane_sel[4]; + u32 dp_aux_dout_sel; + u32 dp_aux_din_sel; + u32 max_link_rate; + u8 bw; /* dp bandwidth */ + int id; + + /* PHY const config */ + const struct rockchip_udphy_cfg *cfgs; +}; + +#define UDPHY_SIGNATURE SIGNATURE_32 ('U', 'D', 'P', 'Y') + +#define ROCKCHIP_UDPHY_FROM_DP_PHY_PROTOCOL(a) CR (a, struct rockchip_udphy, DpPhyProtocol, UDPHY_SIGNATURE) + +static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x20, 0x10, 0x42, 0xe5 }, + { 0x26, 0x14, 0x42, 0xe5 }, + { 0x29, 0x18, 0x42, 0xe5 }, + { 0x2b, 0x1c, 0x43, 0xe7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x23, 0x10, 0x42, 0xe7 }, + { 0x2a, 0x17, 0x43, 0xe7 }, + { 0x2b, 0x1a, 0x43, 0xe7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x27, 0x10, 0x42, 0xe7 }, + { 0x2b, 0x17, 0x43, 0xe7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x29, 0x10, 0x43, 0xe7 }, + }, +}; + +static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x21, 0x10, 0x42, 0xe5 }, + { 0x26, 0x14, 0x42, 0xe5 }, + { 0x26, 0x16, 0x43, 0xe5 }, + { 0x2a, 0x19, 0x43, 0xe7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x24, 0x10, 0x42, 0xe7 }, + { 0x2a, 0x17, 0x43, 0xe7 }, + { 0x2b, 0x1a, 0x43, 0xe7 }, + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x28, 0x10, 0x42, 0xe7 }, + { 0x2b, 0x17, 0x43, 0xe7 }, + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x28, 0x10, 0x43, 0xe7 }, + }, +}; + +static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { + /* voltage swing 0, pre-emphasis 0->3 */ + { + { 0x21, 0x10, 0x42, 0xe5 }, + { 0x26, 0x14, 0x42, 0xe5 }, + { 0x26, 0x16, 0x43, 0xe5 }, + { 0x29, 0x18, 0x43, 0xe7 }, + }, + + /* voltage swing 1, pre-emphasis 0->2 */ + { + { 0x24, 0x10, 0x42, 0xe7 }, + { 0x2a, 0x18, 0x43, 0xe7 }, + { 0x2b, 0x1b, 0x43, 0xe7 } + }, + + /* voltage swing 2, pre-emphasis 0->1 */ + { + { 0x27, 0x10, 0x42, 0xe7 }, + { 0x2b, 0x18, 0x43, 0xe7 } + }, + + /* voltage swing 3, pre-emphasis 0 */ + { + { 0x28, 0x10, 0x43, 0xe7 }, + }, +}; + +static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = { + {0x0090, 0x68}, {0x0094, 0x68}, + {0x0128, 0x24}, {0x012c, 0x44}, + {0x0130, 0x3f}, {0x0134, 0x44}, + {0x015c, 0xa9}, {0x0160, 0x71}, + {0x0164, 0x71}, {0x0168, 0xa9}, + {0x0174, 0xa9}, {0x0178, 0x71}, + {0x017c, 0x71}, {0x0180, 0xa9}, + {0x018c, 0x41}, {0x0190, 0x00}, + {0x0194, 0x05}, {0x01ac, 0x2a}, + {0x01b0, 0x17}, {0x01b4, 0x17}, + {0x01b8, 0x2a}, {0x01c8, 0x04}, + {0x01cc, 0x08}, {0x01d0, 0x08}, + {0x01d4, 0x04}, {0x01d8, 0x20}, + {0x01dc, 0x01}, {0x01e0, 0x09}, + {0x01e4, 0x03}, {0x01f0, 0x29}, + {0x01f4, 0x02}, {0x01f8, 0x02}, + {0x01fc, 0x29}, {0x0208, 0x2a}, + {0x020c, 0x17}, {0x0210, 0x17}, + {0x0214, 0x2a}, {0x0224, 0x20}, + {0x03f0, 0x0d}, {0x03f4, 0x09}, + {0x03f8, 0x09}, {0x03fc, 0x0d}, + {0x0404, 0x0e}, {0x0408, 0x14}, + {0x040c, 0x14}, {0x0410, 0x3b}, + {0x0ce0, 0x68}, {0x0ce8, 0xd0}, + {0x0cf0, 0x87}, {0x0cf8, 0x70}, + {0x0d00, 0x70}, {0x0d08, 0xa9}, + {0x1ce0, 0x68}, {0x1ce8, 0xd0}, + {0x1cf0, 0x87}, {0x1cf8, 0x70}, + {0x1d00, 0x70}, {0x1d08, 0xa9}, + {0x0a3c, 0xd0}, {0x0a44, 0xd0}, + {0x0a48, 0x01}, {0x0a4c, 0x0d}, + {0x0a54, 0xe0}, {0x0a5c, 0xe0}, + {0x0a64, 0xa8}, {0x1a3c, 0xd0}, + {0x1a44, 0xd0}, {0x1a48, 0x01}, + {0x1a4c, 0x0d}, {0x1a54, 0xe0}, + {0x1a5c, 0xe0}, {0x1a64, 0xa8} +}; + +static const struct reg_sequence rk3588_udphy_init_sequence[] = { + {0x0104, 0x44}, {0x0234, 0xE8}, + {0x0248, 0x44}, {0x028C, 0x18}, + {0x081C, 0xE5}, {0x0878, 0x00}, + {0x0994, 0x1C}, {0x0AF0, 0x00}, + {0x181C, 0xE5}, {0x1878, 0x00}, + {0x1994, 0x1C}, {0x1AF0, 0x00}, + {0x0428, 0x60}, {0x0D58, 0x33}, + {0x1D58, 0x33}, {0x0990, 0x74}, + {0x0D64, 0x17}, {0x08C8, 0x13}, + {0x1990, 0x74}, {0x1D64, 0x17}, + {0x18C8, 0x13}, {0x0D90, 0x40}, + {0x0DA8, 0x40}, {0x0DC0, 0x40}, + {0x0DD8, 0x40}, {0x1D90, 0x40}, + {0x1DA8, 0x40}, {0x1DC0, 0x40}, + {0x1DD8, 0x40}, {0x03C0, 0x30}, + {0x03C4, 0x06}, {0x0E10, 0x00}, + {0x1E10, 0x00}, {0x043C, 0x0F}, + {0x0D2C, 0xFF}, {0x1D2C, 0xFF}, + {0x0D34, 0x0F}, {0x1D34, 0x0F}, + {0x08FC, 0x2A}, {0x0914, 0x28}, + {0x0A30, 0x03}, {0x0E38, 0x05}, + {0x0ECC, 0x27}, {0x0ED0, 0x22}, + {0x0ED4, 0x26}, {0x18FC, 0x2A}, + {0x1914, 0x28}, {0x1A30, 0x03}, + {0x1E38, 0x05}, {0x1ECC, 0x27}, + {0x1ED0, 0x22}, {0x1ED4, 0x26}, + {0x0048, 0x0F}, {0x0060, 0x3C}, + {0x0064, 0xF7}, {0x006C, 0x20}, + {0x0070, 0x7D}, {0x0074, 0x68}, + {0x0AF4, 0x1A}, {0x1AF4, 0x1A}, + {0x0440, 0x3F}, {0x10D4, 0x08}, + {0x20D4, 0x08}, {0x00D4, 0x30}, + {0x0024, 0x6e}, +}; + +static inline int grfreg_write(UINTN base, + const struct udphy_grf_reg *reg, bool en) +{ + u32 val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + return regmap_write(base, reg->offset, val); +} + +static int __regmap_multi_reg_write(UINTN map, + const struct reg_sequence *regs, + int num_regs) +{ + int i, ret = 0; + + for (i = 0; i < num_regs; i++) { + ret = regmap_write(map, regs[i].reg, regs[i].def); + + if (regs[i].delay_us) + udelay(regs[i].delay_us); + } + + return ret; +} + +static int udphy_clk_init(struct rockchip_udphy *udphy) +{ + return 0; +} + +static int udphy_reset(struct cru_reset_reg *reset, BOOLEAN assert) +{ + struct udphy_grf_reg grf; + grf.offset = reset->offset; + grf.bitend = reset->bit; + grf.bitstart = reset->bit; + grf.disable = 0; + grf.enable = 1; + + return grfreg_write(CRU_BASE, &grf, assert); +} + +static int udphy_reset_assert(struct cru_reset_reg *reset) +{ + return udphy_reset(reset, TRUE); +} + +static int udphy_reset_deassert(struct cru_reset_reg *reset) +{ + return udphy_reset(reset, FALSE); +} + +static int udphy_reset_init(struct rockchip_udphy *udphy) +{ + udphy_reset_assert (&udphy->rst_init); + udphy_reset_assert (&udphy->rst_cmn); + udphy_reset_assert (&udphy->rst_lane); + udphy_reset_assert (&udphy->rst_pcs_apb); + udphy_reset_assert (&udphy->rst_pma_apb); + + return 0; +} + +static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + const struct udphy_grf_reg *preg; + + preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; + grfreg_write(udphy->usbgrf, preg, disable); +} + +__maybe_unused +static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + + grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); + grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); +} + +/* + * In usb/dp combo phy driver, here are 2 ways to mapping lanes. + * + * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) + * --------------------------------------------------------------------------- + * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 + * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * C/E(Normal) dpln3 dpln2 dpln0 dpln1 + * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 + * D/F(Normal) usbrx usbtx dpln0 dpln1 + * D/F(Flip ) dpln0 dpln1 usbrx usbtx + * A(Normal ) dpln3 dpln1 dpln2 dpln0 + * A(Flip ) dpln2 dpln0 dpln3 dpln1 + * B(Normal ) usbrx usbtx dpln1 dpln0 + * B(Flip ) dpln1 dpln0 usbrx usbtx + * --------------------------------------------------------------------------- + * + * 2 Mapping the lanes in dtsi + * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = ; + * sample as follow: + * --------------------------------------------------------------------------- + * B11-B10 A2-A3 A11-A10 B2-B3 + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 + * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 + * --------------------------------------------------------------------------- + * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = ; + * sample as follow: + * --------------------------------------------------------------------------- + * B11-B10 A2-A3 A11-A10 B2-B3 + * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) + * <0 1> dpln0 dpln1 usbrx usbtx + * <2 3> usbrx usbtx dpln0 dpln1 + * --------------------------------------------------------------------------- + */ +static int udphy_dplane_select(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + + if (cfg->dplane_select) + return cfg->dplane_select(udphy); + + return 0; +} + +static int udphy_dplane_get(struct rockchip_udphy *udphy) +{ + int dp_lanes; + + switch (udphy->mode) { + case UDPHY_MODE_DP: + dp_lanes = 4; + break; + case UDPHY_MODE_DP_USB: + dp_lanes = 2; + break; + case UDPHY_MODE_USB: + /* fallthrough; */ + default: + dp_lanes = 0; + break; + } + + return dp_lanes; +} + +static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret = 0; + + if (cfg->dplane_enable) + ret = cfg->dplane_enable(udphy, dp_lanes); + + return ret; +} + +__maybe_unused +static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy) +{ + if (udphy->flip) { + udphy->dp_lane_sel[0] = 0; + udphy->dp_lane_sel[1] = 1; + udphy->dp_lane_sel[2] = 3; + udphy->dp_lane_sel[3] = 2; + udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; + udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; + udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; + } else { + udphy->dp_lane_sel[0] = 2; + udphy->dp_lane_sel[1] = 3; + udphy->dp_lane_sel[2] = 1; + udphy->dp_lane_sel[3] = 0; + udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; + udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; + udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; + udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; + udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; + } + + udphy->mode = UDPHY_MODE_DP_USB; + + return 0; +} + +static int udphy_setup(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret = 0; + + if (cfg->combophy_init) { + ret = cfg->combophy_init(udphy); + if (ret) + dev_err(udphy->dev, "failed to init usbdp combophy\n"); + } + + return ret; +} + +static int udphy_disable(struct rockchip_udphy *udphy) +{ + udphy_reset_assert (&udphy->rst_init); + udphy_reset_assert (&udphy->rst_cmn); + udphy_reset_assert (&udphy->rst_lane); + udphy_reset_assert (&udphy->rst_pcs_apb); + udphy_reset_assert (&udphy->rst_pma_apb); + + return 0; +} + +static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, UINT8 *prop, UINTN num_lanes) +{ + int ret, i; + + if (!prop) { + dev_dbg(udphy->dev, + "failed to find dp lane mux, following dp alt mode\n"); + udphy->mode = UDPHY_MODE_USB; + return 0; + } + + if (num_lanes != 2 && num_lanes != 4) { + dev_err(udphy->dev, "invalid number of lane mux\n"); + return -EINVAL; + } + + for (i = 0; i < num_lanes; i++) { + udphy->dp_lane_sel[i] = prop[i]; + } + + for (i = 0; i < num_lanes; i++) { + int j; + + if (udphy->dp_lane_sel[i] > 3) { + dev_err(udphy->dev, + "lane mux between 0 and 3, exceeding the range\n"); + return -EINVAL; + } + + udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; + + for (j = i + 1; j < num_lanes; j++) { + if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) { + dev_err(udphy->dev, + "set repeat lane mux value\n"); + return -EINVAL; + } + } + } + + udphy->mode = UDPHY_MODE_DP; + if (num_lanes == 2) { + udphy->mode |= UDPHY_MODE_USB; + udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false; + } + + return 0; +} + +static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode) +{ + int ret; + + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); + return 0; + } + + if (udphy->status == UDPHY_MODE_NONE) { + udphy->mode_change = false; + ret = udphy_setup(udphy); + if (ret) + return ret; + + if (udphy->mode & UDPHY_MODE_USB) + udphy_u3_port_disable(udphy, false); + } else if (udphy->mode_change) { + udphy->mode_change = false; + udphy->status = UDPHY_MODE_NONE; + if (udphy->mode == UDPHY_MODE_DP) + udphy_u3_port_disable(udphy, true); + + ret = udphy_disable(udphy); + if (ret) + return ret; + ret = udphy_setup(udphy); + if (ret) + return ret; + } + + udphy->status |= mode; + + return 0; +} + +static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode) +{ + int ret; + + if (!(udphy->mode & mode)) { + dev_info(udphy->dev, "mode 0x%02x is not supported\n", mode); + return 0; + } + + if (!udphy->status) + return 0; + + udphy->status &= ~mode; + + if (udphy->status == UDPHY_MODE_NONE) { + ret = udphy_disable(udphy); + if (ret) + return ret; + } + + return 0; +} + +static int rockchip_dpphy_power_on(struct rockchip_udphy *udphy) +{ + int ret, dp_lanes; + + dp_lanes = udphy_dplane_get(udphy); + udphy->DpPhyProtocol.Capabilities.BusWidth = dp_lanes; + udphy->DpPhyProtocol.Capabilities.MaximumLinkRate = udphy->max_link_rate; + + ret = udphy_power_on(udphy, UDPHY_MODE_DP); + if (ret) + return ret; + + ret = udphy_dplane_enable(udphy, dp_lanes); + if (ret) + return ret; + + return udphy_dplane_select(udphy); +} + +static int rockchip_dpphy_power_off(struct rockchip_udphy *udphy) +{ + int ret; + + ret = udphy_dplane_enable(udphy, 0); + if (ret) + return ret; + + return udphy_power_off(udphy, UDPHY_MODE_DP); +} + +static int rockchip_dpphy_verify_config(struct rockchip_udphy *udphy, + DP_PHY_CONFIGURATION *dp) +{ + int i; + + /* If changing link rate was required, verify it's supported. */ + if (dp->SetLinkRateAndSpreadSpectrum) { + switch (dp->LinkRate) { + case 1620: + case 2700: + case 5400: + case 8100: + /* valid bit rate */ + break; + default: + return -EINVAL; + } + } + + /* Verify lane count. */ + switch (dp->LaneCount) { + case 1: + case 2: + case 4: + /* valid lane count. */ + break; + default: + return -EINVAL; + } + + /* + * If changing voltages is required, check swing and pre-emphasis + * levels, per-lane. + */ + if (dp->SetVoltageSwingAndPreEmphasisLevels) { + /* Lane count verified previously. */ + for (i = 0; i < dp->LaneCount; i++) { + if (dp->LaneVoltageSwingLevels[i] > 3 || dp->LanePreEmphasisLevels[i] > 3) + return -EINVAL; + + /* + * Sum of voltage swing and pre-emphasis levels cannot + * exceed 3. + */ + if (dp->LaneVoltageSwingLevels[i] + dp->LanePreEmphasisLevels[i] > 3) + return -EINVAL; + } + } + + return 0; +} + +static int rockchip_dpphy_configure(struct rockchip_udphy *udphy, + DP_PHY_CONFIGURATION *dp) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret; + + ret = rockchip_dpphy_verify_config(udphy, dp); + if (ret) + return ret; + + if (dp->SetLinkRateAndSpreadSpectrum && cfg->dp_phy_set_rate) { + ret = cfg->dp_phy_set_rate(udphy, dp); + if (ret) { + dev_err(udphy->dev, "rockchip_hdptx_phy_set_rate failed\n"); + return ret; + } + } + + if (dp->SetVoltageSwingAndPreEmphasisLevels && cfg->dp_phy_set_voltages) { + ret = cfg->dp_phy_set_voltages(udphy, dp); + if (ret) { + dev_err(udphy->dev, "rockchip_dp_phy_set_voltages failed\n"); + return ret; + } + } + + return 0; +} + +static int rockchip_u3phy_init(struct rockchip_udphy *udphy) +{ + /* DP only or high-speed, disable U3 port */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { + udphy_u3_port_disable(udphy, true); + return 0; + } + + return udphy_power_on(udphy, UDPHY_MODE_USB); +} + +static int rockchip_u3phy_exit(struct rockchip_udphy *udphy) +{ + /* DP only or high-speed */ + if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) + return 0; + + return udphy_power_off(udphy, UDPHY_MODE_USB); +} + +static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy) +{ + /* configure phy reference clock */ + return __regmap_multi_reg_write(udphy->pma_regmap, + rk3588_udphy_24m_refclk_cfg, + ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg)); +} + +static int rk3588_udphy_status_check(struct rockchip_udphy *udphy) +{ + unsigned int val; + int ret; + + if (!(udphy->mode & UDPHY_MODE_USB)) + return 0; + + /* LCPLL check */ + ret = regmap_read_poll_timeout(udphy->pma_regmap, + CMN_ANA_LCPLL_DONE_OFFSET, + val, (val & CMN_ANA_LCPLL_AFC_DONE) && + (val & CMN_ANA_LCPLL_LOCK_DONE), + 200, 100); + if (ret) { + dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); + return ret; + } + + if (!udphy->flip) { + ret = regmap_read_poll_timeout(udphy->pma_regmap, + TRSV_LN0_MON_RX_CDR_DONE_OFFSET, + val, + val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, + 200, 100); + if (ret) + dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); + } else { + ret = regmap_read_poll_timeout(udphy->pma_regmap, + TRSV_LN2_MON_RX_CDR_DONE_OFFSET, + val, + val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, + 200, 100); + if (ret) + dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); + } + + return 0; +} + +static int rk3588_udphy_init(struct rockchip_udphy *udphy) +{ + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + int ret; + + /* enable rx lfps for usb */ + if (udphy->mode & UDPHY_MODE_USB) + grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); + + /* Step 1: power on pma and deassert apb rstn */ + grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); + + udphy_reset_deassert(&udphy->rst_pma_apb); + udphy_reset_deassert(&udphy->rst_pcs_apb); + + /* Step 2: set init sequence and phy refclk */ + ret = __regmap_multi_reg_write(udphy->pma_regmap, + rk3588_udphy_init_sequence, + ARRAY_SIZE(rk3588_udphy_init_sequence)); + if (ret) { + dev_err(udphy->dev, "init sequence set error %d\n", ret); + goto assert_apb; + } + + ret = rk3588_udphy_refclk_set(udphy); + if (ret) { + dev_err(udphy->dev, "refclk set error %d\n", ret); + goto assert_apb; + } + + /* Step 3: configure lane mux */ + regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, + CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, + FIELD_PREP(CMN_DP_LANE_MUX_N(3), + udphy->lane_mux_sel[3]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(2), + udphy->lane_mux_sel[2]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(1), + udphy->lane_mux_sel[1]) | + FIELD_PREP(CMN_DP_LANE_MUX_N(0), + udphy->lane_mux_sel[0]) | + FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); + + /* Step 4: deassert init rstn and wait for 200ns from datasheet */ + if (udphy->mode & UDPHY_MODE_USB) + udphy_reset_deassert(&udphy->rst_init); + + if (udphy->mode & UDPHY_MODE_DP) { + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, + CMN_DP_INIT_RSTN, + FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); + } + + udelay(1); + + /* Step 5: deassert cmn/lane rstn */ + if (udphy->mode & UDPHY_MODE_USB) { + udphy_reset_deassert(&udphy->rst_cmn); + udphy_reset_deassert(&udphy->rst_lane); + } + + /* Step 6: wait for lock done of pll */ + ret = rk3588_udphy_status_check(udphy); + if (ret) + goto assert_phy; + + return 0; + +assert_phy: + udphy_reset_assert(&udphy->rst_init); + udphy_reset_assert(&udphy->rst_cmn); + udphy_reset_assert(&udphy->rst_lane); + +assert_apb: + udphy_reset_assert(&udphy->rst_pma_apb); + udphy_reset_assert(&udphy->rst_pcs_apb); + + return ret; +} + +static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes) +{ + int i; + u32 val = 0; + + for (i = 0; i < dp_lanes; i++) + val |= BIT(udphy->dp_lane_sel[i]); + + regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, + FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); + + if (!dp_lanes) + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, + CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); + + return 0; +} + +static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy) +{ + u32 value = 0; + + switch (udphy->mode) { + case UDPHY_MODE_DP: + value |= 2 << udphy->dp_lane_sel[2] * 2; + value |= 3 << udphy->dp_lane_sel[3] * 2; + case UDPHY_MODE_DP_USB: + value |= 0 << udphy->dp_lane_sel[0] * 2; + value |= 1 << udphy->dp_lane_sel[1] * 2; + break; + case UDPHY_MODE_USB: + break; + default: + break; + } + + regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0, + ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | + FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | + FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); + + return 0; +} + +static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy, + DP_PHY_CONFIGURATION *dp) +{ + u32 val; + int ret; + + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, + CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); + + switch (dp->LinkRate) { + case 1620: + udphy->bw = DP_BW_RBR; + break; + case 2700: + udphy->bw = DP_BW_HBR; + break; + case 5400: + udphy->bw = DP_BW_HBR2; + break; + case 8100: + udphy->bw = DP_BW_HBR3; + break; + default: + return -EINVAL; + } + + regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, + FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); + regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, + FIELD_PREP(CMN_ROPLL_SSC_EN, dp->EnableSpreadSpectrum)); + regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, + FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); + + ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, + FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && + FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), + 0, 1000); + if (ret) { + printf("ROPLL is not lock\n"); + return ret; + } + + return 0; +} + +static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw, + u32 voltage, u32 pre, u32 lane) +{ + u32 offset = 0x800 * lane; + u32 val; + const struct rockchip_udphy_cfg *cfg = udphy->cfgs; + const struct dp_tx_drv_ctrl (*dp_ctrl)[4]; + + dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; + val = dp_ctrl[voltage][pre].trsv_reg0204; + regmap_write(udphy->pma_regmap, 0x0810 + offset, val); + + val = dp_ctrl[voltage][pre].trsv_reg0205; + regmap_write(udphy->pma_regmap, 0x0814 + offset, val); + + val = dp_ctrl[voltage][pre].trsv_reg0206; + regmap_write(udphy->pma_regmap, 0x0818 + offset, val); + + val = dp_ctrl[voltage][pre].trsv_reg0207; + regmap_write(udphy->pma_regmap, 0x081c + offset, val); +} + +static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy, + DP_PHY_CONFIGURATION *dp) +{ + u32 i, lane; + + for (i = 0; i < dp->LaneCount; i++) { + lane = udphy->dp_lane_sel[i]; + switch (dp->LinkRate) { + case 1620: + case 2700: + regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), + LN_ANA_TX_SER_TXCLK_INV, + FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, + udphy->lane_mux_sel[lane])); + break; + case 5400: + case 8100: + regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane), + LN_ANA_TX_SER_TXCLK_INV, + FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); + break; + } + + rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->LaneVoltageSwingLevels[i], dp->LanePreEmphasisLevels[i], lane); + } + + return 0; +} + +EFI_STATUS +EFIAPI +DpPhyPowerOn ( + IN DP_PHY_PROTOCOL *This + ) +{ + struct rockchip_udphy *udphy; + int ret; + + udphy = ROCKCHIP_UDPHY_FROM_DP_PHY_PROTOCOL (This); + + ret = rockchip_dpphy_power_on (udphy); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +DpPhyPowerOff ( + IN DP_PHY_PROTOCOL *This + ) +{ + struct rockchip_udphy *udphy; + int ret; + + udphy = ROCKCHIP_UDPHY_FROM_DP_PHY_PROTOCOL (This); + + ret = rockchip_dpphy_power_off (udphy); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +DpPhyConfigure ( + IN DP_PHY_PROTOCOL *This, + IN DP_PHY_CONFIGURATION *Configuration + ) +{ + struct rockchip_udphy *udphy; + int ret; + + udphy = ROCKCHIP_UDPHY_FROM_DP_PHY_PROTOCOL (This); + + ret = rockchip_dpphy_configure (udphy, Configuration); + if (ret) + return EFI_DEVICE_ERROR; + + return EFI_SUCCESS; +} + +EFI_STATUS +UsbDpPhySetup ( + IN struct rockchip_udphy *UdPhy, + IN UINT8 *DpLaneMux, + IN UINTN DpNumLanes, + IN UINT32 Usb3State + ) +{ + EFI_STATUS Status; + int ret = 0; + + // treat default byte array definition as NULL + if (DpNumLanes == 1 && DpLaneMux[0] == 0) { + DpLaneMux = NULL; + } + + UdPhy->hs = Usb3State == USBDP_PHY_USB3_STATE_DISABLED; + + ret = udphy_parse_lane_mux_data(UdPhy, DpLaneMux, DpNumLanes); + if (ret) { + DEBUG ((DEBUG_ERROR, "%a: udphy_parse_lane_mux_data errno %d\n", __func__, ret)); + return EFI_INVALID_PARAMETER; + } + ret = udphy_clk_init(UdPhy); + if (ret) { + DEBUG ((DEBUG_ERROR, "%a: udphy_clk_init errno %d\n", __func__, ret)); + return EFI_DEVICE_ERROR; + } + ret = udphy_reset_init(UdPhy); + if (ret) { + DEBUG ((DEBUG_ERROR, "%a: udphy_reset_init errno %d\n", __func__, ret)); + return EFI_DEVICE_ERROR; + } + ret = rockchip_u3phy_init (UdPhy); + if (ret) { + DEBUG ((DEBUG_ERROR, "%a: rockchip_u3phy_init errno %d\n", __func__, ret)); + return EFI_DEVICE_ERROR; + } + + if (UdPhy->mode & UDPHY_MODE_DP) { + UdPhy->Signature = UDPHY_SIGNATURE; + UdPhy->DpPhyProtocol.PowerOn = DpPhyPowerOn; + UdPhy->DpPhyProtocol.PowerOff = DpPhyPowerOff; + UdPhy->DpPhyProtocol.Configure = DpPhyConfigure; + UdPhy->DpPhyProtocol.Id = UdPhy->id; + + Status = gBS->InstallMultipleProtocolInterfaces (&UdPhy->Handle, + &gDpPhyProtocolGuid, &UdPhy->DpPhyProtocol, + NULL); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to install DP PHY protocol. Status=%r\n", + __func__, Status)); + return Status; + } + } + + return EFI_SUCCESS; +} + +static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = { + .grfcfg = { + /* u2phy-grf */ + .bvalid_phy_con = { 0x0008, 1, 0, 0x2, 0x3 }, + .bvalid_grf_con = { 0x0010, 3, 2, 0x2, 0x3 }, + + /* usb-grf */ + .usb3otg0_cfg = { 0x001c, 15, 0, 0x1100, 0x0188 }, + .usb3otg1_cfg = { 0x0034, 15, 0, 0x1100, 0x0188 }, + + /* usbdpphy-grf */ + .low_pwrn = { 0x0004, 13, 13, 0, 1 }, + .rx_lfps = { 0x0004, 14, 14, 0, 1 }, + }, + .dp_tx_ctrl_cfg = { + rk3588_dp_tx_drv_ctrl_rbr_hbr, + rk3588_dp_tx_drv_ctrl_rbr_hbr, + rk3588_dp_tx_drv_ctrl_hbr2, + rk3588_dp_tx_drv_ctrl_hbr3, + }, + .combophy_init = rk3588_udphy_init, + .dp_phy_set_rate = rk3588_dp_phy_set_rate, + .dp_phy_set_voltages = rk3588_dp_phy_set_voltages, + .dplane_enable = rk3588_udphy_dplane_enable, + .dplane_select = rk3588_udphy_dplane_select, +}; + +static struct rockchip_udphy usbdp_phy[] = { + { + .pma_regmap = 0xfed80000 + UDPHY_PMA, + .u2phygrf = 0xfd5d0000, + .udphygrf = 0xfd5c8000, + .usbgrf = 0xfd5ac000, + .vogrf = 0xfd5a6000, + + .rst_init = { 0xA08, 8 }, + .rst_cmn = { 0xA08, 9 }, + .rst_lane = { 0xA08, 10 }, + .rst_pcs_apb = { 0xA08, 11 }, + .rst_pma_apb = { 0xB20, 2 }, + + .max_link_rate = 8100, + + .id = 0, + + .cfgs = &rk3588_udphy_cfgs, + }, + { + .pma_regmap = 0xfed90000 + UDPHY_PMA, + .u2phygrf = 0xfd5d4000, + .udphygrf = 0xfd5cc000, + .usbgrf = 0xfd5ac000, + .vogrf = 0xfd5a6000, + + .rst_init = { 0xA08, 15 }, + .rst_cmn = { 0xA0C, 0 }, + .rst_lane = { 0xA0C, 1 }, + .rst_pcs_apb = { 0xA0C, 2 }, + .rst_pma_apb = { 0xB20, 4 }, + + .max_link_rate = 8100, + + .id = 1, + + .cfgs = &rk3588_udphy_cfgs, + }, +}; + +EFI_STATUS +EFIAPI +UsbDpPhyDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + if (PcdGetBool (PcdUsbDpPhy0Supported)) { + UsbDpPhySetup (&usbdp_phy[0], + PcdGetPtr (PcdDp0LaneMux), + PcdGetSize (PcdDp0LaneMux), + PcdGet32 (PcdUsbDpPhy0Usb3State) + ); + } + + if (PcdGetBool (PcdUsbDpPhy1Supported)) { + UsbDpPhySetup (&usbdp_phy[1], + PcdGetPtr (PcdDp1LaneMux), + PcdGetSize (PcdDp1LaneMux), + PcdGet32 (PcdUsbDpPhy1Usb3State) + ); + } + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.inf new file mode 100644 index 0000000..82fc1bc --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Rockchip USB/DP Combo PHY Driver +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = UsbDpPhyDxe + FILE_GUID = 6fbd6b56-e302-4560-85f4-0e78fb731922 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = UsbDpPhyDxeInitialize + +[Sources.common] + UsbDpPhyDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + IoLib + TimerLib + RockchipPlatformLib + +[Protocols] + gDpPhyProtocolGuid ## PRODUCES + +[Pcd] + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported + gRK3588TokenSpaceGuid.PcdDp0LaneMux + gRK3588TokenSpaceGuid.PcdDp1LaneMux + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Usb3State + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Usb3State + +[Depex] + gRockchipPlatformConfigAppliedProtocolGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/errno.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/errno.h new file mode 100644 index 0000000..3767df3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/errno.h @@ -0,0 +1,168 @@ +#ifndef _LINUX_ERRNO_H +#define _LINUX_ERRNO_H + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* I/O error */ +#define ENXIO 6 /* No such device or address */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file number */ +#define ECHILD 10 /* No child processes */ +#define EAGAIN 11 /* Try again */ +#define ENOMEM 12 /* Out of memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#define ENOTBLK 15 /* Block device required */ +#define EBUSY 16 /* Device or resource busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* No such device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* File table overflow */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Not a typewriter */ +#define ETXTBSY 26 /* Text file busy */ +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only file system */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ +#define EDOM 33 /* Math argument out of domain of func */ +#define ERANGE 34 /* Math result not representable */ + +#define EDEADLK 35 /* Resource deadlock would occur */ +#define ENAMETOOLONG 36 /* File name too long */ +#define ENOLCK 37 /* No record locks available */ + +#define ENOSYS 38 /* Invalid system call number */ + +#define ENOTEMPTY 39 /* Directory not empty */ +#define ELOOP 40 /* Too many symbolic links encountered */ +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define ENOMSG 42 /* No message of desired type */ +#define EIDRM 43 /* Identifier removed */ +#define ECHRNG 44 /* Channel number out of range */ +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#define EL3HLT 46 /* Level 3 halted */ +#define EL3RST 47 /* Level 3 reset */ +#define ELNRNG 48 /* Link number out of range */ +#define EUNATCH 49 /* Protocol driver not attached */ +#define ENOCSI 50 /* No CSI structure available */ +#define EL2HLT 51 /* Level 2 halted */ +#define EBADE 52 /* Invalid exchange */ +#define EBADR 53 /* Invalid request descriptor */ +#define EXFULL 54 /* Exchange full */ +#define ENOANO 55 /* No anode */ +#define EBADRQC 56 /* Invalid request code */ +#define EBADSLT 57 /* Invalid slot */ + +#define EDEADLOCK EDEADLK + +#define EBFONT 59 /* Bad font file format */ +#define ENOSTR 60 /* Device not a stream */ +#define ENODATA 61 /* No data available */ +#define ETIME 62 /* Timer expired */ +#define ENOSR 63 /* Out of streams resources */ +#define ENONET 64 /* Machine is not on the network */ +#define ENOPKG 65 /* Package not installed */ +#define EREMOTE 66 /* Object is remote */ +#define ENOLINK 67 /* Link has been severed */ +#define EADV 68 /* Advertise error */ +#define ESRMNT 69 /* Srmount error */ +#define ECOMM 70 /* Communication error on send */ +#define EPROTO 71 /* Protocol error */ +#define EMULTIHOP 72 /* Multihop attempted */ +#define EDOTDOT 73 /* RFS specific error */ +#define EBADMSG 74 /* Not a data message */ +#define EOVERFLOW 75 /* Value too large for defined data type */ +#define ENOTUNIQ 76 /* Name not unique on network */ +#define EBADFD 77 /* File descriptor in bad state */ +#define EREMCHG 78 /* Remote address changed */ +#define ELIBACC 79 /* Can not access a needed shared library */ +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#define EILSEQ 84 /* Illegal byte sequence */ +#define ERESTART 85 /* Interrupted system call should be restarted */ +#define ESTRPIPE 86 /* Streams pipe error */ +#define EUSERS 87 /* Too many users */ +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#define EDESTADDRREQ 89 /* Destination address required */ +#define EMSGSIZE 90 /* Message too long */ +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 92 /* Protocol not available */ +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#define EADDRINUSE 98 /* Address already in use */ +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#define ENETDOWN 100 /* Network is down */ +#define ENETUNREACH 101 /* Network is unreachable */ +#define ENETRESET 102 /* Network dropped connection because of reset */ +#define ECONNABORTED 103 /* Software caused connection abort */ +#define ECONNRESET 104 /* Connection reset by peer */ +#define ENOBUFS 105 /* No buffer space available */ +#define EISCONN 106 /* Transport endpoint is already connected */ +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#define ETIMEDOUT 110 /* Connection timed out */ +#define ECONNREFUSED 111 /* Connection refused */ +#define EHOSTDOWN 112 /* Host is down */ +#define EHOSTUNREACH 113 /* No route to host */ +#define EALREADY 114 /* Operation already in progress */ +#define EINPROGRESS 115 /* Operation now in progress */ +#define ESTALE 116 /* Stale file handle */ +#define EUCLEAN 117 /* Structure needs cleaning */ +#define ENOTNAM 118 /* Not a XENIX named type file */ +#define ENAVAIL 119 /* No XENIX semaphores available */ +#define EISNAM 120 /* Is a named type file */ +#define EREMOTEIO 121 /* Remote I/O error */ +#define EDQUOT 122 /* Quota exceeded */ + +#define ENOMEDIUM 123 /* No medium found */ +#define EMEDIUMTYPE 124 /* Wrong medium type */ +#define ECANCELED 125 /* Operation Canceled */ +#define ENOKEY 126 /* Required key not available */ +#define EKEYEXPIRED 127 /* Key has expired */ +#define EKEYREVOKED 128 /* Key has been revoked */ +#define EKEYREJECTED 129 /* Key was rejected by service */ + +/* for robust mutexes */ +#define EOWNERDEAD 130 /* Owner died */ +#define ENOTRECOVERABLE 131 /* State not recoverable */ + +#define ERFKILL 132 /* Operation not possible due to RF-kill */ + +#define EHWPOISON 133 /* Memory page has hardware error */ + +#define ERESTARTSYS 512 +#define ERESTARTNOINTR 513 +#define ERESTARTNOHAND 514 /* restart if no handler.. */ +#define ENOIOCTLCMD 515 /* No ioctl command */ +#define ERESTART_RESTARTBLOCK 516 /* restart by calling sys_restart_syscall */ +#define EPROBE_DEFER 517 /* Driver requests probe retry */ +#define EOPENSTALE 518 /* open found a stale dentry */ + +/* Defined for the NFSv3 protocol */ +#define EBADHANDLE 521 /* Illegal NFS file handle */ +#define ENOTSYNC 522 /* Update synchronization mismatch */ +#define EBADCOOKIE 523 /* Cookie is stale */ +#define ENOTSUPP 524 /* Operation is not supported */ +#define ETOOSMALL 525 /* Buffer or request is too small */ +#define ESERVERFAULT 526 /* An untranslatable error occurred */ +#define EBADTYPE 527 /* Type not supported by server */ +#define EJUKEBOX 528 /* Request initiated, but will not complete before timeout */ +#define EIOCBQUEUED 529 /* iocb queued, will get completion event */ +#define ERECALLCONFLICT 530 /* conflict with recalled state */ + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/uboot-env.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/uboot-env.h new file mode 100644 index 0000000..c8b26e0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/uboot-env.h @@ -0,0 +1,85 @@ +#ifndef _UBOOT_ENV_H +#define _UBOOT_ENV_H + +#include "errno.h" + +#define __maybe_unused + +typedef UINT8 u8; +typedef UINT32 u32; +typedef UINT64 u64; +typedef unsigned int uint; +typedef UINTN ulong; +typedef BOOLEAN bool; + +#define true TRUE +#define false FALSE + +#define udelay(x) MicroSecondDelay (x) + +#define dev_err(dev, args...) DEBUG ((DEBUG_ERROR, args)) +#define dev_info(dev, args...) DEBUG ((DEBUG_INFO, args)) +#define dev_dbg(dev, args...) DEBUG ((DEBUG_INFO, args)) +#define printf(args...) DEBUG ((DEBUG_INFO, args)) + +#define BITS_PER_LONG (sizeof(UINTN) * 8) +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define BIT(x) (1 << (x)) + +#define __bf_shf(x) (__builtin_ffsll(x) - 1) + +#define FIELD_PREP(_mask, _val) \ + ({ \ + ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ + }) + +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +#define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, \ + timeout_ms) \ +({ \ + int __ret; \ + for (;;) { \ + __ret = regmap_read((map), (addr), &(val)); \ + if (__ret) \ + break; \ + if (cond) \ + break; \ + if ((sleep_us)) \ + udelay((sleep_us)); \ + } \ + __ret ?: ((cond) ? 0 : -ETIMEDOUT); \ +}) + +static inline int regmap_write(UINTN map, uint offset, uint val) +{ + MmioWrite32 (map + offset, val); + return 0; +} + +static inline int regmap_read(UINTN map, uint offset, uint *valp) +{ + *valp = MmioRead32 (map + offset); + return 0; +} + +static inline int regmap_update_bits(UINTN map, uint offset, uint mask, uint val) +{ + uint reg; + int ret; + + ret = regmap_read(map, offset, ®); + if (ret) + return ret; + + reg &= ~mask; + + return regmap_write(map, offset, reg | (val & mask)); +} + +#endif // _UBOOT_ENV_H diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/AcpiTables.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/AcpiTables.h new file mode 100644 index 0000000..b525f89 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/AcpiTables.h @@ -0,0 +1,126 @@ +/** @file + * + * RK3588 defines for constructing ACPI tables + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2020, Pete Batard + * Copyright (c) 2019, ARM Ltd. All rights reserved. + * Copyright (c) 2018, Andrei Warkentin + * Copyright (c) Microsoft Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __ACPITABLES_H__ +#define __ACPITABLES_H__ + +#include +#include +#include +#include + +#define EFI_ACPI_OEM_ID {'R','K','C','P',' ',' '} + +#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64 ('R','K','3','5','8','8',' ',' ') + +#define EFI_ACPI_OEM_REVISION 0x00000000 +#define EFI_ACPI_CREATOR_ID SIGNATURE_32 ('E','D','K','2') +#define EFI_ACPI_CREATOR_REVISION 0x00000000 +#define EFI_ACPI_VENDOR_ID SIGNATURE_32 ('R','K','C','P') + +// A macro to initialise the common header part of EFI ACPI tables as defined by +// EFI_ACPI_DESCRIPTION_HEADER structure. +#define ACPI_HEADER(Signature, Type, Revision) { \ + Signature, /* UINT32 Signature */ \ + sizeof (Type), /* UINT32 Length */ \ + Revision, /* UINT8 Revision */ \ + 0, /* UINT8 Checksum */ \ + EFI_ACPI_OEM_ID, /* UINT8 OemId[6] */ \ + EFI_ACPI_OEM_TABLE_ID, /* UINT64 OemTableId */ \ + EFI_ACPI_OEM_REVISION, /* UINT32 OemRevision */ \ + EFI_ACPI_CREATOR_ID, /* UINT32 CreatorId */ \ + EFI_ACPI_CREATOR_REVISION /* UINT32 CreatorRevision */ \ + } + +#define EFI_ACPI_6_0_GIC_REDISTRIBUTOR_INIT(RedisRegionAddr, RedisDiscLength) \ + { \ + EFI_ACPI_6_0_GICR, \ + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), \ + 0, \ + RedisRegionAddr, \ + RedisDiscLength \ + } + +#define EFI_ACPI_6_0_GIC_ITS_FRAME_INIT(Id, PhysAddress) \ + { \ + EFI_ACPI_6_0_GIC_ITS, \ + sizeof (EFI_ACPI_6_0_GIC_ITS_STRUCTURE), \ + 0, \ + Id, \ + PhysAddress, \ + 0 \ + } + +// +// Device resource helpers +// +#define QWORDMEMORY_BUF(Index, ResourceType) \ + QWordMemory (ResourceType,, \ + MinFixed, MaxFixed, NonCacheable, ReadWrite, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define QWORDIO_BUF(Index, ResourceType) \ + QWordIO (ResourceType, \ + MinFixed, MaxFixed, PosDecode, EntireRange, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define DWORDMEMORY_BUF(Index, ResourceType) \ + DWordMemory (ResourceType,, \ + MinFixed, MaxFixed, NonCacheable, ReadWrite, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define WORDBUSNUMBER_BUF(Index, ResourceType) \ + WordBusNumber (ResourceType, \ + MinFixed, MaxFixed, PosDecode, \ + 0x0, 0x0, 0x0, 0x0, 0x1,,, RB ## Index) + +#define QWORD_SET(Index, Minimum, Length, Translation) \ + CreateQWordField (RBUF, RB ## Index._MIN, MI ## Index) \ + CreateQWordField (RBUF, RB ## Index._MAX, MA ## Index) \ + CreateQWordField (RBUF, RB ## Index._TRA, TR ## Index) \ + CreateQWordField (RBUF, RB ## Index._LEN, LE ## Index) \ + LE ## Index = Length \ + MI ## Index = Minimum \ + TR ## Index = Translation \ + MA ## Index = MI ## Index + LE ## Index - 1 + +#define DWORD_SET(Index, Minimum, Length, Translation) \ + CreateDWordField (RBUF, RB ## Index._MIN, MI ## Index) \ + CreateDWordField (RBUF, RB ## Index._MAX, MA ## Index) \ + CreateDWordField (RBUF, RB ## Index._TRA, TR ## Index) \ + CreateDWordField (RBUF, RB ## Index._LEN, LE ## Index) \ + LE ## Index = Length \ + MI ## Index = Minimum \ + TR ## Index = Translation \ + MA ## Index = MI ## Index + LE ## Index - 1 + +#define WORD_SET(Index, Minimum, Length, Translation) \ + CreateWordField (RBUF, RB ## Index._MIN, MI ## Index) \ + CreateWordField (RBUF, RB ## Index._MAX, MA ## Index) \ + CreateWordField (RBUF, RB ## Index._TRA, TR ## Index) \ + CreateWordField (RBUF, RB ## Index._LEN, LE ## Index) \ + LE ## Index = Length \ + MI ## Index = Minimum \ + TR ## Index = Translation \ + MA ## Index = MI ## Index + LE ## Index - 1 + +#pragma pack(push, 1) +typedef struct { + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE MainEntries[NUM_PCIE_CONTROLLER]; + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE RootPortEntries[NUM_PCIE_CONTROLLER]; +} RK3588_MCFG_TABLE; +#pragma pack(pop) + +#endif // __ACPITABLES_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/GpioLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/GpioLib.h new file mode 100644 index 0000000..e82a947 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/GpioLib.h @@ -0,0 +1,143 @@ +/** @file + * + * Copyright (c) 2021, Jared McNeill + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef GPIOLIB_H__ +#define GPIOLIB_H__ + +#define GPIO_PIN_PA0 0 +#define GPIO_PIN_PA1 1 +#define GPIO_PIN_PA2 2 +#define GPIO_PIN_PA3 3 +#define GPIO_PIN_PA4 4 +#define GPIO_PIN_PA5 5 +#define GPIO_PIN_PA6 6 +#define GPIO_PIN_PA7 7 +#define GPIO_PIN_PB0 8 +#define GPIO_PIN_PB1 9 +#define GPIO_PIN_PB2 10 +#define GPIO_PIN_PB3 11 +#define GPIO_PIN_PB4 12 +#define GPIO_PIN_PB5 13 +#define GPIO_PIN_PB6 14 +#define GPIO_PIN_PB7 15 +#define GPIO_PIN_PC0 16 +#define GPIO_PIN_PC1 17 +#define GPIO_PIN_PC2 18 +#define GPIO_PIN_PC3 19 +#define GPIO_PIN_PC4 20 +#define GPIO_PIN_PC5 21 +#define GPIO_PIN_PC6 22 +#define GPIO_PIN_PC7 23 +#define GPIO_PIN_PD0 24 +#define GPIO_PIN_PD1 25 +#define GPIO_PIN_PD2 26 +#define GPIO_PIN_PD3 27 +#define GPIO_PIN_PD4 28 +#define GPIO_PIN_PD5 29 +#define GPIO_PIN_PD6 30 +#define GPIO_PIN_PD7 31 + +typedef enum { + GPIO_PIN_INPUT = 0, + GPIO_PIN_OUTPUT = 1 +} GPIO_PIN_DIRECTION; + +typedef enum { + GPIO_PIN_PULL_NONE = 0, + GPIO_PIN_PULL_UP = 1, + GPIO_PIN_PULL_DOWN = 2 +} GPIO_PIN_PULL; + +typedef enum { + GPIO_PIN_DRIVE_DEFAULT = 0xFF, + GPIO_PIN_DRIVE_DISABLE = 0x0, + GPIO_PIN_DRIVE_0 = 0x1, + GPIO_PIN_DRIVE_1 = 0x3, + GPIO_PIN_DRIVE_2 = 0x7, + GPIO_PIN_DRIVE_3 = 0xF, + GPIO_PIN_DRIVE_4 = 0x1F, + GPIO_PIN_DRIVE_5 = 0x3F +} GPIO_PIN_DRIVE; + +typedef enum { + GPIO_PIN_INPUT_DEFAULT = 0xFF, + GPIO_PIN_INPUT_DISABLE = 0x0, + GPIO_PIN_INPUT_NON_SCHMITT = 0x1, + GPIO_PIN_INPUT_SCHMITT = 0x2 +} GPIO_PIN_INPUT_ENABLE; + +typedef struct { + CONST char *Name; + UINT8 Group; + UINT8 Pin; + UINT8 Function; + GPIO_PIN_PULL Pull; + GPIO_PIN_DRIVE Drive; +} GPIO_IOMUX_CONFIG; + +VOID +GpioPinSetDirection ( + IN UINT8 Group, + IN UINT8 Pin, + IN GPIO_PIN_DIRECTION Direction + ); + +VOID +GpioPinWrite ( + IN UINT8 Group, + IN UINT8 Pin, + IN BOOLEAN Value + ); + +BOOLEAN +GpioPinRead ( + IN UINT8 Group, + IN UINT8 Pin + ); + +BOOLEAN +GpioPinReadActual ( + IN UINT8 Group, + IN UINT8 Pin + ); + +VOID +GpioPinSetFunction ( + IN UINT8 Group, + IN UINT8 Pin, + IN UINT8 Function + ); + +VOID +GpioPinSetPull ( + IN UINT8 Group, + IN UINT8 Pin, + IN GPIO_PIN_PULL Pull + ); + +VOID +GpioPinSetDrive ( + IN UINT8 Group, + IN UINT8 Pin, + IN GPIO_PIN_DRIVE Drive + ); + +VOID +GpioPinSetInput ( + IN UINT8 Group, + IN UINT8 Pin, + IN GPIO_PIN_INPUT_ENABLE InputEnable + ); + +VOID +GpioSetIomuxConfig ( + IN CONST GPIO_IOMUX_CONFIG *Configs, + IN UINT32 NumConfigs + ); + +#endif /* GPIOLIB_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Pcie30PhyLib.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Pcie30PhyLib.h new file mode 100755 index 0000000..4370afe --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Pcie30PhyLib.h @@ -0,0 +1,17 @@ +/** @file + * + * Copyright (c) 2023, Jared McNeill + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef PCIE30PHYLIB_H__ +#define PCIE30PHYLIB_H__ + +EFI_STATUS +Pcie30PhyInit ( + VOID + ); + +#endif /* PCIE30PHYLIB_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Mem.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Mem.h new file mode 100644 index 0000000..fe14133 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Mem.h @@ -0,0 +1,28 @@ +/** @file + * + * Copyright (c) 2021, Andrey Warkentin + * Copyright (c) 2019, Pete Batard + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef RK3588_MEM_H__ +#define RK3588_MEM_H__ + +#define RK3588_MEM_UNMAPPED_REGION 0 +#define RK3588_MEM_BASIC_REGION 1 +#define RK3588_MEM_RUNTIME_REGION 2 +#define RK3588_MEM_RESERVED_REGION 3 + +typedef struct { + CONST CHAR16* Name; + UINTN Type; +} RK3588_MEMORY_REGION_INFO; + +VOID +Rk3588PlatformGetVirtualMemoryInfo ( + IN RK3588_MEMORY_REGION_INFO** MemoryInfo + ); + +#endif /* RK3588_MEM_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h new file mode 100644 index 0000000..52b9aad --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h @@ -0,0 +1,67 @@ +/** @file +* +* Copyright (c) 2023, Molly Sophia +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef RK3588PCIE_H +#define RK3588PCIE_H + +BOOLEAN +IsPcieNumEnabled( + UINTN PcieNum + ); + +VOID +PciePinmuxInit( + UINTN PcieNum, + UINTN MuxNum + ); + +// +// PCIe 3x4 is the first PCIe controller in memory, the others +// immediately follow it in the order of the segments below. +// + +#define NUM_PCIE_CONTROLLER 5 + +/* + * All pcie controllers supports PCIe 3.0 + * Here we name them using their device tree name in the linux kernel source + */ +#define PCIE_SEGMENT_PCIE30X4 0 +#define PCIE_SEGMENT_PCIE30X2 1 +#define PCIE_SEGMENT_PCIE20L0 2 +#define PCIE_SEGMENT_PCIE20L1 3 +#define PCIE_SEGMENT_PCIE20L2 4 + +#define PCIE_3X4_APB_BASE 0xfe150000 +#define PCIE_3X4_DBI_BASE 0xa40000000ULL +#define PCIE_3X4_CFG_BASE 0x900000000ULL +#define PCIE_3X4_MEM_BASE 0xf0000000 + +#define PCIE_APB_SIZE SIZE_64KB +#define PCIE_DBI_SIZE SIZE_4MB +#define PCIE_CFG_SIZE SIZE_1GB +#define PCIE_MEM_SIZE SIZE_16MB + +#define PCIE_MEM64_OFFSET 0x10000000ULL + +#define PCIE_APB_BASE(Segment) (PCIE_3X4_APB_BASE + (Segment * PCIE_APB_SIZE)) +#define PCIE_DBI_BASE(Segment) (PCIE_3X4_DBI_BASE + (Segment * 1ULL * PCIE_DBI_SIZE)) +#define PCIE_CFG_BASE(Segment) (PCIE_3X4_CFG_BASE + (Segment * 1ULL * PCIE_CFG_SIZE)) + +#define PCIE_MEM_BASE(Segment) (PCIE_3X4_MEM_BASE + (Segment * PCIE_MEM_SIZE)) +#define PCIE_MEM64_BASE(Segment) (PCIE_CFG_BASE(Segment) + PCIE_MEM64_OFFSET) + +#define PCIE_IO_BASE 0x0000 +#define PCIE_IO_SIZE SIZE_64KB +#define PCIE_IO_XLATE(Segment) (PCIE_CFG_BASE(Segment) + PCIE_CFG_SIZE - PCIE_IO_SIZE) + +#define PCIE_MEM64_SIZE (PCIE_CFG_SIZE - PCIE_IO_SIZE - PCIE_MEM64_OFFSET) + +#define PCIE_BUS_LIMIT 252 // limited by CFG1 iATU window size + +#endif diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/RK3588.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/RK3588.h new file mode 100644 index 0000000..1bcf6cb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/RK3588.h @@ -0,0 +1,5519 @@ +#ifndef __RK3588_H +#define __RK3588_H +#ifdef __cplusplus + extern "C" { +#endif +/****************************************************************************************/ +/* */ +/* Module Structure Section */ +/* */ +/****************************************************************************************/ +#ifndef __ASSEMBLY__ +/* DCACHE Register Structure Define */ +struct DCACHE_REG { + __IO uint32_t CACHE_CTRL; /* Address Offset: 0x0000 */ + __IO uint32_t CACHE_MAINTAIN[2]; /* Address Offset: 0x0004 */ + __IO uint32_t STB_TIMEOUT_CTRL; /* Address Offset: 0x000C */ + uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */ + __IO uint32_t CACHE_INT_EN; /* Address Offset: 0x0020 */ + __IO uint32_t CACHE_INT_ST; /* Address Offset: 0x0024 */ + __IO uint32_t CACHE_ERR_HADDR; /* Address Offset: 0x0028 */ + uint32_t RESERVED002C; /* Address Offset: 0x002C */ + __I uint32_t CACHE_STATUS; /* Address Offset: 0x0030 */ + uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ + __I uint32_t PMU_RD_NUM_CNT; /* Address Offset: 0x0040 */ + __I uint32_t PMU_WR_NUM_CNT; /* Address Offset: 0x0044 */ + __I uint32_t PMU_SRAM_RD_HIT_CNT; /* Address Offset: 0x0048 */ + __I uint32_t PMU_HB_RD_HIT_CNT; /* Address Offset: 0x004C */ + __IO uint32_t PMU_STB_RD_HIT_CNT; /* Address Offset: 0x0050 */ + __I uint32_t PMU_RD_HIT_CNT; /* Address Offset: 0x0054 */ + __I uint32_t PMU_WR_HIT_CNT; /* Address Offset: 0x0058 */ + __I uint32_t PMU_RD_MISS_PENALTY_CNT; /* Address Offset: 0x005C */ + __I uint32_t PMU_WR_MISS_PENALTY_CNT; /* Address Offset: 0x0060 */ + __I uint32_t PMU_RD_LAT_CNT; /* Address Offset: 0x0064 */ + __I uint32_t PMU_WR_LAT_CNT; /* Address Offset: 0x0068 */ + uint32_t RESERVED006C[33]; /* Address Offset: 0x006C */ + __IO uint32_t REVISION; /* Address Offset: 0x00F0 */ +}; +/* ICACHE Register Structure Define */ +struct ICACHE_REG { + __IO uint32_t CACHE_CTRL; /* Address Offset: 0x0000 */ + __IO uint32_t CACHE_MAINTAIN[2]; /* Address Offset: 0x0004 */ + __IO uint32_t STB_TIMEOUT_CTRL; /* Address Offset: 0x000C */ + uint32_t RESERVED0010[4]; /* Address Offset: 0x0010 */ + __IO uint32_t CACHE_INT_EN; /* Address Offset: 0x0020 */ + __IO uint32_t CACHE_INT_ST; /* Address Offset: 0x0024 */ + __IO uint32_t CACHE_ERR_HADDR; /* Address Offset: 0x0028 */ + uint32_t RESERVED002C; /* Address Offset: 0x002C */ + __I uint32_t CACHE_STATUS; /* Address Offset: 0x0030 */ + uint32_t RESERVED0034[3]; /* Address Offset: 0x0034 */ + __I uint32_t PMU_RD_NUM_CNT; /* Address Offset: 0x0040 */ + __I uint32_t PMU_WR_NUM_CNT; /* Address Offset: 0x0044 */ + __I uint32_t PMU_SRAM_RD_HIT_CNT; /* Address Offset: 0x0048 */ + __I uint32_t PMU_HB_RD_HIT_CNT; /* Address Offset: 0x004C */ + __IO uint32_t PMU_STB_RD_HIT_CNT; /* Address Offset: 0x0050 */ + __I uint32_t PMU_RD_HIT_CNT; /* Address Offset: 0x0054 */ + __I uint32_t PMU_WR_HIT_CNT; /* Address Offset: 0x0058 */ + __I uint32_t PMU_RD_MISS_PENALTY_CNT; /* Address Offset: 0x005C */ + __I uint32_t PMU_WR_MISS_PENALTY_CNT; /* Address Offset: 0x0060 */ + __I uint32_t PMU_RD_LAT_CNT; /* Address Offset: 0x0064 */ + __I uint32_t PMU_WR_LAT_CNT; /* Address Offset: 0x0068 */ + uint32_t RESERVED006C[33]; /* Address Offset: 0x006C */ + __IO uint32_t REVISION; /* Address Offset: 0x00F0 */ +}; +/* PMU1_IOC Register Structure Define */ +struct PMU1_IOC_REG { + __IO uint32_t GPIO0A_IOMUX_SEL_L; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO0A_IOMUX_SEL_H; /* Address Offset: 0x0004 */ + __IO uint32_t GPIO0B_IOMUX_SEL_L; /* Address Offset: 0x0008 */ + uint32_t RESERVED000C; /* Address Offset: 0x000C */ + __IO uint32_t GPIO0A_DS_L; /* Address Offset: 0x0010 */ + __IO uint32_t GPIO0A_DS_H; /* Address Offset: 0x0014 */ + __IO uint32_t GPIO0B_DS_L; /* Address Offset: 0x0018 */ + uint32_t RESERVED001C; /* Address Offset: 0x001C */ + __IO uint32_t GPIO0A_P; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO0B_P; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO0A_IE; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO0B_IE; /* Address Offset: 0x002C */ + __IO uint32_t GPIO0A_SMT; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO0B_SMT; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO0A_PDIS; /* Address Offset: 0x0038 */ + __IO uint32_t GPIO0B_PDIS; /* Address Offset: 0x003C */ + __IO uint32_t XIN_CON; /* Address Offset: 0x0040 */ +}; +/* PMU2_IOC Register Structure Define */ +struct PMU2_IOC_REG { + __IO uint32_t GPIO0B_IOMUX_SEL_H; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO0C_IOMUX_SEL_L; /* Address Offset: 0x0004 */ + __IO uint32_t GPIO0C_IOMUX_SEL_H; /* Address Offset: 0x0008 */ + __IO uint32_t GPIO0D_IOMUX_SEL_L; /* Address Offset: 0x000C */ + __IO uint32_t GPIO0D_IOMUX_SEL_H; /* Address Offset: 0x0010 */ + __IO uint32_t GPIO0B_DS_H; /* Address Offset: 0x0014 */ + __IO uint32_t GPIO0C_DS_L; /* Address Offset: 0x0018 */ + __IO uint32_t GPIO0C_DS_H; /* Address Offset: 0x001C */ + __IO uint32_t GPIO0D_DS_L; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO0D_DS_H; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO0B_P; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO0C_P; /* Address Offset: 0x002C */ + __IO uint32_t GPIO0D_P; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO0B_IE; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO0C_IE; /* Address Offset: 0x0038 */ + __IO uint32_t GPIO0D_IE; /* Address Offset: 0x003C */ + __IO uint32_t GPIO0B_SMT; /* Address Offset: 0x0040 */ + __IO uint32_t GPIO0C_SMT; /* Address Offset: 0x0044 */ + __IO uint32_t GPIO0D_SMT; /* Address Offset: 0x0048 */ + __IO uint32_t GPIO0B_PDIS; /* Address Offset: 0x004C */ + __IO uint32_t GPIO0C_PDIS; /* Address Offset: 0x0050 */ + __IO uint32_t GPIO0D_PDIS; /* Address Offset: 0x0054 */ +}; +/* BUS_IOC Register Structure Define */ +struct BUS_IOC_REG { + uint32_t RESERVED0000[3]; /* Address Offset: 0x0000 */ + __IO uint32_t GPIO0B_IOMUX_SEL_H; /* Address Offset: 0x000C */ + __IO uint32_t GPIO0C_IOMUX_SEL_L; /* Address Offset: 0x0010 */ + __IO uint32_t GPIO0C_IOMUX_SEL_H; /* Address Offset: 0x0014 */ + __IO uint32_t GPIO0D_IOMUX_SEL_L; /* Address Offset: 0x0018 */ + __IO uint32_t GPIO0D_IOMUX_SEL_H; /* Address Offset: 0x001C */ + __IO uint32_t GPIO1A_IOMUX_SEL_L; /* Address Offset: 0x0020 */ + __IO uint32_t GPIO1A_IOMUX_SEL_H; /* Address Offset: 0x0024 */ + __IO uint32_t GPIO1B_IOMUX_SEL_L; /* Address Offset: 0x0028 */ + __IO uint32_t GPIO1B_IOMUX_SEL_H; /* Address Offset: 0x002C */ + __IO uint32_t GPIO1C_IOMUX_SEL_L; /* Address Offset: 0x0030 */ + __IO uint32_t GPIO1C_IOMUX_SEL_H; /* Address Offset: 0x0034 */ + __IO uint32_t GPIO1D_IOMUX_SEL_L; /* Address Offset: 0x0038 */ + __IO uint32_t GPIO1D_IOMUX_SEL_H; /* Address Offset: 0x003C */ + __IO uint32_t GPIO2A_IOMUX_SEL_L; /* Address Offset: 0x0040 */ + __IO uint32_t GPIO2A_IOMUX_SEL_H; /* Address Offset: 0x0044 */ + __IO uint32_t GPIO2B_IOMUX_SEL_L; /* Address Offset: 0x0048 */ + __IO uint32_t GPIO2B_IOMUX_SEL_H; /* Address Offset: 0x004C */ + __IO uint32_t GPIO2C_IOMUX_SEL_L; /* Address Offset: 0x0050 */ + __IO uint32_t GPIO2C_IOMUX_SEL_H; /* Address Offset: 0x0054 */ + __IO uint32_t GPIO2D_IOMUX_SEL_L; /* Address Offset: 0x0058 */ + __IO uint32_t GPIO2D_IOMUX_SEL_H; /* Address Offset: 0x005C */ + __IO uint32_t GPIO3A_IOMUX_SEL_L; /* Address Offset: 0x0060 */ + __IO uint32_t GPIO3A_IOMUX_SEL_H; /* Address Offset: 0x0064 */ + __IO uint32_t GPIO3B_IOMUX_SEL_L; /* Address Offset: 0x0068 */ + __IO uint32_t GPIO3B_IOMUX_SEL_H; /* Address Offset: 0x006C */ + __IO uint32_t GPIO3C_IOMUX_SEL_L; /* Address Offset: 0x0070 */ + __IO uint32_t GPIO3C_IOMUX_SEL_H; /* Address Offset: 0x0074 */ + __IO uint32_t GPIO3D_IOMUX_SEL_L; /* Address Offset: 0x0078 */ + __IO uint32_t GPIO3D_IOMUX_SEL_H; /* Address Offset: 0x007C */ + __IO uint32_t GPIO4A_IOMUX_SEL_L; /* Address Offset: 0x0080 */ + __IO uint32_t GPIO4A_IOMUX_SEL_H; /* Address Offset: 0x0084 */ + __IO uint32_t GPIO4B_IOMUX_SEL_L; /* Address Offset: 0x0088 */ + __IO uint32_t GPIO4B_IOMUX_SEL_H; /* Address Offset: 0x008C */ + __IO uint32_t GPIO4C_IOMUX_SEL_L; /* Address Offset: 0x0090 */ + __IO uint32_t GPIO4C_IOMUX_SEL_H; /* Address Offset: 0x0094 */ + __IO uint32_t GPIO4D_IOMUX_SEL_L; /* Address Offset: 0x0098 */ + __IO uint32_t GPIO4D_IOMUX_SEL_H; /* Address Offset: 0x009C */ +}; +/* UART Register Structure Define */ +struct UART_REG { + union { + __I uint32_t RBR; /* Address Offset: 0x0000 */ + __IO uint32_t DLL; /* Address Offset: 0x0000 */ + __O uint32_t THR; /* Address Offset: 0x0000 */ + }; + union { + __IO uint32_t DLH; /* Address Offset: 0x0004 */ + __IO uint32_t IER; /* Address Offset: 0x0004 */ + }; + union { + __O uint32_t FCR; /* Address Offset: 0x0008 */ + __I uint32_t IIR; /* Address Offset: 0x0008 */ + }; + __IO uint32_t LCR; /* Address Offset: 0x000C */ + __IO uint32_t MCR; /* Address Offset: 0x0010 */ + __I uint32_t LSR; /* Address Offset: 0x0014 */ + __I uint32_t MSR; /* Address Offset: 0x0018 */ + __IO uint32_t SCR; /* Address Offset: 0x001C */ + uint32_t RESERVED0020[4]; /* Address Offset: 0x0020 */ + union { + __I uint32_t SRBR; /* Address Offset: 0x0030 */ + __O uint32_t STHR; /* Address Offset: 0x0030 */ + }; + uint32_t RESERVED0034[15]; /* Address Offset: 0x0034 */ + __IO uint32_t FAR; /* Address Offset: 0x0070 */ + __I uint32_t TFR; /* Address Offset: 0x0074 */ + __O uint32_t RFW; /* Address Offset: 0x0078 */ + __I uint32_t USR; /* Address Offset: 0x007C */ + __I uint32_t TFL; /* Address Offset: 0x0080 */ + __I uint32_t RFL; /* Address Offset: 0x0084 */ + __O uint32_t SRR; /* Address Offset: 0x0088 */ + __IO uint32_t SRTS; /* Address Offset: 0x008C */ + __IO uint32_t SBCR; /* Address Offset: 0x0090 */ + __IO uint32_t SDMAM; /* Address Offset: 0x0094 */ + __IO uint32_t SFE; /* Address Offset: 0x0098 */ + __IO uint32_t SRT; /* Address Offset: 0x009C */ + __IO uint32_t STET; /* Address Offset: 0x00A0 */ + __IO uint32_t HTX; /* Address Offset: 0x00A4 */ + __O uint32_t DMASA; /* Address Offset: 0x00A8 */ + uint32_t RESERVED00AC[18]; /* Address Offset: 0x00AC */ + __I uint32_t CPR; /* Address Offset: 0x00F4 */ + __I uint32_t UCV; /* Address Offset: 0x00F8 */ + __I uint32_t CTR; /* Address Offset: 0x00FC */ +}; +/* WDT Register Structure Define */ +struct WDT_REG { + __IO uint32_t CR; /* Address Offset: 0x0000 */ + __IO uint32_t TORR; /* Address Offset: 0x0004 */ + __I uint32_t CCVR; /* Address Offset: 0x0008 */ + __O uint32_t CRR; /* Address Offset: 0x000C */ + __I uint32_t STAT; /* Address Offset: 0x0010 */ + __I uint32_t EOI; /* Address Offset: 0x0014 */ +}; +/* TIMER Register Structure Define */ +struct TIMER_REG { + __IO uint32_t LOAD_COUNT[2]; /* Address Offset: 0x0000 */ + __I uint32_t CURRENT_VALUE[2]; /* Address Offset: 0x0008 */ + __IO uint32_t CONTROLREG; /* Address Offset: 0x0010 */ + uint32_t RESERVED0014; /* Address Offset: 0x0014 */ + __IO uint32_t INTSTATUS; /* Address Offset: 0x0018 */ +}; +/* FSPI Register Structure Define */ +struct FSPI_REG { + __IO uint32_t CTRL0; /* Address Offset: 0x0000 */ + __IO uint32_t IMR; /* Address Offset: 0x0004 */ + __IO uint32_t ICLR; /* Address Offset: 0x0008 */ + __IO uint32_t FTLR; /* Address Offset: 0x000C */ + __IO uint32_t RCVR; /* Address Offset: 0x0010 */ + __IO uint32_t AX0; /* Address Offset: 0x0014 */ + __IO uint32_t ABIT0; /* Address Offset: 0x0018 */ + __IO uint32_t ISR; /* Address Offset: 0x001C */ + __IO uint32_t FSR; /* Address Offset: 0x0020 */ + __I uint32_t SR; /* Address Offset: 0x0024 */ + __I uint32_t RISR; /* Address Offset: 0x0028 */ + __I uint32_t VER; /* Address Offset: 0x002C */ + __IO uint32_t QOP; /* Address Offset: 0x0030 */ + __IO uint32_t EXT_CTRL; /* Address Offset: 0x0034 */ + uint32_t RESERVED0038; /* Address Offset: 0x0038 */ + __IO uint32_t DLL_CTRL0; /* Address Offset: 0x003C */ + uint32_t RESERVED0040; /* Address Offset: 0x0040 */ + __IO uint32_t EXT_AX; /* Address Offset: 0x0044 */ + __IO uint32_t SCLK_INATM_CNT; /* Address Offset: 0x0048 */ + uint32_t RESERVED004C; /* Address Offset: 0x004C */ + __O uint32_t XMMC_WCMD0; /* Address Offset: 0x0050 */ + __O uint32_t XMMC_RCMD0; /* Address Offset: 0x0054 */ + __IO uint32_t XMMC_CTRL; /* Address Offset: 0x0058 */ + __IO uint32_t MODE; /* Address Offset: 0x005C */ + __IO uint32_t DEVRGN; /* Address Offset: 0x0060 */ + __IO uint32_t DEVSIZE0; /* Address Offset: 0x0064 */ + __IO uint32_t TME0; /* Address Offset: 0x0068 */ + uint32_t RESERVED006C; /* Address Offset: 0x006C */ + __IO uint32_t XMMC_RX_WTMRK; /* Address Offset: 0x0070 */ + uint32_t RESERVED0074[3]; /* Address Offset: 0x0074 */ + __IO uint32_t DMATR; /* Address Offset: 0x0080 */ + __IO uint32_t DMAADDR; /* Address Offset: 0x0084 */ + __IO uint32_t LEN_CTRL; /* Address Offset: 0x0088 */ + __IO uint32_t LEN_EXT; /* Address Offset: 0x008C */ + uint32_t RESERVED0090; /* Address Offset: 0x0090 */ + __IO uint32_t XMMCSR; /* Address Offset: 0x0094 */ + uint32_t RESERVED0098[26]; /* Address Offset: 0x0098 */ + __O uint32_t CMD; /* Address Offset: 0x0100 */ + __O uint32_t ADDR; /* Address Offset: 0x0104 */ + __IO uint32_t DATA; /* Address Offset: 0x0108 */ + uint32_t RESERVED010C[61]; /* Address Offset: 0x010C */ + __IO uint32_t CTRL1; /* Address Offset: 0x0200 */ + uint32_t RESERVED0204[4]; /* Address Offset: 0x0204 */ + __IO uint32_t AX1; /* Address Offset: 0x0214 */ + __IO uint32_t ABIT1; /* Address Offset: 0x0218 */ + uint32_t RESERVED021C[8]; /* Address Offset: 0x021C */ + __IO uint32_t DLL_CTRL1; /* Address Offset: 0x023C */ + uint32_t RESERVED0240[4]; /* Address Offset: 0x0240 */ + __O uint32_t XMMC_WCMD1; /* Address Offset: 0x0250 */ + __O uint32_t XMMC_RCMD1; /* Address Offset: 0x0254 */ + uint32_t RESERVED0258[3]; /* Address Offset: 0x0258 */ + __IO uint32_t DEVSIZE1; /* Address Offset: 0x0264 */ + __IO uint32_t TME1; /* Address Offset: 0x0268 */ +}; +/* SPI Register Structure Define */ +struct SPI_REG { + __IO uint32_t CTRLR[2]; /* Address Offset: 0x0000 */ + __IO uint32_t ENR; /* Address Offset: 0x0008 */ + __IO uint32_t SER; /* Address Offset: 0x000C */ + __IO uint32_t BAUDR; /* Address Offset: 0x0010 */ + __IO uint32_t TXFTLR; /* Address Offset: 0x0014 */ + __IO uint32_t RXFTLR; /* Address Offset: 0x0018 */ + __I uint32_t TXFLR; /* Address Offset: 0x001C */ + __I uint32_t RXFLR; /* Address Offset: 0x0020 */ + __I uint32_t SR; /* Address Offset: 0x0024 */ + __IO uint32_t IPR; /* Address Offset: 0x0028 */ + __IO uint32_t IMR; /* Address Offset: 0x002C */ + __IO uint32_t ISR; /* Address Offset: 0x0030 */ + __IO uint32_t RISR; /* Address Offset: 0x0034 */ + __O uint32_t ICR; /* Address Offset: 0x0038 */ + __IO uint32_t DMACR; /* Address Offset: 0x003C */ + __IO uint32_t DMATDLR; /* Address Offset: 0x0040 */ + __IO uint32_t DMARDLR; /* Address Offset: 0x0044 */ + uint32_t RESERVED0048; /* Address Offset: 0x0048 */ + __IO uint32_t TIMEOUT; /* Address Offset: 0x004C */ + __IO uint32_t BYPASS; /* Address Offset: 0x0050 */ + uint32_t RESERVED0054[235]; /* Address Offset: 0x0054 */ + __O uint32_t TXDR; /* Address Offset: 0x0400 */ + uint32_t RESERVED0404[255]; /* Address Offset: 0x0404 */ + __I uint32_t RXDR; /* Address Offset: 0x0800 */ +}; +/* MBOX Register Structure Define */ +struct MBOX_CMD_DAT { + __IO uint32_t CMD; + __IO uint32_t DATA; +}; +struct MBOX_REG { + __IO uint32_t A2B_INTEN; /* Address Offset: 0x0000 */ + __IO uint32_t A2B_STATUS; /* Address Offset: 0x0004 */ + struct MBOX_CMD_DAT A2B[4]; /* Address Offset: 0x0008 */ + __IO uint32_t B2A_INTEN; /* Address Offset: 0x0028 */ + __IO uint32_t B2A_STATUS; /* Address Offset: 0x002C */ + struct MBOX_CMD_DAT B2A[4]; /* Address Offset: 0x0030 */ + uint32_t RESERVED0050[44]; /* Address Offset: 0x0050 */ + __IO uint32_t ATOMIC_LOCK[32]; /* Address Offset: 0x0100 */ +}; +/* INTMUX Register Structure Define */ +struct INTMUX_REG { +}; +/* INTMUX0_ Register Structure Define */ +struct INTMUX0__REG { +}; +/* CRU Register Structure Define */ +struct CRU_REG { + uint32_t RESERVED0000[88]; /* Address Offset: 0x0000 */ + __IO uint32_t V0PLL_CON[7]; /* Address Offset: 0x0160 */ + uint32_t RESERVED017C; /* Address Offset: 0x017C */ + __IO uint32_t AUPLL_CON[7]; /* Address Offset: 0x0180 */ + uint32_t RESERVED019C; /* Address Offset: 0x019C */ + __IO uint32_t CPLL_CON[7]; /* Address Offset: 0x01A0 */ + uint32_t RESERVED01BC; /* Address Offset: 0x01BC */ + __IO uint32_t GPLL_CON[7]; /* Address Offset: 0x01C0 */ + uint32_t RESERVED01DC; /* Address Offset: 0x01DC */ + __IO uint32_t NPLL_CON[7]; /* Address Offset: 0x01E0 */ + uint32_t RESERVED01FC[33]; /* Address Offset: 0x01FC */ + __IO uint32_t MODE_CON00; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CRU_CLKSEL_CON[178]; /* Address Offset: 0x0300 */ + uint32_t RESERVED05C8[142]; /* Address Offset: 0x05C8 */ + __IO uint32_t CRU_CLKGATE_CON[78]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0938[51]; /* Address Offset: 0x0938 */ + __IO uint32_t CRU_SOFTRST_CON[77]; /* Address Offset: 0x0A04 */ + uint32_t RESERVED0B38[50]; /* Address Offset: 0x0B38 */ + __IO uint32_t GLB_CNT_TH; /* Address Offset: 0x0C00 */ + __IO uint32_t GLBRST_ST; /* Address Offset: 0x0C04 */ + __IO uint32_t GLB_SRST_FST_VALUE; /* Address Offset: 0x0C08 */ + __IO uint32_t GLB_SRST_SND_VALUE; /* Address Offset: 0x0C0C */ + __IO uint32_t GLB_RST_CON; /* Address Offset: 0x0C10 */ + uint32_t RESERVED0C14[4]; /* Address Offset: 0x0C14 */ + __IO uint32_t SDIO_CON[2]; /* Address Offset: 0x0C24 */ + uint32_t RESERVED0C2C; /* Address Offset: 0x0C2C */ + __IO uint32_t SDMMC_CON[2]; /* Address Offset: 0x0C30 */ + __IO uint32_t PHYREF_ALT_GATE_CON; /* Address Offset: 0x0C38 */ + __IO uint32_t CM0_GATEMASK_CON; /* Address Offset: 0x0C3C */ + uint32_t RESERVED0C40[25]; /* Address Offset: 0x0C40 */ + __IO uint32_t QCHANNEL_CON01; /* Address Offset: 0x0CA4 */ +}; +/* BIGCORE0CRU Register Structure Define */ +struct BIGCORE0CRU_REG { + __IO uint32_t B0PLL_CON[7]; /* Address Offset: 0x0000 */ + uint32_t RESERVED001C[153]; /* Address Offset: 0x001C */ + __IO uint32_t MODE_CON00; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CLKSEL_CON[3]; /* Address Offset: 0x0300 */ + uint32_t RESERVED030C[317]; /* Address Offset: 0x030C */ + __IO uint32_t GATE_CON[2]; /* Address Offset: 0x0800 */ + __IO uint32_t SOFTRST_CON[2]; /* Address Offset: 0x0A00 */ + __IO uint32_t SMOTH_DIVFREE_CON04; /* Address Offset: 0x0CC0 */ + __IO uint32_t SMOTH_DIVFREE_CON05; /* Address Offset: 0x0CC4 */ + __IO uint32_t AUTOCS_CLK_CORE_B01_I_CON0; /* Address Offset: 0x0D00 */ + __IO uint32_t AUTOCS_CLK_CORE_B01_I_CON1; /* Address Offset: 0x0D04 */ +}; +/* BIGCORE1CRU Register Structure Define */ +struct BIGCORE1CRU_REG { + uint32_t RESERVED0000[8]; /* Address Offset: 0x0000 */ + __IO uint32_t B1PLL_CON[7]; /* Address Offset: 0x0020 */ + uint32_t RESERVED003C[145]; /* Address Offset: 0x003C */ + __IO uint32_t MODE_CON00; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CLKSEL_CON[3]; /* Address Offset: 0x0300 */ + uint32_t RESERVED030C[317]; /* Address Offset: 0x030C */ + __IO uint32_t GATE_CON[2]; /* Address Offset: 0x0800 */ + __IO uint32_t SOFTRST_CON[2]; /* Address Offset: 0x0A00 */ + __IO uint32_t SMOTH_DIVFREE_CON06; /* Address Offset: 0x0CC0 */ + __IO uint32_t SMOTH_DIVFREE_CON07; /* Address Offset: 0x0CC4 */ + __IO uint32_t AUTOCS_CLK_CORE_B23_I_CON0; /* Address Offset: 0x0D00 */ + __IO uint32_t AUTOCS_CLK_CORE_B23_I_CON1; /* Address Offset: 0x0D04 */ +}; +/* DSUCRU Register Structure Define */ +struct DSUCRU_REG { + uint32_t RESERVED0000[16]; /* Address Offset: 0x0000 */ + __IO uint32_t LPLL_CON[7]; /* Address Offset: 0x0040 */ + uint32_t RESERVED005C[137]; /* Address Offset: 0x005C */ + __IO uint32_t MODE_CON00; /* Address Offset: 0x0280 */ + uint32_t RESERVED0284[31]; /* Address Offset: 0x0284 */ + __IO uint32_t CLKSEL_CON[8]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0320[312]; /* Address Offset: 0x0320 */ + __IO uint32_t GATE_CON[4]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0810[124]; /* Address Offset: 0x0810 */ + __IO uint32_t SOFTRST_CON[4]; /* Address Offset: 0x0A00 */ + uint32_t RESERVED0A10[188]; /* Address Offset: 0x0A10 */ + __IO uint32_t AUTOCS_ACLK_M_DSU_BIU_CON0; /* Address Offset: 0x0D00 */ + __IO uint32_t AUTOCS_ACLK_M_DSU_BIU_CON1; /* Address Offset: 0x0D04 */ + __IO uint32_t AUTOCS_ACLK_S_DSU_BIU_CON0; /* Address Offset: 0x0D08 */ + __IO uint32_t AUTOCS_ACLK_S_DSU_BIU_CON1; /* Address Offset: 0x0D0C */ + __IO uint32_t AUTOCS_ACLK_MP_DSU_BIU_CON0; /* Address Offset: 0x0D10 */ + __IO uint32_t AUTOCS_ACLK_MP_DSU_BIU_CON1; /* Address Offset: 0x0D14 */ + __IO uint32_t AUTOCS_SCLK_DSU_SRC_CON0; /* Address Offset: 0x0D18 */ + __IO uint32_t AUTOCS_SCLK_DSU_SRC_CON1; /* Address Offset: 0x0D1C */ + __IO uint32_t AUTOCS_CLK_CORE_L_CON0; /* Address Offset: 0x0D20 */ + __IO uint32_t AUTOCS_CLK_CORE_L_CON1; /* Address Offset: 0x0D24 */ + uint32_t RESERVED0D28[118]; /* Address Offset: 0x0D28 */ + __IO uint32_t QCHANNEL_CON00; /* Address Offset: 0x0F00 */ + uint32_t RESERVED0F04[3]; /* Address Offset: 0x0F04 */ + __IO uint32_t SMOTH_DIVFREE_CON00; /* Address Offset: 0x0F10 */ + __IO uint32_t SMOTH_DIVFREE_CON01; /* Address Offset: 0x0F14 */ + __IO uint32_t SMOTH_DIVFREE_CON02; /* Address Offset: 0x0F18 */ + __IO uint32_t SMOTH_DIVFREE_CON03; /* Address Offset: 0x0F1C */ +}; +/* PHPTOPCRU Register Structure Define */ +struct PHPTOPCRU_REG { + uint32_t RESERVED0000[128]; /* Address Offset: 0x0000 */ + __IO uint32_t PPLL_CON[7]; /* Address Offset: 0x0200 */ + uint32_t RESERVED021C[377]; /* Address Offset: 0x021C */ + __IO uint32_t GATE_CON00; /* Address Offset: 0x0800 */ + uint32_t RESERVED0804[127]; /* Address Offset: 0x0804 */ + __IO uint32_t SOFTRST_CON00; /* Address Offset: 0x0A00 */ +}; +/* PMU1CRU Register Structure Define */ +struct PMU1CRU_REG { + uint32_t RESERVED0000[192]; /* Address Offset: 0x0000 */ + __IO uint32_t PMU_CLKSEL_CON[18]; /* Address Offset: 0x0300 */ + uint32_t RESERVED0348[302]; /* Address Offset: 0x0348 */ + __IO uint32_t PMU_CLKGATE_CON[6]; /* Address Offset: 0x0800 */ + uint32_t RESERVED0818[122]; /* Address Offset: 0x0818 */ + __IO uint32_t PMU_SOFTRST_CON[6]; /* Address Offset: 0x0A00 */ + uint32_t RESERVED0A18[186]; /* Address Offset: 0x0A18 */ + __IO uint32_t AUTOCS_HCLK_PMU_CM0_ROOT_I_CON0; /* Address Offset: 0x0D00 */ + __IO uint32_t AUTOCS_HCLK_PMU_CM0_ROOT_I_CON1; /* Address Offset: 0x0D04 */ +}; +#endif /* __ASSEMBLY__ */ +/****************************************************************************************/ +/* */ +/* Module Address Section */ +/* */ +/****************************************************************************************/ +/* Memory Base */ +#define DCACHE_BASE 0xF6F10000U /* DCACHE base address */ +#define ICACHE_BASE 0xF6F10000U /* ICACHE base address */ +#define PMU1_IOC_BASE 0xFD5F0000U /* PMU1_IOC base address */ +#define PMU2_IOC_BASE 0xFD5F4000U /* PMU2_IOC base address */ +#define BUS_IOC_BASE 0xFD5F8000U /* BUS_IOC base address */ +#define CRU_BASE 0xFD7C0000U /* CRU base address */ +#define BIGCORE0CRU_BASE 0xFD810000U /* BIGCORE0CRU base address */ +#define BIGCORE1CRU_BASE 0xFD812000U /* BIGCORE1CRU base address */ +#define DSUCRU_BASE 0xFD818000U /* DSUCRU base address */ +#define PHPTOPCRU_BASE 0xFD7C8000U /* PHPTOPCRU base address */ +#define PMU1CRU_BASE 0xFD7F0000U /* PMU1CRU base address */ +#define UART0_BASE 0xFD890000U /* UART0 base address */ +#define SYS_PMU_BASE 0xFD8D8000U /* SYS_PMU base address */ +#define WDTPMU_BASE 0xFD8E0000U /* WDTPMU base address */ +#define TIMERPMU_BASE 0xFD8F0000U /* TIMERPMU base address */ +#define WDTNPU_BASE 0xFDAF8000U /* WDTNPU base address */ +#define TIMERNPU_BASE 0xFDB00000U /* TIMERNPU base address */ +#define WDTDDR_BASE 0xFE110000U /* WDTDDR base address */ +#define TIMERDDR_BASE 0xFE118000U /* TIMERDDR base address */ +#define FSPI_BASE 0xFE2B0000U /* FSPI base address */ +#define SPI0_BASE 0xFEB00000U /* SPI0 base address */ +#define SPI1_BASE 0xFEB10000U /* SPI1 base address */ +#define SPI2_BASE 0xFEB20000U /* SPI2 base address */ +#define UART1_BASE 0xFEB40000U /* UART1 base address */ +#define UART2_BASE 0xFEB50000U /* UART2 base address */ +#define UART3_BASE 0xFEB60000U /* UART3 base address */ +#define UART4_BASE 0xFEB70000U /* UART4 base address */ +#define UART5_BASE 0xFEB80000U /* UART5 base address */ +#define UART6_BASE 0xFEB90000U /* UART6 base address */ +#define UART7_BASE 0xFEBA0000U /* UART7 base address */ +#define UART8_BASE 0xFEBB0000U /* UART8 base address */ +#define UART9_BASE 0xFEBC0000U /* UART9 base address */ +#define MBOX0_BASE 0xFEC60000U /* MBOX0 base address */ +#define MBOX1_BASE 0xFEC70000U /* MBOX1 base address */ +#define MBOX2_BASE 0xFECE0000U /* MBOX2 base address */ +#define INTMUX0_PMU_BASE 0xFECF0000U /* INTMUX0_PMU base address */ +#define INTMUX1_PMU_BASE 0xFECF4000U /* INTMUX1_PMU base address */ +#define INTMUX0_DDR_BASE 0xFECF8000U /* INTMUX0_DDR base address */ +#define INTMUX1_DDR_BASE 0xFECFC000U /* INTMUX1_DDR base address */ +/****************************************************************************************/ +/* */ +/* Module Variable Section */ +/* */ +/****************************************************************************************/ +/* Module Variable Define */ + +#define DCACHE ((struct DCACHE_REG *) DCACHE_BASE) +#define ICACHE ((struct ICACHE_REG *) ICACHE_BASE) +#define PMU1_IOC ((struct PMU1_IOC_REG *) PMU1_IOC_BASE) +#define PMU2_IOC ((struct PMU2_IOC_REG *) PMU2_IOC_BASE) +#define BUS_IOC ((struct BUS_IOC_REG *) BUS_IOC_BASE) +#define CRU ((struct CRU_REG *) CRU_BASE) +#define BIGCORE0CRU ((struct BIGCORE0CRU_REG *) BIGCORE0CRU_BASE) +#define BIGCORE1CRU ((struct BIGCORE1CRU_REG *) BIGCORE1CRU_BASE) +#define DSUCRU ((struct DSUCRU_REG *) DSUCRU_BASE) +#define PHPTOPCRU ((struct PHPTOPCRU_REG *) PHPTOPCRU_BASE) +#define PMU1CRU ((struct PMU1CRU_REG *) PMU1CRU_BASE) +#define UART0 ((struct UART_REG *) UART0_BASE) +#define WDTPMU ((struct WDTPMU_REG *) WDTPMU_BASE) +#define TIMERPMU ((struct TIMERPMU_REG *) TIMERPMU_BASE) +#define WDTNPU ((struct WDTNPU_REG *) WDTNPU_BASE) +#define TIMERNPU ((struct TIMERNPU_REG *) TIMERNPU_BASE) +#define WDTDDR ((struct WDTDDR_REG *) WDTDDR_BASE) +#define TIMERDDR ((struct TIMERDDR_REG *) TIMERDDR_BASE) +#define FSPI ((struct FSPI_REG *) FSPI_BASE) +#define SPI0 ((struct SPI_REG *) SPI0_BASE) +#define SPI1 ((struct SPI_REG *) SPI1_BASE) +#define SPI2 ((struct SPI_REG *) SPI2_BASE) +#define UART1 ((struct UART_REG *) UART1_BASE) +#define UART2 ((struct UART_REG *) UART2_BASE) +#define UART3 ((struct UART_REG *) UART3_BASE) +#define UART4 ((struct UART_REG *) UART4_BASE) +#define UART5 ((struct UART_REG *) UART5_BASE) +#define UART6 ((struct UART_REG *) UART6_BASE) +#define UART7 ((struct UART_REG *) UART7_BASE) +#define UART8 ((struct UART_REG *) UART8_BASE) +#define UART9 ((struct UART_REG *) UART9_BASE) +#define MBOX0 ((struct MBOX_REG *) MBOX0_BASE) +#define MBOX1 ((struct MBOX_REG *) MBOX1_BASE) +#define MBOX2 ((struct MBOX_REG *) MBOX2_BASE) +#define INTMUX0_PMU ((struct INTMUX0_PMU_REG *) INTMUX0_PMU_BASE) +#define INTMUX1_PMU ((struct INTMUX1_PMU_REG *) INTMUX1_PMU_BASE) +#define INTMUX0_DDR ((struct INTMUX0_DDR_REG *) INTMUX0_DDR_BASE) +#define INTMUX1_DDR ((struct INTMUX1_DDR_REG *) INTMUX1_DDR_BASE) + +#define IS_DCACHE_INSTANCE(instance) ((instance) == DCACHE) +#define IS_ICACHE_INSTANCE(instance) ((instance) == ICACHE) +#define IS_PMU1_IOC_INSTANCE(instance) ((instance) == PMU1_IOC) +#define IS_PMU2_IOC_INSTANCE(instance) ((instance) == PMU2_IOC) +#define IS_BUS_IOC_INSTANCE(instance) ((instance) == BUS_IOC) +#define IS_CRU_INSTANCE(instance) ((instance) == CRU) +#define IS_BIGCORE0CRU_INSTANCE(instance) ((instance) == BIGCORE0CRU) +#define IS_BIGCORE1CRU_INSTANCE(instance) ((instance) == BIGCORE1CRU) +#define IS_DSUCRU_INSTANCE(instance) ((instance) == DSUCRU) +#define IS_PHPTOPCRU_INSTANCE(instance) ((instance) == PHPTOPCRU) +#define IS_PMU1CRU_INSTANCE(instance) ((instance) == PMU1CRU) +#define IS_WDTPMU_INSTANCE(instance) ((instance) == WDTPMU) +#define IS_TIMERPMU_INSTANCE(instance) ((instance) == TIMERPMU) +#define IS_WDTNPU_INSTANCE(instance) ((instance) == WDTNPU) +#define IS_TIMERNPU_INSTANCE(instance) ((instance) == TIMERNPU) +#define IS_WDTDDR_INSTANCE(instance) ((instance) == WDTDDR) +#define IS_TIMERDDR_INSTANCE(instance) ((instance) == TIMERDDR) +#define IS_FSPI_INSTANCE(instance) ((instance) == FSPI) +#define IS_INTMUX0_PMU_INSTANCE(instance) ((instance) == INTMUX0_PMU) +#define IS_INTMUX1_PMU_INSTANCE(instance) ((instance) == INTMUX1_PMU) +#define IS_INTMUX0_DDR_INSTANCE(instance) ((instance) == INTMUX0_DDR) +#define IS_INTMUX1_DDR_INSTANCE(instance) ((instance) == INTMUX1_DDR) +#define IS_UART_INSTANCE(instance) (((instance) == UART0) || ((instance) == UART1) || ((instance) == UART2) || ((instance) == UART3) || ((instance) == UART4) || ((instance) == UART5) || ((instance) == UART6) || ((instance) == UART7) || ((instance) == UART8) || ((instance) == UART9)) +#define IS_SPI_INSTANCE(instance) (((instance) == SPI0) || ((instance) == SPI1) || ((instance) == SPI2)) +#define IS_MBOX_INSTANCE(instance) (((instance) == MBOX0) || ((instance) == MBOX1) || ((instance) == MBOX2)) +/****************************************************************************************/ +/* */ +/* Register Bitmap Section */ +/* */ +/****************************************************************************************/ +/*****************************************CRU*****************************************/ +#define CRU_CLKSEL_CON_OFFSET 0x300 +#define CRU_CLKGATE_CON_OFFSET 0x800 +#define CRU_SOFTRST_CON_OFFSET 0xA00 + +/*****************************************DCACHE*****************************************/ +/* CACHE_CTRL */ +#define DCACHE_CACHE_CTRL_OFFSET (0x0U) +#define DCACHE_CACHE_CTRL_CACHE_EN_SHIFT (0U) +#define DCACHE_CACHE_CTRL_CACHE_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_EN_SHIFT) /* 0x00000001 */ +#define DCACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT (1U) +#define DCACHE_CACHE_CTRL_CACHE_WT_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT) /* 0x00000002 */ +#define DCACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT (2U) +#define DCACHE_CACHE_CTRL_CACHE_HB_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT) /* 0x00000004 */ +#define DCACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT (3U) +#define DCACHE_CACHE_CTRL_CACHE_STB_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT) /* 0x00000008 */ +#define DCACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT (4U) +#define DCACHE_CACHE_CTRL_CACHE_FLUSH_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT) /* 0x00000010 */ +#define DCACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT (5U) +#define DCACHE_CACHE_CTRL_CACHE_PMU_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT) /* 0x00000020 */ +#define DCACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT (6U) +#define DCACHE_CACHE_CTRL_CACHE_BYPASS_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT) /* 0x00000040 */ +#define DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT (7U) +#define DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK (0x1U << DCACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT) /* 0x00000080 */ +#define DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT (8U) +#define DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_MASK (0x7U << DCACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) /* 0x00000700 */ +#define DCACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT (12U) +#define DCACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT) /* 0x00001000 */ +#define DCACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT (13U) +#define DCACHE_CACHE_CTRL_CACHE_PF_EN_MASK (0x1U << DCACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT) /* 0x00002000 */ +/* CACHE_MAINTAIN0 */ +#define DCACHE_CACHE_MAINTAIN0_OFFSET (0x4U) +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT (0U) +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK (0x1U << DCACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT) /* 0x00000001 */ +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT (1U) +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_MASK (0x3U << DCACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT) /* 0x00000006 */ +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT (5U) +#define DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK (0x7FFFFFFU << DCACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT) /* 0xFFFFFFE0 */ +/* CACHE_MAINTAIN1 */ +#define DCACHE_CACHE_MAINTAIN1_OFFSET (0x8U) +#define DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT (0U) +#define DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_MASK (0xFFFFU << DCACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT) /* 0x0000FFFF */ +/* STB_TIMEOUT_CTRL */ +#define DCACHE_STB_TIMEOUT_CTRL_OFFSET (0xCU) +#define DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT (0U) +#define DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_MASK (0x7FFFFU << DCACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT) /* 0x0007FFFF */ +/* CACHE_INT_EN */ +#define DCACHE_CACHE_INT_EN_OFFSET (0x20U) +#define DCACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT (0U) +#define DCACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK (0x1U << DCACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT) /* 0x00000001 */ +/* CACHE_INT_ST */ +#define DCACHE_CACHE_INT_ST_OFFSET (0x24U) +#define DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT (0U) +#define DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK (0x1U << DCACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT) /* 0x00000001 */ +/* CACHE_ERR_HADDR */ +#define DCACHE_CACHE_ERR_HADDR_OFFSET (0x28U) +#define DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT (0U) +#define DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_MASK (0x1U << DCACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT) /* 0x00000001 */ +/* CACHE_STATUS */ +#define DCACHE_CACHE_STATUS_OFFSET (0x30U) +#define DCACHE_CACHE_STATUS (0x0U) +#define DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT (0U) +#define DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT) /* 0x00000001 */ +#define DCACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT (1U) +#define DCACHE_CACHE_STATUS_CACHE_M_BUSY_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT) /* 0x00000002 */ +#define DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT (2U) +#define DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_MASK (0x1U << DCACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT) /* 0x00000004 */ +/* PMU_RD_NUM_CNT */ +#define DCACHE_PMU_RD_NUM_CNT_OFFSET (0x40U) +#define DCACHE_PMU_RD_NUM_CNT (0x0U) +#define DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT (0U) +#define DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_NUM_CNT */ +#define DCACHE_PMU_WR_NUM_CNT_OFFSET (0x44U) +#define DCACHE_PMU_WR_NUM_CNT (0x0U) +#define DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT (0U) +#define DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_SRAM_RD_HIT_CNT */ +#define DCACHE_PMU_SRAM_RD_HIT_CNT_OFFSET (0x48U) +#define DCACHE_PMU_SRAM_RD_HIT_CNT (0x0U) +#define DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_HB_RD_HIT_CNT */ +#define DCACHE_PMU_HB_RD_HIT_CNT_OFFSET (0x4CU) +#define DCACHE_PMU_HB_RD_HIT_CNT (0x0U) +#define DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_STB_RD_HIT_CNT */ +#define DCACHE_PMU_STB_RD_HIT_CNT_OFFSET (0x50U) +#define DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_HIT_CNT */ +#define DCACHE_PMU_RD_HIT_CNT_OFFSET (0x54U) +#define DCACHE_PMU_RD_HIT_CNT (0x0U) +#define DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_HIT_CNT */ +#define DCACHE_PMU_WR_HIT_CNT_OFFSET (0x58U) +#define DCACHE_PMU_WR_HIT_CNT (0x0U) +#define DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT (0U) +#define DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_MISS_PENALTY_CNT */ +#define DCACHE_PMU_RD_MISS_PENALTY_CNT_OFFSET (0x5CU) +#define DCACHE_PMU_RD_MISS_PENALTY_CNT (0x0U) +#define DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT (0U) +#define DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_MISS_PENALTY_CNT */ +#define DCACHE_PMU_WR_MISS_PENALTY_CNT_OFFSET (0x60U) +#define DCACHE_PMU_WR_MISS_PENALTY_CNT (0x0U) +#define DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT (0U) +#define DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_LAT_CNT */ +#define DCACHE_PMU_RD_LAT_CNT_OFFSET (0x64U) +#define DCACHE_PMU_RD_LAT_CNT (0x0U) +#define DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) +#define DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_LAT_CNT */ +#define DCACHE_PMU_WR_LAT_CNT_OFFSET (0x68U) +#define DCACHE_PMU_WR_LAT_CNT (0x0U) +#define DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) +#define DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << DCACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* REVISION */ +#define DCACHE_REVISION_OFFSET (0xF0U) +#define DCACHE_REVISION_REVISION_SHIFT (0U) +#define DCACHE_REVISION_REVISION_MASK (0xFFFFFFFFU << DCACHE_REVISION_REVISION_SHIFT) /* 0xFFFFFFFF */ +/*****************************************ICACHE*****************************************/ +/* CACHE_CTRL */ +#define ICACHE_CACHE_CTRL_OFFSET (0x0U) +#define ICACHE_CACHE_CTRL_CACHE_EN_SHIFT (0U) +#define ICACHE_CACHE_CTRL_CACHE_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_EN_SHIFT) /* 0x00000001 */ +#define ICACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT (1U) +#define ICACHE_CACHE_CTRL_CACHE_WT_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_WT_EN_SHIFT) /* 0x00000002 */ +#define ICACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT (2U) +#define ICACHE_CACHE_CTRL_CACHE_HB_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_HB_EN_SHIFT) /* 0x00000004 */ +#define ICACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT (3U) +#define ICACHE_CACHE_CTRL_CACHE_STB_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_STB_EN_SHIFT) /* 0x00000008 */ +#define ICACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT (4U) +#define ICACHE_CACHE_CTRL_CACHE_FLUSH_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_FLUSH_SHIFT) /* 0x00000010 */ +#define ICACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT (5U) +#define ICACHE_CACHE_CTRL_CACHE_PMU_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_PMU_EN_SHIFT) /* 0x00000020 */ +#define ICACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT (6U) +#define ICACHE_CACHE_CTRL_CACHE_BYPASS_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_BYPASS_SHIFT) /* 0x00000040 */ +#define ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT (7U) +#define ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_MASK (0x1U << ICACHE_CACHE_CTRL_STB_TIMEOUT_EN_SHIFT) /* 0x00000080 */ +#define ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT (8U) +#define ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_MASK (0x7U << ICACHE_CACHE_CTRL_CACHE_ENTRY_THRESH_SHIFT) /* 0x00000700 */ +#define ICACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT (12U) +#define ICACHE_CACHE_CTRL_CACHE_MPU_MODE_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_MPU_MODE_SHIFT) /* 0x00001000 */ +#define ICACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT (13U) +#define ICACHE_CACHE_CTRL_CACHE_PF_EN_MASK (0x1U << ICACHE_CACHE_CTRL_CACHE_PF_EN_SHIFT) /* 0x00002000 */ +/* CACHE_MAINTAIN0 */ +#define ICACHE_CACHE_MAINTAIN0_OFFSET (0x4U) +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT (0U) +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_MASK (0x1U << ICACHE_CACHE_MAINTAIN0_CACHE_M_VALID_SHIFT) /* 0x00000001 */ +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT (1U) +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_MASK (0x3U << ICACHE_CACHE_MAINTAIN0_CACHE_M_CMD_SHIFT) /* 0x00000006 */ +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT (5U) +#define ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_MASK (0x7FFFFFFU << ICACHE_CACHE_MAINTAIN0_CACHE_M_ADDR_SHIFT) /* 0xFFFFFFE0 */ +/* CACHE_MAINTAIN1 */ +#define ICACHE_CACHE_MAINTAIN1_OFFSET (0x8U) +#define ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT (0U) +#define ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_MASK (0xFFFFU << ICACHE_CACHE_MAINTAIN1_CACHE_M_OFFSET_SHIFT) /* 0x0000FFFF */ +/* STB_TIMEOUT_CTRL */ +#define ICACHE_STB_TIMEOUT_CTRL_OFFSET (0xCU) +#define ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT (0U) +#define ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_MASK (0x7FFFFU << ICACHE_STB_TIMEOUT_CTRL_STB_TIMEOUT_VALUE_SHIFT) /* 0x0007FFFF */ +/* CACHE_INT_EN */ +#define ICACHE_CACHE_INT_EN_OFFSET (0x20U) +#define ICACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT (0U) +#define ICACHE_CACHE_INT_EN_ERR_RECORD_EN_MASK (0x1U << ICACHE_CACHE_INT_EN_ERR_RECORD_EN_SHIFT) /* 0x00000001 */ +/* CACHE_INT_ST */ +#define ICACHE_CACHE_INT_ST_OFFSET (0x24U) +#define ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT (0U) +#define ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_MASK (0x1U << ICACHE_CACHE_INT_ST_AHB_ERROR_STATUS_SHIFT) /* 0x00000001 */ +/* CACHE_ERR_HADDR */ +#define ICACHE_CACHE_ERR_HADDR_OFFSET (0x28U) +#define ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT (0U) +#define ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_MASK (0x1U << ICACHE_CACHE_ERR_HADDR_STATUS_HADDR_SHIFT) /* 0x00000001 */ +/* CACHE_STATUS */ +#define ICACHE_CACHE_STATUS_OFFSET (0x30U) +#define ICACHE_CACHE_STATUS (0x0U) +#define ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT (0U) +#define ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_INIT_FINISH_SHIFT) /* 0x00000001 */ +#define ICACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT (1U) +#define ICACHE_CACHE_STATUS_CACHE_M_BUSY_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_M_BUSY_SHIFT) /* 0x00000002 */ +#define ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT (2U) +#define ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_MASK (0x1U << ICACHE_CACHE_STATUS_CACHE_FLUSH_DONE_SHIFT) /* 0x00000004 */ +/* PMU_RD_NUM_CNT */ +#define ICACHE_PMU_RD_NUM_CNT_OFFSET (0x40U) +#define ICACHE_PMU_RD_NUM_CNT (0x0U) +#define ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT (0U) +#define ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_NUM_CNT_PMU_RD_NUM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_NUM_CNT */ +#define ICACHE_PMU_WR_NUM_CNT_OFFSET (0x44U) +#define ICACHE_PMU_WR_NUM_CNT (0x0U) +#define ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT (0U) +#define ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_NUM_CNT_PMU_WR_NUM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_SRAM_RD_HIT_CNT */ +#define ICACHE_PMU_SRAM_RD_HIT_CNT_OFFSET (0x48U) +#define ICACHE_PMU_SRAM_RD_HIT_CNT (0x0U) +#define ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_SRAM_RD_HIT_CNT_PMU_SRAM_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_HB_RD_HIT_CNT */ +#define ICACHE_PMU_HB_RD_HIT_CNT_OFFSET (0x4CU) +#define ICACHE_PMU_HB_RD_HIT_CNT (0x0U) +#define ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_HB_RD_HIT_CNT_PMU_HB_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_STB_RD_HIT_CNT */ +#define ICACHE_PMU_STB_RD_HIT_CNT_OFFSET (0x50U) +#define ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_STB_RD_HIT_CNT_PMU_STB_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_HIT_CNT */ +#define ICACHE_PMU_RD_HIT_CNT_OFFSET (0x54U) +#define ICACHE_PMU_RD_HIT_CNT (0x0U) +#define ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_HIT_CNT_PMU_RD_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_HIT_CNT */ +#define ICACHE_PMU_WR_HIT_CNT_OFFSET (0x58U) +#define ICACHE_PMU_WR_HIT_CNT (0x0U) +#define ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT (0U) +#define ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_HIT_CNT_PMU_WR_HIT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_MISS_PENALTY_CNT */ +#define ICACHE_PMU_RD_MISS_PENALTY_CNT_OFFSET (0x5CU) +#define ICACHE_PMU_RD_MISS_PENALTY_CNT (0x0U) +#define ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT (0U) +#define ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_MISS_PENALTY_CNT_PMU_RD_MISS_PENALTY_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_MISS_PENALTY_CNT */ +#define ICACHE_PMU_WR_MISS_PENALTY_CNT_OFFSET (0x60U) +#define ICACHE_PMU_WR_MISS_PENALTY_CNT (0x0U) +#define ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT (0U) +#define ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_MISS_PENALTY_CNT_PMU_WR_MISS_PENALTY_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_RD_LAT_CNT */ +#define ICACHE_PMU_RD_LAT_CNT_OFFSET (0x64U) +#define ICACHE_PMU_RD_LAT_CNT (0x0U) +#define ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) +#define ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_RD_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* PMU_WR_LAT_CNT */ +#define ICACHE_PMU_WR_LAT_CNT_OFFSET (0x68U) +#define ICACHE_PMU_WR_LAT_CNT (0x0U) +#define ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT (0U) +#define ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_MASK (0xFFFFFFFFU << ICACHE_PMU_WR_LAT_CNT_PMU_RD_LAT_CNT_SHIFT) /* 0xFFFFFFFF */ +/* REVISION */ +#define ICACHE_REVISION_OFFSET (0xF0U) +#define ICACHE_REVISION_REVISION_SHIFT (0U) +#define ICACHE_REVISION_REVISION_MASK (0xFFFFFFFFU << ICACHE_REVISION_REVISION_SHIFT) /* 0xFFFFFFFF */ +/****************************************PMU1_IOC****************************************/ +/* GPIO0A_IOMUX_SEL_L */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_OFFSET (0x0U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A0_SEL_SHIFT (0U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A0_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A0_SEL_SHIFT) /* 0x0000000F */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A1_SEL_SHIFT (4U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A1_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A1_SEL_SHIFT) /* 0x000000F0 */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A2_SEL_SHIFT (8U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A2_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A2_SEL_SHIFT) /* 0x00000F00 */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A3_SEL_SHIFT (12U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A3_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_L_GPIO0A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0A_IOMUX_SEL_H */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_OFFSET (0x4U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A4_SEL_SHIFT (0U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A4_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A4_SEL_SHIFT) /* 0x0000000F */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A5_SEL_SHIFT (4U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A5_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A5_SEL_SHIFT) /* 0x000000F0 */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A6_SEL_SHIFT (8U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A6_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A6_SEL_SHIFT) /* 0x00000F00 */ +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A7_SEL_SHIFT (12U) +#define PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A7_SEL_MASK (0xFU << PMU1_IOC_GPIO0A_IOMUX_SEL_H_GPIO0A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0B_IOMUX_SEL_L */ +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_OFFSET (0x8U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B0_SEL_SHIFT (0U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B0_SEL_MASK (0xFU << PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B0_SEL_SHIFT) /* 0x0000000F */ +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B1_SEL_SHIFT (4U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B1_SEL_MASK (0xFU << PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B1_SEL_SHIFT) /* 0x000000F0 */ +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B2_SEL_SHIFT (8U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B2_SEL_MASK (0xFU << PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B2_SEL_SHIFT) /* 0x00000F00 */ +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B3_SEL_SHIFT (12U) +#define PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B3_SEL_MASK (0xFU << PMU1_IOC_GPIO0B_IOMUX_SEL_L_GPIO0B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0A_DS_L */ +#define PMU1_IOC_GPIO0A_DS_L_OFFSET (0x10U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A0_DS_SHIFT (0U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A0_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_L_GPIO0A0_DS_SHIFT) /* 0x00000003 */ +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A1_DS_SHIFT (4U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A1_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_L_GPIO0A1_DS_SHIFT) /* 0x00000030 */ +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A2_DS_SHIFT (8U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A2_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_L_GPIO0A2_DS_SHIFT) /* 0x00000300 */ +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A3_DS_SHIFT (12U) +#define PMU1_IOC_GPIO0A_DS_L_GPIO0A3_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_L_GPIO0A3_DS_SHIFT) /* 0x00003000 */ +/* GPIO0A_DS_H */ +#define PMU1_IOC_GPIO0A_DS_H_OFFSET (0x14U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A4_DS_SHIFT (0U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A4_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_H_GPIO0A4_DS_SHIFT) /* 0x00000003 */ +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A5_DS_SHIFT (4U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A5_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_H_GPIO0A5_DS_SHIFT) /* 0x00000030 */ +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A6_DS_SHIFT (8U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A6_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_H_GPIO0A6_DS_SHIFT) /* 0x00000300 */ +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A7_DS_SHIFT (12U) +#define PMU1_IOC_GPIO0A_DS_H_GPIO0A7_DS_MASK (0x3U << PMU1_IOC_GPIO0A_DS_H_GPIO0A7_DS_SHIFT) /* 0x00003000 */ +/* GPIO0B_DS_L */ +#define PMU1_IOC_GPIO0B_DS_L_OFFSET (0x18U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B0_DS_SHIFT (0U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B0_DS_MASK (0x3U << PMU1_IOC_GPIO0B_DS_L_GPIO0B0_DS_SHIFT) /* 0x00000003 */ +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B1_DS_SHIFT (4U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B1_DS_MASK (0x3U << PMU1_IOC_GPIO0B_DS_L_GPIO0B1_DS_SHIFT) /* 0x00000030 */ +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B2_DS_SHIFT (8U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B2_DS_MASK (0x3U << PMU1_IOC_GPIO0B_DS_L_GPIO0B2_DS_SHIFT) /* 0x00000300 */ +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B3_DS_SHIFT (12U) +#define PMU1_IOC_GPIO0B_DS_L_GPIO0B3_DS_MASK (0x3U << PMU1_IOC_GPIO0B_DS_L_GPIO0B3_DS_SHIFT) /* 0x00003000 */ +/* GPIO0A_P */ +#define PMU1_IOC_GPIO0A_P_OFFSET (0x20U) +#define PMU1_IOC_GPIO0A_P_GPIO0A0_PE_SHIFT (0U) +#define PMU1_IOC_GPIO0A_P_GPIO0A0_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A0_PE_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A0_PS_SHIFT (1U) +#define PMU1_IOC_GPIO0A_P_GPIO0A0_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A0_PS_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A1_PE_SHIFT (2U) +#define PMU1_IOC_GPIO0A_P_GPIO0A1_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A1_PE_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A1_PS_SHIFT (3U) +#define PMU1_IOC_GPIO0A_P_GPIO0A1_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A1_PS_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A2_PE_SHIFT (4U) +#define PMU1_IOC_GPIO0A_P_GPIO0A2_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A2_PE_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A2_PS_SHIFT (5U) +#define PMU1_IOC_GPIO0A_P_GPIO0A2_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A2_PS_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A3_PE_SHIFT (6U) +#define PMU1_IOC_GPIO0A_P_GPIO0A3_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A3_PE_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A3_PS_SHIFT (7U) +#define PMU1_IOC_GPIO0A_P_GPIO0A3_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A3_PS_SHIFT) /* 0x00000080 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A4_PE_SHIFT (8U) +#define PMU1_IOC_GPIO0A_P_GPIO0A4_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A4_PE_SHIFT) /* 0x00000100 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A4_PS_SHIFT (9U) +#define PMU1_IOC_GPIO0A_P_GPIO0A4_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A4_PS_SHIFT) /* 0x00000200 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A5_PE_SHIFT (10U) +#define PMU1_IOC_GPIO0A_P_GPIO0A5_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A5_PE_SHIFT) /* 0x00000400 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A5_PS_SHIFT (11U) +#define PMU1_IOC_GPIO0A_P_GPIO0A5_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A5_PS_SHIFT) /* 0x00000800 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A6_PE_SHIFT (12U) +#define PMU1_IOC_GPIO0A_P_GPIO0A6_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A6_PE_SHIFT) /* 0x00001000 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A6_PS_SHIFT (13U) +#define PMU1_IOC_GPIO0A_P_GPIO0A6_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A6_PS_SHIFT) /* 0x00002000 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A7_PE_SHIFT (14U) +#define PMU1_IOC_GPIO0A_P_GPIO0A7_PE_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A7_PE_SHIFT) /* 0x00004000 */ +#define PMU1_IOC_GPIO0A_P_GPIO0A7_PS_SHIFT (15U) +#define PMU1_IOC_GPIO0A_P_GPIO0A7_PS_MASK (0x1U << PMU1_IOC_GPIO0A_P_GPIO0A7_PS_SHIFT) /* 0x00008000 */ +/* GPIO0B_P */ +#define PMU1_IOC_GPIO0B_P_OFFSET (0x24U) +#define PMU1_IOC_GPIO0B_P_GPIO0B0_PE_SHIFT (0U) +#define PMU1_IOC_GPIO0B_P_GPIO0B0_PE_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B0_PE_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B0_PS_SHIFT (1U) +#define PMU1_IOC_GPIO0B_P_GPIO0B0_PS_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B0_PS_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B1_PE_SHIFT (2U) +#define PMU1_IOC_GPIO0B_P_GPIO0B1_PE_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B1_PE_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B1_PS_SHIFT (3U) +#define PMU1_IOC_GPIO0B_P_GPIO0B1_PS_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B1_PS_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B2_PE_SHIFT (4U) +#define PMU1_IOC_GPIO0B_P_GPIO0B2_PE_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B2_PE_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B2_PS_SHIFT (5U) +#define PMU1_IOC_GPIO0B_P_GPIO0B2_PS_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B2_PS_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B3_PE_SHIFT (6U) +#define PMU1_IOC_GPIO0B_P_GPIO0B3_PE_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B3_PE_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0B_P_GPIO0B3_PS_SHIFT (7U) +#define PMU1_IOC_GPIO0B_P_GPIO0B3_PS_MASK (0x1U << PMU1_IOC_GPIO0B_P_GPIO0B3_PS_SHIFT) /* 0x00000080 */ +/* GPIO0A_IE */ +#define PMU1_IOC_GPIO0A_IE_OFFSET (0x28U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A0_IE_SHIFT (0U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A0_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A0_IE_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A1_IE_SHIFT (1U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A1_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A1_IE_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A2_IE_SHIFT (2U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A2_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A2_IE_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A3_IE_SHIFT (3U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A3_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A3_IE_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A4_IE_SHIFT (4U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A4_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A4_IE_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A5_IE_SHIFT (5U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A5_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A5_IE_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A6_IE_SHIFT (6U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A6_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A6_IE_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0A_IE_GPIO0A7_IE_SHIFT (7U) +#define PMU1_IOC_GPIO0A_IE_GPIO0A7_IE_MASK (0x1U << PMU1_IOC_GPIO0A_IE_GPIO0A7_IE_SHIFT) /* 0x00000080 */ +/* GPIO0B_IE */ +#define PMU1_IOC_GPIO0B_IE_OFFSET (0x2CU) +#define PMU1_IOC_GPIO0B_IE_GPIO0B0_IE_SHIFT (0U) +#define PMU1_IOC_GPIO0B_IE_GPIO0B0_IE_MASK (0x1U << PMU1_IOC_GPIO0B_IE_GPIO0B0_IE_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0B_IE_GPIO0B1_IE_SHIFT (1U) +#define PMU1_IOC_GPIO0B_IE_GPIO0B1_IE_MASK (0x1U << PMU1_IOC_GPIO0B_IE_GPIO0B1_IE_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0B_IE_GPIO0B2_IE_SHIFT (2U) +#define PMU1_IOC_GPIO0B_IE_GPIO0B2_IE_MASK (0x1U << PMU1_IOC_GPIO0B_IE_GPIO0B2_IE_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0B_IE_GPIO0B3_IE_SHIFT (3U) +#define PMU1_IOC_GPIO0B_IE_GPIO0B3_IE_MASK (0x1U << PMU1_IOC_GPIO0B_IE_GPIO0B3_IE_SHIFT) /* 0x00000008 */ +/* GPIO0A_SMT */ +#define PMU1_IOC_GPIO0A_SMT_OFFSET (0x30U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A0_SMT_SHIFT (0U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A0_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A0_SMT_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A1_SMT_SHIFT (1U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A1_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A1_SMT_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A2_SMT_SHIFT (2U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A2_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A2_SMT_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A3_SMT_SHIFT (3U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A3_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A3_SMT_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A4_SMT_SHIFT (4U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A4_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A4_SMT_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A5_SMT_SHIFT (5U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A5_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A5_SMT_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A6_SMT_SHIFT (6U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A6_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A6_SMT_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0A_SMT_GPIO0A7_SMT_SHIFT (7U) +#define PMU1_IOC_GPIO0A_SMT_GPIO0A7_SMT_MASK (0x1U << PMU1_IOC_GPIO0A_SMT_GPIO0A7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO0B_SMT */ +#define PMU1_IOC_GPIO0B_SMT_OFFSET (0x34U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B0_SMT_SHIFT (0U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B0_SMT_MASK (0x1U << PMU1_IOC_GPIO0B_SMT_GPIO0B0_SMT_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0B_SMT_GPIO0B1_SMT_SHIFT (1U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B1_SMT_MASK (0x1U << PMU1_IOC_GPIO0B_SMT_GPIO0B1_SMT_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0B_SMT_GPIO0B2_SMT_SHIFT (2U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B2_SMT_MASK (0x1U << PMU1_IOC_GPIO0B_SMT_GPIO0B2_SMT_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0B_SMT_GPIO0B3_SMT_SHIFT (3U) +#define PMU1_IOC_GPIO0B_SMT_GPIO0B3_SMT_MASK (0x1U << PMU1_IOC_GPIO0B_SMT_GPIO0B3_SMT_SHIFT) /* 0x00000008 */ +/* GPIO0A_PDIS */ +#define PMU1_IOC_GPIO0A_PDIS_OFFSET (0x38U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A0_PULL_DIS_SHIFT (0U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A0_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A0_PULL_DIS_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A1_PULL_DIS_SHIFT (1U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A1_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A1_PULL_DIS_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A2_PULL_DIS_SHIFT (2U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A2_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A2_PULL_DIS_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A3_PULL_DIS_SHIFT (3U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A3_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A3_PULL_DIS_SHIFT) /* 0x00000008 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A4_PULL_DIS_SHIFT (4U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A4_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A4_PULL_DIS_SHIFT) /* 0x00000010 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A5_PULL_DIS_SHIFT (5U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A5_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A5_PULL_DIS_SHIFT) /* 0x00000020 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A6_PULL_DIS_SHIFT (6U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A6_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A6_PULL_DIS_SHIFT) /* 0x00000040 */ +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A7_PULL_DIS_SHIFT (7U) +#define PMU1_IOC_GPIO0A_PDIS_GPIO0A7_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0A_PDIS_GPIO0A7_PULL_DIS_SHIFT) /* 0x00000080 */ +/* GPIO0B_PDIS */ +#define PMU1_IOC_GPIO0B_PDIS_OFFSET (0x3CU) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B0_PULL_DIS_SHIFT (0U) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B0_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0B_PDIS_GPIO0B0_PULL_DIS_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B1_PULL_DIS_SHIFT (1U) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B1_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0B_PDIS_GPIO0B1_PULL_DIS_SHIFT) /* 0x00000002 */ +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B2_PULL_DIS_SHIFT (2U) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B2_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0B_PDIS_GPIO0B2_PULL_DIS_SHIFT) /* 0x00000004 */ +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B3_PULL_DIS_SHIFT (3U) +#define PMU1_IOC_GPIO0B_PDIS_GPIO0B3_PULL_DIS_MASK (0x1U << PMU1_IOC_GPIO0B_PDIS_GPIO0B3_PULL_DIS_SHIFT) /* 0x00000008 */ +/* XIN_CON */ +#define PMU1_IOC_XIN_CON_OFFSET (0x40U) +#define PMU1_IOC_XIN_CON_XIN_OSC_EN_SHIFT (0U) +#define PMU1_IOC_XIN_CON_XIN_OSC_EN_MASK (0x1U << PMU1_IOC_XIN_CON_XIN_OSC_EN_SHIFT) /* 0x00000001 */ +#define PMU1_IOC_XIN_CON_XIN_OSC_SF_SHIFT (2U) +#define PMU1_IOC_XIN_CON_XIN_OSC_SF_MASK (0x3U << PMU1_IOC_XIN_CON_XIN_OSC_SF_SHIFT) /* 0x0000000C */ +/****************************************PMU2_IOC****************************************/ +/* GPIO0B_IOMUX_SEL_H */ +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_OFFSET (0x0U) +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_MASK (0xFU << PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_MASK (0xFU << PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_SHIFT) /* 0x00000F00 */ +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_SHIFT (12U) +#define PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_MASK (0xFU << PMU2_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0C_IOMUX_SEL_L */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_OFFSET (0x4U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_SHIFT (0U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_SHIFT) /* 0x0000000F */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C1_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C1_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C1_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C2_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C2_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C2_SEL_SHIFT) /* 0x00000F00 */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C3_SEL_SHIFT (12U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C3_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0C_IOMUX_SEL_H */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_OFFSET (0x8U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_SHIFT (0U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_SHIFT) /* 0x0000000F */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_SHIFT) /* 0x00000F00 */ +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_SHIFT (12U) +#define PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_MASK (0xFU << PMU2_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_SEL_L */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_OFFSET (0xCU) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_SHIFT (0U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_SHIFT) /* 0x0000000F */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_SHIFT) /* 0x00000F00 */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_SHIFT (12U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_SEL_H */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_OFFSET (0x10U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_SHIFT (0U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_SHIFT) /* 0x0000000F */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_SHIFT (4U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_SHIFT) /* 0x000000F0 */ +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D6_SEL_SHIFT (8U) +#define PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D6_SEL_MASK (0xFU << PMU2_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D6_SEL_SHIFT) /* 0x00000F00 */ +/* GPIO0B_DS_H */ +#define PMU2_IOC_GPIO0B_DS_H_OFFSET (0x14U) +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B5_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B5_DS_MASK (0x7U << PMU2_IOC_GPIO0B_DS_H_GPIO0B5_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B6_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B6_DS_MASK (0x7U << PMU2_IOC_GPIO0B_DS_H_GPIO0B6_DS_SHIFT) /* 0x00000700 */ +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B7_DS_SHIFT (12U) +#define PMU2_IOC_GPIO0B_DS_H_GPIO0B7_DS_MASK (0x7U << PMU2_IOC_GPIO0B_DS_H_GPIO0B7_DS_SHIFT) /* 0x00007000 */ +/* GPIO0C_DS_L */ +#define PMU2_IOC_GPIO0C_DS_L_OFFSET (0x18U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C0_DS_SHIFT (0U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C0_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_L_GPIO0C0_DS_SHIFT) /* 0x00000007 */ +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C1_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C1_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_L_GPIO0C1_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C2_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C2_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_L_GPIO0C2_DS_SHIFT) /* 0x00000700 */ +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C3_DS_SHIFT (12U) +#define PMU2_IOC_GPIO0C_DS_L_GPIO0C3_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_L_GPIO0C3_DS_SHIFT) /* 0x00007000 */ +/* GPIO0C_DS_H */ +#define PMU2_IOC_GPIO0C_DS_H_OFFSET (0x1CU) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C4_DS_SHIFT (0U) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C4_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_H_GPIO0C4_DS_SHIFT) /* 0x00000007 */ +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C5_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C5_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_H_GPIO0C5_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C6_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C6_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_H_GPIO0C6_DS_SHIFT) /* 0x00000700 */ +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C7_DS_SHIFT (12U) +#define PMU2_IOC_GPIO0C_DS_H_GPIO0C7_DS_MASK (0x7U << PMU2_IOC_GPIO0C_DS_H_GPIO0C7_DS_SHIFT) /* 0x00007000 */ +/* GPIO0D_DS_L */ +#define PMU2_IOC_GPIO0D_DS_L_OFFSET (0x20U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D0_DS_SHIFT (0U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D0_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_L_GPIO0D0_DS_SHIFT) /* 0x00000007 */ +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D1_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D1_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_L_GPIO0D1_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D2_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D2_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_L_GPIO0D2_DS_SHIFT) /* 0x00000700 */ +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D3_DS_SHIFT (12U) +#define PMU2_IOC_GPIO0D_DS_L_GPIO0D3_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_L_GPIO0D3_DS_SHIFT) /* 0x00007000 */ +/* GPIO0D_DS_H */ +#define PMU2_IOC_GPIO0D_DS_H_OFFSET (0x24U) +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D4_DS_SHIFT (0U) +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D4_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_H_GPIO0D4_DS_SHIFT) /* 0x00000007 */ +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D5_DS_SHIFT (4U) +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D5_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_H_GPIO0D5_DS_SHIFT) /* 0x00000070 */ +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D6_DS_SHIFT (8U) +#define PMU2_IOC_GPIO0D_DS_H_GPIO0D6_DS_MASK (0x7U << PMU2_IOC_GPIO0D_DS_H_GPIO0D6_DS_SHIFT) /* 0x00000700 */ +/* GPIO0B_P */ +#define PMU2_IOC_GPIO0B_P_OFFSET (0x28U) +#define PMU2_IOC_GPIO0B_P_GPIO0B5_PE_SHIFT (10U) +#define PMU2_IOC_GPIO0B_P_GPIO0B5_PE_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B5_PE_SHIFT) /* 0x00000400 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B5_PS_SHIFT (11U) +#define PMU2_IOC_GPIO0B_P_GPIO0B5_PS_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B5_PS_SHIFT) /* 0x00000800 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B6_PE_SHIFT (12U) +#define PMU2_IOC_GPIO0B_P_GPIO0B6_PE_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B6_PE_SHIFT) /* 0x00001000 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B6_PS_SHIFT (13U) +#define PMU2_IOC_GPIO0B_P_GPIO0B6_PS_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B6_PS_SHIFT) /* 0x00002000 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B7_PE_SHIFT (14U) +#define PMU2_IOC_GPIO0B_P_GPIO0B7_PE_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B7_PE_SHIFT) /* 0x00004000 */ +#define PMU2_IOC_GPIO0B_P_GPIO0B7_PS_SHIFT (15U) +#define PMU2_IOC_GPIO0B_P_GPIO0B7_PS_MASK (0x1U << PMU2_IOC_GPIO0B_P_GPIO0B7_PS_SHIFT) /* 0x00008000 */ +/* GPIO0C_P */ +#define PMU2_IOC_GPIO0C_P_OFFSET (0x2CU) +#define PMU2_IOC_GPIO0C_P_GPIO0C0_PE_SHIFT (0U) +#define PMU2_IOC_GPIO0C_P_GPIO0C0_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C0_PE_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C0_PS_SHIFT (1U) +#define PMU2_IOC_GPIO0C_P_GPIO0C0_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C0_PS_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C1_PE_SHIFT (2U) +#define PMU2_IOC_GPIO0C_P_GPIO0C1_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C1_PE_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C1_PS_SHIFT (3U) +#define PMU2_IOC_GPIO0C_P_GPIO0C1_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C1_PS_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C2_PE_SHIFT (4U) +#define PMU2_IOC_GPIO0C_P_GPIO0C2_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C2_PE_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C2_PS_SHIFT (5U) +#define PMU2_IOC_GPIO0C_P_GPIO0C2_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C2_PS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C3_PE_SHIFT (6U) +#define PMU2_IOC_GPIO0C_P_GPIO0C3_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C3_PE_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C3_PS_SHIFT (7U) +#define PMU2_IOC_GPIO0C_P_GPIO0C3_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C3_PS_SHIFT) /* 0x00000080 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C4_PE_SHIFT (8U) +#define PMU2_IOC_GPIO0C_P_GPIO0C4_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C4_PE_SHIFT) /* 0x00000100 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C4_PS_SHIFT (9U) +#define PMU2_IOC_GPIO0C_P_GPIO0C4_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C4_PS_SHIFT) /* 0x00000200 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C5_PE_SHIFT (10U) +#define PMU2_IOC_GPIO0C_P_GPIO0C5_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C5_PE_SHIFT) /* 0x00000400 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C5_PS_SHIFT (11U) +#define PMU2_IOC_GPIO0C_P_GPIO0C5_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C5_PS_SHIFT) /* 0x00000800 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C6_PE_SHIFT (12U) +#define PMU2_IOC_GPIO0C_P_GPIO0C6_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C6_PE_SHIFT) /* 0x00001000 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C6_PS_SHIFT (13U) +#define PMU2_IOC_GPIO0C_P_GPIO0C6_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C6_PS_SHIFT) /* 0x00002000 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C7_PE_SHIFT (14U) +#define PMU2_IOC_GPIO0C_P_GPIO0C7_PE_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C7_PE_SHIFT) /* 0x00004000 */ +#define PMU2_IOC_GPIO0C_P_GPIO0C7_PS_SHIFT (15U) +#define PMU2_IOC_GPIO0C_P_GPIO0C7_PS_MASK (0x1U << PMU2_IOC_GPIO0C_P_GPIO0C7_PS_SHIFT) /* 0x00008000 */ +/* GPIO0D_P */ +#define PMU2_IOC_GPIO0D_P_OFFSET (0x30U) +#define PMU2_IOC_GPIO0D_P_GPIO0D0_PE_SHIFT (0U) +#define PMU2_IOC_GPIO0D_P_GPIO0D0_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D0_PE_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D0_PS_SHIFT (1U) +#define PMU2_IOC_GPIO0D_P_GPIO0D0_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D0_PS_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D1_PE_SHIFT (2U) +#define PMU2_IOC_GPIO0D_P_GPIO0D1_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D1_PE_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D1_PS_SHIFT (3U) +#define PMU2_IOC_GPIO0D_P_GPIO0D1_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D1_PS_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D2_PE_SHIFT (4U) +#define PMU2_IOC_GPIO0D_P_GPIO0D2_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D2_PE_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D2_PS_SHIFT (5U) +#define PMU2_IOC_GPIO0D_P_GPIO0D2_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D2_PS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D3_PE_SHIFT (6U) +#define PMU2_IOC_GPIO0D_P_GPIO0D3_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D3_PE_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D3_PS_SHIFT (7U) +#define PMU2_IOC_GPIO0D_P_GPIO0D3_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D3_PS_SHIFT) /* 0x00000080 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D4_PE_SHIFT (8U) +#define PMU2_IOC_GPIO0D_P_GPIO0D4_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D4_PE_SHIFT) /* 0x00000100 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D4_PS_SHIFT (9U) +#define PMU2_IOC_GPIO0D_P_GPIO0D4_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D4_PS_SHIFT) /* 0x00000200 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D5_PE_SHIFT (10U) +#define PMU2_IOC_GPIO0D_P_GPIO0D5_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D5_PE_SHIFT) /* 0x00000400 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D5_PS_SHIFT (11U) +#define PMU2_IOC_GPIO0D_P_GPIO0D5_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D5_PS_SHIFT) /* 0x00000800 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D6_PE_SHIFT (12U) +#define PMU2_IOC_GPIO0D_P_GPIO0D6_PE_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D6_PE_SHIFT) /* 0x00001000 */ +#define PMU2_IOC_GPIO0D_P_GPIO0D6_PS_SHIFT (13U) +#define PMU2_IOC_GPIO0D_P_GPIO0D6_PS_MASK (0x1U << PMU2_IOC_GPIO0D_P_GPIO0D6_PS_SHIFT) /* 0x00002000 */ +/* GPIO0B_IE */ +#define PMU2_IOC_GPIO0B_IE_OFFSET (0x34U) +#define PMU2_IOC_GPIO0B_IE_GPIO0B5_IE_SHIFT (5U) +#define PMU2_IOC_GPIO0B_IE_GPIO0B5_IE_MASK (0x1U << PMU2_IOC_GPIO0B_IE_GPIO0B5_IE_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0B_IE_GPIO0B6_IE_SHIFT (6U) +#define PMU2_IOC_GPIO0B_IE_GPIO0B6_IE_MASK (0x1U << PMU2_IOC_GPIO0B_IE_GPIO0B6_IE_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0B_IE_GPIO0B7_IE_SHIFT (7U) +#define PMU2_IOC_GPIO0B_IE_GPIO0B7_IE_MASK (0x1U << PMU2_IOC_GPIO0B_IE_GPIO0B7_IE_SHIFT) /* 0x00000080 */ +/* GPIO0C_IE */ +#define PMU2_IOC_GPIO0C_IE_OFFSET (0x38U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C0_IE_SHIFT (0U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C0_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C0_IE_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C1_IE_SHIFT (1U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C1_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C1_IE_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C2_IE_SHIFT (2U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C2_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C2_IE_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C3_IE_SHIFT (3U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C3_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C3_IE_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C4_IE_SHIFT (4U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C4_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C4_IE_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C5_IE_SHIFT (5U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C5_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C5_IE_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C6_IE_SHIFT (6U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C6_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C6_IE_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0C_IE_GPIO0C7_IE_SHIFT (7U) +#define PMU2_IOC_GPIO0C_IE_GPIO0C7_IE_MASK (0x1U << PMU2_IOC_GPIO0C_IE_GPIO0C7_IE_SHIFT) /* 0x00000080 */ +/* GPIO0D_IE */ +#define PMU2_IOC_GPIO0D_IE_OFFSET (0x3CU) +#define PMU2_IOC_GPIO0D_IE_GPIO0D0_IE_SHIFT (0U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D0_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D0_IE_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D1_IE_SHIFT (1U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D1_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D1_IE_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D2_IE_SHIFT (2U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D2_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D2_IE_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D3_IE_SHIFT (3U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D3_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D3_IE_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D4_IE_SHIFT (4U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D4_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D4_IE_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D5_IE_SHIFT (5U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D5_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D5_IE_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0D_IE_GPIO0D6_IE_SHIFT (6U) +#define PMU2_IOC_GPIO0D_IE_GPIO0D6_IE_MASK (0x1U << PMU2_IOC_GPIO0D_IE_GPIO0D6_IE_SHIFT) /* 0x00000040 */ +/* GPIO0B_SMT */ +#define PMU2_IOC_GPIO0B_SMT_OFFSET (0x40U) +#define PMU2_IOC_GPIO0B_SMT_GPIO0B5_SMT_SHIFT (5U) +#define PMU2_IOC_GPIO0B_SMT_GPIO0B5_SMT_MASK (0x1U << PMU2_IOC_GPIO0B_SMT_GPIO0B5_SMT_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0B_SMT_GPIO0B6_SMT_SHIFT (6U) +#define PMU2_IOC_GPIO0B_SMT_GPIO0B6_SMT_MASK (0x1U << PMU2_IOC_GPIO0B_SMT_GPIO0B6_SMT_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0B_SMT_GPIO0B7_SMT_SHIFT (7U) +#define PMU2_IOC_GPIO0B_SMT_GPIO0B7_SMT_MASK (0x1U << PMU2_IOC_GPIO0B_SMT_GPIO0B7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO0C_SMT */ +#define PMU2_IOC_GPIO0C_SMT_OFFSET (0x44U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C0_SMT_SHIFT (0U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C0_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C0_SMT_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C1_SMT_SHIFT (1U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C1_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C1_SMT_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C2_SMT_SHIFT (2U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C2_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C2_SMT_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C3_SMT_SHIFT (3U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C3_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C3_SMT_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C4_SMT_SHIFT (4U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C4_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C4_SMT_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C5_SMT_SHIFT (5U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C5_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C5_SMT_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C6_SMT_SHIFT (6U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C6_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C6_SMT_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0C_SMT_GPIO0C7_SMT_SHIFT (7U) +#define PMU2_IOC_GPIO0C_SMT_GPIO0C7_SMT_MASK (0x1U << PMU2_IOC_GPIO0C_SMT_GPIO0C7_SMT_SHIFT) /* 0x00000080 */ +/* GPIO0D_SMT */ +#define PMU2_IOC_GPIO0D_SMT_OFFSET (0x48U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D0_SMT_SHIFT (0U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D0_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D0_SMT_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D1_SMT_SHIFT (1U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D1_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D1_SMT_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D2_SMT_SHIFT (2U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D2_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D2_SMT_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D3_SMT_SHIFT (3U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D3_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D3_SMT_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D4_SMT_SHIFT (4U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D4_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D4_SMT_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D5_SMT_SHIFT (5U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D5_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D5_SMT_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0D_SMT_GPIO0D6_SMT_SHIFT (6U) +#define PMU2_IOC_GPIO0D_SMT_GPIO0D6_SMT_MASK (0x1U << PMU2_IOC_GPIO0D_SMT_GPIO0D6_SMT_SHIFT) /* 0x00000040 */ +/* GPIO0B_PDIS */ +#define PMU2_IOC_GPIO0B_PDIS_OFFSET (0x4CU) +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B5_PULL_DIS_SHIFT (5U) +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B5_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0B_PDIS_GPIO0B5_PULL_DIS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B6_PULL_DIS_SHIFT (6U) +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B6_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0B_PDIS_GPIO0B6_PULL_DIS_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B7_PULL_DIS_SHIFT (7U) +#define PMU2_IOC_GPIO0B_PDIS_GPIO0B7_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0B_PDIS_GPIO0B7_PULL_DIS_SHIFT) /* 0x00000080 */ +/* GPIO0C_PDIS */ +#define PMU2_IOC_GPIO0C_PDIS_OFFSET (0x50U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C0_PULL_DIS_SHIFT (0U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C0_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C0_PULL_DIS_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C1_PULL_DIS_SHIFT (1U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C1_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C1_PULL_DIS_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C2_PULL_DIS_SHIFT (2U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C2_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C2_PULL_DIS_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C3_PULL_DIS_SHIFT (3U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C3_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C3_PULL_DIS_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C4_PULL_DIS_SHIFT (4U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C4_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C4_PULL_DIS_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C5_PULL_DIS_SHIFT (5U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C5_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C5_PULL_DIS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C6_PULL_DIS_SHIFT (6U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C6_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C6_PULL_DIS_SHIFT) /* 0x00000040 */ +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C7_PULL_DIS_SHIFT (7U) +#define PMU2_IOC_GPIO0C_PDIS_GPIO0C7_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0C_PDIS_GPIO0C7_PULL_DIS_SHIFT) /* 0x00000080 */ +/* GPIO0D_PDIS */ +#define PMU2_IOC_GPIO0D_PDIS_OFFSET (0x54U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D0_PULL_DIS_SHIFT (0U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D0_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D0_PULL_DIS_SHIFT) /* 0x00000001 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D1_PULL_DIS_SHIFT (1U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D1_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D1_PULL_DIS_SHIFT) /* 0x00000002 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D2_PULL_DIS_SHIFT (2U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D2_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D2_PULL_DIS_SHIFT) /* 0x00000004 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D3_PULL_DIS_SHIFT (3U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D3_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D3_PULL_DIS_SHIFT) /* 0x00000008 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D4_PULL_DIS_SHIFT (4U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D4_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D4_PULL_DIS_SHIFT) /* 0x00000010 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D5_PULL_DIS_SHIFT (5U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D5_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D5_PULL_DIS_SHIFT) /* 0x00000020 */ +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D6_PULL_DIS_SHIFT (6U) +#define PMU2_IOC_GPIO0D_PDIS_GPIO0D6_PULL_DIS_MASK (0x1U << PMU2_IOC_GPIO0D_PDIS_GPIO0D6_PULL_DIS_SHIFT) /* 0x00000040 */ +/****************************************BUS_IOC*****************************************/ +/* GPIO0B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_OFFSET (0xCU) +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_MASK (0xFU << BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_MASK (0xFU << BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_MASK (0xFU << BUS_IOC_GPIO0B_IOMUX_SEL_H_GPIO0B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_L_OFFSET (0x10U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_L_GPIO0C0_SEL_SHIFT) /* 0x0000000F */ +/* GPIO0C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_OFFSET (0x14U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_MASK (0xFU << BUS_IOC_GPIO0C_IOMUX_SEL_H_GPIO0C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_OFFSET (0x18U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_L_GPIO0D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO0D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_OFFSET (0x1CU) +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_MASK (0xFU << BUS_IOC_GPIO0D_IOMUX_SEL_H_GPIO0D5_SEL_SHIFT) /* 0x000000F0 */ +/* GPIO1A_IOMUX_SEL_L */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_OFFSET (0x20U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A0_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A1_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A2_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A3_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_L_GPIO1A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1A_IOMUX_SEL_H */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_OFFSET (0x24U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A4_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A5_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A6_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A7_SEL_MASK (0xFU << BUS_IOC_GPIO1A_IOMUX_SEL_H_GPIO1A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1B_IOMUX_SEL_L */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_OFFSET (0x28U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B0_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B1_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B2_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B3_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_L_GPIO1B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_OFFSET (0x2CU) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B4_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B5_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B6_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B7_SEL_MASK (0xFU << BUS_IOC_GPIO1B_IOMUX_SEL_H_GPIO1B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_OFFSET (0x30U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C0_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C1_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C2_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C3_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_L_GPIO1C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_OFFSET (0x34U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C4_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C5_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C6_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C7_SEL_MASK (0xFU << BUS_IOC_GPIO1C_IOMUX_SEL_H_GPIO1C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_OFFSET (0x38U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D0_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D1_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D2_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D3_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_L_GPIO1D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO1D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_OFFSET (0x3CU) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D4_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D5_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D6_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D7_SEL_MASK (0xFU << BUS_IOC_GPIO1D_IOMUX_SEL_H_GPIO1D7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2A_IOMUX_SEL_L */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_OFFSET (0x40U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A0_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A1_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A2_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A3_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_L_GPIO2A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2A_IOMUX_SEL_H */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_OFFSET (0x44U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A6_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A7_SEL_MASK (0xFU << BUS_IOC_GPIO2A_IOMUX_SEL_H_GPIO2A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2B_IOMUX_SEL_L */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_OFFSET (0x48U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B0_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B1_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B2_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B3_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_L_GPIO2B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_OFFSET (0x4CU) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B4_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B5_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B6_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B7_SEL_MASK (0xFU << BUS_IOC_GPIO2B_IOMUX_SEL_H_GPIO2B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_OFFSET (0x50U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C0_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C1_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C2_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C3_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_L_GPIO2C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_OFFSET (0x54U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C4_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C5_SEL_MASK (0xFU << BUS_IOC_GPIO2C_IOMUX_SEL_H_GPIO2C5_SEL_SHIFT) /* 0x000000F0 */ +/* GPIO2D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_OFFSET (0x58U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D0_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D1_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D2_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D3_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_L_GPIO2D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO2D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_OFFSET (0x5CU) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D4_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D5_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D6_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D7_SEL_MASK (0xFU << BUS_IOC_GPIO2D_IOMUX_SEL_H_GPIO2D7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3A_IOMUX_SEL_L */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_OFFSET (0x60U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A0_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A1_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A2_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A3_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_L_GPIO3A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3A_IOMUX_SEL_H */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_OFFSET (0x64U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A4_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A5_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A6_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A7_SEL_MASK (0xFU << BUS_IOC_GPIO3A_IOMUX_SEL_H_GPIO3A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3B_IOMUX_SEL_L */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_OFFSET (0x68U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B0_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B1_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B2_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B3_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_L_GPIO3B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_OFFSET (0x6CU) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B4_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B5_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B6_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B7_SEL_MASK (0xFU << BUS_IOC_GPIO3B_IOMUX_SEL_H_GPIO3B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_OFFSET (0x70U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C0_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C1_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C2_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C3_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_L_GPIO3C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_OFFSET (0x74U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C4_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C5_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C6_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C7_SEL_MASK (0xFU << BUS_IOC_GPIO3C_IOMUX_SEL_H_GPIO3C7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_OFFSET (0x78U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D0_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D1_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D2_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D3_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_L_GPIO3D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO3D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_OFFSET (0x7CU) +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D4_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D5_SEL_MASK (0xFU << BUS_IOC_GPIO3D_IOMUX_SEL_H_GPIO3D5_SEL_SHIFT) /* 0x000000F0 */ +/* GPIO4A_IOMUX_SEL_L */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_OFFSET (0x80U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A0_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A1_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A2_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A3_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_L_GPIO4A3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4A_IOMUX_SEL_H */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_OFFSET (0x84U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A4_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A5_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A6_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A7_SEL_MASK (0xFU << BUS_IOC_GPIO4A_IOMUX_SEL_H_GPIO4A7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4B_IOMUX_SEL_L */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_OFFSET (0x88U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B0_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B1_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B2_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B3_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_L_GPIO4B3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4B_IOMUX_SEL_H */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_OFFSET (0x8CU) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B4_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B5_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B6_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B6_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B7_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B7_SEL_MASK (0xFU << BUS_IOC_GPIO4B_IOMUX_SEL_H_GPIO4B7_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4C_IOMUX_SEL_L */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_OFFSET (0x90U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C0_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C1_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C2_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C3_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_L_GPIO4C3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4C_IOMUX_SEL_H */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_OFFSET (0x94U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C4_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C5_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C5_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C6_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C6_SEL_MASK (0xFU << BUS_IOC_GPIO4C_IOMUX_SEL_H_GPIO4C6_SEL_SHIFT) /* 0x00000F00 */ +/* GPIO4D_IOMUX_SEL_L */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_OFFSET (0x98U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D0_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D0_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D0_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D1_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D1_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D1_SEL_SHIFT) /* 0x000000F0 */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D2_SEL_SHIFT (8U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D2_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D2_SEL_SHIFT) /* 0x00000F00 */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D3_SEL_SHIFT (12U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D3_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_L_GPIO4D3_SEL_SHIFT) /* 0x0000F000 */ +/* GPIO4D_IOMUX_SEL_H */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_OFFSET (0x9CU) +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D4_SEL_SHIFT (0U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D4_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D4_SEL_SHIFT) /* 0x0000000F */ +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D5_SEL_SHIFT (4U) +#define BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D5_SEL_MASK (0xFU << BUS_IOC_GPIO4D_IOMUX_SEL_H_GPIO4D5_SEL_SHIFT) /* 0x000000F0 */ +/******************************************UART******************************************/ +/* RBR */ +#define UART_RBR_OFFSET (0x0U) +#define UART_RBR (0x0U) +#define UART_RBR_DATA_INPUT_SHIFT (0U) +#define UART_RBR_DATA_INPUT_MASK (0xFFU << UART_RBR_DATA_INPUT_SHIFT) /* 0x000000FF */ +/* DLL */ +#define UART_DLL_OFFSET (0x0U) +#define UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT (0U) +#define UART_DLL_BAUD_RATE_DIVISOR_L_MASK (0xFFU << UART_DLL_BAUD_RATE_DIVISOR_L_SHIFT) /* 0x000000FF */ +/* THR */ +#define UART_THR_OFFSET (0x0U) +#define UART_THR_DATA_OUTPUT_SHIFT (0U) +#define UART_THR_DATA_OUTPUT_MASK (0xFFU << UART_THR_DATA_OUTPUT_SHIFT) /* 0x000000FF */ +/* DLH */ +#define UART_DLH_OFFSET (0x4U) +#define UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT (0U) +#define UART_DLH_BAUD_RATE_DIVISOR_H_MASK (0xFFU << UART_DLH_BAUD_RATE_DIVISOR_H_SHIFT) /* 0x000000FF */ +/* IER */ +#define UART_IER_OFFSET (0x4U) +#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT (0U) +#define UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_MASK (0x1U << UART_IER_RECEIVE_DATA_AVAILABLE_INT_EN_SHIFT) /* 0x00000001 */ +#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT (1U) +#define UART_IER_TRANS_HOLD_EMPTY_INT_EN_MASK (0x1U << UART_IER_TRANS_HOLD_EMPTY_INT_EN_SHIFT) /* 0x00000002 */ +#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT (2U) +#define UART_IER_RECEIVE_LINE_STATUS_INT_EN_MASK (0x1U << UART_IER_RECEIVE_LINE_STATUS_INT_EN_SHIFT) /* 0x00000004 */ +#define UART_IER_MODEM_STATUS_INT_EN_SHIFT (3U) +#define UART_IER_MODEM_STATUS_INT_EN_MASK (0x1U << UART_IER_MODEM_STATUS_INT_EN_SHIFT) /* 0x00000008 */ +#define UART_IER_PROG_THRE_INT_EN_SHIFT (7U) +#define UART_IER_PROG_THRE_INT_EN_MASK (0x1U << UART_IER_PROG_THRE_INT_EN_SHIFT) /* 0x00000080 */ +/* FCR */ +#define UART_FCR_OFFSET (0x8U) +#define UART_FCR_FIFO_EN_SHIFT (0U) +#define UART_FCR_FIFO_EN_MASK (0x1U << UART_FCR_FIFO_EN_SHIFT) /* 0x00000001 */ +#define UART_FCR_RCVR_FIFO_RESET_SHIFT (1U) +#define UART_FCR_RCVR_FIFO_RESET_MASK (0x1U << UART_FCR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define UART_FCR_XMIT_FIFO_RESET_SHIFT (2U) +#define UART_FCR_XMIT_FIFO_RESET_MASK (0x1U << UART_FCR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */ +#define UART_FCR_DMA_MODE_SHIFT (3U) +#define UART_FCR_DMA_MODE_MASK (0x1U << UART_FCR_DMA_MODE_SHIFT) /* 0x00000008 */ +#define UART_FCR_TX_EMPTY_TRIGGER_SHIFT (4U) +#define UART_FCR_TX_EMPTY_TRIGGER_MASK (0x3U << UART_FCR_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000030 */ +#define UART_FCR_RCVR_TRIGGER_SHIFT (6U) +#define UART_FCR_RCVR_TRIGGER_MASK (0x3U << UART_FCR_RCVR_TRIGGER_SHIFT) /* 0x000000C0 */ +/* IIR */ +#define UART_IIR_OFFSET (0x8U) +#define UART_IIR (0x1U) +#define UART_IIR_INT_ID_SHIFT (0U) +#define UART_IIR_INT_ID_MASK (0xFU << UART_IIR_INT_ID_SHIFT) /* 0x0000000F */ +#define UART_IIR_FIFOS_EN_SHIFT (6U) +#define UART_IIR_FIFOS_EN_MASK (0x3U << UART_IIR_FIFOS_EN_SHIFT) /* 0x000000C0 */ +/* LCR */ +#define UART_LCR_OFFSET (0xCU) +#define UART_LCR_DATA_LENGTH_SEL_SHIFT (0U) +#define UART_LCR_DATA_LENGTH_SEL_MASK (0x3U << UART_LCR_DATA_LENGTH_SEL_SHIFT) /* 0x00000003 */ +#define UART_LCR_STOP_BITS_NUM_SHIFT (2U) +#define UART_LCR_STOP_BITS_NUM_MASK (0x1U << UART_LCR_STOP_BITS_NUM_SHIFT) /* 0x00000004 */ +#define UART_LCR_PARITY_EN_SHIFT (3U) +#define UART_LCR_PARITY_EN_MASK (0x1U << UART_LCR_PARITY_EN_SHIFT) /* 0x00000008 */ +#define UART_LCR_EVEN_PARITY_SEL_SHIFT (4U) +#define UART_LCR_EVEN_PARITY_SEL_MASK (0x1U << UART_LCR_EVEN_PARITY_SEL_SHIFT) /* 0x00000010 */ +#define UART_LCR_STICK_PARITY_SHIFT (5U) +#define UART_LCR_STICK_PARITY_MASK (0x1U << UART_LCR_STICK_PARITY_SHIFT) /* 0x00000020 */ +#define UART_LCR_BREAK_CTRL_SHIFT (6U) +#define UART_LCR_BREAK_CTRL_MASK (0x1U << UART_LCR_BREAK_CTRL_SHIFT) /* 0x00000040 */ +#define UART_LCR_DIV_LAT_ACCESS_SHIFT (7U) +#define UART_LCR_DIV_LAT_ACCESS_MASK (0x1U << UART_LCR_DIV_LAT_ACCESS_SHIFT) /* 0x00000080 */ +/* MCR */ +#define UART_MCR_OFFSET (0x10U) +#define UART_MCR_DATA_TERMINAL_READY_SHIFT (0U) +#define UART_MCR_DATA_TERMINAL_READY_MASK (0x1U << UART_MCR_DATA_TERMINAL_READY_SHIFT) /* 0x00000001 */ +#define UART_MCR_REQ_TO_SEND_SHIFT (1U) +#define UART_MCR_REQ_TO_SEND_MASK (0x1U << UART_MCR_REQ_TO_SEND_SHIFT) /* 0x00000002 */ +#define UART_MCR_OUT1_SHIFT (2U) +#define UART_MCR_OUT1_MASK (0x1U << UART_MCR_OUT1_SHIFT) /* 0x00000004 */ +#define UART_MCR_OUT2_SHIFT (3U) +#define UART_MCR_OUT2_MASK (0x1U << UART_MCR_OUT2_SHIFT) /* 0x00000008 */ +#define UART_MCR_LOOPBACK_SHIFT (4U) +#define UART_MCR_LOOPBACK_MASK (0x1U << UART_MCR_LOOPBACK_SHIFT) /* 0x00000010 */ +#define UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT (5U) +#define UART_MCR_AUTO_FLOW_CTRL_EN_MASK (0x1U << UART_MCR_AUTO_FLOW_CTRL_EN_SHIFT) /* 0x00000020 */ +#define UART_MCR_SIR_MODE_EN_SHIFT (6U) +#define UART_MCR_SIR_MODE_EN_MASK (0x1U << UART_MCR_SIR_MODE_EN_SHIFT) /* 0x00000040 */ +/* LSR */ +#define UART_LSR_OFFSET (0x14U) +#define UART_LSR (0x60U) +#define UART_LSR_DATA_READY_SHIFT (0U) +#define UART_LSR_DATA_READY_MASK (0x1U << UART_LSR_DATA_READY_SHIFT) /* 0x00000001 */ +#define UART_LSR_OVERRUN_ERROR_SHIFT (1U) +#define UART_LSR_OVERRUN_ERROR_MASK (0x1U << UART_LSR_OVERRUN_ERROR_SHIFT) /* 0x00000002 */ +#define UART_LSR_PARITY_ERROR_SHIFT (2U) +#define UART_LSR_PARITY_ERROR_MASK (0x1U << UART_LSR_PARITY_ERROR_SHIFT) /* 0x00000004 */ +#define UART_LSR_FRAMING_ERROR_SHIFT (3U) +#define UART_LSR_FRAMING_ERROR_MASK (0x1U << UART_LSR_FRAMING_ERROR_SHIFT) /* 0x00000008 */ +#define UART_LSR_BREAK_INT_SHIFT (4U) +#define UART_LSR_BREAK_INT_MASK (0x1U << UART_LSR_BREAK_INT_SHIFT) /* 0x00000010 */ +#define UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT (5U) +#define UART_LSR_TRANS_HOLD_REG_EMPTY_MASK (0x1U << UART_LSR_TRANS_HOLD_REG_EMPTY_SHIFT) /* 0x00000020 */ +#define UART_LSR_TRANS_EMPTY_SHIFT (6U) +#define UART_LSR_TRANS_EMPTY_MASK (0x1U << UART_LSR_TRANS_EMPTY_SHIFT) /* 0x00000040 */ +#define UART_LSR_RECEIVER_FIFO_ERROR_SHIFT (7U) +#define UART_LSR_RECEIVER_FIFO_ERROR_MASK (0x1U << UART_LSR_RECEIVER_FIFO_ERROR_SHIFT) /* 0x00000080 */ +/* MSR */ +#define UART_MSR_OFFSET (0x18U) +#define UART_MSR (0x0U) +#define UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT (0U) +#define UART_MSR_DELTA_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_DELTA_CLEAR_TO_SEND_SHIFT) /* 0x00000001 */ +#define UART_MSR_DELTA_DATA_SET_READY_SHIFT (1U) +#define UART_MSR_DELTA_DATA_SET_READY_MASK (0x1U << UART_MSR_DELTA_DATA_SET_READY_SHIFT) /* 0x00000002 */ +#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT (2U) +#define UART_MSR_TRAILING_EDGE_RING_INDICATOR_MASK (0x1U << UART_MSR_TRAILING_EDGE_RING_INDICATOR_SHIFT) /* 0x00000004 */ +#define UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT (3U) +#define UART_MSR_DELTA_DATA_CARRIER_DETECT_MASK (0x1U << UART_MSR_DELTA_DATA_CARRIER_DETECT_SHIFT) /* 0x00000008 */ +#define UART_MSR_CLEAR_TO_SEND_SHIFT (4U) +#define UART_MSR_CLEAR_TO_SEND_MASK (0x1U << UART_MSR_CLEAR_TO_SEND_SHIFT) /* 0x00000010 */ +#define UART_MSR_DATA_SET_READY_SHIFT (5U) +#define UART_MSR_DATA_SET_READY_MASK (0x1U << UART_MSR_DATA_SET_READY_SHIFT) /* 0x00000020 */ +#define UART_MSR_RING_INDICATOR_SHIFT (6U) +#define UART_MSR_RING_INDICATOR_MASK (0x1U << UART_MSR_RING_INDICATOR_SHIFT) /* 0x00000040 */ +#define UART_MSR_DATA_CARRIOR_DETECT_SHIFT (7U) +#define UART_MSR_DATA_CARRIOR_DETECT_MASK (0x1U << UART_MSR_DATA_CARRIOR_DETECT_SHIFT) /* 0x00000080 */ +/* SCR */ +#define UART_SCR_OFFSET (0x1CU) +#define UART_SCR_TEMP_STORE_SPACE_SHIFT (0U) +#define UART_SCR_TEMP_STORE_SPACE_MASK (0xFFU << UART_SCR_TEMP_STORE_SPACE_SHIFT) /* 0x000000FF */ +/* SRBR */ +#define UART_SRBR_OFFSET (0x30U) +#define UART_SRBR (0x0U) +#define UART_SRBR_SHADOW_RBR_SHIFT (0U) +#define UART_SRBR_SHADOW_RBR_MASK (0xFFU << UART_SRBR_SHADOW_RBR_SHIFT) /* 0x000000FF */ +/* STHR */ +#define UART_STHR_OFFSET (0x30U) +#define UART_STHR_SHADOW_THR_SHIFT (0U) +#define UART_STHR_SHADOW_THR_MASK (0xFFU << UART_STHR_SHADOW_THR_SHIFT) /* 0x000000FF */ +/* FAR */ +#define UART_FAR_OFFSET (0x70U) +#define UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT (0U) +#define UART_FAR_FIFO_ACCESS_TEST_EN_MASK (0x1U << UART_FAR_FIFO_ACCESS_TEST_EN_SHIFT) /* 0x00000001 */ +/* TFR */ +#define UART_TFR_OFFSET (0x74U) +#define UART_TFR (0x0U) +#define UART_TFR_TRANS_FIFO_READ_SHIFT (0U) +#define UART_TFR_TRANS_FIFO_READ_MASK (0xFFU << UART_TFR_TRANS_FIFO_READ_SHIFT) /* 0x000000FF */ +/* RFW */ +#define UART_RFW_OFFSET (0x78U) +#define UART_RFW_RECEIVE_FIFO_WRITE_SHIFT (0U) +#define UART_RFW_RECEIVE_FIFO_WRITE_MASK (0xFFU << UART_RFW_RECEIVE_FIFO_WRITE_SHIFT) /* 0x000000FF */ +#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT (8U) +#define UART_RFW_RECEIVE_FIFO_PARITY_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_PARITY_ERROR_SHIFT) /* 0x00000100 */ +#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT (9U) +#define UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_MASK (0x1U << UART_RFW_RECEIVE_FIFO_FRAMING_ERROR_SHIFT) /* 0x00000200 */ +/* USR */ +#define UART_USR_OFFSET (0x7CU) +#define UART_USR (0x6U) +#define UART_USR_UART_BUSY_SHIFT (0U) +#define UART_USR_UART_BUSY_MASK (0x1U << UART_USR_UART_BUSY_SHIFT) /* 0x00000001 */ +#define UART_USR_TRANS_FIFO_NOT_FULL_SHIFT (1U) +#define UART_USR_TRANS_FIFO_NOT_FULL_MASK (0x1U << UART_USR_TRANS_FIFO_NOT_FULL_SHIFT) /* 0x00000002 */ +#define UART_USR_TRASN_FIFO_EMPTY_SHIFT (2U) +#define UART_USR_TRASN_FIFO_EMPTY_MASK (0x1U << UART_USR_TRASN_FIFO_EMPTY_SHIFT) /* 0x00000004 */ +#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT (3U) +#define UART_USR_RECEIVE_FIFO_NOT_EMPTY_MASK (0x1U << UART_USR_RECEIVE_FIFO_NOT_EMPTY_SHIFT) /* 0x00000008 */ +#define UART_USR_RECEIVE_FIFO_FULL_SHIFT (4U) +#define UART_USR_RECEIVE_FIFO_FULL_MASK (0x1U << UART_USR_RECEIVE_FIFO_FULL_SHIFT) /* 0x00000010 */ +/* TFL */ +#define UART_TFL_OFFSET (0x80U) +#define UART_TFL (0x0U) +#define UART_TFL_TRANS_FIFO_LEVEL_SHIFT (0U) +#define UART_TFL_TRANS_FIFO_LEVEL_MASK (0x3FU << UART_TFL_TRANS_FIFO_LEVEL_SHIFT) /* 0x0000003F */ +/* RFL */ +#define UART_RFL_OFFSET (0x84U) +#define UART_RFL (0x0U) +#define UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT (0U) +#define UART_RFL_RECEIVE_FIFO_LEVEL_MASK (0x3FU << UART_RFL_RECEIVE_FIFO_LEVEL_SHIFT) /* 0x0000003F */ +/* SRR */ +#define UART_SRR_OFFSET (0x88U) +#define UART_SRR_UART_RESET_SHIFT (0U) +#define UART_SRR_UART_RESET_MASK (0x1U << UART_SRR_UART_RESET_SHIFT) /* 0x00000001 */ +#define UART_SRR_RCVR_FIFO_RESET_SHIFT (1U) +#define UART_SRR_RCVR_FIFO_RESET_MASK (0x1U << UART_SRR_RCVR_FIFO_RESET_SHIFT) /* 0x00000002 */ +#define UART_SRR_XMIT_FIFO_RESET_SHIFT (2U) +#define UART_SRR_XMIT_FIFO_RESET_MASK (0x1U << UART_SRR_XMIT_FIFO_RESET_SHIFT) /* 0x00000004 */ +/* SRTS */ +#define UART_SRTS_OFFSET (0x8CU) +#define UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT (0U) +#define UART_SRTS_SHADOW_REQ_TO_SEND_MASK (0x1U << UART_SRTS_SHADOW_REQ_TO_SEND_SHIFT) /* 0x00000001 */ +/* SBCR */ +#define UART_SBCR_OFFSET (0x90U) +#define UART_SBCR_SHADOW_BREAK_CTRL_SHIFT (0U) +#define UART_SBCR_SHADOW_BREAK_CTRL_MASK (0x1U << UART_SBCR_SHADOW_BREAK_CTRL_SHIFT) /* 0x00000001 */ +/* SDMAM */ +#define UART_SDMAM_OFFSET (0x94U) +#define UART_SDMAM_SHADOW_DMA_MODE_SHIFT (0U) +#define UART_SDMAM_SHADOW_DMA_MODE_MASK (0x1U << UART_SDMAM_SHADOW_DMA_MODE_SHIFT) /* 0x00000001 */ +/* SFE */ +#define UART_SFE_OFFSET (0x98U) +#define UART_SFE_SHADOW_FIFO_EN_SHIFT (0U) +#define UART_SFE_SHADOW_FIFO_EN_MASK (0x1U << UART_SFE_SHADOW_FIFO_EN_SHIFT) /* 0x00000001 */ +/* SRT */ +#define UART_SRT_OFFSET (0x9CU) +#define UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT (0U) +#define UART_SRT_SHADOW_RCVR_TRIGGER_MASK (0x3U << UART_SRT_SHADOW_RCVR_TRIGGER_SHIFT) /* 0x00000003 */ +/* STET */ +#define UART_STET_OFFSET (0xA0U) +#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT (0U) +#define UART_STET_SHADOW_TX_EMPTY_TRIGGER_MASK (0x3U << UART_STET_SHADOW_TX_EMPTY_TRIGGER_SHIFT) /* 0x00000003 */ +/* HTX */ +#define UART_HTX_OFFSET (0xA4U) +#define UART_HTX_HALT_TX_EN_SHIFT (0U) +#define UART_HTX_HALT_TX_EN_MASK (0x1U << UART_HTX_HALT_TX_EN_SHIFT) /* 0x00000001 */ +/* DMASA */ +#define UART_DMASA_OFFSET (0xA8U) +#define UART_DMASA_DMA_SOFTWARE_ACK_SHIFT (0U) +#define UART_DMASA_DMA_SOFTWARE_ACK_MASK (0x1U << UART_DMASA_DMA_SOFTWARE_ACK_SHIFT) /* 0x00000001 */ +/* CPR */ +#define UART_CPR_OFFSET (0xF4U) +#define UART_CPR (0x43FF2U) +#define UART_CPR_APB_DATA_WIDTH_SHIFT (0U) +#define UART_CPR_APB_DATA_WIDTH_MASK (0x3U << UART_CPR_APB_DATA_WIDTH_SHIFT) /* 0x00000003 */ +#define UART_CPR_AFCE_MODE_SHIFT (4U) +#define UART_CPR_AFCE_MODE_MASK (0x1U << UART_CPR_AFCE_MODE_SHIFT) /* 0x00000010 */ +#define UART_CPR_THRE_MODE_SHIFT (5U) +#define UART_CPR_THRE_MODE_MASK (0x1U << UART_CPR_THRE_MODE_SHIFT) /* 0x00000020 */ +#define UART_CPR_SIR_MODE_SHIFT (6U) +#define UART_CPR_SIR_MODE_MASK (0x1U << UART_CPR_SIR_MODE_SHIFT) /* 0x00000040 */ +#define UART_CPR_SIR_LP_MODE_SHIFT (7U) +#define UART_CPR_SIR_LP_MODE_MASK (0x1U << UART_CPR_SIR_LP_MODE_SHIFT) /* 0x00000080 */ +#define UART_CPR_NEW_FEAT_SHIFT (8U) +#define UART_CPR_NEW_FEAT_MASK (0x1U << UART_CPR_NEW_FEAT_SHIFT) /* 0x00000100 */ +#define UART_CPR_FIFO_ACCESS_SHIFT (9U) +#define UART_CPR_FIFO_ACCESS_MASK (0x1U << UART_CPR_FIFO_ACCESS_SHIFT) /* 0x00000200 */ +#define UART_CPR_FIFO_STAT_SHIFT (10U) +#define UART_CPR_FIFO_STAT_MASK (0x1U << UART_CPR_FIFO_STAT_SHIFT) /* 0x00000400 */ +#define UART_CPR_SHADOW_SHIFT (11U) +#define UART_CPR_SHADOW_MASK (0x1U << UART_CPR_SHADOW_SHIFT) /* 0x00000800 */ +#define UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT (12U) +#define UART_CPR_UART_ADD_ENCODED_PARAMS_MASK (0x1U << UART_CPR_UART_ADD_ENCODED_PARAMS_SHIFT) /* 0x00001000 */ +#define UART_CPR_DMA_EXTRA_SHIFT (13U) +#define UART_CPR_DMA_EXTRA_MASK (0x1U << UART_CPR_DMA_EXTRA_SHIFT) /* 0x00002000 */ +#define UART_CPR_FIFO_MODE_SHIFT (16U) +#define UART_CPR_FIFO_MODE_MASK (0xFFU << UART_CPR_FIFO_MODE_SHIFT) /* 0x00FF0000 */ +/* UCV */ +#define UART_UCV_OFFSET (0xF8U) +#define UART_UCV (0x3430322AU) +#define UART_UCV_VER_SHIFT (0U) +#define UART_UCV_VER_MASK (0xFFFFFFFFU << UART_UCV_VER_SHIFT) /* 0xFFFFFFFF */ +/* CTR */ +#define UART_CTR_OFFSET (0xFCU) +#define UART_CTR (0x44570110U) +#define UART_CTR_PERIPHERAL_ID_SHIFT (0U) +#define UART_CTR_PERIPHERAL_ID_MASK (0xFFFFFFFFU << UART_CTR_PERIPHERAL_ID_SHIFT) /* 0xFFFFFFFF */ +/******************************************WDT*******************************************/ +/* CR */ +#define WDT_CR_OFFSET (0x0U) +#define WDT_CR_EN_SHIFT (0U) +#define WDT_CR_EN_MASK (0x1U << WDT_CR_EN_SHIFT) /* 0x00000001 */ +#define WDT_CR_RESP_MODE_SHIFT (1U) +#define WDT_CR_RESP_MODE_MASK (0x1U << WDT_CR_RESP_MODE_SHIFT) /* 0x00000002 */ +#define WDT_CR_RST_PLUSE_LENGTH_SHIFT (2U) +#define WDT_CR_RST_PLUSE_LENGTH_MASK (0x7U << WDT_CR_RST_PLUSE_LENGTH_SHIFT) /* 0x0000001C */ +/* TORR */ +#define WDT_TORR_OFFSET (0x4U) +#define WDT_TORR_TIMEOUT_PERIOD_SHIFT (0U) +#define WDT_TORR_TIMEOUT_PERIOD_MASK (0xFU << WDT_TORR_TIMEOUT_PERIOD_SHIFT) /* 0x0000000F */ +/* CCVR */ +#define WDT_CCVR_OFFSET (0x8U) +#define WDT_CCVR (0xFFFFU) +#define WDT_CCVR_CUR_CNT_SHIFT (0U) +#define WDT_CCVR_CUR_CNT_MASK (0xFFFFFFFFU << WDT_CCVR_CUR_CNT_SHIFT) /* 0xFFFFFFFF */ +/* CRR */ +#define WDT_CRR_OFFSET (0xCU) +#define WDT_CRR_CNT_RESTART_SHIFT (0U) +#define WDT_CRR_CNT_RESTART_MASK (0xFFU << WDT_CRR_CNT_RESTART_SHIFT) /* 0x000000FF */ +/* STAT */ +#define WDT_STAT_OFFSET (0x10U) +#define WDT_STAT (0x0U) +#define WDT_STAT_STATUS_SHIFT (0U) +#define WDT_STAT_STATUS_MASK (0x1U << WDT_STAT_STATUS_SHIFT) /* 0x00000001 */ +/* EOI */ +#define WDT_EOI_OFFSET (0x14U) +#define WDT_EOI (0x0U) +#define WDT_EOI_INT_CLR_SHIFT (0U) +#define WDT_EOI_INT_CLR_MASK (0x1U << WDT_EOI_INT_CLR_SHIFT) /* 0x00000001 */ +/*****************************************TIMER******************************************/ +/* LOAD_COUNT0 */ +#define TIMER_LOAD_COUNT0_OFFSET (0x0U) +#define TIMER_LOAD_COUNT0_COUNT0_SHIFT (0U) +#define TIMER_LOAD_COUNT0_COUNT0_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT0_COUNT0_SHIFT) /* 0xFFFFFFFF */ +/* LOAD_COUNT1 */ +#define TIMER_LOAD_COUNT1_OFFSET (0x4U) +#define TIMER_LOAD_COUNT1_COUNT1_SHIFT (0U) +#define TIMER_LOAD_COUNT1_COUNT1_MASK (0xFFFFFFFFU << TIMER_LOAD_COUNT1_COUNT1_SHIFT) /* 0xFFFFFFFF */ +/* CURRENT_VALUE0 */ +#define TIMER_CURRENT_VALUE0_OFFSET (0x8U) +#define TIMER_CURRENT_VALUE0 (0x0U) +#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT (0U) +#define TIMER_CURRENT_VALUE0_CURRENT_VALUE0_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE0_CURRENT_VALUE0_SHIFT) /* 0xFFFFFFFF */ +/* CURRENT_VALUE1 */ +#define TIMER_CURRENT_VALUE1_OFFSET (0xCU) +#define TIMER_CURRENT_VALUE1 (0x0U) +#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT (0U) +#define TIMER_CURRENT_VALUE1_CURRENT_VALUE1_MASK (0xFFFFFFFFU << TIMER_CURRENT_VALUE1_CURRENT_VALUE1_SHIFT) /* 0xFFFFFFFF */ +/* CONTROLREG */ +#define TIMER_CONTROLREG_OFFSET (0x10U) +#define TIMER_CONTROLREG_TIMER_ENABLE_SHIFT (0U) +#define TIMER_CONTROLREG_TIMER_ENABLE_MASK (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT) /* 0x00000001 */ +#define TIMER_CONTROLREG_TIMER_MODE_SHIFT (1U) +#define TIMER_CONTROLREG_TIMER_MODE_MASK (0x1U << TIMER_CONTROLREG_TIMER_MODE_SHIFT) /* 0x00000002 */ +#define TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT (2U) +#define TIMER_CONTROLREG_TIMER_INT_MASK_MASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT) /* 0x00000004 */ +/* INTSTATUS */ +#define TIMER_INTSTATUS_OFFSET (0x18U) +#define TIMER_INTSTATUS_INT_PD_SHIFT (0U) +#define TIMER_INTSTATUS_INT_PD_MASK (0x1U << TIMER_INTSTATUS_INT_PD_SHIFT) /* 0x00000001 */ +/******************************************FSPI******************************************/ +/* CTRL0 */ +#define FSPI_CTRL0_OFFSET (0x0U) +#define FSPI_CTRL0_SPIM_SHIFT (0U) +#define FSPI_CTRL0_SPIM_MASK (0x1U << FSPI_CTRL0_SPIM_SHIFT) /* 0x00000001 */ +#define FSPI_CTRL0_SHIFTPHASE_SHIFT (1U) +#define FSPI_CTRL0_SHIFTPHASE_MASK (0x1U << FSPI_CTRL0_SHIFTPHASE_SHIFT) /* 0x00000002 */ +#define FSPI_CTRL0_IDLE_CYCLE_SHIFT (4U) +#define FSPI_CTRL0_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL0_IDLE_CYCLE_SHIFT) /* 0x000000F0 */ +#define FSPI_CTRL0_CMDB_SHIFT (8U) +#define FSPI_CTRL0_CMDB_MASK (0x3U << FSPI_CTRL0_CMDB_SHIFT) /* 0x00000300 */ +#define FSPI_CTRL0_ADRB_SHIFT (10U) +#define FSPI_CTRL0_ADRB_MASK (0x3U << FSPI_CTRL0_ADRB_SHIFT) /* 0x00000C00 */ +#define FSPI_CTRL0_DATB_SHIFT (12U) +#define FSPI_CTRL0_DATB_MASK (0x3U << FSPI_CTRL0_DATB_SHIFT) /* 0x00003000 */ +/* IMR */ +#define FSPI_IMR_OFFSET (0x4U) +#define FSPI_IMR_RXFM_SHIFT (0U) +#define FSPI_IMR_RXFM_MASK (0x1U << FSPI_IMR_RXFM_SHIFT) /* 0x00000001 */ +#define FSPI_IMR_RXUM_SHIFT (1U) +#define FSPI_IMR_RXUM_MASK (0x1U << FSPI_IMR_RXUM_SHIFT) /* 0x00000002 */ +#define FSPI_IMR_TXOM_SHIFT (2U) +#define FSPI_IMR_TXOM_MASK (0x1U << FSPI_IMR_TXOM_SHIFT) /* 0x00000004 */ +#define FSPI_IMR_TXEM_SHIFT (3U) +#define FSPI_IMR_TXEM_MASK (0x1U << FSPI_IMR_TXEM_SHIFT) /* 0x00000008 */ +#define FSPI_IMR_TRANSM_SHIFT (4U) +#define FSPI_IMR_TRANSM_MASK (0x1U << FSPI_IMR_TRANSM_SHIFT) /* 0x00000010 */ +#define FSPI_IMR_AHBM_SHIFT (5U) +#define FSPI_IMR_AHBM_MASK (0x1U << FSPI_IMR_AHBM_SHIFT) /* 0x00000020 */ +#define FSPI_IMR_NSPIM_SHIFT (6U) +#define FSPI_IMR_NSPIM_MASK (0x1U << FSPI_IMR_NSPIM_SHIFT) /* 0x00000040 */ +#define FSPI_IMR_DMAM_SHIFT (7U) +#define FSPI_IMR_DMAM_MASK (0x1U << FSPI_IMR_DMAM_SHIFT) /* 0x00000080 */ +/* ICLR */ +#define FSPI_ICLR_OFFSET (0x8U) +#define FSPI_ICLR_RXFC_SHIFT (0U) +#define FSPI_ICLR_RXFC_MASK (0x1U << FSPI_ICLR_RXFC_SHIFT) /* 0x00000001 */ +#define FSPI_ICLR_RXUC_SHIFT (1U) +#define FSPI_ICLR_RXUC_MASK (0x1U << FSPI_ICLR_RXUC_SHIFT) /* 0x00000002 */ +#define FSPI_ICLR_TXOC_SHIFT (2U) +#define FSPI_ICLR_TXOC_MASK (0x1U << FSPI_ICLR_TXOC_SHIFT) /* 0x00000004 */ +#define FSPI_ICLR_TXEC_SHIFT (3U) +#define FSPI_ICLR_TXEC_MASK (0x1U << FSPI_ICLR_TXEC_SHIFT) /* 0x00000008 */ +#define FSPI_ICLR_TRANSC_SHIFT (4U) +#define FSPI_ICLR_TRANSC_MASK (0x1U << FSPI_ICLR_TRANSC_SHIFT) /* 0x00000010 */ +#define FSPI_ICLR_AHBC_SHIFT (5U) +#define FSPI_ICLR_AHBC_MASK (0x1U << FSPI_ICLR_AHBC_SHIFT) /* 0x00000020 */ +#define FSPI_ICLR_NSPIC_SHIFT (6U) +#define FSPI_ICLR_NSPIC_MASK (0x1U << FSPI_ICLR_NSPIC_SHIFT) /* 0x00000040 */ +#define FSPI_ICLR_DMAC_SHIFT (7U) +#define FSPI_ICLR_DMAC_MASK (0x1U << FSPI_ICLR_DMAC_SHIFT) /* 0x00000080 */ +/* FTLR */ +#define FSPI_FTLR_OFFSET (0xCU) +#define FSPI_FTLR_TXFTLR_SHIFT (0U) +#define FSPI_FTLR_TXFTLR_MASK (0xFFU << FSPI_FTLR_TXFTLR_SHIFT) /* 0x000000FF */ +#define FSPI_FTLR_RXFTLR_SHIFT (8U) +#define FSPI_FTLR_RXFTLR_MASK (0xFFU << FSPI_FTLR_RXFTLR_SHIFT) /* 0x0000FF00 */ +/* RCVR */ +#define FSPI_RCVR_OFFSET (0x10U) +#define FSPI_RCVR_RCVR_SHIFT (0U) +#define FSPI_RCVR_RCVR_MASK (0x1U << FSPI_RCVR_RCVR_SHIFT) /* 0x00000001 */ +/* AX0 */ +#define FSPI_AX0_OFFSET (0x14U) +#define FSPI_AX0_AX_SHIFT (0U) +#define FSPI_AX0_AX_MASK (0xFFU << FSPI_AX0_AX_SHIFT) /* 0x000000FF */ +/* ABIT0 */ +#define FSPI_ABIT0_OFFSET (0x18U) +#define FSPI_ABIT0_ABIT_SHIFT (0U) +#define FSPI_ABIT0_ABIT_MASK (0x1FU << FSPI_ABIT0_ABIT_SHIFT) /* 0x0000001F */ +/* ISR */ +#define FSPI_ISR_OFFSET (0x1CU) +#define FSPI_ISR_RXFS_SHIFT (0U) +#define FSPI_ISR_RXFS_MASK (0x1U << FSPI_ISR_RXFS_SHIFT) /* 0x00000001 */ +#define FSPI_ISR_RXUS_SHIFT (1U) +#define FSPI_ISR_RXUS_MASK (0x1U << FSPI_ISR_RXUS_SHIFT) /* 0x00000002 */ +#define FSPI_ISR_TXOS_SHIFT (2U) +#define FSPI_ISR_TXOS_MASK (0x1U << FSPI_ISR_TXOS_SHIFT) /* 0x00000004 */ +#define FSPI_ISR_TXES_SHIFT (3U) +#define FSPI_ISR_TXES_MASK (0x1U << FSPI_ISR_TXES_SHIFT) /* 0x00000008 */ +#define FSPI_ISR_TRANSS_SHIFT (4U) +#define FSPI_ISR_TRANSS_MASK (0x1U << FSPI_ISR_TRANSS_SHIFT) /* 0x00000010 */ +#define FSPI_ISR_AHBS_SHIFT (5U) +#define FSPI_ISR_AHBS_MASK (0x1U << FSPI_ISR_AHBS_SHIFT) /* 0x00000020 */ +#define FSPI_ISR_NSPIS_SHIFT (6U) +#define FSPI_ISR_NSPIS_MASK (0x1U << FSPI_ISR_NSPIS_SHIFT) /* 0x00000040 */ +#define FSPI_ISR_DMAS_SHIFT (7U) +#define FSPI_ISR_DMAS_MASK (0x1U << FSPI_ISR_DMAS_SHIFT) /* 0x00000080 */ +/* FSR */ +#define FSPI_FSR_OFFSET (0x20U) +#define FSPI_FSR_TXFS_SHIFT (0U) +#define FSPI_FSR_TXFS_MASK (0x1U << FSPI_FSR_TXFS_SHIFT) /* 0x00000001 */ +#define FSPI_FSR_TXES_SHIFT (1U) +#define FSPI_FSR_TXES_MASK (0x1U << FSPI_FSR_TXES_SHIFT) /* 0x00000002 */ +#define FSPI_FSR_RXES_SHIFT (2U) +#define FSPI_FSR_RXES_MASK (0x1U << FSPI_FSR_RXES_SHIFT) /* 0x00000004 */ +#define FSPI_FSR_RXFS_SHIFT (3U) +#define FSPI_FSR_RXFS_MASK (0x1U << FSPI_FSR_RXFS_SHIFT) /* 0x00000008 */ +#define FSPI_FSR_TXWLVL_SHIFT (8U) +#define FSPI_FSR_TXWLVL_MASK (0x1FU << FSPI_FSR_TXWLVL_SHIFT) /* 0x00001F00 */ +#define FSPI_FSR_RXWLVL_SHIFT (16U) +#define FSPI_FSR_RXWLVL_MASK (0x1FU << FSPI_FSR_RXWLVL_SHIFT) /* 0x001F0000 */ +/* SR */ +#define FSPI_SR_OFFSET (0x24U) +#define FSPI_SR (0x0U) +#define FSPI_SR_SR_SHIFT (0U) +#define FSPI_SR_SR_MASK (0x1U << FSPI_SR_SR_SHIFT) /* 0x00000001 */ +/* RISR */ +#define FSPI_RISR_OFFSET (0x28U) +#define FSPI_RISR (0x0U) +#define FSPI_RISR_RXFS_SHIFT (0U) +#define FSPI_RISR_RXFS_MASK (0x1U << FSPI_RISR_RXFS_SHIFT) /* 0x00000001 */ +#define FSPI_RISR_RXUS_SHIFT (1U) +#define FSPI_RISR_RXUS_MASK (0x1U << FSPI_RISR_RXUS_SHIFT) /* 0x00000002 */ +#define FSPI_RISR_TXOS_SHIFT (2U) +#define FSPI_RISR_TXOS_MASK (0x1U << FSPI_RISR_TXOS_SHIFT) /* 0x00000004 */ +#define FSPI_RISR_TXES_SHIFT (3U) +#define FSPI_RISR_TXES_MASK (0x1U << FSPI_RISR_TXES_SHIFT) /* 0x00000008 */ +#define FSPI_RISR_TRANSS_SHIFT (4U) +#define FSPI_RISR_TRANSS_MASK (0x1U << FSPI_RISR_TRANSS_SHIFT) /* 0x00000010 */ +#define FSPI_RISR_AHBS_SHIFT (5U) +#define FSPI_RISR_AHBS_MASK (0x1U << FSPI_RISR_AHBS_SHIFT) /* 0x00000020 */ +#define FSPI_RISR_NSPIS_SHIFT (6U) +#define FSPI_RISR_NSPIS_MASK (0x1U << FSPI_RISR_NSPIS_SHIFT) /* 0x00000040 */ +#define FSPI_RISR_DMAS_SHIFT (7U) +#define FSPI_RISR_DMAS_MASK (0x1U << FSPI_RISR_DMAS_SHIFT) /* 0x00000080 */ +/* VER */ +#define FSPI_VER_OFFSET (0x2CU) +#define FSPI_VER (0x5U) +#define FSPI_VER_VER_SHIFT (0U) +#define FSPI_VER_VER_MASK (0xFFFFU << FSPI_VER_VER_SHIFT) /* 0x0000FFFF */ +/* QOP */ +#define FSPI_QOP_OFFSET (0x30U) +#define FSPI_QOP_SO123_SHIFT (0U) +#define FSPI_QOP_SO123_MASK (0x1U << FSPI_QOP_SO123_SHIFT) /* 0x00000001 */ +#define FSPI_QOP_SO123BP_SHIFT (1U) +#define FSPI_QOP_SO123BP_MASK (0x1U << FSPI_QOP_SO123BP_SHIFT) /* 0x00000002 */ +/* EXT_CTRL */ +#define FSPI_EXT_CTRL_OFFSET (0x34U) +#define FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT (0U) +#define FSPI_EXT_CTRL_CS_DESEL_CTRL_MASK (0xFU << FSPI_EXT_CTRL_CS_DESEL_CTRL_SHIFT) /* 0x0000000F */ +#define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT (4U) +#define FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_DUMM_CNT_SHIFT) /* 0x000000F0 */ +#define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT (8U) +#define FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_MASK (0xFU << FSPI_EXT_CTRL_SWITCH_IO_O2I_CNT_SHIFT) /* 0x00000F00 */ +#define FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT (13U) +#define FSPI_EXT_CTRL_TRANS_INT_MODE_MASK (0x1U << FSPI_EXT_CTRL_TRANS_INT_MODE_SHIFT) /* 0x00002000 */ +#define FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT (14U) +#define FSPI_EXT_CTRL_SR_GEN_MODE_MASK (0x1U << FSPI_EXT_CTRL_SR_GEN_MODE_SHIFT) /* 0x00004000 */ +/* DLL_CTRL0 */ +#define FSPI_DLL_CTRL0_OFFSET (0x3CU) +#define FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT (0U) +#define FSPI_DLL_CTRL0_SMP_DLL_CFG_MASK (0x1FFU << FSPI_DLL_CTRL0_SMP_DLL_CFG_SHIFT) /* 0x000001FF */ +#define FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT (15U) +#define FSPI_DLL_CTRL0_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL0_SCLK_SMP_SEL_SHIFT) /* 0x00008000 */ +/* EXT_AX */ +#define FSPI_EXT_AX_OFFSET (0x44U) +#define FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT (0U) +#define FSPI_EXT_AX_AX_CANCEL_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_CANCEL_PAT_SHIFT) /* 0x000000FF */ +#define FSPI_EXT_AX_AX_SETUP_PAT_SHIFT (8U) +#define FSPI_EXT_AX_AX_SETUP_PAT_MASK (0xFFU << FSPI_EXT_AX_AX_SETUP_PAT_SHIFT) /* 0x0000FF00 */ +/* SCLK_INATM_CNT */ +#define FSPI_SCLK_INATM_CNT_OFFSET (0x48U) +#define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT (0U) +#define FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_MASK (0xFFFFFFFFU << FSPI_SCLK_INATM_CNT_SCLK_INATM_CNT_SHIFT) /* 0xFFFFFFFF */ +/* XMMC_WCMD0 */ +#define FSPI_XMMC_WCMD0_OFFSET (0x50U) +#define FSPI_XMMC_WCMD0_CMD_SHIFT (0U) +#define FSPI_XMMC_WCMD0_CMD_MASK (0xFFU << FSPI_XMMC_WCMD0_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_WCMD0_DUMM_SHIFT (8U) +#define FSPI_XMMC_WCMD0_DUMM_MASK (0xFU << FSPI_XMMC_WCMD0_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_WCMD0_CONT_SHIFT (13U) +#define FSPI_XMMC_WCMD0_CONT_MASK (0x1U << FSPI_XMMC_WCMD0_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_WCMD0_ADDRB_SHIFT (14U) +#define FSPI_XMMC_WCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD0_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_RCMD0 */ +#define FSPI_XMMC_RCMD0_OFFSET (0x54U) +#define FSPI_XMMC_RCMD0_CMD_SHIFT (0U) +#define FSPI_XMMC_RCMD0_CMD_MASK (0xFFU << FSPI_XMMC_RCMD0_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_RCMD0_DUMM_SHIFT (8U) +#define FSPI_XMMC_RCMD0_DUMM_MASK (0xFU << FSPI_XMMC_RCMD0_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_RCMD0_CONT_SHIFT (13U) +#define FSPI_XMMC_RCMD0_CONT_MASK (0x1U << FSPI_XMMC_RCMD0_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_RCMD0_ADDRB_SHIFT (14U) +#define FSPI_XMMC_RCMD0_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD0_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_CTRL */ +#define FSPI_XMMC_CTRL_OFFSET (0x58U) +#define FSPI_XMMC_CTRL_DEV_HWEN_SHIFT (5U) +#define FSPI_XMMC_CTRL_DEV_HWEN_MASK (0x1U << FSPI_XMMC_CTRL_DEV_HWEN_SHIFT) /* 0x00000020 */ +#define FSPI_XMMC_CTRL_PFT_EN_SHIFT (6U) +#define FSPI_XMMC_CTRL_PFT_EN_MASK (0x1U << FSPI_XMMC_CTRL_PFT_EN_SHIFT) /* 0x00000040 */ +/* MODE */ +#define FSPI_MODE_OFFSET (0x5CU) +#define FSPI_MODE_XMMC_MODE_EN_SHIFT (0U) +#define FSPI_MODE_XMMC_MODE_EN_MASK (0x1U << FSPI_MODE_XMMC_MODE_EN_SHIFT) /* 0x00000001 */ +/* DEVRGN */ +#define FSPI_DEVRGN_OFFSET (0x60U) +#define FSPI_DEVRGN_RSIZE_SHIFT (0U) +#define FSPI_DEVRGN_RSIZE_MASK (0x1FU << FSPI_DEVRGN_RSIZE_SHIFT) /* 0x0000001F */ +#define FSPI_DEVRGN_DEC_CTRL_SHIFT (8U) +#define FSPI_DEVRGN_DEC_CTRL_MASK (0x3U << FSPI_DEVRGN_DEC_CTRL_SHIFT) /* 0x00000300 */ +/* DEVSIZE0 */ +#define FSPI_DEVSIZE0_OFFSET (0x64U) +#define FSPI_DEVSIZE0_DSIZE_SHIFT (0U) +#define FSPI_DEVSIZE0_DSIZE_MASK (0x1FU << FSPI_DEVSIZE0_DSIZE_SHIFT) /* 0x0000001F */ +/* TME0 */ +#define FSPI_TME0_OFFSET (0x68U) +#define FSPI_TME0_SCLK_INATM_EN_SHIFT (1U) +#define FSPI_TME0_SCLK_INATM_EN_MASK (0x1U << FSPI_TME0_SCLK_INATM_EN_SHIFT) /* 0x00000002 */ +/* XMMC_RX_WTMRK */ +#define FSPI_XMMC_RX_WTMRK_OFFSET (0x70U) +#define FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_SHIFT (0U) +#define FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_MASK (0xFFU << FSPI_XMMC_RX_WTMRK_RX_FULL_WTMRK_SHIFT) /* 0x000000FF */ +/* DMATR */ +#define FSPI_DMATR_OFFSET (0x80U) +#define FSPI_DMATR_DMATR_SHIFT (0U) +#define FSPI_DMATR_DMATR_MASK (0x1U << FSPI_DMATR_DMATR_SHIFT) /* 0x00000001 */ +/* DMAADDR */ +#define FSPI_DMAADDR_OFFSET (0x84U) +#define FSPI_DMAADDR_DMAADDR_SHIFT (0U) +#define FSPI_DMAADDR_DMAADDR_MASK (0xFFFFFFFFU << FSPI_DMAADDR_DMAADDR_SHIFT) /* 0xFFFFFFFF */ +/* LEN_CTRL */ +#define FSPI_LEN_CTRL_OFFSET (0x88U) +#define FSPI_LEN_CTRL_TRB_SEL_SHIFT (0U) +#define FSPI_LEN_CTRL_TRB_SEL_MASK (0x1U << FSPI_LEN_CTRL_TRB_SEL_SHIFT) /* 0x00000001 */ +/* LEN_EXT */ +#define FSPI_LEN_EXT_OFFSET (0x8CU) +#define FSPI_LEN_EXT_TRB_EXT_SHIFT (0U) +#define FSPI_LEN_EXT_TRB_EXT_MASK (0xFFFFFFFFU << FSPI_LEN_EXT_TRB_EXT_SHIFT) /* 0xFFFFFFFF */ +/* XMMCSR */ +#define FSPI_XMMCSR_OFFSET (0x94U) +#define FSPI_XMMCSR_SLOPOVER0_SHIFT (0U) +#define FSPI_XMMCSR_SLOPOVER0_MASK (0x1U << FSPI_XMMCSR_SLOPOVER0_SHIFT) /* 0x00000001 */ +#define FSPI_XMMCSR_SLOPOVER1_SHIFT (1U) +#define FSPI_XMMCSR_SLOPOVER1_MASK (0x1U << FSPI_XMMCSR_SLOPOVER1_SHIFT) /* 0x00000002 */ +/* CMD */ +#define FSPI_CMD_OFFSET (0x100U) +#define FSPI_CMD_CMD_SHIFT (0U) +#define FSPI_CMD_CMD_MASK (0xFFU << FSPI_CMD_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_CMD_DUMM_SHIFT (8U) +#define FSPI_CMD_DUMM_MASK (0xFU << FSPI_CMD_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_CMD_WR_SHIFT (12U) +#define FSPI_CMD_WR_MASK (0x1U << FSPI_CMD_WR_SHIFT) /* 0x00001000 */ +#define FSPI_CMD_CONT_SHIFT (13U) +#define FSPI_CMD_CONT_MASK (0x1U << FSPI_CMD_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_CMD_ADDRB_SHIFT (14U) +#define FSPI_CMD_ADDRB_MASK (0x3U << FSPI_CMD_ADDRB_SHIFT) /* 0x0000C000 */ +#define FSPI_CMD_TRB_SHIFT (16U) +#define FSPI_CMD_TRB_MASK (0x3FFFU << FSPI_CMD_TRB_SHIFT) /* 0x3FFF0000 */ +#define FSPI_CMD_CS_SHIFT (30U) +#define FSPI_CMD_CS_MASK (0x3U << FSPI_CMD_CS_SHIFT) /* 0xC0000000 */ +/* ADDR */ +#define FSPI_ADDR_OFFSET (0x104U) +#define FSPI_ADDR_ADDR_SHIFT (0U) +#define FSPI_ADDR_ADDR_MASK (0xFFFFFFFFU << FSPI_ADDR_ADDR_SHIFT) /* 0xFFFFFFFF */ +/* DATA */ +#define FSPI_DATA_OFFSET (0x108U) +#define FSPI_DATA_DATA_SHIFT (0U) +#define FSPI_DATA_DATA_MASK (0xFFFFFFFFU << FSPI_DATA_DATA_SHIFT) /* 0xFFFFFFFF */ +/* CTRL1 */ +#define FSPI_CTRL1_OFFSET (0x200U) +#define FSPI_CTRL1_SPIM_SHIFT (0U) +#define FSPI_CTRL1_SPIM_MASK (0x1U << FSPI_CTRL1_SPIM_SHIFT) /* 0x00000001 */ +#define FSPI_CTRL1_SHIFTPHASE_SHIFT (1U) +#define FSPI_CTRL1_SHIFTPHASE_MASK (0x1U << FSPI_CTRL1_SHIFTPHASE_SHIFT) /* 0x00000002 */ +#define FSPI_CTRL1_IDLE_CYCLE_SHIFT (4U) +#define FSPI_CTRL1_IDLE_CYCLE_MASK (0xFU << FSPI_CTRL1_IDLE_CYCLE_SHIFT) /* 0x000000F0 */ +#define FSPI_CTRL1_CMDB_SHIFT (8U) +#define FSPI_CTRL1_CMDB_MASK (0x3U << FSPI_CTRL1_CMDB_SHIFT) /* 0x00000300 */ +#define FSPI_CTRL1_ADRB_SHIFT (10U) +#define FSPI_CTRL1_ADRB_MASK (0x3U << FSPI_CTRL1_ADRB_SHIFT) /* 0x00000C00 */ +#define FSPI_CTRL1_DATB_SHIFT (12U) +#define FSPI_CTRL1_DATB_MASK (0x3U << FSPI_CTRL1_DATB_SHIFT) /* 0x00003000 */ +/* AX1 */ +#define FSPI_AX1_OFFSET (0x214U) +#define FSPI_AX1_AX_SHIFT (0U) +#define FSPI_AX1_AX_MASK (0xFFU << FSPI_AX1_AX_SHIFT) /* 0x000000FF */ +/* ABIT1 */ +#define FSPI_ABIT1_OFFSET (0x218U) +#define FSPI_ABIT1_ABIT_SHIFT (0U) +#define FSPI_ABIT1_ABIT_MASK (0x1FU << FSPI_ABIT1_ABIT_SHIFT) /* 0x0000001F */ +/* DLL_CTRL1 */ +#define FSPI_DLL_CTRL1_OFFSET (0x23CU) +#define FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT (0U) +#define FSPI_DLL_CTRL1_SMP_DLL_CFG_MASK (0x1FFU << FSPI_DLL_CTRL1_SMP_DLL_CFG_SHIFT) /* 0x000001FF */ +#define FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT (15U) +#define FSPI_DLL_CTRL1_SCLK_SMP_SEL_MASK (0x1U << FSPI_DLL_CTRL1_SCLK_SMP_SEL_SHIFT) /* 0x00008000 */ +/* XMMC_WCMD1 */ +#define FSPI_XMMC_WCMD1_OFFSET (0x250U) +#define FSPI_XMMC_WCMD1_CMD_SHIFT (0U) +#define FSPI_XMMC_WCMD1_CMD_MASK (0xFFU << FSPI_XMMC_WCMD1_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_WCMD1_DUMM_SHIFT (8U) +#define FSPI_XMMC_WCMD1_DUMM_MASK (0xFU << FSPI_XMMC_WCMD1_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_WCMD1_CONT_SHIFT (13U) +#define FSPI_XMMC_WCMD1_CONT_MASK (0x1U << FSPI_XMMC_WCMD1_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_WCMD1_ADDRB_SHIFT (14U) +#define FSPI_XMMC_WCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_WCMD1_ADDRB_SHIFT) /* 0x0000C000 */ +/* XMMC_RCMD1 */ +#define FSPI_XMMC_RCMD1_OFFSET (0x254U) +#define FSPI_XMMC_RCMD1_CMD_SHIFT (0U) +#define FSPI_XMMC_RCMD1_CMD_MASK (0xFFU << FSPI_XMMC_RCMD1_CMD_SHIFT) /* 0x000000FF */ +#define FSPI_XMMC_RCMD1_DUMM_SHIFT (8U) +#define FSPI_XMMC_RCMD1_DUMM_MASK (0xFU << FSPI_XMMC_RCMD1_DUMM_SHIFT) /* 0x00000F00 */ +#define FSPI_XMMC_RCMD1_CONT_SHIFT (13U) +#define FSPI_XMMC_RCMD1_CONT_MASK (0x1U << FSPI_XMMC_RCMD1_CONT_SHIFT) /* 0x00002000 */ +#define FSPI_XMMC_RCMD1_ADDRB_SHIFT (14U) +#define FSPI_XMMC_RCMD1_ADDRB_MASK (0x3U << FSPI_XMMC_RCMD1_ADDRB_SHIFT) /* 0x0000C000 */ +/* DEVSIZE1 */ +#define FSPI_DEVSIZE1_OFFSET (0x264U) +#define FSPI_DEVSIZE1_DSIZE_SHIFT (0U) +#define FSPI_DEVSIZE1_DSIZE_MASK (0x1FU << FSPI_DEVSIZE1_DSIZE_SHIFT) /* 0x0000001F */ +/* TME1 */ +#define FSPI_TME1_OFFSET (0x268U) +#define FSPI_TME1_SCLK_INATM_EN_SHIFT (1U) +#define FSPI_TME1_SCLK_INATM_EN_MASK (0x1U << FSPI_TME1_SCLK_INATM_EN_SHIFT) /* 0x00000002 */ +/******************************************SPI*******************************************/ +/* CTRLR0 */ +#define SPI_CTRLR0_OFFSET (0x0U) +#define SPI_CTRLR0_DFS_SHIFT (0U) +#define SPI_CTRLR0_DFS_MASK (0x3U << SPI_CTRLR0_DFS_SHIFT) /* 0x00000003 */ +#define SPI_CTRLR0_CFS_SHIFT (2U) +#define SPI_CTRLR0_CFS_MASK (0xFU << SPI_CTRLR0_CFS_SHIFT) /* 0x0000003C */ +#define SPI_CTRLR0_SCPH_SHIFT (6U) +#define SPI_CTRLR0_SCPH_MASK (0x1U << SPI_CTRLR0_SCPH_SHIFT) /* 0x00000040 */ +#define SPI_CTRLR0_SCPOL_SHIFT (7U) +#define SPI_CTRLR0_SCPOL_MASK (0x1U << SPI_CTRLR0_SCPOL_SHIFT) /* 0x00000080 */ +#define SPI_CTRLR0_CSM_SHIFT (8U) +#define SPI_CTRLR0_CSM_MASK (0x3U << SPI_CTRLR0_CSM_SHIFT) /* 0x00000300 */ +#define SPI_CTRLR0_SSD_SHIFT (10U) +#define SPI_CTRLR0_SSD_MASK (0x1U << SPI_CTRLR0_SSD_SHIFT) /* 0x00000400 */ +#define SPI_CTRLR0_EM_SHIFT (11U) +#define SPI_CTRLR0_EM_MASK (0x1U << SPI_CTRLR0_EM_SHIFT) /* 0x00000800 */ +#define SPI_CTRLR0_FBM_SHIFT (12U) +#define SPI_CTRLR0_FBM_MASK (0x1U << SPI_CTRLR0_FBM_SHIFT) /* 0x00001000 */ +#define SPI_CTRLR0_BHT_SHIFT (13U) +#define SPI_CTRLR0_BHT_MASK (0x1U << SPI_CTRLR0_BHT_SHIFT) /* 0x00002000 */ +#define SPI_CTRLR0_RSD_SHIFT (14U) +#define SPI_CTRLR0_RSD_MASK (0x3U << SPI_CTRLR0_RSD_SHIFT) /* 0x0000C000 */ +#define SPI_CTRLR0_FRF_SHIFT (16U) +#define SPI_CTRLR0_FRF_MASK (0x3U << SPI_CTRLR0_FRF_SHIFT) /* 0x00030000 */ +#define SPI_CTRLR0_XFM_SHIFT (18U) +#define SPI_CTRLR0_XFM_MASK (0x3U << SPI_CTRLR0_XFM_SHIFT) /* 0x000C0000 */ +#define SPI_CTRLR0_OPM_SHIFT (20U) +#define SPI_CTRLR0_OPM_MASK (0x1U << SPI_CTRLR0_OPM_SHIFT) /* 0x00100000 */ +#define SPI_CTRLR0_MTM_SHIFT (21U) +#define SPI_CTRLR0_MTM_MASK (0x1U << SPI_CTRLR0_MTM_SHIFT) /* 0x00200000 */ +#define SPI_CTRLR0_SOI_SHIFT (23U) +#define SPI_CTRLR0_SOI_MASK (0x3U << SPI_CTRLR0_SOI_SHIFT) /* 0x01800000 */ +#define SPI_CTRLR0_LBK_SHIFT (25U) +#define SPI_CTRLR0_LBK_MASK (0x1U << SPI_CTRLR0_LBK_SHIFT) /* 0x02000000 */ +/* CTRLR1 */ +#define SPI_CTRLR1_OFFSET (0x4U) +#define SPI_CTRLR1_NDM_SHIFT (0U) +#define SPI_CTRLR1_NDM_MASK (0xFFFFFFFFU << SPI_CTRLR1_NDM_SHIFT) /* 0xFFFFFFFF */ +/* ENR */ +#define SPI_ENR_OFFSET (0x8U) +#define SPI_ENR_ENR_SHIFT (0U) +#define SPI_ENR_ENR_MASK (0x1U << SPI_ENR_ENR_SHIFT) /* 0x00000001 */ +/* SER */ +#define SPI_SER_OFFSET (0xCU) +#define SPI_SER_SER_SHIFT (0U) +#define SPI_SER_SER_MASK (0x3U << SPI_SER_SER_SHIFT) /* 0x00000003 */ +/* BAUDR */ +#define SPI_BAUDR_OFFSET (0x10U) +#define SPI_BAUDR_BAUDR_SHIFT (0U) +#define SPI_BAUDR_BAUDR_MASK (0xFFFFU << SPI_BAUDR_BAUDR_SHIFT) /* 0x0000FFFF */ +/* TXFTLR */ +#define SPI_TXFTLR_OFFSET (0x14U) +#define SPI_TXFTLR_XFTLR_SHIFT (0U) +#define SPI_TXFTLR_XFTLR_MASK (0x3FU << SPI_TXFTLR_XFTLR_SHIFT) /* 0x0000003F */ +/* RXFTLR */ +#define SPI_RXFTLR_OFFSET (0x18U) +#define SPI_RXFTLR_RXFTLR_SHIFT (0U) +#define SPI_RXFTLR_RXFTLR_MASK (0x3FU << SPI_RXFTLR_RXFTLR_SHIFT) /* 0x0000003F */ +/* TXFLR */ +#define SPI_TXFLR_OFFSET (0x1CU) +#define SPI_TXFLR (0x0U) +#define SPI_TXFLR_TXFLR_SHIFT (0U) +#define SPI_TXFLR_TXFLR_MASK (0x7FU << SPI_TXFLR_TXFLR_SHIFT) /* 0x0000007F */ +/* RXFLR */ +#define SPI_RXFLR_OFFSET (0x20U) +#define SPI_RXFLR (0x0U) +#define SPI_RXFLR_RXFLR_SHIFT (0U) +#define SPI_RXFLR_RXFLR_MASK (0x7FU << SPI_RXFLR_RXFLR_SHIFT) /* 0x0000007F */ +/* SR */ +#define SPI_SR_OFFSET (0x24U) +#define SPI_SR (0x4CU) +#define SPI_SR_BSF_SHIFT (0U) +#define SPI_SR_BSF_MASK (0x1U << SPI_SR_BSF_SHIFT) /* 0x00000001 */ +#define SPI_SR_TFF_SHIFT (1U) +#define SPI_SR_TFF_MASK (0x1U << SPI_SR_TFF_SHIFT) /* 0x00000002 */ +#define SPI_SR_TFE_SHIFT (2U) +#define SPI_SR_TFE_MASK (0x1U << SPI_SR_TFE_SHIFT) /* 0x00000004 */ +#define SPI_SR_RFE_SHIFT (3U) +#define SPI_SR_RFE_MASK (0x1U << SPI_SR_RFE_SHIFT) /* 0x00000008 */ +#define SPI_SR_RFF_SHIFT (4U) +#define SPI_SR_RFF_MASK (0x1U << SPI_SR_RFF_SHIFT) /* 0x00000010 */ +#define SPI_SR_STB_SHIFT (5U) +#define SPI_SR_STB_MASK (0x1U << SPI_SR_STB_SHIFT) /* 0x00000020 */ +#define SPI_SR_SSI_SHIFT (6U) +#define SPI_SR_SSI_MASK (0x1U << SPI_SR_SSI_SHIFT) /* 0x00000040 */ +/* IPR */ +#define SPI_IPR_OFFSET (0x28U) +#define SPI_IPR_IPR_SHIFT (0U) +#define SPI_IPR_IPR_MASK (0x1U << SPI_IPR_IPR_SHIFT) /* 0x00000001 */ +/* IMR */ +#define SPI_IMR_OFFSET (0x2CU) +#define SPI_IMR_TFEIM_SHIFT (0U) +#define SPI_IMR_TFEIM_MASK (0x1U << SPI_IMR_TFEIM_SHIFT) /* 0x00000001 */ +#define SPI_IMR_TFOIM_SHIFT (1U) +#define SPI_IMR_TFOIM_MASK (0x1U << SPI_IMR_TFOIM_SHIFT) /* 0x00000002 */ +#define SPI_IMR_RFUIM_SHIFT (2U) +#define SPI_IMR_RFUIM_MASK (0x1U << SPI_IMR_RFUIM_SHIFT) /* 0x00000004 */ +#define SPI_IMR_RFOIM_SHIFT (3U) +#define SPI_IMR_RFOIM_MASK (0x1U << SPI_IMR_RFOIM_SHIFT) /* 0x00000008 */ +#define SPI_IMR_RFFIM_SHIFT (4U) +#define SPI_IMR_RFFIM_MASK (0x1U << SPI_IMR_RFFIM_SHIFT) /* 0x00000010 */ +#define SPI_IMR_TOIM_SHIFT (5U) +#define SPI_IMR_TOIM_MASK (0x1U << SPI_IMR_TOIM_SHIFT) /* 0x00000020 */ +#define SPI_IMR_SSPIM_SHIFT (6U) +#define SPI_IMR_SSPIM_MASK (0x1U << SPI_IMR_SSPIM_SHIFT) /* 0x00000040 */ +#define SPI_IMR_TXFIM_SHIFT (7U) +#define SPI_IMR_TXFIM_MASK (0x1U << SPI_IMR_TXFIM_SHIFT) /* 0x00000080 */ +/* ISR */ +#define SPI_ISR_OFFSET (0x30U) +#define SPI_ISR_TFEIS_SHIFT (0U) +#define SPI_ISR_TFEIS_MASK (0x1U << SPI_ISR_TFEIS_SHIFT) /* 0x00000001 */ +#define SPI_ISR_TFOIS_SHIFT (1U) +#define SPI_ISR_TFOIS_MASK (0x1U << SPI_ISR_TFOIS_SHIFT) /* 0x00000002 */ +#define SPI_ISR_RFUIS_SHIFT (2U) +#define SPI_ISR_RFUIS_MASK (0x1U << SPI_ISR_RFUIS_SHIFT) /* 0x00000004 */ +#define SPI_ISR_RFOIS_SHIFT (3U) +#define SPI_ISR_RFOIS_MASK (0x1U << SPI_ISR_RFOIS_SHIFT) /* 0x00000008 */ +#define SPI_ISR_RFFIS_SHIFT (4U) +#define SPI_ISR_RFFIS_MASK (0x1U << SPI_ISR_RFFIS_SHIFT) /* 0x00000010 */ +#define SPI_ISR_TOIS_SHIFT (5U) +#define SPI_ISR_TOIS_MASK (0x1U << SPI_ISR_TOIS_SHIFT) /* 0x00000020 */ +#define SPI_ISR_SSPIS_SHIFT (6U) +#define SPI_ISR_SSPIS_MASK (0x1U << SPI_ISR_SSPIS_SHIFT) /* 0x00000040 */ +#define SPI_ISR_TXFIS_SHIFT (7U) +#define SPI_ISR_TXFIS_MASK (0x1U << SPI_ISR_TXFIS_SHIFT) /* 0x00000080 */ +/* RISR */ +#define SPI_RISR_OFFSET (0x34U) +#define SPI_RISR_TFERIS_SHIFT (0U) +#define SPI_RISR_TFERIS_MASK (0x1U << SPI_RISR_TFERIS_SHIFT) /* 0x00000001 */ +#define SPI_RISR_TFORIS_SHIFT (1U) +#define SPI_RISR_TFORIS_MASK (0x1U << SPI_RISR_TFORIS_SHIFT) /* 0x00000002 */ +#define SPI_RISR_RFURIS_SHIFT (2U) +#define SPI_RISR_RFURIS_MASK (0x1U << SPI_RISR_RFURIS_SHIFT) /* 0x00000004 */ +#define SPI_RISR_RFORIS_SHIFT (3U) +#define SPI_RISR_RFORIS_MASK (0x1U << SPI_RISR_RFORIS_SHIFT) /* 0x00000008 */ +#define SPI_RISR_RFFRIS_SHIFT (4U) +#define SPI_RISR_RFFRIS_MASK (0x1U << SPI_RISR_RFFRIS_SHIFT) /* 0x00000010 */ +#define SPI_RISR_TORIS_SHIFT (5U) +#define SPI_RISR_TORIS_MASK (0x1U << SPI_RISR_TORIS_SHIFT) /* 0x00000020 */ +#define SPI_RISR_SSPRIS_SHIFT (6U) +#define SPI_RISR_SSPRIS_MASK (0x1U << SPI_RISR_SSPRIS_SHIFT) /* 0x00000040 */ +#define SPI_RISR_TXFRIS_SHIFT (7U) +#define SPI_RISR_TXFRIS_MASK (0x1U << SPI_RISR_TXFRIS_SHIFT) /* 0x00000080 */ +/* ICR */ +#define SPI_ICR_OFFSET (0x38U) +#define SPI_ICR_CCI_SHIFT (0U) +#define SPI_ICR_CCI_MASK (0x1U << SPI_ICR_CCI_SHIFT) /* 0x00000001 */ +#define SPI_ICR_CRFUI_SHIFT (1U) +#define SPI_ICR_CRFUI_MASK (0x1U << SPI_ICR_CRFUI_SHIFT) /* 0x00000002 */ +#define SPI_ICR_CRFOI_SHIFT (2U) +#define SPI_ICR_CRFOI_MASK (0x1U << SPI_ICR_CRFOI_SHIFT) /* 0x00000004 */ +#define SPI_ICR_CTFOI_SHIFT (3U) +#define SPI_ICR_CTFOI_MASK (0x1U << SPI_ICR_CTFOI_SHIFT) /* 0x00000008 */ +#define SPI_ICR_CTOI_SHIFT (4U) +#define SPI_ICR_CTOI_MASK (0x1U << SPI_ICR_CTOI_SHIFT) /* 0x00000010 */ +#define SPI_ICR_CSSPI_SHIFT (5U) +#define SPI_ICR_CSSPI_MASK (0x1U << SPI_ICR_CSSPI_SHIFT) /* 0x00000020 */ +#define SPI_ICR_CTXFI_SHIFT (6U) +#define SPI_ICR_CTXFI_MASK (0x1U << SPI_ICR_CTXFI_SHIFT) /* 0x00000040 */ +/* DMACR */ +#define SPI_DMACR_OFFSET (0x3CU) +#define SPI_DMACR_RDE_SHIFT (0U) +#define SPI_DMACR_RDE_MASK (0x1U << SPI_DMACR_RDE_SHIFT) /* 0x00000001 */ +#define SPI_DMACR_TDE_SHIFT (1U) +#define SPI_DMACR_TDE_MASK (0x1U << SPI_DMACR_TDE_SHIFT) /* 0x00000002 */ +/* DMATDLR */ +#define SPI_DMATDLR_OFFSET (0x40U) +#define SPI_DMATDLR_TDL_SHIFT (0U) +#define SPI_DMATDLR_TDL_MASK (0x3FU << SPI_DMATDLR_TDL_SHIFT) /* 0x0000003F */ +/* DMARDLR */ +#define SPI_DMARDLR_OFFSET (0x44U) +#define SPI_DMARDLR_RDL_SHIFT (0U) +#define SPI_DMARDLR_RDL_MASK (0x3FU << SPI_DMARDLR_RDL_SHIFT) /* 0x0000003F */ +/* TIMEOUT */ +#define SPI_TIMEOUT_OFFSET (0x4CU) +#define SPI_TIMEOUT_TOV_SHIFT (0U) +#define SPI_TIMEOUT_TOV_MASK (0xFFFFU << SPI_TIMEOUT_TOV_SHIFT) /* 0x0000FFFF */ +#define SPI_TIMEOUT_TOE_SHIFT (16U) +#define SPI_TIMEOUT_TOE_MASK (0x1U << SPI_TIMEOUT_TOE_SHIFT) /* 0x00010000 */ +/* BYPASS */ +#define SPI_BYPASS_OFFSET (0x50U) +#define SPI_BYPASS_BYEN_SHIFT (0U) +#define SPI_BYPASS_BYEN_MASK (0x1U << SPI_BYPASS_BYEN_SHIFT) /* 0x00000001 */ +#define SPI_BYPASS_FBM_SHIFT (1U) +#define SPI_BYPASS_FBM_MASK (0x1U << SPI_BYPASS_FBM_SHIFT) /* 0x00000002 */ +#define SPI_BYPASS_END_SHIFT (2U) +#define SPI_BYPASS_END_MASK (0x1U << SPI_BYPASS_END_SHIFT) /* 0x00000004 */ +#define SPI_BYPASS_RXCP_SHIFT (3U) +#define SPI_BYPASS_RXCP_MASK (0x1U << SPI_BYPASS_RXCP_SHIFT) /* 0x00000008 */ +#define SPI_BYPASS_TXCP_SHIFT (4U) +#define SPI_BYPASS_TXCP_MASK (0x1U << SPI_BYPASS_TXCP_SHIFT) /* 0x00000010 */ +/* TXDR */ +#define SPI_TXDR_OFFSET (0x400U) +#define SPI_TXDR_TXDR_SHIFT (0U) +#define SPI_TXDR_TXDR_MASK (0xFFFFU << SPI_TXDR_TXDR_SHIFT) /* 0x0000FFFF */ +/* RXDR */ +#define SPI_RXDR_OFFSET (0x800U) +#define SPI_RXDR (0x0U) +#define SPI_RXDR_RXDR_SHIFT (0U) +#define SPI_RXDR_RXDR_MASK (0xFFFFU << SPI_RXDR_RXDR_SHIFT) /* 0x0000FFFF */ +/******************************************MBOX******************************************/ +/* A2B_INTEN */ +#define MBOX_A2B_INTEN_OFFSET (0x0U) +#define MBOX_A2B_INTEN_INT0_SHIFT (0U) +#define MBOX_A2B_INTEN_INT0_MASK (0x1U << MBOX_A2B_INTEN_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_A2B_INTEN_INT1_SHIFT (1U) +#define MBOX_A2B_INTEN_INT1_MASK (0x1U << MBOX_A2B_INTEN_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_A2B_INTEN_INT2_SHIFT (2U) +#define MBOX_A2B_INTEN_INT2_MASK (0x1U << MBOX_A2B_INTEN_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_A2B_INTEN_INT3_SHIFT (3U) +#define MBOX_A2B_INTEN_INT3_MASK (0x1U << MBOX_A2B_INTEN_INT3_SHIFT) /* 0x00000008 */ +/* A2B_STATUS */ +#define MBOX_A2B_STATUS_OFFSET (0x4U) +#define MBOX_A2B_STATUS_INT0_SHIFT (0U) +#define MBOX_A2B_STATUS_INT0_MASK (0x1U << MBOX_A2B_STATUS_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_A2B_STATUS_INT1_SHIFT (1U) +#define MBOX_A2B_STATUS_INT1_MASK (0x1U << MBOX_A2B_STATUS_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_A2B_STATUS_INT2_SHIFT (2U) +#define MBOX_A2B_STATUS_INT2_MASK (0x1U << MBOX_A2B_STATUS_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_A2B_STATUS_INT3_SHIFT (3U) +#define MBOX_A2B_STATUS_INT3_MASK (0x1U << MBOX_A2B_STATUS_INT3_SHIFT) /* 0x00000008 */ +/* A2B_CMD_0 */ +#define MBOX_A2B_CMD_0_OFFSET (0x8U) +#define MBOX_A2B_CMD_0_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_0 */ +#define MBOX_A2B_DAT_0_OFFSET (0xCU) +#define MBOX_A2B_DAT_0_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_1 */ +#define MBOX_A2B_CMD_1_OFFSET (0x10U) +#define MBOX_A2B_CMD_1_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_1 */ +#define MBOX_A2B_DAT_1_OFFSET (0x14U) +#define MBOX_A2B_DAT_1_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_2 */ +#define MBOX_A2B_CMD_2_OFFSET (0x18U) +#define MBOX_A2B_CMD_2_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_2 */ +#define MBOX_A2B_DAT_2_OFFSET (0x1CU) +#define MBOX_A2B_DAT_2_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */ +/* A2B_CMD_3 */ +#define MBOX_A2B_CMD_3_OFFSET (0x20U) +#define MBOX_A2B_CMD_3_COMMAND_SHIFT (0U) +#define MBOX_A2B_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_A2B_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* A2B_DAT_3 */ +#define MBOX_A2B_DAT_3_OFFSET (0x24U) +#define MBOX_A2B_DAT_3_DATA_SHIFT (0U) +#define MBOX_A2B_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_A2B_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_INTEN */ +#define MBOX_B2A_INTEN_OFFSET (0x28U) +#define MBOX_B2A_INTEN_INT0_SHIFT (0U) +#define MBOX_B2A_INTEN_INT0_MASK (0x1U << MBOX_B2A_INTEN_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_B2A_INTEN_INT1_SHIFT (1U) +#define MBOX_B2A_INTEN_INT1_MASK (0x1U << MBOX_B2A_INTEN_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_B2A_INTEN_INT2_SHIFT (2U) +#define MBOX_B2A_INTEN_INT2_MASK (0x1U << MBOX_B2A_INTEN_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_B2A_INTEN_INT3_SHIFT (3U) +#define MBOX_B2A_INTEN_INT3_MASK (0x1U << MBOX_B2A_INTEN_INT3_SHIFT) /* 0x00000008 */ +/* B2A_STATUS */ +#define MBOX_B2A_STATUS_OFFSET (0x2CU) +#define MBOX_B2A_STATUS_INT0_SHIFT (0U) +#define MBOX_B2A_STATUS_INT0_MASK (0x1U << MBOX_B2A_STATUS_INT0_SHIFT) /* 0x00000001 */ +#define MBOX_B2A_STATUS_INT1_SHIFT (1U) +#define MBOX_B2A_STATUS_INT1_MASK (0x1U << MBOX_B2A_STATUS_INT1_SHIFT) /* 0x00000002 */ +#define MBOX_B2A_STATUS_INT2_SHIFT (2U) +#define MBOX_B2A_STATUS_INT2_MASK (0x1U << MBOX_B2A_STATUS_INT2_SHIFT) /* 0x00000004 */ +#define MBOX_B2A_STATUS_INT3_SHIFT (3U) +#define MBOX_B2A_STATUS_INT3_MASK (0x1U << MBOX_B2A_STATUS_INT3_SHIFT) /* 0x00000008 */ +/* B2A_CMD_0 */ +#define MBOX_B2A_CMD_0_OFFSET (0x30U) +#define MBOX_B2A_CMD_0_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_0_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_0_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_0 */ +#define MBOX_B2A_DAT_0_OFFSET (0x34U) +#define MBOX_B2A_DAT_0_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_0_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_0_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_1 */ +#define MBOX_B2A_CMD_1_OFFSET (0x38U) +#define MBOX_B2A_CMD_1_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_1_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_1_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_1 */ +#define MBOX_B2A_DAT_1_OFFSET (0x3CU) +#define MBOX_B2A_DAT_1_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_1_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_1_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_2 */ +#define MBOX_B2A_CMD_2_OFFSET (0x40U) +#define MBOX_B2A_CMD_2_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_2_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_2_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_2 */ +#define MBOX_B2A_DAT_2_OFFSET (0x44U) +#define MBOX_B2A_DAT_2_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_2_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_2_DATA_SHIFT) /* 0xFFFFFFFF */ +/* B2A_CMD_3 */ +#define MBOX_B2A_CMD_3_OFFSET (0x48U) +#define MBOX_B2A_CMD_3_COMMAND_SHIFT (0U) +#define MBOX_B2A_CMD_3_COMMAND_MASK (0xFFFFFFFFU << MBOX_B2A_CMD_3_COMMAND_SHIFT) /* 0xFFFFFFFF */ +/* B2A_DAT_3 */ +#define MBOX_B2A_DAT_3_OFFSET (0x4CU) +#define MBOX_B2A_DAT_3_DATA_SHIFT (0U) +#define MBOX_B2A_DAT_3_DATA_MASK (0xFFFFFFFFU << MBOX_B2A_DAT_3_DATA_SHIFT) /* 0xFFFFFFFF */ +/* ATOMIC_LOCK_00 */ +#define MBOX_ATOMIC_LOCK_00_OFFSET (0x100U) +#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_MASK (0x1U << MBOX_ATOMIC_LOCK_00_ATOMIC_LOCK_00_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_01 */ +#define MBOX_ATOMIC_LOCK_01_OFFSET (0x104U) +#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_MASK (0x1U << MBOX_ATOMIC_LOCK_01_ATOMIC_LOCK_01_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_02 */ +#define MBOX_ATOMIC_LOCK_02_OFFSET (0x108U) +#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_MASK (0x1U << MBOX_ATOMIC_LOCK_02_ATOMIC_LOCK_02_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_03 */ +#define MBOX_ATOMIC_LOCK_03_OFFSET (0x10CU) +#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_MASK (0x1U << MBOX_ATOMIC_LOCK_03_ATOMIC_LOCK_03_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_04 */ +#define MBOX_ATOMIC_LOCK_04_OFFSET (0x110U) +#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_MASK (0x1U << MBOX_ATOMIC_LOCK_04_ATOMIC_LOCK_04_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_05 */ +#define MBOX_ATOMIC_LOCK_05_OFFSET (0x114U) +#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_MASK (0x1U << MBOX_ATOMIC_LOCK_05_ATOMIC_LOCK_05_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_06 */ +#define MBOX_ATOMIC_LOCK_06_OFFSET (0x118U) +#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_MASK (0x1U << MBOX_ATOMIC_LOCK_06_ATOMIC_LOCK_06_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_07 */ +#define MBOX_ATOMIC_LOCK_07_OFFSET (0x11CU) +#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_MASK (0x1U << MBOX_ATOMIC_LOCK_07_ATOMIC_LOCK_07_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_08 */ +#define MBOX_ATOMIC_LOCK_08_OFFSET (0x120U) +#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_MASK (0x1U << MBOX_ATOMIC_LOCK_08_ATOMIC_LOCK_08_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_09 */ +#define MBOX_ATOMIC_LOCK_09_OFFSET (0x124U) +#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_MASK (0x1U << MBOX_ATOMIC_LOCK_09_ATOMIC_LOCK_09_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_10 */ +#define MBOX_ATOMIC_LOCK_10_OFFSET (0x128U) +#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_MASK (0x1U << MBOX_ATOMIC_LOCK_10_ATOMIC_LOCK_10_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_11 */ +#define MBOX_ATOMIC_LOCK_11_OFFSET (0x12CU) +#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_MASK (0x1U << MBOX_ATOMIC_LOCK_11_ATOMIC_LOCK_11_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_12 */ +#define MBOX_ATOMIC_LOCK_12_OFFSET (0x130U) +#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_MASK (0x1U << MBOX_ATOMIC_LOCK_12_ATOMIC_LOCK_12_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_13 */ +#define MBOX_ATOMIC_LOCK_13_OFFSET (0x134U) +#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_MASK (0x1U << MBOX_ATOMIC_LOCK_13_ATOMIC_LOCK_13_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_14 */ +#define MBOX_ATOMIC_LOCK_14_OFFSET (0x138U) +#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_MASK (0x1U << MBOX_ATOMIC_LOCK_14_ATOMIC_LOCK_14_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_15 */ +#define MBOX_ATOMIC_LOCK_15_OFFSET (0x13CU) +#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_MASK (0x1U << MBOX_ATOMIC_LOCK_15_ATOMIC_LOCK_15_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_16 */ +#define MBOX_ATOMIC_LOCK_16_OFFSET (0x140U) +#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_MASK (0x1U << MBOX_ATOMIC_LOCK_16_ATOMIC_LOCK_16_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_17 */ +#define MBOX_ATOMIC_LOCK_17_OFFSET (0x144U) +#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_MASK (0x1U << MBOX_ATOMIC_LOCK_17_ATOMIC_LOCK_17_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_18 */ +#define MBOX_ATOMIC_LOCK_18_OFFSET (0x148U) +#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_MASK (0x1U << MBOX_ATOMIC_LOCK_18_ATOMIC_LOCK_18_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_19 */ +#define MBOX_ATOMIC_LOCK_19_OFFSET (0x14CU) +#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_MASK (0x1U << MBOX_ATOMIC_LOCK_19_ATOMIC_LOCK_19_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_20 */ +#define MBOX_ATOMIC_LOCK_20_OFFSET (0x150U) +#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_MASK (0x1U << MBOX_ATOMIC_LOCK_20_ATOMIC_LOCK_20_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_21 */ +#define MBOX_ATOMIC_LOCK_21_OFFSET (0x154U) +#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_MASK (0x1U << MBOX_ATOMIC_LOCK_21_ATOMIC_LOCK_21_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_22 */ +#define MBOX_ATOMIC_LOCK_22_OFFSET (0x158U) +#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_MASK (0x1U << MBOX_ATOMIC_LOCK_22_ATOMIC_LOCK_22_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_23 */ +#define MBOX_ATOMIC_LOCK_23_OFFSET (0x15CU) +#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_MASK (0x1U << MBOX_ATOMIC_LOCK_23_ATOMIC_LOCK_23_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_24 */ +#define MBOX_ATOMIC_LOCK_24_OFFSET (0x160U) +#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_MASK (0x1U << MBOX_ATOMIC_LOCK_24_ATOMIC_LOCK_24_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_25 */ +#define MBOX_ATOMIC_LOCK_25_OFFSET (0x164U) +#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_MASK (0x1U << MBOX_ATOMIC_LOCK_25_ATOMIC_LOCK_25_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_26 */ +#define MBOX_ATOMIC_LOCK_26_OFFSET (0x168U) +#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_MASK (0x1U << MBOX_ATOMIC_LOCK_26_ATOMIC_LOCK_26_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_27 */ +#define MBOX_ATOMIC_LOCK_27_OFFSET (0x16CU) +#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_MASK (0x1U << MBOX_ATOMIC_LOCK_27_ATOMIC_LOCK_27_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_28 */ +#define MBOX_ATOMIC_LOCK_28_OFFSET (0x170U) +#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_MASK (0x1U << MBOX_ATOMIC_LOCK_28_ATOMIC_LOCK_28_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_29 */ +#define MBOX_ATOMIC_LOCK_29_OFFSET (0x174U) +#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_MASK (0x1U << MBOX_ATOMIC_LOCK_29_ATOMIC_LOCK_29_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_30 */ +#define MBOX_ATOMIC_LOCK_30_OFFSET (0x178U) +#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_MASK (0x1U << MBOX_ATOMIC_LOCK_30_ATOMIC_LOCK_30_SHIFT) /* 0x00000001 */ +/* ATOMIC_LOCK_31 */ +#define MBOX_ATOMIC_LOCK_31_OFFSET (0x17CU) +#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT (0U) +#define MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_MASK (0x1U << MBOX_ATOMIC_LOCK_31_ATOMIC_LOCK_31_SHIFT) /* 0x00000001 */ +/*****************************************INTMUX*****************************************/ + +/********Name=SOFTRST_CON01,Offset=0xA04********/ +#define SRST_A_TOP_NIU 19U +#define SRST_P_TOP_NIU 20U +#define SRST_A_LOW_TOP_NIU 21U +#define SRST_P_CSIPHY0 22U +#define SRST_SCAN_CSIPHY0 23U +#define SRST_P_CSIPHY1 24U +#define SRST_SCAN_CSIPHY1 25U +#define SRST_A_TOP_M500_NIU 31U +/********Name=SOFTRST_CON02,Offset=0xA08********/ +#define SRST_A_TOP_M400_NIU 32U +#define SRST_A_TOP_S200_NIU 33U +#define SRST_A_TOP_S400_NIU 34U +#define SRST_A_TOP_M300_NIU 35U +#define SRST_USBDP_COMBO_PHY0_INIT 40U +#define SRST_USBDP_COMBO_PHY0_CMN 41U +#define SRST_USBDP_COMBO_PHY0_LANE 42U +#define SRST_USBDP_COMBO_PHY0_PCS 43U +#define SRST_USBDP_COMBO_PHY1_INIT 47U +/********Name=SOFTRST_CON03,Offset=0xA0C********/ +#define SRST_USBDP_COMBO_PHY1_CMN 48U +#define SRST_USBDP_COMBO_PHY1_LANE 49U +#define SRST_USBDP_COMBO_PHY1_PCS 50U +#define SRST_SCAN_DCPHY0 59U +#define SRST_P_MIPI_DCPHY0 62U +#define SRST_P_MIPI_DCPHY0_GRF 63U +/********Name=SOFTRST_CON04,Offset=0xA10********/ +#define SRST_SCAN_DCPHY1 64U +#define SRST_P_MIPI_DCPHY1 67U +#define SRST_P_MIPI_DCPHY1_GRF 68U +#define SRST_P_APB2ASB_SLV_CDPHY 69U +#define SRST_P_APB2ASB_SLV_CSIPHY 70U +#define SRST_P_APB2ASB_SLV_VCCIO3_5 71U +#define SRST_P_APB2ASB_SLV_VCCIO6 72U +#define SRST_P_APB2ASB_SLV_EMMCIO 73U +#define SRST_P_APB2ASB_SLV_IOC_TOP 74U +#define SRST_P_APB2ASB_SLV_IOC_RIGHT 75U +/********Name=SOFTRST_CON05,Offset=0xA14********/ +#define SRST_P_CRU 80U +#define SRST_NPOR_PAD 81U +#define SRST_NPOR_TM_DECODER 82U +#define SRST_A_CHANNEL_SECURE2VO1USB 87U +#define SRST_A_CHANNEL_SECURE2CENTER 88U +#define SRST_H_CHANNEL_SECURE2VO1USB 94U +#define SRST_H_CHANNEL_SECURE2CENTER 95U +/********Name=SOFTRST_CON06,Offset=0xA18********/ +#define SRST_P_CHANNEL_SECURE2VO1USB 96U +#define SRST_P_CHANNEL_SECURE2CENTER 97U +/********Name=SOFTRST_CON07,Offset=0xA1C********/ +#define SRST_H_AUDIO_NIU 114U +#define SRST_P_AUDIO_NIU 115U +#define SRST_H_I2S0_8CH 116U +#define SRST_M_I2S0_8CH_TX 119U +#define SRST_M_I2S0_8CH_RX 122U +#define SRST_P_ACDCDIG 123U +#define SRST_H_I2S2_2CH 124U +#define SRST_H_I2S3_2CH 125U +/********Name=SOFTRST_CON08,Offset=0xA20********/ +#define SRST_M_I2S2_2CH 128U +#define SRST_M_I2S3_2CH 131U +#define SRST_DAC_ACDCDIG 132U +#define SRST_H_SPDIF0 142U +/********Name=SOFTRST_CON09,Offset=0xA24********/ +#define SRST_M_SPDIF0 145U +#define SRST_H_SPDIF1 146U +#define SRST_M_SPDIF1 149U +#define SRST_H_PDM1 150U +#define SRST_PDM1 151U +/********Name=SOFTRST_CON10,Offset=0xA28********/ +#define SRST_A_BUS_NIU 161U +#define SRST_P_BUS_NIU 162U +#define SRST_A_GIC 163U +#define SRST_A_GIC_DBG 164U +#define SRST_A_DMAC0 165U +#define SRST_A_DMAC1 166U +#define SRST_A_DMAC2 167U +#define SRST_P_I2C1 168U +#define SRST_P_I2C2 169U +#define SRST_P_I2C3 170U +#define SRST_P_I2C4 171U +#define SRST_P_I2C5 172U +#define SRST_P_I2C6 173U +#define SRST_P_I2C7 174U +#define SRST_P_I2C8 175U +/********Name=SOFTRST_CON11,Offset=0xA2C********/ +#define SRST_I2C1 176U +#define SRST_I2C2 177U +#define SRST_I2C3 178U +#define SRST_I2C4 179U +#define SRST_I2C5 180U +#define SRST_I2C6 181U +#define SRST_I2C7 182U +#define SRST_I2C8 183U +#define SRST_P_CAN0 184U +#define SRST_CAN0 185U +#define SRST_P_CAN1 186U +#define SRST_CAN1 187U +#define SRST_P_CAN2 188U +#define SRST_CAN2 189U +#define SRST_P_SARADC 190U +/********Name=SOFTRST_CON12,Offset=0xA30********/ +#define SRST_P_TSADC 192U +#define SRST_TSADC 193U +#define SRST_P_UART1 194U +#define SRST_P_UART2 195U +#define SRST_P_UART3 196U +#define SRST_P_UART4 197U +#define SRST_P_UART5 198U +#define SRST_P_UART6 199U +#define SRST_P_UART7 200U +#define SRST_P_UART8 201U +#define SRST_P_UART9 202U +#define SRST_S_UART1 205U +/********Name=SOFTRST_CON13,Offset=0xA34********/ +#define SRST_S_UART2 208U +#define SRST_S_UART3 211U +#define SRST_S_UART4 214U +#define SRST_S_UART5 217U +#define SRST_S_UART6 220U +#define SRST_S_UART7 223U +/********Name=SOFTRST_CON14,Offset=0xA38********/ +#define SRST_S_UART8 226U +#define SRST_S_UART9 229U +#define SRST_P_SPI0 230U +#define SRST_P_SPI1 231U +#define SRST_P_SPI2 232U +#define SRST_P_SPI3 233U +#define SRST_P_SPI4 234U +#define SRST_SPI0 235U +#define SRST_SPI1 236U +#define SRST_SPI2 237U +#define SRST_SPI3 238U +#define SRST_SPI4 239U +/********Name=SOFTRST_CON15,Offset=0xA3C********/ +#define SRST_P_WDT0 240U +#define SRST_T_WDT0 241U +#define SRST_P_SYS_GRF 242U +#define SRST_P_PWM1 243U +#define SRST_PWM1 244U +#define SRST_P_PWM2 246U +#define SRST_PWM2 247U +#define SRST_P_PWM3 249U +#define SRST_PWM3 250U +#define SRST_P_BUSTIMER0 252U +#define SRST_P_BUSTIMER1 253U +#define SRST_BUSTIMER0 255U +/********Name=SOFTRST_CON16,Offset=0xA40********/ +#define SRST_BUSTIMER1 256U +#define SRST_BUSTIMER2 257U +#define SRST_BUSTIMER3 258U +#define SRST_BUSTIMER4 259U +#define SRST_BUSTIMER5 260U +#define SRST_BUSTIMER6 261U +#define SRST_BUSTIMER7 262U +#define SRST_BUSTIMER8 263U +#define SRST_BUSTIMER9 264U +#define SRST_BUSTIMER10 265U +#define SRST_BUSTIMER11 266U +#define SRST_P_MAILBOX0 267U +#define SRST_P_MAILBOX1 268U +#define SRST_P_MAILBOX2 269U +#define SRST_P_GPIO1 270U +#define SRST_DB_GPIO1 271U +/********Name=SOFTRST_CON17,Offset=0xA44********/ +#define SRST_P_GPIO2 272U +#define SRST_DB_GPIO2 273U +#define SRST_P_GPIO3 274U +#define SRST_DB_GPIO3 275U +#define SRST_P_GPIO4 276U +#define SRST_DB_GPIO4 277U +#define SRST_A_DECOM 278U +#define SRST_P_DECOM 279U +#define SRST_D_DECOM 280U +#define SRST_P_TOP 281U +#define SRST_A_GICADB_CORE2GIC_BUS 282U +#define SRST_A_GICADB_GIC2CORE_BUS 283U +#define SRST_P_DFT2APB 284U +#define SRST_P_APB2ASB_MST_TOP 285U +#define SRST_P_APB2ASB_MST_CDPHY 286U +#define SRST_P_APB2ASB_MST_BOT_RIGHT 287U +/********Name=SOFTRST_CON18,Offset=0xA48********/ +#define SRST_P_APB2ASB_MST_IOC_TOP 288U +#define SRST_P_APB2ASB_MST_IOC_RIGHT 289U +#define SRST_P_APB2ASB_MST_CSIPHY 290U +#define SRST_P_APB2ASB_MST_VCCIO3_5 291U +#define SRST_P_APB2ASB_MST_VCCIO6 292U +#define SRST_P_APB2ASB_MST_EMMCIO 293U +#define SRST_A_SPINLOCK 294U +#define SRST_P_OTPC_TM 295U +#define SRST_OTPC_TM 296U +#define SRST_P_OTPC_NS 297U +#define SRST_OTPC_NS 298U +#define SRST_OTPC_ARB 299U +#define SRST_P_JDBCK_DFT 302U +#define SRST_JDBCK_DFT 303U +/********Name=SOFTRST_CON19,Offset=0xA4C********/ +#define SRST_P_BUSIOC 304U +#define SRST_BISRINTF 306U +#define SRST_P_PMUCM0_INTMUX 308U +#define SRST_P_DDRCM0_INTMUX 309U +/********Name=SOFTRST_CON20,Offset=0xA50********/ +#define SRST_P_DDR_DFICTL_CH0 320U +#define SRST_P_DDR_MON_CH0 321U +#define SRST_P_DDR_STANDBY_CH0 322U +#define SRST_P_DDR_UPCTL_CH0 323U +#define SRST_TM_DDR_MON_CH0 324U +#define SRST_P_DDR_GRF_CH01 325U +#define SRST_DFI_CH0 326U +#define SRST_SBR_CH0 327U +#define SRST_DDR_UPCTL_CH0 328U +#define SRST_DDR_DFICTL_CH0 329U +#define SRST_DDR_MON_CH0 330U +#define SRST_DDR_STANDBY_CH0 331U +#define SRST_A_DDR_UPCTL_CH0 332U +#define SRST_P_DDR_DFICTL_CH1 333U +#define SRST_P_DDR_MON_CH1 334U +#define SRST_P_DDR_STANDBY_CH1 335U +/********Name=SOFTRST_CON21,Offset=0xA54********/ +#define SRST_P_DDR_UPCTL_CH1 336U +#define SRST_TM_DDR_MON_CH1 337U +#define SRST_DFI_CH1 338U +#define SRST_SBR_CH1 339U +#define SRST_DDR_UPCTL_CH1 340U +#define SRST_DDR_DFICTL_CH1 341U +#define SRST_DDR_MON_CH1 342U +#define SRST_DDR_STANDBY_CH1 343U +#define SRST_A_DDR_UPCTL_CH1 344U +#define SRST_A_DDR01_MSCH0 349U +#define SRST_A_DDR01_RS_MSCH0 350U +#define SRST_A_DDR01_FRS_MSCH0 351U +/********Name=SOFTRST_CON22,Offset=0xA58********/ +#define SRST_A_DDR01_SCRAMBLE0 352U +#define SRST_A_DDR01_FRS_SCRAMBLE0 353U +#define SRST_A_DDR01_MSCH1 354U +#define SRST_A_DDR01_RS_MSCH1 355U +#define SRST_A_DDR01_FRS_MSCH1 356U +#define SRST_A_DDR01_SCRAMBLE1 357U +#define SRST_A_DDR01_FRS_SCRAMBLE1 358U +#define SRST_P_DDR01_MSCH0 359U +#define SRST_P_DDR01_MSCH1 360U +/********Name=SOFTRST_CON23,Offset=0xA5C********/ +#define SRST_P_DDR_DFICTL_CH2 368U +#define SRST_P_DDR_MON_CH2 369U +#define SRST_P_DDR_STANDBY_CH2 370U +#define SRST_P_DDR_UPCTL_CH2 371U +#define SRST_TM_DDR_MON_CH2 372U +#define SRST_P_DDR_GRF_CH23 373U +#define SRST_DFI_CH2 374U +#define SRST_SBR_CH2 375U +#define SRST_DDR_UPCTL_CH2 376U +#define SRST_DDR_DFICTL_CH2 377U +#define SRST_DDR_MON_CH2 378U +#define SRST_DDR_STANDBY_CH2 379U +#define SRST_A_DDR_UPCTL_CH2 380U +#define SRST_P_DDR_DFICTL_CH3 381U +#define SRST_P_DDR_MON_CH3 382U +#define SRST_P_DDR_STANDBY_CH3 383U +/********Name=SOFTRST_CON24,Offset=0xA60********/ +#define SRST_P_DDR_UPCTL_CH3 384U +#define SRST_TM_DDR_MON_CH3 385U +#define SRST_DFI_CH3 386U +#define SRST_SBR_CH3 387U +#define SRST_DDR_UPCTL_CH3 388U +#define SRST_DDR_DFICTL_CH3 389U +#define SRST_DDR_MON_CH3 390U +#define SRST_DDR_STANDBY_CH3 391U +#define SRST_A_DDR_UPCTL_CH3 392U +#define SRST_A_DDR23_MSCH2 397U +#define SRST_A_DDR23_RS_MSCH2 398U +#define SRST_A_DDR23_FRS_MSCH2 399U +/********Name=SOFTRST_CON25,Offset=0xA64********/ +#define SRST_A_DDR23_SCRAMBLE2 400U +#define SRST_A_DDR23_FRS_SCRAMBLE2 401U +#define SRST_A_DDR23_MSCH3 402U +#define SRST_A_DDR23_RS_MSCH3 403U +#define SRST_A_DDR23_FRS_MSCH3 404U +#define SRST_A_DDR23_SCRAMBLE3 405U +#define SRST_A_DDR23_FRS_SCRAMBLE3 406U +#define SRST_P_DDR23_MSCH2 407U +#define SRST_P_DDR23_MSCH3 408U +/********Name=SOFTRST_CON26,Offset=0xA68********/ +#define SRST_ISP1 419U +#define SRST_ISP1_VICAP 420U +#define SRST_A_ISP1_NIU 422U +#define SRST_H_ISP1_NIU 424U +/********Name=SOFTRST_CON27,Offset=0xA6C********/ +#define SRST_A_RKNN1 432U +#define SRST_A_RKNN1_NIU 433U +#define SRST_H_RKNN1 434U +#define SRST_H_RKNN1_NIU 435U +/********Name=SOFTRST_CON28,Offset=0xA70********/ +#define SRST_A_RKNN2 448U +#define SRST_A_RKNN2_NIU 449U +#define SRST_H_RKNN2 450U +#define SRST_H_RKNN2_NIU 451U +/********Name=SOFTRST_CON29,Offset=0xA74********/ +#define SRST_A_RKNN_DSU0 467U +#define SRST_P_NPUTOP_NIU 469U +#define SRST_P_NPU_TIMER 470U +#define SRST_NPUTIMER0 472U +#define SRST_NPUTIMER1 473U +#define SRST_P_NPU_WDT 474U +#define SRST_T_NPU_WDT 475U +#define SRST_P_PVTM1 476U +#define SRST_P_NPU_GRF 477U +#define SRST_PVTM1 478U +/********Name=SOFTRST_CON30,Offset=0xA78********/ +#define SRST_NPU_PVTPLL 480U +#define SRST_H_NPU_CM0_NIU 482U +#define SRST_F_NPU_CM0_CORE 483U +#define SRST_T_NPU_CM0_JTAG 484U +#define SRST_A_RKNN0 486U +#define SRST_A_RKNN0_NIU 487U +#define SRST_H_RKNN0 488U +#define SRST_H_RKNN0_NIU 489U +/********Name=SOFTRST_CON31,Offset=0xA7C********/ +#define SRST_H_NVM_NIU 498U +#define SRST_A_NVM_NIU 499U +#define SRST_H_EMMC 500U +#define SRST_A_EMMC 501U +#define SRST_C_EMMC 502U +#define SRST_B_EMMC 503U +#define SRST_T_EMMC 504U +#define SRST_S_SFC 505U +#define SRST_H_SFC 506U +#define SRST_H_SFC_XIP 507U +/********Name=SOFTRST_CON32,Offset=0xA80********/ +#define SRST_P_GRF 513U +#define SRST_P_DEC_NIU 514U +#define SRST_P_PHP_NIU 517U +#define SRST_A_PCIE_GRIDGE 520U +#define SRST_A_PHP_NIU 521U +#define SRST_A_GMAC0 522U +#define SRST_A_GMAC1 523U +#define SRST_A_PCIE_NIU 524U +#define SRST_PCIE0_POWER_UP 525U +#define SRST_PCIE1_POWER_UP 526U +#define SRST_PCIE2_POWER_UP 527U +/********Name=SOFTRST_CON33,Offset=0xA84********/ +#define SRST_PCIE3_POWER_UP 528U +#define SRST_PCIE4_POWER_UP 529U +#define SRST_P_PCIE0 540U +#define SRST_P_PCIE1 541U +#define SRST_P_PCIE2 542U +#define SRST_P_PCIE3 543U +/********Name=SOFTRST_CON34,Offset=0xA88********/ +#define SRST_P_PCIE4 544U +#define SRST_A_PHP_GIC_ITS 550U +#define SRST_A_MMU_PCIE 551U +#define SRST_A_MMU_PHP 552U +#define SRST_A_MMU_NIU 553U +/********Name=SOFTRST_CON35,Offset=0xA8C********/ +#define SRST_A_USB3OTG2 567U +/********Name=SOFTRST_CON37,Offset=0xA94********/ +#define SRST_PMALIVE0 596U +#define SRST_PMALIVE1 597U +#define SRST_PMALIVE2 598U +#define SRST_A_SATA0 599U +#define SRST_A_SATA1 600U +#define SRST_A_SATA2 601U +#define SRST_RXOOB0 602U +#define SRST_RXOOB1 603U +#define SRST_RXOOB2 604U +#define SRST_ASIC0 605U +#define SRST_ASIC1 606U +#define SRST_ASIC2 607U +/********Name=SOFTRST_CON40,Offset=0xAA0********/ +#define SRST_A_RKVDEC_CCU 642U +#define SRST_H_RKVDEC0 643U +#define SRST_A_RKVDEC0 644U +#define SRST_H_RKVDEC0_NIU 645U +#define SRST_A_RKVDEC0_NIU 646U +#define SRST_RKVDEC0_CA 647U +#define SRST_RKVDEC0_HEVC_CA 648U +#define SRST_RKVDEC0_CORE 649U +/********Name=SOFTRST_CON41,Offset=0xAA4********/ +#define SRST_H_RKVDEC1 658U +#define SRST_A_RKVDEC1 659U +#define SRST_H_RKVDEC1_NIU 660U +#define SRST_A_RKVDEC1_NIU 661U +#define SRST_RKVDEC1_CA 662U +#define SRST_RKVDEC1_HEVC_CA 663U +#define SRST_RKVDEC1_CORE 664U +/********Name=SOFTRST_CON42,Offset=0xAA8********/ +#define SRST_A_USB_NIU 674U +#define SRST_H_USB_NIU 675U +#define SRST_A_USB3OTG0 676U +#define SRST_A_USB3OTG1 679U +#define SRST_H_HOST0 682U +#define SRST_H_HOST_ARB0 683U +#define SRST_H_HOST1 684U +#define SRST_H_HOST_ARB1 685U +#define SRST_A_USB_GRF 686U +#define SRST_C_USB2P0_HOST0 687U +/********Name=SOFTRST_CON43,Offset=0xAAC********/ +#define SRST_C_USB2P0_HOST1 688U +#define SRST_HOST_UTMI0 689U +#define SRST_HOST_UTMI1 690U +/********Name=SOFTRST_CON44,Offset=0xAB0********/ +#define SRST_A_VDPU_NIU 708U +#define SRST_A_VDPU_LOW_NIU 709U +#define SRST_H_VDPU_NIU 710U +#define SRST_A_JPEG_DECODER_NIU 711U +#define SRST_A_VPU 712U +#define SRST_H_VPU 713U +#define SRST_A_JPEG_ENCODER0 714U +#define SRST_H_JPEG_ENCODER0 715U +#define SRST_A_JPEG_ENCODER1 716U +#define SRST_H_JPEG_ENCODER1 717U +#define SRST_A_JPEG_ENCODER2 718U +#define SRST_H_JPEG_ENCODER2 719U +/********Name=SOFTRST_CON45,Offset=0xAB4********/ +#define SRST_A_JPEG_ENCODER3 720U +#define SRST_H_JPEG_ENCODER3 721U +#define SRST_A_JPEG_DECODER 722U +#define SRST_H_JPEG_DECODER 723U +#define SRST_H_IEP2P0 724U +#define SRST_A_IEP2P0 725U +#define SRST_IEP2P0_CORE 726U +#define SRST_H_RGA2 727U +#define SRST_A_RGA2 728U +#define SRST_RGA2_CORE 729U +#define SRST_H_RGA3_0 730U +#define SRST_A_RGA3_0 731U +#define SRST_RGA3_0_CORE 732U +/********Name=SOFTRST_CON47,Offset=0xABC********/ +#define SRST_H_RKVENC0_NIU 754U +#define SRST_A_RKVENC0_NIU 755U +#define SRST_H_RKVENC0 756U +#define SRST_A_RKVENC0 757U +#define SRST_RKVENC0_CORE 758U +/********Name=SOFTRST_CON48,Offset=0xAC0********/ +#define SRST_H_RKVENC1_NIU 770U +#define SRST_A_RKVENC1_NIU 771U +#define SRST_H_RKVENC1 772U +#define SRST_A_RKVENC1 773U +#define SRST_RKVENC1_CORE 774U +/********Name=SOFTRST_CON49,Offset=0xAC4********/ +#define SRST_A_VI_NIU 787U +#define SRST_H_VI_NIU 788U +#define SRST_P_VI_NIU 789U +#define SRST_D_VICAP 790U +#define SRST_A_VICAP 791U +#define SRST_H_VICAP 792U +#define SRST_ISP0 794U +#define SRST_ISP0_VICAP 795U +/********Name=SOFTRST_CON50,Offset=0xAC8********/ +#define SRST_FISHEYE0 800U +#define SRST_FISHEYE1 803U +#define SRST_P_CSI_HOST_0 804U +#define SRST_P_CSI_HOST_1 805U +#define SRST_P_CSI_HOST_2 806U +#define SRST_P_CSI_HOST_3 807U +#define SRST_P_CSI_HOST_4 808U +#define SRST_P_CSI_HOST_5 809U +/********Name=SOFTRST_CON51,Offset=0xACC********/ +#define SRST_CSIHOST0_VICAP 820U +#define SRST_CSIHOST1_VICAP 821U +#define SRST_CSIHOST2_VICAP 822U +#define SRST_CSIHOST3_VICAP 823U +#define SRST_CSIHOST4_VICAP 824U +#define SRST_CSIHOST5_VICAP 825U +#define SRST_CIFIN 829U +/********Name=SOFTRST_CON52,Offset=0xAD0********/ +#define SRST_A_VOP_NIU 836U +#define SRST_A_VOP_LOW_NIU 837U +#define SRST_H_VOP_NIU 838U +#define SRST_P_VOP_NIU 839U +#define SRST_H_VOP 840U +#define SRST_A_VOP 841U +#define SRST_D_VOP0 845U +#define SRST_D_VOP2HDMI_BRIDGE0 846U +#define SRST_D_VOP2HDMI_BRIDGE1 847U +/********Name=SOFTRST_CON53,Offset=0xAD4********/ +#define SRST_D_VOP1 848U +#define SRST_D_VOP2 849U +#define SRST_D_VOP3 850U +#define SRST_P_VOPGRF 851U +#define SRST_P_DSIHOST0 852U +#define SRST_P_DSIHOST1 853U +#define SRST_DSIHOST0 854U +#define SRST_DSIHOST1 855U +#define SRST_VOP_PMU 856U +#define SRST_P_VOP_CHANNEL_NIU 857U +/********Name=SOFTRST_CON55,Offset=0xADC********/ +#define SRST_H_VO0_NIU 885U +#define SRST_H_VO0_S_NIU 886U +#define SRST_P_VO0_NIU 887U +#define SRST_P_VO0_S_NIU 888U +#define SRST_A_HDCP0_NIU 889U +#define SRST_P_VO0GRF 890U +#define SRST_H_HDCP_KEY0 891U +#define SRST_A_HDCP0 892U +#define SRST_H_HDCP0 893U +#define SRST_P_HDCP0 894U +#define SRST_HDCP0 895U +/********Name=SOFTRST_CON56,Offset=0xAE0********/ +#define SRST_A_TRNG0 896U +#define SRST_P_TRNG0 897U +#define SRST_DP0 904U +#define SRST_DP1 905U +#define SRST_H_I2S4_8CH 906U +#define SRST_M_I2S4_8CH_TX 909U +#define SRST_H_I2S8_8CH 910U +/********Name=SOFTRST_CON57,Offset=0xAE4********/ +#define SRST_M_I2S8_8CH_TX 913U +#define SRST_H_SPDIF2_DP0 914U +#define SRST_M_SPDIF2_DP0 918U +#define SRST_H_SPDIF5_DP1 919U +#define SRST_M_SPDIF5_DP1 923U +/********Name=SOFTRST_CON59,Offset=0xAEC********/ +#define SRST_A_HDCP1_NIU 950U +#define SRST_A_HDMIRX_NIU 951U +#define SRST_A_VO1_NIU 952U +#define SRST_H_VOP1_NIU 953U +#define SRST_H_VOP1_S_NIU 954U +#define SRST_P_VOP1_NIU 955U +#define SRST_P_VO1GRF 956U +#define SRST_P_VO1_S_NIU 957U +/********Name=SOFTRST_CON60,Offset=0xAF0********/ +#define SRST_H_I2S7_8CH 960U +#define SRST_M_I2S7_8CH_RX 963U +#define SRST_H_HDCP_KEY1 964U +#define SRST_A_HDCP1 965U +#define SRST_H_HDCP1 966U +#define SRST_HDCP1 968U +#define SRST_P_TRNG1 970U +#define SRST_P_HDMITX0 971U +/********Name=SOFTRST_CON61,Offset=0xAF4********/ +#define SRST_HDMITX0_REF 976U +#define SRST_P_HDMITX1 978U +#define SRST_HDMITX1_REF 983U +#define SRST_A_HDMIRX 985U +#define SRST_P_HDMIRX 986U +#define SRST_HDMIRX_REF 987U +/********Name=SOFTRST_CON62,Offset=0xAF8********/ +#define SRST_P_EDP0 992U +#define SRST_EDP0_24M 993U +#define SRST_P_EDP1 995U +#define SRST_EDP1_24M 996U +#define SRST_M_I2S5_8CH_TX 1000U +#define SRST_H_I2S5_8CH 1004U +#define SRST_M_I2S6_8CH_TX 1007U +/********Name=SOFTRST_CON63,Offset=0xAFC********/ +#define SRST_M_I2S6_8CH_RX 1010U +#define SRST_H_I2S6_8CH 1011U +#define SRST_H_SPDIF3 1012U +#define SRST_M_SPDIF3 1015U +#define SRST_H_SPDIF4 1016U +#define SRST_M_SPDIF4 1019U +#define SRST_H_SPDIFRX0 1020U +#define SRST_M_SPDIFRX0 1021U +#define SRST_H_SPDIFRX1 1022U +#define SRST_M_SPDIFRX1 1023U +/********Name=SOFTRST_CON64,Offset=0xB00********/ +#define SRST_H_SPDIFRX2 1024U +#define SRST_M_SPDIFRX2 1025U +#define SRST_LINKSYM_HDMITXPHY0 1036U +#define SRST_LINKSYM_HDMITXPHY1 1037U +#define SRST_VO1_BRIDGE0 1038U +#define SRST_VO1_BRIDGE1 1039U +/********Name=SOFTRST_CON65,Offset=0xB04********/ +#define SRST_H_I2S9_8CH 1040U +#define SRST_M_I2S9_8CH_RX 1043U +#define SRST_H_I2S10_8CH 1044U +#define SRST_M_I2S10_8CH_RX 1047U +#define SRST_P_S_HDMIRX 1048U +/********Name=SOFTRST_CON66,Offset=0xB08********/ +#define SRST_GPU 1060U +#define SRST_SYS_GPU 1061U +#define SRST_A_S_GPU_NIU 1064U +#define SRST_A_M0_GPU_NIU 1065U +#define SRST_A_M1_GPU_NIU 1066U +#define SRST_A_M2_GPU_NIU 1067U +#define SRST_A_M3_GPU_NIU 1068U +#define SRST_P_GPU_NIU 1070U +#define SRST_P_PVTM2 1071U +/********Name=SOFTRST_CON67,Offset=0xB0C********/ +#define SRST_PVTM2 1072U +#define SRST_P_GPU_GRF 1074U +#define SRST_GPU_PVTPLL 1075U +#define SRST_PO_GPU_JTAG 1076U +/********Name=SOFTRST_CON68,Offset=0xB10********/ +#define SRST_A_AV1_NIU 1089U +#define SRST_A_AV1 1090U +#define SRST_P_AV1_NIU 1092U +#define SRST_P_AV1 1093U +/********Name=SOFTRST_CON69,Offset=0xB14********/ +#define SRST_A_DDR_NIU 1108U +#define SRST_A_DMA2DDR 1109U +#define SRST_A_DDR_SHAREMEM 1110U +#define SRST_A_DDR_SHAREMEM_NIU 1111U +#define SRST_A_CENTER_S200_NIU 1114U +#define SRST_A_CENTER_S400_NIU 1115U +#define SRST_H_AHB2APB 1116U +#define SRST_H_CENTER_NIU 1117U +#define SRST_F_DDR_CM0_CORE 1118U +/********Name=SOFTRST_CON70,Offset=0xB18********/ +#define SRST_DDR_TIMER0 1120U +#define SRST_DDR_TIMER1 1121U +#define SRST_T_WDT_DDR 1122U +#define SRST_T_DDR_CM0_JTAG 1123U +#define SRST_P_CENTER_GRF 1125U +#define SRST_P_AHB2APB 1126U +#define SRST_P_WDT 1127U +#define SRST_P_TIMER 1128U +#define SRST_P_DMA2DDR 1129U +#define SRST_P_SHAREMEM 1130U +#define SRST_P_CENTER_NIU 1131U +#define SRST_P_CENTER_CHANNEL_NIU 1132U +/********Name=SOFTRST_CON72,Offset=0xB20********/ +#define SRST_P_USBDPGRF0 1153U +#define SRST_P_USBDPPHY0 1154U +#define SRST_P_USBDPGRF1 1155U +#define SRST_P_USBDPPHY1 1156U +#define SRST_P_HDPTX0 1157U +#define SRST_P_HDPTX1 1158U +#define SRST_P_APB2ASB_SLV_BOT_RIGHT 1159U +#define SRST_P_USB2PHY_U3_0_GRF0 1160U +#define SRST_P_USB2PHY_U3_1_GRF0 1161U +#define SRST_P_USB2PHY_U2_0_GRF0 1162U +#define SRST_P_USB2PHY_U2_1_GRF0 1163U +#define SRST_SCAN_HDPTX0_ROPLL 1164U +#define SRST_SCAN_HDPTX0_LCPLL 1165U +#define SRST_SCAN_HDPTX0 1166U +#define SRST_SCAN_HDPTX1_ROPLL 1167U +/********Name=SOFTRST_CON73,Offset=0xB24********/ +#define SRST_SCAN_HDPTX1_LCPLL 1168U +#define SRST_SCAN_HDPTX1 1169U +#define SRST_SCAN_HDPTX0_HDMIRXPHY_SET 1170U +#define SRST_SCAN_USBDP_COMBO_PHY0 1171U +#define SRST_SCAN_USBDP_COMBO_PHY0_LCPLL 1172U +#define SRST_SCAN_USBDP_COMBO_PHY0_ROPLL 1173U +#define SRST_SCAN_USBDP_COMBO_PHY0_PCS_HS 1174U +#define SRST_SCAN_USBDP_COMBO_PHY1 1175U +#define SRST_SCAN_USBDP_COMBO_PHY1_LCPLL 1176U +#define SRST_SCAN_USBDP_COMBO_PHY1_ROPLL 1177U +#define SRST_SCAN_USBDP_COMBO_PHY1_PCS_HS 1178U +#define SRST_HDMIHDP0 1180U +#define SRST_HDMIHDP1 1181U +/********Name=SOFTRST_CON74,Offset=0xB28********/ +#define SRST_A_VO1USB_TOP_NIU 1185U +#define SRST_H_VO1USB_TOP_NIU 1187U +/********Name=SOFTRST_CON75,Offset=0xB2C********/ +#define SRST_H_SDIO_NIU 1201U +#define SRST_H_SDIO 1202U +#define SRST_SDIO 1203U +/********Name=SOFTRST_CON76,Offset=0xB30********/ +#define SRST_H_RGA3_NIU 1218U +#define SRST_A_RGA3_NIU 1219U +#define SRST_H_RGA3_1 1220U +#define SRST_A_RGA3_1 1221U +#define SRST_RGA3_1_CORE 1222U +/********Name=SOFTRST_CON77,Offset=0xB34********/ +#define SRST_REF_PIPE_PHY0 1238U +#define SRST_REF_PIPE_PHY1 1239U +#define SRST_REF_PIPE_PHY2 1240U +/********Name=PMU1SOFTRST_CON00,Offset=0xA00********/ +#define SRST_H_PMU1_NIU 26U +#define SRST_P_PMU1_NIU 27U +#define SRST_H_PMU_CM0_NIU 28U +#define SRST_F_PMU_CM0_CORE 29U +#define SRST_T_PMU1_CM0_JTAG 30U +/********Name=PMU1SOFTRST_CON01,Offset=0xA04********/ +#define SRST_DDR_FAIL_SAFE 17U +#define SRST_P_CRU_PMU1 18U +#define SRST_P_PMU1_GRF 20U +#define SRST_P_PMU1_IOC 21U +#define SRST_P_PMU1WDT 22U +#define SRST_T_PMU1WDT 23U +#define SRST_P_PMU1TIMER 24U +#define SRST_PMU1TIMER0 26U +#define SRST_PMU1TIMER1 27U +#define SRST_P_PMU1PWM 28U +#define SRST_PMU1PWM 29U +/********Name=PMU1SOFTRST_CON02,Offset=0xA08********/ +#define SRST_P_I2C0 17U +#define SRST_I2C0 18U +#define SRST_S_UART0 21U +#define SRST_P_UART0 22U +#define SRST_H_I2S1_8CH 23U +#define SRST_M_I2S1_8CH_TX 26U +#define SRST_M_I2S1_8CH_RX 29U +#define SRST_H_PDM0 30U +#define SRST_PDM0 31U +/********Name=PMU1SOFTRST_CON03,Offset=0xA0C********/ +#define SRST_H_VAD 16U +#define SRST_HDPTX0_INIT 27U +#define SRST_HDPTX0_CMN 28U +#define SRST_HDPTX0_LANE 29U +#define SRST_HDPTX1_INIT 31U +/********Name=PMU1SOFTRST_CON04,Offset=0xA10********/ +#define SRST_HDPTX1_CMN 16U +#define SRST_HDPTX1_LANE 17U +#define SRST_M_MIPI_DCPHY0 19U +#define SRST_S_MIPI_DCPHY0 20U +#define SRST_M_MIPI_DCPHY1 21U +#define SRST_S_MIPI_DCPHY1 22U +#define SRST_OTGPHY_U3_0 23U +#define SRST_OTGPHY_U3_1 24U +#define SRST_OTGPHY_U2_0 25U +#define SRST_OTGPHY_U2_1 26U +/********Name=PMU1SOFTRST_CON05,Offset=0xA14********/ +#define SRST_P_PMU0GRF 19U +#define SRST_P_PMU0IOC 20U +#define SRST_P_GPIO0 21U +#define SRST_DB_GPIO0 22U + +/********Name=GATE_CON00,Offset=0x800********/ +#define CLK_MATRIX_50M_SRC_GATE 0U +#define CLK_MATRIX_100M_SRC_GATE 1U +#define CLK_MATRIX_150M_SRC_GATE 2U +#define CLK_MATRIX_200M_SRC_GATE 3U +#define CLK_MATRIX_250M_SRC_GATE 4U +#define CLK_MATRIX_300M_SRC_GATE 5U +#define CLK_MATRIX_350M_SRC_GATE 6U +#define CLK_MATRIX_400M_SRC_GATE 7U +#define CLK_MATRIX_450M_SRC_GATE 8U +#define CLK_MATRIX_500M_SRC_GATE 9U +#define CLK_MATRIX_600M_SRC_GATE 10U +#define CLK_MATRIX_650M_SRC_GATE 11U +#define CLK_MATRIX_700M_SRC_GATE 12U +#define CLK_MATRIX_800M_SRC_GATE 13U +#define CLK_MATRIX_1000M_SRC_GATE 14U +#define CLK_MATRIX_1200M_SRC_GATE 15U +/********Name=GATE_CON01,Offset=0x804********/ +#define ACLK_TOP_ROOT_GATE 16U +#define PCLK_TOP_ROOT_GATE 17U +#define ACLK_LOW_TOP_ROOT_GATE 18U +#define ACLK_TOP_NIU_GATE 19U +#define PCLK_TOP_NIU_GATE 20U +#define ACLK_LOW_TOP_NIU_GATE 21U +#define PCLK_CSIPHY0_GATE 22U +#define PCLK_CSIPHY1_GATE 24U +#define ACLK_TOP_M300_ROOT_GATE 26U +#define ACLK_TOP_M500_ROOT_GATE 27U +#define ACLK_TOP_M400_ROOT_GATE 28U +#define ACLK_TOP_S200_ROOT_GATE 29U +#define ACLK_TOP_S400_ROOT_GATE 30U +#define ACLK_TOP_M500_NIU_GATE 31U +/********Name=GATE_CON02,Offset=0x808********/ +#define ACLK_TOP_M400_NIU_GATE 32U +#define ACLK_TOP_S200_NIU_GATE 33U +#define ACLK_TOP_S400_NIU_GATE 34U +#define ACLK_TOP_M300_NIU_GATE 35U +#define CLK_TESTOUT_TOP_GATE 36U +#define CLK_TESTOUT_GRP0_GATE 38U +#define CLK_USBDP_COMBO_PHY0_IMMORTAL_GATE 40U +#define CLK_USBDP_COMBO_PHY1_IMMORTAL_GATE 47U +/********Name=GATE_CON03,Offset=0x80C********/ +#define PCLK_MIPI_DCPHY0_GATE 62U +#define PCLK_MIPI_DCPHY0_GRF_GATE 63U +/********Name=GATE_CON04,Offset=0x810********/ +#define PCLK_MIPI_DCPHY1_GATE 67U +#define PCLK_MIPI_DCPHY1_GRF_GATE 68U +#define PCLK_APB2ASB_SLV_CDPHY_GATE 69U +#define PCLK_APB2ASB_SLV_CSIPHY_GATE 70U +#define PCLK_APB2ASB_SLV_VCCIO3_5_GATE 71U +#define PCLK_APB2ASB_SLV_VCCIO6_GATE 72U +#define PCLK_APB2ASB_SLV_EMMCIO_GATE 73U +#define PCLK_APB2ASB_SLV_IOC_TOP_GATE 74U +#define PCLK_APB2ASB_SLV_IOC_RIGHT_GATE 75U +/********Name=GATE_CON05,Offset=0x814********/ +#define PCLK_CRU_GATE 80U +#define XIN_OSC0_PAD_GATE 81U +#define XIN_OSC0_TMDECODER_GATE 82U +#define MCLK_GMAC0_OUT_GATE 83U +#define REFCLKO25M_ETH0_OUT_GATE 84U +#define REFCLKO25M_ETH1_OUT_GATE 85U +#define CLK_CIFOUT_OUT_GATE 86U +#define ACLK_CHANNEL_SECURE2VO1USB_GATE 87U +#define ACLK_CHANNEL_SECURE2CENTER_GATE 88U +#define CLK_MIPI_CAMERAOUT_M0_GATE 89U +#define CLK_MIPI_CAMERAOUT_M1_GATE 90U +#define CLK_MIPI_CAMERAOUT_M2_GATE 91U +#define CLK_MIPI_CAMERAOUT_M3_GATE 92U +#define CLK_MIPI_CAMERAOUT_M4_GATE 93U +#define HCLK_CHANNEL_SECURE2VO1USB_GATE 94U +#define HCLK_CHANNEL_SECURE2CENTER_GATE 95U +/********Name=GATE_CON06,Offset=0x818********/ +#define PCLK_CHANNEL_SECURE2VO1USB_GATE 96U +#define PCLK_CHANNEL_SECURE2CENTER_GATE 97U +/********Name=GATE_CON07,Offset=0x81C********/ +#define HCLK_AUDIO_ROOT_GATE 112U +#define PCLK_AUDIO_ROOT_GATE 113U +#define HCLK_AUDIO_NIU_GATE 114U +#define PCLK_AUDIO_NIU_GATE 115U +#define HCLK_I2S0_8CH_GATE 116U +#define CLK_I2S0_8CH_TX_GATE 117U +#define CLK_I2S0_8CH_FRAC_TX_GATE 118U +#define MCLK_I2S0_8CH_TX_GATE 119U +#define CLK_I2S0_8CH_RX_GATE 120U +#define CLK_I2S0_8CH_FRAC_RX_GATE 121U +#define MCLK_I2S0_8CH_RX_GATE 122U +#define PCLK_ACDCDIG_GATE 123U +#define HCLK_I2S2_2CH_GATE 124U +#define HCLK_I2S3_2CH_GATE 125U +#define CLK_I2S2_2CH_GATE 126U +#define CLK_I2S2_2CH_FRAC_GATE 127U +/********Name=GATE_CON08,Offset=0x820********/ +#define MCLK_I2S2_2CH_GATE 128U +#define CLK_I2S3_2CH_GATE 129U +#define CLK_I2S3_2CH_FRAC_GATE 130U +#define MCLK_I2S3_2CH_GATE 131U +#define CLK_DAC_ACDCDIG_GATE 132U +#define HCLK_SPDIF0_GATE 142U +#define CLK_SPDIF0_GATE 143U +/********Name=GATE_CON09,Offset=0x824********/ +#define CLK_SPDIF0_FRAC_GATE 144U +#define MCLK_SPDIF0_GATE 145U +#define HCLK_SPDIF1_GATE 146U +#define CLK_SPDIF1_GATE 147U +#define CLK_SPDIF1_FRAC_GATE 148U +#define MCLK_SPDIF1_GATE 149U +#define HCLK_PDM1_GATE 150U +#define MCLK_PDM1_GATE 151U +#define MBIST_CLK_MCLK_PDM1_GATE 152U +#define MBIST_CLK_CLK_ACDCDIG_GATE 153U +/********Name=GATE_CON10,Offset=0x828********/ +#define ACLK_BUS_ROOT_GATE 160U +#define ACLK_BUS_NIU_GATE 161U +#define PCLK_BUS_NIU_GATE 162U +#define ACLK_GIC_GATE 163U +#define ACLK_DMAC0_GATE 165U +#define ACLK_DMAC1_GATE 166U +#define ACLK_DMAC2_GATE 167U +#define PCLK_I2C1_GATE 168U +#define PCLK_I2C2_GATE 169U +#define PCLK_I2C3_GATE 170U +#define PCLK_I2C4_GATE 171U +#define PCLK_I2C5_GATE 172U +#define PCLK_I2C6_GATE 173U +#define PCLK_I2C7_GATE 174U +#define PCLK_I2C8_GATE 175U +/********Name=GATE_CON11,Offset=0x82C********/ +#define CLK_I2C1_GATE 176U +#define CLK_I2C2_GATE 177U +#define CLK_I2C3_GATE 178U +#define CLK_I2C4_GATE 179U +#define CLK_I2C5_GATE 180U +#define CLK_I2C6_GATE 181U +#define CLK_I2C7_GATE 182U +#define CLK_I2C8_GATE 183U +#define PCLK_CAN0_GATE 184U +#define CLK_CAN0_GATE 185U +#define PCLK_CAN1_GATE 186U +#define CLK_CAN1_GATE 187U +#define PCLK_CAN2_GATE 188U +#define CLK_CAN2_GATE 189U +#define PCLK_SARADC_GATE 190U +#define CLK_SARADC_GATE 191U +/********Name=GATE_CON12,Offset=0x830********/ +#define PCLK_TSADC_GATE 192U +#define CLK_TSADC_GATE 193U +#define PCLK_UART1_GATE 194U +#define PCLK_UART2_GATE 195U +#define PCLK_UART3_GATE 196U +#define PCLK_UART4_GATE 197U +#define PCLK_UART5_GATE 198U +#define PCLK_UART6_GATE 199U +#define PCLK_UART7_GATE 200U +#define PCLK_UART8_GATE 201U +#define PCLK_UART9_GATE 202U +#define CLK_UART1_GATE 203U +#define CLK_UART1_FRAC_GATE 204U +#define SCLK_UART1_GATE 205U +#define CLK_UART2_GATE 206U +#define CLK_UART2_FRAC_GATE 207U +/********Name=GATE_CON13,Offset=0x834********/ +#define SCLK_UART2_GATE 208U +#define CLK_UART3_GATE 209U +#define CLK_UART3_FRAC_GATE 210U +#define SCLK_UART3_GATE 211U +#define CLK_UART4_GATE 212U +#define CLK_UART4_FRAC_GATE 213U +#define SCLK_UART4_GATE 214U +#define CLK_UART5_GATE 215U +#define CLK_UART5_FRAC_GATE 216U +#define SCLK_UART5_GATE 217U +#define CLK_UART6_GATE 218U +#define CLK_UART6_FRAC_GATE 219U +#define SCLK_UART6_GATE 220U +#define CLK_UART7_GATE 221U +#define CLK_UART7_FRAC_GATE 222U +#define SCLK_UART7_GATE 223U +/********Name=GATE_CON14,Offset=0x838********/ +#define CLK_UART8_GATE 224U +#define CLK_UART8_FRAC_GATE 225U +#define SCLK_UART8_GATE 226U +#define CLK_UART9_GATE 227U +#define CLK_UART9_FRAC_GATE 228U +#define SCLK_UART9_GATE 229U +#define PCLK_SPI0_GATE 230U +#define PCLK_SPI1_GATE 231U +#define PCLK_SPI2_GATE 232U +#define PCLK_SPI3_GATE 233U +#define PCLK_SPI4_GATE 234U +#define CLK_SPI0_GATE 235U +#define CLK_SPI1_GATE 236U +#define CLK_SPI2_GATE 237U +#define CLK_SPI3_GATE 238U +#define CLK_SPI4_GATE 239U +/********Name=GATE_CON15,Offset=0x83C********/ +#define PCLK_WDT0_GATE 240U +#define TCLK_WDT0_GATE 241U +#define PCLK_SYS_GRF_GATE 242U +#define PCLK_PWM1_GATE 243U +#define CLK_PWM1_GATE 244U +#define CLK_PWM1_CAPTURE_GATE 245U +#define PCLK_PWM2_GATE 246U +#define CLK_PWM2_GATE 247U +#define CLK_PWM2_CAPTURE_GATE 248U +#define PCLK_PWM3_GATE 249U +#define CLK_PWM3_GATE 250U +#define CLK_PWM3_CAPTURE_GATE 251U +#define PCLK_BUSTIMER0_GATE 252U +#define PCLK_BUSTIMER1_GATE 253U +#define CLK_BUSTIMER_ROOT_GATE 254U +#define CLK_BUSTIMER0_GATE 255U +/********Name=GATE_CON16,Offset=0x840********/ +#define CLK_BUSTIMER1_GATE 256U +#define CLK_BUSTIMER2_GATE 257U +#define CLK_BUSTIMER3_GATE 258U +#define CLK_BUSTIMER4_GATE 259U +#define CLK_BUSTIMER5_GATE 260U +#define CLK_BUSTIMER6_GATE 261U +#define CLK_BUSTIMER7_GATE 262U +#define CLK_BUSTIMER8_GATE 263U +#define CLK_BUSTIMER9_GATE 264U +#define CLK_BUSTIMER10_GATE 265U +#define CLK_BUSTIMER11_GATE 266U +#define PCLK_MAILBOX0_GATE 267U +#define PCLK_MAILBOX1_GATE 268U +#define PCLK_MAILBOX2_GATE 269U +#define PCLK_GPIO1_GATE 270U +#define DBCLK_GPIO1_GATE 271U +/********Name=GATE_CON17,Offset=0x844********/ +#define PCLK_GPIO2_GATE 272U +#define DBCLK_GPIO2_GATE 273U +#define PCLK_GPIO3_GATE 274U +#define DBCLK_GPIO3_GATE 275U +#define PCLK_GPIO4_GATE 276U +#define DBCLK_GPIO4_GATE 277U +#define ACLK_DECOM_GATE 278U +#define PCLK_DECOM_GATE 279U +#define DCLK_DECOM_GATE 280U +#define PCLK_TOP_GATE 281U +#define ACLK_GICADB_CORE2GIC_BUS_GATE 282U +#define ACLK_GICADB_GIC2CORE_BUS_GATE 283U +#define PCLK_DFT2APB_GATE 284U +#define PCLK_APB2ASB_MST_TOP_GATE 285U +#define PCLK_APB2ASB_MST_CDPHY_GATE 286U +#define PCLK_APB2ASB_MST_BOT_RIGHT_GATE 287U +/********Name=GATE_CON18,Offset=0x848********/ +#define PCLK_APB2ASB_MST_IOC_TOP_GATE 288U +#define PCLK_APB2ASB_MST_IOC_RIGHT_GATE 289U +#define PCLK_APB2ASB_MST_CSIPHY_GATE 290U +#define PCLK_APB2ASB_MST_VCCIO3_5_GATE 291U +#define PCLK_APB2ASB_MST_VCCIO6_GATE 292U +#define PCLK_APB2ASB_MST_EMMCIO_GATE 293U +#define ACLK_SPINLOCK_GATE 294U +#define PCLK_OTPC_TM_GATE 295U +#define CLK_OTPC_TM_GATE 296U +#define PCLK_OTPC_NS_GATE 297U +#define CLK_OTPC_NS_GATE 298U +#define CLK_OTPC_ARB_GATE 299U +#define CLK_OTPC_AUTO_RD_GATE 300U +#define CLK_OTP_PHY_GATE 301U +#define PCLK_JDBCK_DFT_GATE 302U +#define CLK_JDBCK_DFT_GATE 303U +/********Name=GATE_CON19,Offset=0x84C********/ +#define PCLK_BUSIOC_GATE 304U +#define CLK_BISRINTF_PLLSRC_GATE 305U +#define CLK_BISRINTF_GATE 306U +#define PCLK_PMU2_GATE 307U +#define PCLK_PMUCM0_INTMUX_GATE 308U +#define PCLK_DDRCM0_INTMUX_GATE 309U +#define MBIST_CLK_ACLK_DECOM_GATE 310U +/********Name=GATE_CON20,Offset=0x850********/ +#define PCLK_DDR_DFICTL_CH0_GATE 320U +#define PCLK_DDR_MON_CH0_GATE 321U +#define PCLK_DDR_STANDBY_CH0_GATE 322U +#define PCLK_DDR_UPCTL_CH0_GATE 323U +#define TMCLK_DDR_MON_CH0_GATE 324U +#define PCLK_DDR_GRF_CH01_GATE 325U +#define CLK_DFI_CH0_GATE 326U +#define CLK_SBR_CH0_GATE 327U +#define CLK_DDR_UPCTL_CH0_GATE 328U +#define CLK_DDR_DFICTL_CH0_GATE 329U +#define CLK_DDR_MON_CH0_GATE 330U +#define CLK_DDR_STANDBY_CH0_GATE 331U +#define ACLK_DDR_UPCTL_CH0_GATE 332U +#define PCLK_DDR_DFICTL_CH1_GATE 333U +#define PCLK_DDR_MON_CH1_GATE 334U +#define PCLK_DDR_STANDBY_CH1_GATE 335U +/********Name=GATE_CON21,Offset=0x854********/ +#define PCLK_DDR_UPCTL_CH1_GATE 336U +#define TMCLK_DDR_MON_CH1_GATE 337U +#define CLK_DFI_CH1_GATE 338U +#define CLK_SBR_CH1_GATE 339U +#define CLK_DDR_UPCTL_CH1_GATE 340U +#define CLK_DDR_DFICTL_CH1_GATE 341U +#define CLK_DDR_MON_CH1_GATE 342U +#define CLK_DDR_STANDBY_CH1_GATE 343U +#define ACLK_DDR_UPCTL_CH1_GATE 344U +#define MBIST_CLK_CLK_DDR_UPCTRL_CH0_GATE 345U +#define MBIST_CLK_CLK_DDR_UPCTRL_CH1_GATE 346U +#define MBIST_CLK_ACLK_DDR01_MSCH_CH0_GATE 347U +#define MBIST_CLK_ACLK_DDR01_MSCH_CH1_GATE 348U +#define ACLK_DDR01_MSCH0_GATE 349U +#define ACLK_DDR01_RS_MSCH0_GATE 350U +#define ACLK_DDR01_FRS_MSCH0_GATE 351U +/********Name=GATE_CON22,Offset=0x858********/ +#define ACLK_DDR01_SCRAMBLE0_GATE 352U +#define ACLK_DDR01_FRS_SCRAMBLE0_GATE 353U +#define ACLK_DDR01_MSCH1_GATE 354U +#define ACLK_DDR01_RS_MSCH1_GATE 355U +#define ACLK_DDR01_FRS_MSCH1_GATE 356U +#define ACLK_DDR01_SCRAMBLE1_GATE 357U +#define ACLK_DDR01_FRS_SCRAMBLE1_GATE 358U +#define PCLK_DDR01_MSCH0_GATE 359U +#define PCLK_DDR01_MSCH1_GATE 360U +#define CLK_TESTOUT_DDR01_GATE 361U +/********Name=GATE_CON23,Offset=0x85C********/ +#define PCLK_DDR_DFICTL_CH2_GATE 368U +#define PCLK_DDR_MON_CH2_GATE 369U +#define PCLK_DDR_STANDBY_CH2_GATE 370U +#define PCLK_DDR_UPCTL_CH2_GATE 371U +#define TMCLK_DDR_MON_CH2_GATE 372U +#define PCLK_DDR_GRF_CH23_GATE 373U +#define CLK_DFI_CH2_GATE 374U +#define CLK_SBR_CH2_GATE 375U +#define CLK_DDR_UPCTL_CH2_GATE 376U +#define CLK_DDR_DFICTL_CH2_GATE 377U +#define CLK_DDR_MON_CH2_GATE 378U +#define CLK_DDR_STANDBY_CH2_GATE 379U +#define ACLK_DDR_UPCTL_CH2_GATE 380U +#define PCLK_DDR_DFICTL_CH3_GATE 381U +#define PCLK_DDR_MON_CH3_GATE 382U +#define PCLK_DDR_STANDBY_CH3_GATE 383U +/********Name=GATE_CON24,Offset=0x860********/ +#define PCLK_DDR_UPCTL_CH3_GATE 384U +#define TMCLK_DDR_MON_CH3_GATE 385U +#define CLK_DFI_CH3_GATE 386U +#define CLK_SBR_CH3_GATE 387U +#define CLK_DDR_UPCTL_CH3_GATE 388U +#define CLK_DDR_DFICTL_CH3_GATE 389U +#define CLK_DDR_MON_CH3_GATE 390U +#define CLK_DDR_STANDBY_CH3_GATE 391U +#define ACLK_DDR_UPCTL_CH3_GATE 392U +#define MBIST_CLK_CLK_DDR_UPCTRL_CH2_GATE 393U +#define MBIST_CLK_CLK_DDR_UPCTRL_CH3_GATE 394U +#define MBIST_CLK_ACLK_DDR23_MSCH_CH2_GATE 395U +#define MBIST_CLK_ACLK_DDR23_MSCH_CH3_GATE 396U +#define ACLK_DDR23_MSCH2_GATE 397U +#define ACLK_DDR23_RS_MSCH2_GATE 398U +#define ACLK_DDR23_FRS_MSCH2_GATE 399U +/********Name=GATE_CON25,Offset=0x864********/ +#define ACLK_DDR23_SCRAMBLE2_GATE 400U +#define ACLK_DDR23_FRS_SCRAMBLE2_GATE 401U +#define ACLK_DDR23_MSCH3_GATE 402U +#define ACLK_DDR23_RS_MSCH3_GATE 403U +#define ACLK_DDR23_FRS_MSCH3_GATE 404U +#define ACLK_DDR23_SCRAMBLE3_GATE 405U +#define ACLK_DDR23_FRS_SCRAMBLE3_GATE 406U +#define PCLK_DDR23_MSCH2_GATE 407U +#define PCLK_DDR23_MSCH3_GATE 408U +#define CLK_TESTOUT_DDR23_GATE 409U +/********Name=GATE_CON26,Offset=0x868********/ +#define ACLK_ISP1_ROOT_GATE 416U +#define HCLK_ISP1_ROOT_GATE 417U +#define CLK_ISP1_CORE_GATE 418U +#define CLK_ISP1_CORE_MARVIN_GATE 419U +#define CLK_ISP1_CORE_VICAP_GATE 420U +#define ACLK_ISP1_GATE 421U +#define ACLK_ISP1_NIU_GATE 422U +#define HCLK_ISP1_GATE 423U +#define HCLK_ISP1_NIU_GATE 424U +#define MBIST_CLK_CLK_ISP1_CORE_GATE 425U +#define MBIST_CLK_ACLK_ISP1_GATE 426U +#define MBIST_CLK_HCLK_ISP1_GATE 427U +/********Name=GATE_CON27,Offset=0x86C********/ +#define ACLK_RKNN1_GATE 432U +#define ACLK_RKNN1_NIU_GATE 433U +#define HCLK_RKNN1_GATE 434U +#define HCLK_RKNN1_NIU_GATE 435U +/********Name=GATE_CON28,Offset=0x870********/ +#define ACLK_RKNN2_GATE 448U +#define ACLK_RKNN2_NIU_GATE 449U +#define HCLK_RKNN2_GATE 450U +#define HCLK_RKNN2_NIU_GATE 451U +/********Name=GATE_CON29,Offset=0x874********/ +#define HCLK_RKNN_ROOT_GATE 464U +#define CLK_RKNN_DSU0_DF_GATE 465U +#define CLK_TESTOUT_NPU_GATE 466U +#define CLK_RKNN_DSU0_GATE 467U +#define PCLK_NPUTOP_ROOT_GATE 468U +#define PCLK_NPUTOP_NIU_GATE 469U +#define PCLK_NPU_TIMER_GATE 470U +#define CLK_NPUTIMER_ROOT_GATE 471U +#define CLK_NPUTIMER0_GATE 472U +#define CLK_NPUTIMER1_GATE 473U +#define PCLK_NPU_WDT_GATE 474U +#define TCLK_NPU_WDT_GATE 475U +#define PCLK_PVTM1_GATE 476U +#define PCLK_NPU_GRF_GATE 477U +#define CLK_PVTM1_GATE 478U +#define CLK_NPU_PVTM_GATE 479U +/********Name=GATE_CON30,Offset=0x878********/ +#define CLK_NPU_PVTPLL_GATE 480U +#define HCLK_NPU_CM0_ROOT_GATE 481U +#define HCLK_NPU_CM0_NIU_GATE 482U +#define FCLK_NPU_CM0_CORE_GATE 483U +#define CLK_NPU_CM0_RTC_GATE 485U +#define ACLK_RKNN0_GATE 486U +#define ACLK_RKNN0_NIU_GATE 487U +#define HCLK_RKNN0_GATE 488U +#define HCLK_RKNN0_NIU_GATE 489U +/********Name=GATE_CON31,Offset=0x87C********/ +#define HCLK_NVM_ROOT_GATE 496U +#define ACLK_NVM_ROOT_GATE 497U +#define HCLK_NVM_NIU_GATE 498U +#define ACLK_NVM_NIU_GATE 499U +#define HCLK_EMMC_GATE 500U +#define ACLK_EMMC_GATE 501U +#define CCLK_EMMC_GATE 502U +#define BCLK_EMMC_GATE 503U +#define TMCLK_EMMC_GATE 504U +#define SCLK_SFC_GATE 505U +#define HCLK_SFC_GATE 506U +#define HCLK_SFC_XIP_GATE 507U +#define MBIST_CLK_EMMC_GATE 508U +/********Name=GATE_CON32,Offset=0x880********/ +#define PCLK_PHP_ROOT_GATE 512U +#define PCLK_GRF_GATE 513U +#define PCLK_DEC_NIU_GATE 514U +#define PCLK_GMAC0_GATE 515U +#define PCLK_GMAC1_GATE 516U +#define PCLK_PHP_NIU_GATE 517U +#define ACLK_PCIE_ROOT_GATE 518U +#define ACLK_PHP_ROOT_GATE 519U +#define ACLK_PCIE_GRIDGE_GATE 520U +#define ACLK_PHP_NIU_GATE 521U +#define ACLK_GMAC0_GATE 522U +#define ACLK_GMAC1_GATE 523U +#define ACLK_PCIE_NIU_GATE 524U +#define ACLK_PCIE_DBI0_GATE 525U +#define ACLK_PCIE_DBI1_GATE 526U +#define ACLK_PCIE_DBI2_GATE 527U +/********Name=GATE_CON33,Offset=0x884********/ +#define ACLK_PCIE_DBI3_GATE 528U +#define ACLK_PCIE_DBI4_GATE 529U +#define ACLK_PCIE_MSTR0_GATE 530U +#define ACLK_PCIE_MSTR1_GATE 531U +#define ACLK_PCIE_MSTR2_GATE 532U +#define ACLK_PCIE_MSTR3_GATE 533U +#define ACLK_PCIE_MSTR4_GATE 534U +#define ACLK_PCIE_SLV0_GATE 535U +#define ACLK_PCIE_SLV1_GATE 536U +#define ACLK_PCIE_SLV2_GATE 537U +#define ACLK_PCIE_SLV3_GATE 538U +#define ACLK_PCIE_SLV4_GATE 539U +#define PCLK_PCIE0_GATE 540U +#define PCLK_PCIE1_GATE 541U +#define PCLK_PCIE2_GATE 542U +#define PCLK_PCIE3_GATE 543U +/********Name=GATE_CON34,Offset=0x888********/ +#define PCLK_PCIE4_GATE 544U +#define CLK_PCIE_AUX0_GATE 545U +#define CLK_PCIE_AUX1_GATE 546U +#define CLK_PCIE_AUX2_GATE 547U +#define CLK_PCIE_AUX3_GATE 548U +#define CLK_PCIE_AUX4_GATE 549U +#define ACLK_PHP_GIC_ITS_GATE 550U +#define ACLK_MMU_PCIE_GATE 551U +#define ACLK_MMU_PHP_GATE 552U +#define ACLK_MMU_NIU_GATE 553U +#define CLK_GMAC0_PTP_REF_GATE 554U +#define CLK_GMAC1_PTP_REF_GATE 555U +/********Name=GATE_CON35,Offset=0x88C********/ +#define CLK_GMAC_125M_CRU_GATE 565U +#define CLK_GMAC_50M_CRU_GATE 566U +#define ACLK_USB3OTG2_GATE 567U +#define SUSPEND_CLK_USB3OTG2_GATE 568U +#define REF_CLK_USB3OTG2_GATE 569U +#define CLK_UTMI_OTG2_GATE 570U +#define MBIST_CLK_ACLK_SATA0_GATE 571U +#define MBIST_CLK_ACLK_SATA1_GATE 572U +#define MBIST_CLK_ACLK_SATA2_GATE 573U +#define MBIST_CLK_CLK_PCIE4L_PIPE_GATE 574U +#define MBIST_CLK_ACLK_PCIE_MSTR0_GATE 575U +/********Name=GATE_CON36,Offset=0x890********/ +#define MBIST_CLK_ACLK_PCIE_SLV0_GATE 576U +#define MBIST_CLK_CLK_PCIE2L_PIPE_GATE 577U +#define MBIST_CLK_ACLK_PCIE_MSTR1_GATE 578U +#define MBIST_CLK_ACLK_PCIE_SLV1_GATE 579U +#define MBIST_CLK_CLK_PCIE1L0_PIPE_GATE 580U +#define MBIST_CLK_ACLK_PCIE_MSTR2_GATE 581U +#define MBIST_CLK_ACLK_PCIE_SLV2_GATE 582U +#define MBIST_CLK_CLK_PCIE1L1_PIPE_GATE 583U +#define MBIST_CLK_ACLK_PCIE_MSTR3_GATE 584U +#define MBIST_CLK_ACLK_PCIE_SLV3_GATE 585U +#define MBIST_CLK_CLK_PCIE1L2_PIPE_GATE 586U +#define MBIST_CLK_ACLK_PCIE_MSTR4_GATE 587U +#define MBIST_CLK_ACLK_PCIE_SLV4_GATE 588U +#define MBIST_CLK_ACLK_GMAC0_GATE 589U +#define MBIST_CLK_ACLK_GMAC1_GATE 590U +#define MBIST_CLK_ACLK_USB3OTG2_GATE 591U +/********Name=GATE_CON37,Offset=0x894********/ +#define CLK_PIPEPHY0_REF_GATE 592U +#define CLK_PIPEPHY1_REF_GATE 593U +#define CLK_PIPEPHY2_REF_GATE 594U +#define CLK_PMALIVE0_GATE 596U +#define CLK_PMALIVE1_GATE 597U +#define CLK_PMALIVE2_GATE 598U +#define ACLK_SATA0_GATE 599U +#define ACLK_SATA1_GATE 600U +#define ACLK_SATA2_GATE 601U +#define CLK_RXOOB0_GATE 602U +#define CLK_RXOOB1_GATE 603U +#define CLK_RXOOB2_GATE 604U +/********Name=GATE_CON38,Offset=0x898********/ +#define CLK_PIPEPHY0_PIPE_G_GATE 611U +#define CLK_PIPEPHY1_PIPE_G_GATE 612U +#define CLK_PIPEPHY2_PIPE_G_GATE 613U +#define CLK_PIPEPHY0_PIPE_ASIC_G_GATE 614U +#define CLK_PIPEPHY1_PIPE_ASIC_G_GATE 615U +#define CLK_PIPEPHY2_PIPE_ASIC_G_GATE 616U +#define CLK_PIPEPHY2_PIPE_U3_G_GATE 617U +#define CLK_PCIE1L2_PIPE_GATE 621U +#define CLK_PCIE1L0_PIPE_GATE 622U +#define CLK_PCIE1L1_PIPE_GATE 623U +/********Name=GATE_CON39,Offset=0x89C********/ +#define CLK_PCIE4L_PIPE_GATE 624U +#define CLK_PCIE2L_PIPE_GATE 625U +/********Name=GATE_CON40,Offset=0x8A0********/ +#define HCLK_RKVDEC0_ROOT_GATE 640U +#define ACLK_RKVDEC0_ROOT_GATE 641U +#define ACLK_RKVDEC_CCU_GATE 642U +#define HCLK_RKVDEC0_GATE 643U +#define ACLK_RKVDEC0_GATE 644U +#define HCLK_RKVDEC0_NIU_GATE 645U +#define ACLK_RKVDEC0_NIU_GATE 646U +#define CLK_RKVDEC0_CA_GATE 647U +#define CLK_RKVDEC0_HEVC_CA_GATE 648U +#define CLK_RKVDEC0_CORE_GATE 649U +#define MBIST_CLK_ACLK_RKVDEC0_GATE 650U +#define MBIST_CLK_CLK_RKVDEC0_HEVC_CA_GATE 651U +#define MBIST_CLK_CLK_RKVDEC0_CORE_GATE 652U +#define MBIST_CLK_CLK_RKVDEC0_CA_GATE 653U +/********Name=GATE_CON41,Offset=0x8A4********/ +#define HCLK_RKVDEC1_ROOT_GATE 656U +#define ACLK_RKVDEC1_ROOT_GATE 657U +#define HCLK_RKVDEC1_GATE 658U +#define ACLK_RKVDEC1_GATE 659U +#define HCLK_RKVDEC1_NIU_GATE 660U +#define ACLK_RKVDEC1_NIU_GATE 661U +#define CLK_RKVDEC1_CA_GATE 662U +#define CLK_RKVDEC1_HEVC_CA_GATE 663U +#define CLK_RKVDEC1_CORE_GATE 664U +#define MBIST_CLK_ACLK_RKVDEC1_GATE 665U +#define MBIST_CLK_CLK_RKVDEC1_HEVC_CA_GATE 666U +#define MBIST_CLK_CLK_RKVDEC1_CORE_GATE 667U +#define MBIST_CLK_CLK_RKVDEC1_CA_GATE 668U +/********Name=GATE_CON42,Offset=0x8A8********/ +#define ACLK_USB_ROOT_GATE 672U +#define HCLK_USB_ROOT_GATE 673U +#define ACLK_USB_NIU_GATE 674U +#define HCLK_USB_NIU_GATE 675U +#define ACLK_USB3OTG0_GATE 676U +#define SUSPEND_CLK_USB3OTG0_GATE 677U +#define REF_CLK_USB3OTG0_GATE 678U +#define ACLK_USB3OTG1_GATE 679U +#define SUSPEND_CLK_USB3OTG1_GATE 680U +#define REF_CLK_USB3OTG1_GATE 681U +#define HCLK_HOST0_GATE 682U +#define HCLK_HOST_ARB0_GATE 683U +#define HCLK_HOST1_GATE 684U +#define HCLK_HOST_ARB1_GATE 685U +#define ACLK_USB_GRF_GATE 686U +#define UTMI_OHCI_CLK48_HOST0_GATE 687U +/********Name=GATE_CON43,Offset=0x8AC********/ +#define UTMI_OHCI_CLK48_HOST1_GATE 688U +#define MBIST_CLK_HCLK_HOST0_GATE 691U +#define MBIST_CLK_HCLK_HOST1_GATE 692U +#define MBIST_CLK_ACLK_USB3OTG0_GATE 693U +#define MBIST_CLK_ACLK_USB3OTG1_GATE 694U +/********Name=GATE_CON44,Offset=0x8B0********/ +#define ACLK_VDPU_ROOT_GATE 704U +#define ACLK_VDPU_LOW_ROOT_GATE 705U +#define HCLK_VDPU_ROOT_GATE 706U +#define ACLK_JPEG_DECODER_ROOT_GATE 707U +#define ACLK_VDPU_NIU_GATE 708U +#define ACLK_VDPU_LOW_NIU_GATE 709U +#define HCLK_VDPU_NIU_GATE 710U +#define ACLK_JPEG_DECODER_NIU_GATE 711U +#define ACLK_VPU_GATE 712U +#define HCLK_VPU_GATE 713U +#define ACLK_JPEG_ENCODER0_GATE 714U +#define HCLK_JPEG_ENCODER0_GATE 715U +#define ACLK_JPEG_ENCODER1_GATE 716U +#define HCLK_JPEG_ENCODER1_GATE 717U +#define ACLK_JPEG_ENCODER2_GATE 718U +#define HCLK_JPEG_ENCODER2_GATE 719U +/********Name=GATE_CON45,Offset=0x8B4********/ +#define ACLK_JPEG_ENCODER3_GATE 720U +#define HCLK_JPEG_ENCODER3_GATE 721U +#define ACLK_JPEG_DECODER_GATE 722U +#define HCLK_JPEG_DECODER_GATE 723U +#define HCLK_IEP2P0_GATE 724U +#define ACLK_IEP2P0_GATE 725U +#define CLK_IEP2P0_CORE_GATE 726U +#define HCLK_RGA2_GATE 727U +#define ACLK_RGA2_GATE 728U +#define CLK_RGA2_CORE_GATE 729U +#define HCLK_RGA3_0_GATE 730U +#define ACLK_RGA3_0_GATE 731U +#define CLK_RGA3_0_CORE_GATE 732U +#define MBIST_CLK_ACLK_RGA3_0_GATE 733U +#define MBIST_CLK_CLK_RGA3_0_CORE_GATE 734U +#define MBIST_CLK_CLK_RGA2_GATE 735U +/********Name=GATE_CON46,Offset=0x8B8********/ +#define MBIST_CLK_ACLK_IEP2P0_GATE 736U +#define MBIST_CLK_CLK_IEP2P0_CORE_GATE 737U +#define MBIST_CLK_ACLK_JPEG_ENCODER0_GATE 738U +#define MBIST_CLK_ACLK_JPEG_ENCODER1_GATE 739U +#define MBIST_CLK_ACLK_JPEG_ENCODER2_GATE 740U +#define MBIST_CLK_ACLK_JPEG_ENCODER3_GATE 741U +#define MBIST_CLK_ACLK_JPEG_DECODER_GATE 742U +#define MBIST_CLK_ACLK_VPU_GATE 743U +/********Name=GATE_CON47,Offset=0x8BC********/ +#define HCLK_RKVENC0_ROOT_GATE 752U +#define ACLK_RKVENC0_ROOT_GATE 753U +#define HCLK_RKVENC0_NIU_GATE 754U +#define ACLK_RKVENC0_NIU_GATE 755U +#define HCLK_RKVENC0_GATE 756U +#define ACLK_RKVENC0_GATE 757U +#define CLK_RKVENC0_CORE_GATE 758U +/********Name=GATE_CON48,Offset=0x8C0********/ +#define HCLK_RKVENC1_ROOT_GATE 768U +#define ACLK_RKVENC1_ROOT_GATE 769U +#define HCLK_RKVENC1_NIU_GATE 770U +#define ACLK_RKVENC1_NIU_GATE 771U +#define HCLK_RKVENC1_GATE 772U +#define ACLK_RKVENC1_GATE 773U +#define CLK_RKVENC1_CORE_GATE 774U +/********Name=GATE_CON49,Offset=0x8C4********/ +#define ACLK_VI_ROOT_GATE 784U +#define HCLK_VI_ROOT_GATE 785U +#define PCLK_VI_ROOT_GATE 786U +#define ACLK_VI_NIU_GATE 787U +#define HCLK_VI_NIU_GATE 788U +#define PCLK_VI_NIU_GATE 789U +#define DCLK_VICAP_GATE 790U +#define ACLK_VICAP_GATE 791U +#define HCLK_VICAP_GATE 792U +#define CLK_ISP0_CORE_GATE 793U +#define CLK_ISP0_CORE_MARVIN_GATE 794U +#define CLK_ISP0_CORE_VICAP_GATE 795U +#define ACLK_ISP0_GATE 796U +#define HCLK_ISP0_GATE 797U +#define ACLK_FISHEYE0_GATE 798U +#define HCLK_FISHEYE0_GATE 799U +/********Name=GATE_CON50,Offset=0x8C8********/ +#define CLK_FISHEYE0_CORE_GATE 800U +#define ACLK_FISHEYE1_GATE 801U +#define HCLK_FISHEYE1_GATE 802U +#define CLK_FISHEYE1_CORE_GATE 803U +#define PCLK_CSI_HOST_0_GATE 804U +#define PCLK_CSI_HOST_1_GATE 805U +#define PCLK_CSI_HOST_2_GATE 806U +#define PCLK_CSI_HOST_3_GATE 807U +#define PCLK_CSI_HOST_4_GATE 808U +#define PCLK_CSI_HOST_5_GATE 809U +#define MBIST_CLK_CLK_ISP0_CORE_GATE 810U +#define MBIST_CLK_ACLK_ISP0_GATE 811U +#define MBIST_CLK_ACLK_VICAP_GATE 812U +#define MBIST_CLK_VICAP_CLK_ISP0_CORE_GATE 813U +#define MBIST_CLK_VICAP_CLK_ISP1_CORE_GATE 814U +#define MBIST_CLK_ACLK_FISHEYE0_GATE 815U +/********Name=GATE_CON51,Offset=0x8CC********/ +#define MBIST_CLK_CLK_FISHEYE0_CORE_GATE 816U +#define MBIST_CLK_ACLK_FISHEYE1_GATE 817U +#define MBIST_CLK_CLK_FISHEYE1_CORE_GATE 818U +#define MBIST_CLK_DCLK_VICAP_GATE 819U +#define CLK_CSIHOST0_VICAP_GATE 820U +#define CLK_CSIHOST1_VICAP_GATE 821U +#define CLK_CSIHOST2_VICAP_GATE 822U +#define CLK_CSIHOST3_VICAP_GATE 823U +#define CLK_CSIHOST4_VICAP_GATE 824U +#define CLK_CSIHOST5_VICAP_GATE 825U +#define ICLK_CSIHOST01_GATE 826U +#define ICLK_CSIHOST0_GATE 827U +#define ICLK_CSIHOST1_GATE 828U +/********Name=GATE_CON52,Offset=0x8D0********/ +#define ACLK_VOP_ROOT_GATE 832U +#define ACLK_VOP_LOW_ROOT_GATE 833U +#define HCLK_VOP_ROOT_GATE 834U +#define PCLK_VOP_ROOT_GATE 835U +#define ACLK_VOP_NIU_GATE 836U +#define ACLK_VOP_LOW_NIU_GATE 837U +#define HCLK_VOP_NIU_GATE 838U +#define PCLK_VOP_NIU_GATE 839U +#define HCLK_VOP_GATE 840U +#define ACLK_VOP_GATE 841U +#define DCLK_VOP0_SRC_GATE 842U +#define DCLK_VOP1_SRC_GATE 843U +#define DCLK_VOP2_SRC_GATE 844U +#define DCLK_VOP0_GATE 845U +/********Name=GATE_CON53,Offset=0x8D4********/ +#define DCLK_VOP1_GATE 848U +#define DCLK_VOP2_GATE 849U +#define DCLK_VOP3_GATE 850U +#define PCLK_VOPGRF_GATE 851U +#define PCLK_DSIHOST0_GATE 852U +#define PCLK_DSIHOST1_GATE 853U +#define CLK_DSIHOST0_GATE 854U +#define CLK_DSIHOST1_GATE 855U +#define CLK_VOP_PMU_GATE 856U +#define PCLK_VOP_CHANNEL_NIU_GATE 857U +#define ACLK_VOP_DOBY_GATE 858U +#define MBIST_CLK_DCLK_VOP0_GATE 859U +#define MBIST_CLK_DCLK_VOP1_GATE 860U +#define MBIST_CLK_DCLK_VOP2_GATE 861U +#define MBIST_CLK_DCLK_VOP3_GATE 862U +#define MBIST_CLK_ACLK_VOP_GATE 863U +/********Name=GATE_CON54,Offset=0x8D8********/ +#define MBIST_CLK_CLK_DSIHOST0_GATE 864U +#define MBIST_CLK_CLK_DSIHOST1_GATE 865U +#define MBIST_CLK_VOP_DSC_GATE 866U +/********Name=GATE_CON55,Offset=0x8DC********/ +#define ACLK_VO0_ROOT_GATE 880U +#define HCLK_VO0_ROOT_GATE 881U +#define HCLK_VO0_S_ROOT_GATE 882U +#define PCLK_VO0_ROOT_GATE 883U +#define PCLK_VO0_S_ROOT_GATE 884U +#define HCLK_VO0_NIU_GATE 885U +#define HCLK_VO0_S_NIU_GATE 886U +#define PCLK_VO0_NIU_GATE 887U +#define PCLK_VO0_S_NIU_GATE 888U +#define ACLK_HDCP0_NIU_GATE 889U +#define PCLK_VO0GRF_GATE 890U +#define HCLK_HDCP_KEY0_GATE 891U +#define ACLK_HDCP0_GATE 892U +#define HCLK_HDCP0_GATE 893U +#define PCLK_HDCP0_GATE 894U +/********Name=GATE_CON56,Offset=0x8E0********/ +#define ACLK_TRNG0_GATE 896U +#define PCLK_TRNG0_GATE 897U +#define CLK_AUX16MHZ_0_GATE 898U +#define CLK_AUX16MHZ_1_GATE 899U +#define PCLK_DP0_GATE 900U +#define PCLK_DP1_GATE 901U +#define PCLK_S_DP0_GATE 902U +#define PCLK_S_DP1_GATE 903U +#define CLK_DP0_GATE 904U +#define CLK_DP1_GATE 905U +#define HCLK_I2S4_8CH_GATE 906U +#define CLK_I2S4_8CH_TX_GATE 907U +#define CLK_I2S4_8CH_FRAC_TX_GATE 908U +#define MCLK_I2S4_8CH_TX_GATE 909U +#define HCLK_I2S8_8CH_GATE 910U +#define CLK_I2S8_8CH_TX_GATE 911U +/********Name=GATE_CON57,Offset=0x8E4********/ +#define CLK_I2S8_8CH_FRAC_TX_GATE 912U +#define MCLK_I2S8_8CH_TX_GATE 913U +#define HCLK_SPDIF2_DP0_GATE 914U +#define CLK_SPDIF2_DP0_GATE 915U +#define CLK_SPDIF2_DP0_FRAC_GATE 916U +#define MCLK_SPDIF2_DP0_GATE 917U +#define MCLK_SPDIF2_GATE 918U +#define HCLK_SPDIF5_DP1_GATE 919U +#define CLK_SPDIF5_DP1_GATE 920U +#define CLK_SPDIF5_DP1_FRAC_GATE 921U +#define MCLK_SPDIF5_DP1_GATE 922U +#define MCLK_SPDIF5_GATE 923U +#define MBIST_CLK_CLK_DP0_600M_GATE 924U +#define MBIST_CLK_CLK_DP0_300M_GATE 925U +#define MBIST_CLK_CLK_DP0_100M_GATE 926U +#define MBIST_CLK_CLK_DP1_600M_GATE 927U +/********Name=GATE_CON58,Offset=0x8E8********/ +#define MBIST_CLK_CLK_DP1_300M_GATE 928U +#define MBIST_CLK_CLK_DP1_100M_GATE 929U +#define MBIST_CLK_ACLK_HDCP0_GATE 930U +/********Name=GATE_CON59,Offset=0x8EC********/ +#define ACLK_HDCP1_ROOT_GATE 944U +#define ACLK_HDMIRX_ROOT_GATE 945U +#define HCLK_VO1_ROOT_GATE 946U +#define HCLK_VO1_S_ROOT_GATE 947U +#define PCLK_VO1_ROOT_GATE 948U +#define PCLK_VO1_S_ROOT_GATE 949U +#define ACLK_HDCP1_NIU_GATE 950U +#define ACLK_HDMIRX_NIU_GATE 951U +#define ACLK_VO1_NIU_GATE 952U +#define HCLK_VO1_NIU_GATE 953U +#define HCLK_VO1_S_NIU_GATE 954U +#define PCLK_VO1_NIU_GATE 955U +#define PCLK_VO1GRF_GATE 956U +#define PCLK_VO1_S_NIU_GATE 957U +#define PCLK_S_EDP0_GATE 958U +#define PCLK_S_EDP1_GATE 959U +/********Name=GATE_CON60,Offset=0x8F0********/ +#define HCLK_I2S7_8CH_GATE 960U +#define CLK_I2S7_8CH_RX_GATE 961U +#define CLK_I2S7_8CH_FRAC_RX_GATE 962U +#define MCLK_I2S7_8CH_RX_GATE 963U +#define HCLK_HDCP_KEY1_GATE 964U +#define ACLK_HDCP1_GATE 965U +#define HCLK_HDCP1_GATE 966U +#define PCLK_HDCP1_GATE 967U +#define ACLK_TRNG1_GATE 969U +#define PCLK_TRNG1_GATE 970U +#define PCLK_HDMITX0_GATE 971U +#define CLK_HDMITX0_EARC_GATE 975U +/********Name=GATE_CON61,Offset=0x8F4********/ +#define CLK_HDMITX0_REF_GATE 976U +#define PCLK_HDMITX1_GATE 978U +#define CLK_HDMITX1_EARC_GATE 982U +#define CLK_HDMITX1_REF_GATE 983U +#define ACLK_HDMIRX_GATE 985U +#define PCLK_HDMIRX_GATE 986U +#define CLK_HDMIRX_REF_GATE 987U +#define CLK_HDMIRX_AUD_SRC_GATE 988U +#define CLK_HDMIRX_AUD_FRAC_GATE 989U +#define CLK_HDMIRX_AUD_GATE 990U +#define CLK_HDMIRX_TMDSQP_GATE 991U +/********Name=GATE_CON62,Offset=0x8F8********/ +#define PCLK_EDP0_GATE 992U +#define CLK_EDP0_24M_GATE 993U +#define CLK_EDP0_200M_GATE 994U +#define PCLK_EDP1_GATE 995U +#define CLK_EDP1_24M_GATE 996U +#define CLK_EDP1_200M_GATE 997U +#define CLK_I2S5_8CH_TX_GATE 998U +#define CLK_I2S5_8CH_FRAC_TX_GATE 999U +#define MCLK_I2S5_8CH_TX_GATE 1000U +#define HCLK_I2S5_8CH_GATE 1004U +#define CLK_I2S6_8CH_TX_GATE 1005U +#define CLK_I2S6_8CH_FRAC_TX_GATE 1006U +#define MCLK_I2S6_8CH_TX_GATE 1007U +/********Name=GATE_CON63,Offset=0x8FC********/ +#define CLK_I2S6_8CH_RX_GATE 1008U +#define CLK_I2S6_8CH_FRAC_RX_GATE 1009U +#define MCLK_I2S6_8CH_RX_GATE 1010U +#define HCLK_I2S6_8CH_GATE 1011U +#define HCLK_SPDIF3_GATE 1012U +#define CLK_SPDIF3_GATE 1013U +#define CLK_SPDIF3_FRAC_GATE 1014U +#define MCLK_SPDIF3_GATE 1015U +#define HCLK_SPDIF4_GATE 1016U +#define CLK_SPDIF4_GATE 1017U +#define CLK_SPDIF4_FRAC_GATE 1018U +#define MCLK_SPDIF4_GATE 1019U +#define HCLK_SPDIFRX0_GATE 1020U +#define MCLK_SPDIFRX0_GATE 1021U +#define HCLK_SPDIFRX1_GATE 1022U +#define MCLK_SPDIFRX1_GATE 1023U +/********Name=GATE_CON64,Offset=0x900********/ +#define HCLK_SPDIFRX2_GATE 1024U +#define MCLK_SPDIFRX2_GATE 1025U +#define MBIST_CLK_ACLK_HDCP1_GATE 1026U +#define MBIST_CLK_CLK_HDMITX0_VID_GATE 1027U +#define MBIST_CLK_CLK_HDMITX0_LINK_GATE 1028U +#define MBIST_CLK_CLK_HDMITX1_VID_GATE 1029U +#define MBIST_CLK_CLK_HDMITX1_LINK_GATE 1030U +#define MBIST_CLK_CLK_HDMIRX_TMDSQP_GATE 1031U +#define MBIST_CLK_CLK_HDMIRX_REF_GATE 1032U +#define MBIST_CLK_ACLK_HDMIRX_GATE 1033U +#define MBIST_CLK_PCLK_EDP0_GATE 1034U +#define MBIST_CLK_PCLK_EDP1_GATE 1035U +#define DCLK_VOP2HDMI_BRIDGE0_VO1_GATE 1038U +#define DCLK_VOP2HDMI_BRIDGE1_VO1_GATE 1039U +/********Name=GATE_CON65,Offset=0x904********/ +#define HCLK_I2S9_8CH_GATE 1040U +#define CLK_I2S9_8CH_RX_GATE 1041U +#define CLK_I2S9_8CH_FRAC_RX_GATE 1042U +#define MCLK_I2S9_8CH_RX_GATE 1043U +#define HCLK_I2S10_8CH_GATE 1044U +#define CLK_I2S10_8CH_RX_GATE 1045U +#define CLK_I2S10_8CH_FRAC_RX_GATE 1046U +#define MCLK_I2S10_8CH_RX_GATE 1047U +#define PCLK_S_HDMIRX_GATE 1048U +#define CLK_HDMITRX_REFSRC_GATE 1049U +/********Name=GATE_CON66,Offset=0x908********/ +#define CLK_GPU_SRC_DF_GATE 1057U +#define CLK_TESTOUT_GPU_GATE 1058U +#define CLK_GPU_SRC_GATE 1059U +#define CLK_GPU_GATE 1060U +#define CLK_GPU_COREGROUP_GATE 1062U +#define CLK_GPU_STACKS_GATE 1063U +#define ACLK_S_GPU_NIU_GATE 1064U +#define ACLK_M0_GPU_NIU_GATE 1065U +#define ACLK_M1_GPU_NIU_GATE 1066U +#define ACLK_M2_GPU_NIU_GATE 1067U +#define ACLK_M3_GPU_NIU_GATE 1068U +#define PCLK_GPU_ROOT_GATE 1069U +#define PCLK_GPU_NIU_GATE 1070U +#define PCLK_PVTM2_GATE 1071U +/********Name=GATE_CON67,Offset=0x90C********/ +#define CLK_PVTM2_GATE 1072U +#define CLK_GPU_PVTM_GATE 1073U +#define PCLK_GPU_GRF_GATE 1074U +#define CLK_GPU_PVTPLL_GATE 1075U +/********Name=GATE_CON68,Offset=0x910********/ +#define ACLK_AV1_ROOT_GATE 1088U +#define ACLK_AV1_NIU_GATE 1089U +#define ACLK_AV1_GATE 1090U +#define PCLK_AV1_ROOT_GATE 1091U +#define PCLK_AV1_NIU_GATE 1092U +#define PCLK_AV1_GATE 1093U +/********Name=GATE_CON69,Offset=0x914********/ +#define ACLK_CENTER_ROOT_GATE 1104U +#define ACLK_CENTER_LOW_ROOT_GATE 1105U +#define HCLK_CENTER_ROOT_GATE 1106U +#define PCLK_CENTER_ROOT_GATE 1107U +#define ACLK_DDR_NIU_GATE 1108U +#define ACLK_DMA2DDR_GATE 1109U +#define ACLK_DDR_SHAREMEM_GATE 1110U +#define ACLK_DDR_SHAREMEM_NIU_GATE 1111U +#define ACLK_CENTER_S200_ROOT_GATE 1112U +#define ACLK_CENTER_S400_ROOT_GATE 1113U +#define ACLK_CENTER_S200_NIU_GATE 1114U +#define ACLK_CENTER_S400_NIU_GATE 1115U +#define HCLK_AHB2APB_GATE 1116U +#define HCLK_CENTER_NIU_GATE 1117U +#define FCLK_DDR_CM0_CORE_GATE 1118U +#define CLK_DDR_TIMER_ROOT_GATE 1119U +/********Name=GATE_CON70,Offset=0x918********/ +#define CLK_DDR_TIMER0_GATE 1120U +#define CLK_DDR_TIMER1_GATE 1121U +#define TCLK_WDT_DDR_GATE 1122U +#define CLK_DDR_CM0_RTC_GATE 1124U +#define PCLK_CENTER_GRF_GATE 1125U +#define PCLK_AHB2APB_GATE 1126U +#define PCLK_WDT_GATE 1127U +#define PCLK_TIMER_GATE 1128U +#define PCLK_DMA2DDR_GATE 1129U +#define PCLK_SHAREMEM_GATE 1130U +#define PCLK_CENTER_NIU_GATE 1131U +#define PCLK_CENTER_CHANNEL_NIU_GATE 1132U +#define MBIST_CLK_CLK_DDR_CM0_CORE_GATE 1133U +#define MBIST_CLK_SCLK_DDR_SHAREMEM_GATE 1134U +#define MBIST_CLK_ACLK_DMA2DDR_GATE 1135U +/********Name=GATE_CON71,Offset=0x91C********/ +#define MBIST_CLK_ACLK_NSPI_GATE 1136U +/********Name=GATE_CON72,Offset=0x920********/ +#define PCLK_USBDPGRF0_GATE 1153U +#define PCLK_USBDPPHY0_GATE 1154U +#define PCLK_USBDPGRF1_GATE 1155U +#define PCLK_USBDPPHY1_GATE 1156U +#define PCLK_HDPTX0_GATE 1157U +#define PCLK_HDPTX1_GATE 1158U +#define PCLK_APB2ASB_SLV_BOT_RIGHT_GATE 1159U +#define PCLK_USB2PHY_U3_0_GRF0_GATE 1160U +#define PCLK_USB2PHY_U3_1_GRF0_GATE 1161U +#define PCLK_USB2PHY_U2_0_GRF0_GATE 1162U +#define PCLK_USB2PHY_U2_1_GRF0_GATE 1163U +/********Name=GATE_CON73,Offset=0x924********/ +#define MBIST_CLK_HDMIRXPHY_GATE 1179U +#define CLK_HDMIHDP0_GATE 1180U +#define CLK_HDMIHDP1_GATE 1181U +/********Name=GATE_CON74,Offset=0x928********/ +#define ACLK_VO1USB_TOP_ROOT_GATE 1184U +#define ACLK_VO1USB_TOP_NIU_GATE 1185U +#define HCLK_VO1USB_TOP_ROOT_GATE 1186U +#define HCLK_VO1USB_TOP_NIU_GATE 1187U +/********Name=GATE_CON75,Offset=0x92C********/ +#define HCLK_SDIO_ROOT_GATE 1200U +#define HCLK_SDIO_NIU_GATE 1201U +#define HCLK_SDIO_GATE 1202U +#define CCLK_SRC_SDIO_GATE 1203U +#define MBIST_CLK_SDIO_GATE 1204U +/********Name=GATE_CON76,Offset=0x930********/ +#define ACLK_RGA3_ROOT_GATE 1216U +#define HCLK_RGA3_ROOT_GATE 1217U +#define HCLK_RGA3_NIU_GATE 1218U +#define ACLK_RGA3_NIU_GATE 1219U +#define HCLK_RGA3_1_GATE 1220U +#define ACLK_RGA3_1_GATE 1221U +#define CLK_RGA3_1_CORE_GATE 1222U +#define MBIST_CLK_ACLK_RGA3_1_GATE 1223U +#define MBIST_CLK_CLK_RGA3_1_CORE_GATE 1224U +/********Name=GATE_CON77,Offset=0x934********/ +#define CLK_REF_PIPE_PHY0_OSC_SRC_GATE 1232U +#define CLK_REF_PIPE_PHY1_OSC_SRC_GATE 1233U +#define CLK_REF_PIPE_PHY2_OSC_SRC_GATE 1234U +#define CLK_REF_PIPE_PHY0_PLL_SRC_GATE 1235U +#define CLK_REF_PIPE_PHY1_PLL_SRC_GATE 1236U +#define CLK_REF_PIPE_PHY2_PLL_SRC_GATE 1237U + +/********Name=PMU1GATE_CON00,Offset=0x800********/ +#define CLK_MATRIX_PMU1_50M_SRC_GATE 16U +#define CLK_MATRIX_PMU1_100M_SRC_GATE 17U +#define CLK_MATRIX_PMU1_200M_SRC_GATE 18U +#define CLK_MATRIX_PMU1_300M_SRC_GATE 19U +#define CLK_MATRIX_PMU1_400M_SRC_GATE 20U +#define HCLK_PMU1_ROOT_I_GATE 21U +#define HCLK_PMU1_ROOT_GATE 22U +#define PCLK_PMU1_ROOT_I_GATE 23U +#define HCLK_PMU_CM0_ROOT_I_GATE 24U +#define HCLK_PMU_CM0_ROOT_GATE 25U +#define HCLK_PMU1_NIU_GATE 26U +#define PCLK_PMU1_NIU_GATE 27U +#define HCLK_PMU_CM0_NIU_GATE 28U +#define FCLK_PMU_CM0_CORE_GATE 29U +#define CLK_PMU_CM0_RTC_GATE 31U +/********Name=PMU1GATE_CON01,Offset=0x804********/ +#define PCLK_PMU1_GATE 16U +#define CLK_DDR_FAIL_SAFE_GATE 17U +#define PCLK_PMU1_CRU_GATE 18U +#define CLK_PMU1_GATE 19U +#define PCLK_PMU1_GRF_GATE 20U +#define PCLK_PMU1_IOC_GATE 21U +#define PCLK_PMU1WDT_GATE 22U +#define TCLK_PMU1WDT_GATE 23U +#define PCLK_PMU1TIMER_GATE 24U +#define CLK_PMU1TIMER_ROOT_GATE 25U +#define CLK_PMU1TIMER0_GATE 26U +#define CLK_PMU1TIMER1_GATE 27U +#define PCLK_PMU1PWM_GATE 28U +#define CLK_PMU1PWM_GATE 29U +#define CLK_PMU1PWM_CAPTURE_GATE 30U +/********Name=PMU1GATE_CON02,Offset=0x808********/ +#define PCLK_I2C0_GATE 17U +#define CLK_I2C0_GATE 18U +#define CLK_UART0_GATE 19U +#define CLK_UART0_FRAC_GATE 20U +#define SCLK_UART0_GATE 21U +#define PCLK_UART0_GATE 22U +#define HCLK_I2S1_8CH_GATE 23U +#define CLK_I2S1_8CH_TX_GATE 24U +#define CLK_I2S1_8CH_FRAC_TX_GATE 25U +#define MCLK_I2S1_8CH_TX_GATE 26U +#define CLK_I2S1_8CH_RX_GATE 27U +#define CLK_I2S1_8CH_FRAC_RX_GATE 28U +#define MCLK_I2S1_8CH_RX_GATE 29U +#define HCLK_PDM0_GATE 30U +#define MCLK_PDM0_GATE 31U +/********Name=PMU1GATE_CON03,Offset=0x80C********/ +#define HCLK_VAD_GATE 16U +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_GATE 21U +#define CLK_HDPTX0_REF_XTAL_GATE 27U +/********Name=PMU1GATE_CON04,Offset=0x810********/ +#define CLK_REF_MIPI_DCPHY0_GATE 19U +#define CLK_OTGPHY_U3_0_GATE 23U +#define CLK_CR_PARA_GATE 27U +/********Name=PMU1GATE_CON05,Offset=0x814********/ +#define PCLK_PMU0_ROOT_GATE 16U +#define CLK_PMU0_GATE 17U +#define PCLK_PMU0_GATE 18U +#define PCLK_PMU0GRF_GATE 19U +#define PCLK_PMU0IOC_GATE 20U +#define PCLK_GPIO0_GATE 21U +#define DBCLK_GPIO0_GATE 22U + +/********Name=CLKSEL_CON00,Offset=0x300********/ +#define CLK_MATRIX_50M_SRC_DIV 0x05000000U +#define CLK_MATRIX_100M_SRC_DIV 0x05060000U +/********Name=CLKSEL_CON01,Offset=0x304********/ +#define CLK_MATRIX_150M_SRC_DIV 0x05000001U +#define CLK_MATRIX_200M_SRC_DIV 0x05060001U +/********Name=CLKSEL_CON02,Offset=0x308********/ +#define CLK_MATRIX_250M_SRC_DIV 0x05000002U +#define CLK_MATRIX_300M_SRC_DIV 0x05060002U +/********Name=CLKSEL_CON03,Offset=0x30C********/ +#define CLK_MATRIX_350M_SRC_DIV 0x05000003U +#define CLK_MATRIX_400M_SRC_DIV 0x05060003U +/********Name=CLKSEL_CON04,Offset=0x310********/ +#define CLK_MATRIX_450M_SRC_DIV 0x05000004U +#define CLK_MATRIX_500M_SRC_DIV 0x05060004U +/********Name=CLKSEL_CON05,Offset=0x314********/ +#define CLK_MATRIX_600M_SRC_DIV 0x05000005U +#define CLK_MATRIX_650M_SRC_DIV 0x05060005U +/********Name=CLKSEL_CON06,Offset=0x318********/ +#define CLK_MATRIX_700M_SRC_DIV 0x05000006U +#define CLK_MATRIX_800M_SRC_DIV 0x05060006U +/********Name=CLKSEL_CON07,Offset=0x31C********/ +#define CLK_MATRIX_1000M_SRC_DIV 0x05000007U +#define CLK_MATRIX_1200M_SRC_DIV 0x05070007U +/********Name=CLKSEL_CON08,Offset=0x320********/ +#define ACLK_TOP_ROOT_DIV 0x05000008U +#define ACLK_LOW_TOP_ROOT_DIV 0x05090008U +/********Name=CLKSEL_CON09,Offset=0x324********/ +/********Name=CLKSEL_CON10,Offset=0x328********/ +#define CLK_TESTOUT_TOP_DIV 0x0600000AU +/********Name=CLKSEL_CON100,Offset=0x490********/ +#define CLK_RGA2_CORE_DIV 0x05000064U +#define CLK_RGA3_0_CORE_DIV 0x05080064U +/********Name=CLKSEL_CON102,Offset=0x498********/ +#define ACLK_RKVENC0_ROOT_DIV 0x05020066U +#define CLK_RKVENC0_CORE_DIV 0x05090066U +/********Name=CLKSEL_CON104,Offset=0x4A0********/ +#define ACLK_RKVENC1_ROOT_DIV 0x05020068U +#define CLK_RKVENC1_CORE_DIV 0x05090068U +/********Name=CLKSEL_CON106,Offset=0x4A8********/ +#define ACLK_VI_ROOT_DIV 0x0500006AU +/********Name=CLKSEL_CON107,Offset=0x4AC********/ +#define DCLK_VICAP_DIV 0x0500006BU +#define CLK_ISP0_CORE_DIV 0x0506006BU +/********Name=CLKSEL_CON108,Offset=0x4B0********/ +#define CLK_FISHEYE0_CORE_DIV 0x0500006CU +#define CLK_FISHEYE1_CORE_DIV 0x0507006CU +/********Name=CLKSEL_CON110,Offset=0x4B8********/ +#define ACLK_VOP_ROOT_DIV 0x0500006EU +/********Name=CLKSEL_CON111,Offset=0x4BC********/ +#define DCLK_VOP0_SRC_DIV 0x0700006FU +#define DCLK_VOP1_SRC_DIV 0x0509006FU +/********Name=CLKSEL_CON112,Offset=0x4C0********/ +#define DCLK_VOP2_SRC_DIV 0x05000070U +/********Name=CLKSEL_CON113,Offset=0x4C4********/ +#define DCLK_VOP3_DIV 0x07000071U +/********Name=CLKSEL_CON114,Offset=0x4C8********/ +#define CLK_DSIHOST0_DIV 0x07000072U +/********Name=CLKSEL_CON115,Offset=0x4CC********/ +#define CLK_DSIHOST1_DIV 0x07000073U +/********Name=CLKSEL_CON116,Offset=0x4D0********/ +#define ACLK_VO0_ROOT_DIV 0x05000074U +/********Name=CLKSEL_CON117,Offset=0x4D4********/ +#define CLK_AUX16MHZ_0_DIV 0x08000075U +#define CLK_AUX16MHZ_1_DIV 0x08080075U +/********Name=CLKSEL_CON118,Offset=0x4D8********/ +#define CLK_I2S4_8CH_TX_SRC_DIV 0x05000076U +/********Name=CLKSEL_CON119,Offset=0x4DC********/ +#define CLK_I2S4_8CH_TX_FRAC_DIV 0x20000077U +/********Name=CLKSEL_CON120,Offset=0x4E0********/ +#define CLK_I2S8_8CH_TX_SRC_DIV 0x05030078U +/********Name=CLKSEL_CON121,Offset=0x4E4********/ +#define CLK_I2S8_8CH_TX_FRAC_DIV 0x20000079U +/********Name=CLKSEL_CON122,Offset=0x4E8********/ +#define CLK_SPDIF2_DP0_SRC_DIV 0x0503007AU +/********Name=CLKSEL_CON123,Offset=0x4EC********/ +#define CLK_SPDIF2_DP0_FRAC_DIV 0x2000007BU +/********Name=CLKSEL_CON124,Offset=0x4F0********/ +#define CLK_SPDIF5_DP1_SRC_DIV 0x0502007CU +/********Name=CLKSEL_CON125,Offset=0x4F4********/ +#define CLK_SPDIF5_DP1_FRAC_DIV 0x2000007DU +/********Name=CLKSEL_CON126,Offset=0x4F8********/ +/********Name=CLKSEL_CON128,Offset=0x500********/ +#define ACLK_HDCP1_ROOT_DIV 0x05000080U +#define ACLK_HDMIRX_ROOT_DIV 0x05070080U +/********Name=CLKSEL_CON129,Offset=0x504********/ +#define CLK_I2S7_8CH_RX_SRC_DIV 0x05060081U +/********Name=CLKSEL_CON130,Offset=0x508********/ +#define CLK_I2S7_8CH_RX_FRAC_DIV 0x20000082U +/********Name=CLKSEL_CON131,Offset=0x50C********/ +/********Name=CLKSEL_CON133,Offset=0x514********/ +#define CLK_HDMITX0_EARC_DIV 0x05010085U +/********Name=CLKSEL_CON136,Offset=0x520********/ +#define CLK_HDMITX1_EARC_DIV 0x05010088U +/********Name=CLKSEL_CON138,Offset=0x528********/ +#define CLK_HDMIRX_AUD_SRC_DIV 0x0800008AU +/********Name=CLKSEL_CON139,Offset=0x52C********/ +#define CLK_HDMIRX_AUD_FRAC_DIV 0x2000008BU +/********Name=CLKSEL_CON140,Offset=0x530********/ +#define CLK_I2S5_8CH_TX_SRC_DIV 0x0505008CU +/********Name=CLKSEL_CON141,Offset=0x534********/ +#define CLK_I2S5_8CH_TX_FRAC_DIV 0x2000008DU +/********Name=CLKSEL_CON142,Offset=0x538********/ +/********Name=CLKSEL_CON144,Offset=0x540********/ +#define CLK_I2S6_8CH_TX_SRC_DIV 0x05030090U +/********Name=CLKSEL_CON145,Offset=0x544********/ +#define CLK_I2S6_8CH_TX_FRAC_DIV 0x20000091U +/********Name=CLKSEL_CON146,Offset=0x548********/ +#define CLK_I2S6_8CH_RX_SRC_DIV 0x05020092U +/********Name=CLKSEL_CON147,Offset=0x54C********/ +#define CLK_I2S6_8CH_RX_FRAC_DIV 0x20000093U +/********Name=CLKSEL_CON148,Offset=0x550********/ +#define CLK_SPDIF3_SRC_DIV 0x05040094U +/********Name=CLKSEL_CON149,Offset=0x554********/ +#define CLK_SPDIF3_FRAC_DIV 0x20000095U +/********Name=CLKSEL_CON15,Offset=0x33C********/ +#define MCLK_GMAC0_OUT_DIV 0x0700000FU +#define REFCLKO25M_ETH0_OUT_DIV 0x0708000FU +/********Name=CLKSEL_CON150,Offset=0x558********/ +#define CLK_SPDIF4_SRC_DIV 0x05020096U +/********Name=CLKSEL_CON151,Offset=0x55C********/ +#define CLK_SPDIF4_FRAC_DIV 0x20000097U +/********Name=CLKSEL_CON152,Offset=0x560********/ +#define MCLK_SPDIFRX0_DIV 0x05020098U +#define MCLK_SPDIFRX1_DIV 0x05090098U +/********Name=CLKSEL_CON153,Offset=0x564********/ +#define MCLK_SPDIFRX2_DIV 0x05000099U +#define CLK_I2S9_8CH_RX_SRC_DIV 0x05070099U +/********Name=CLKSEL_CON154,Offset=0x568********/ +#define CLK_I2S9_8CH_RX_FRAC_DIV 0x2000009AU +/********Name=CLKSEL_CON155,Offset=0x56C********/ +#define CLK_I2S10_8CH_RX_SRC_DIV 0x0503009BU +/********Name=CLKSEL_CON156,Offset=0x570********/ +#define CLK_I2S10_8CH_RX_FRAC_DIV 0x2000009CU +/********Name=CLKSEL_CON157,Offset=0x574********/ +#define CLK_HDMITRX_REFSRC_DIV 0x0502009DU +/********Name=CLKSEL_CON158,Offset=0x578********/ +#define CLK_GPU_SRC_T_DIV 0x0500009EU +#define CLK_TESTOUT_GPU_DIV 0x0508009EU +/********Name=CLKSEL_CON159,Offset=0x57C********/ +#define CLK_GPU_STACKS_DIV 0x0500009FU +#define ACLK_S_GPU_NIU_DIV 0x0505009FU +#define ACLK_M0_GPU_NIU_DIV 0x050A009FU +/********Name=CLKSEL_CON16,Offset=0x340********/ +#define REFCLKO25M_ETH1_OUT_DIV 0x07000010U +/********Name=CLKSEL_CON160,Offset=0x580********/ +#define ACLK_M1_GPU_NIU_DIV 0x050000A0U +#define ACLK_M2_GPU_NIU_DIV 0x050500A0U +#define ACLK_M3_GPU_NIU_DIV 0x050A00A0U +/********Name=CLKSEL_CON161,Offset=0x584********/ +/********Name=CLKSEL_CON163,Offset=0x58C********/ +#define ACLK_AV1_ROOT_DIV 0x050000A3U +/********Name=CLKSEL_CON165,Offset=0x594********/ +/********Name=CLKSEL_CON166,Offset=0x598********/ +#define CLK_DDR_CM0_RTC_DIV 0x050000A6U +/********Name=CLKSEL_CON17,Offset=0x344********/ +#define CLK_CIFOUT_OUT_DIV 0x08000011U +/********Name=CLKSEL_CON170,Offset=0x5A8********/ +#define ACLK_VO1USB_TOP_ROOT_DIV 0x050000AAU +/********Name=CLKSEL_CON172,Offset=0x5B0********/ +#define CCLK_SRC_SDIO_DIV 0x060200ACU +/********Name=CLKSEL_CON174,Offset=0x5B8********/ +#define ACLK_RGA3_ROOT_DIV 0x050000AEU +#define CLK_RGA3_1_CORE_DIV 0x050900AEU +/********Name=CLKSEL_CON176,Offset=0x5C0********/ +#define CLK_REF_PIPE_PHY0_PLL_SRC_DIV 0x060000B0U +#define CLK_REF_PIPE_PHY1_PLL_SRC_DIV 0x060600B0U +/********Name=CLKSEL_CON177,Offset=0x5C4********/ +#define CLK_REF_PIPE_PHY2_PLL_SRC_DIV 0x060000B1U +/********Name=CLKSEL_CON18,Offset=0x348********/ +#define CLK_MIPI_CAMARAOUT_M0_DIV 0x08000012U +/********Name=CLKSEL_CON19,Offset=0x34C********/ +#define CLK_MIPI_CAMARAOUT_M1_DIV 0x08000013U +/********Name=CLKSEL_CON20,Offset=0x350********/ +#define CLK_MIPI_CAMARAOUT_M2_DIV 0x08000014U +/********Name=CLKSEL_CON21,Offset=0x354********/ +#define CLK_MIPI_CAMARAOUT_M3_DIV 0x08000015U +/********Name=CLKSEL_CON22,Offset=0x358********/ +#define CLK_MIPI_CAMARAOUT_M4_DIV 0x08000016U +/********Name=CLKSEL_CON24,Offset=0x360********/ +#define CLK_I2S0_8CH_TX_SRC_DIV 0x05040018U +/********Name=CLKSEL_CON25,Offset=0x364********/ +#define CLK_I2S0_8CH_TX_FRAC_DIV 0x20000019U +/********Name=CLKSEL_CON26,Offset=0x368********/ +#define CLK_I2S0_8CH_RX_SRC_DIV 0x0502001AU +/********Name=CLKSEL_CON27,Offset=0x36C********/ +#define CLK_I2S0_8CH_RX_FRAC_DIV 0x2000001BU +/********Name=CLKSEL_CON28,Offset=0x370********/ +#define CLK_I2S2_2CH_SRC_DIV 0x0504001CU +/********Name=CLKSEL_CON29,Offset=0x374********/ +#define CLK_I2S2_2CH_FRAC_DIV 0x2000001DU +/********Name=CLKSEL_CON30,Offset=0x378********/ +#define CLK_I2S3_2CH_SRC_DIV 0x0503001EU +/********Name=CLKSEL_CON31,Offset=0x37C********/ +#define CLK_I2S3_2CH_FRAC_DIV 0x2000001FU +/********Name=CLKSEL_CON32,Offset=0x380********/ +#define CLK_SPDIF0_SRC_DIV 0x05030020U +/********Name=CLKSEL_CON33,Offset=0x384********/ +#define CLK_SPDIF0_FRAC_DIV 0x20000021U +/********Name=CLKSEL_CON34,Offset=0x388********/ +#define CLK_SPDIF1_SRC_DIV 0x05020022U +/********Name=CLKSEL_CON35,Offset=0x38C********/ +#define CLK_SPDIF1_FRAC_DIV 0x20000023U +/********Name=CLKSEL_CON36,Offset=0x390********/ +#define MCLK_PDM1_DIV 0x05020024U +/********Name=CLKSEL_CON38,Offset=0x398********/ +#define ACLK_BUS_ROOT_DIV 0x05000026U +/********Name=CLKSEL_CON39,Offset=0x39C********/ +#define CLK_CAN0_DIV 0x05000027U +#define CLK_CAN1_DIV 0x05060027U +/********Name=CLKSEL_CON40,Offset=0x3A0********/ +#define CLK_CAN2_DIV 0x05000028U +#define CLK_SARADC_DIV 0x08060028U +/********Name=CLKSEL_CON41,Offset=0x3A4********/ +#define CLK_TSADC_DIV 0x08000029U +#define CLK_UART1_SRC_DIV 0x05090029U +/********Name=CLKSEL_CON42,Offset=0x3A8********/ +#define CLK_UART1_FRAC_DIV 0x2000002AU +/********Name=CLKSEL_CON43,Offset=0x3AC********/ +#define CLK_UART2_SRC_DIV 0x0502002BU +/********Name=CLKSEL_CON44,Offset=0x3B0********/ +#define CLK_UART2_FRAC_DIV 0x2000002CU +/********Name=CLKSEL_CON45,Offset=0x3B4********/ +#define CLK_UART3_SRC_DIV 0x0502002DU +/********Name=CLKSEL_CON46,Offset=0x3B8********/ +#define CLK_UART3_FRAC_DIV 0x2000002EU +/********Name=CLKSEL_CON47,Offset=0x3BC********/ +#define CLK_UART4_SRC_DIV 0x0502002FU +/********Name=CLKSEL_CON48,Offset=0x3C0********/ +#define CLK_UART4_FRAC_DIV 0x20000030U +/********Name=CLKSEL_CON49,Offset=0x3C4********/ +#define CLK_UART5_SRC_DIV 0x05020031U +/********Name=CLKSEL_CON50,Offset=0x3C8********/ +#define CLK_UART5_FRAC_DIV 0x20000032U +/********Name=CLKSEL_CON51,Offset=0x3CC********/ +#define CLK_UART6_SRC_DIV 0x05020033U +/********Name=CLKSEL_CON52,Offset=0x3D0********/ +#define CLK_UART6_FRAC_DIV 0x20000034U +/********Name=CLKSEL_CON53,Offset=0x3D4********/ +#define CLK_UART7_SRC_DIV 0x05020035U +/********Name=CLKSEL_CON54,Offset=0x3D8********/ +#define CLK_UART7_FRAC_DIV 0x20000036U +/********Name=CLKSEL_CON55,Offset=0x3DC********/ +#define CLK_UART8_SRC_DIV 0x05020037U +/********Name=CLKSEL_CON56,Offset=0x3E0********/ +#define CLK_UART8_FRAC_DIV 0x20000038U +/********Name=CLKSEL_CON57,Offset=0x3E4********/ +#define CLK_UART9_SRC_DIV 0x05020039U +/********Name=CLKSEL_CON58,Offset=0x3E8********/ +#define CLK_UART9_FRAC_DIV 0x2000003AU +/********Name=CLKSEL_CON59,Offset=0x3EC********/ +/********Name=CLKSEL_CON60,Offset=0x3F0********/ +#define DBCLK_GPIO1_DIV 0x0503003CU +#define DBCLK_GPIO2_DIV 0x0509003CU +/********Name=CLKSEL_CON61,Offset=0x3F4********/ +#define DBCLK_GPIO3_DIV 0x0500003DU +#define DBCLK_GPIO4_DIV 0x0506003DU +/********Name=CLKSEL_CON62,Offset=0x3F8********/ +#define DCLK_DECOM_DIV 0x0500003EU +#define CLK_BISRINTF_PLLSRC_DIV 0x0506003EU +/********Name=CLKSEL_CON63,Offset=0x3FC********/ +#define CLK_TESTOUT_DDR01_DIV 0x0600003FU +/********Name=CLKSEL_CON65,Offset=0x404********/ +#define CLK_TESTOUT_DDR23_DIV 0x06000041U +/********Name=CLKSEL_CON67,Offset=0x40C********/ +#define ACLK_ISP1_ROOT_DIV 0x05000043U +#define CLK_ISP1_CORE_DIV 0x05090043U +/********Name=CLKSEL_CON73,Offset=0x424********/ +#define CLK_RKNN_DSU0_SRC_T_DIV 0x05020049U +#define CLK_TESTOUT_NPU_DIV 0x050A0049U +/********Name=CLKSEL_CON74,Offset=0x428********/ +#define CLK_NPU_CM0_RTC_DIV 0x0507004AU +/********Name=CLKSEL_CON77,Offset=0x434********/ +#define ACLK_NVM_ROOT_DIV 0x0502004DU +#define CCLK_EMMC_DIV 0x0608004DU +/********Name=CLKSEL_CON78,Offset=0x438********/ +#define BCLK_EMMC_DIV 0x0500004EU +#define SCLK_SFC_DIV 0x0606004EU +/********Name=CLKSEL_CON80,Offset=0x440********/ +#define ACLK_PCIE_ROOT_DIV 0x05020050U +#define ACLK_PHP_ROOT_DIV 0x05080050U +/********Name=CLKSEL_CON81,Offset=0x444********/ +#define CLK_GMAC0_PTP_REF_DIV 0x06000051U +#define CLK_GMAC1_PTP_REF_DIV 0x06070051U +/********Name=CLKSEL_CON82,Offset=0x448********/ +#define CLK_RXOOB0_DIV 0x07000052U +#define CLK_RXOOB1_DIV 0x07080052U +/********Name=CLKSEL_CON83,Offset=0x44C********/ +#define CLK_RXOOB2_DIV 0x07000053U +#define CLK_GMAC_125M_CRU_I_DIV 0x07080053U +/********Name=CLKSEL_CON84,Offset=0x450********/ +#define CLK_GMAC_50M_CRU_I_DIV 0x07000054U +#define CLK_UTMI_OTG2_DIV 0x04080054U +/********Name=CLKSEL_CON85,Offset=0x454********/ +#define CLK_GMAC0_TX_125M_O_DIV 0x06000055U +#define CLK_GMAC1_TX_125M_O_DIV 0x06060055U +/********Name=CLKSEL_CON89,Offset=0x464********/ +#define ACLK_RKVDEC0_ROOT_DIV 0x05020059U +#define ACLK_RKVDEC_CCU_DIV 0x05090059U +/********Name=CLKSEL_CON90,Offset=0x468********/ +#define CLK_RKVDEC0_CA_DIV 0x0500005AU +#define CLK_RKVDEC0_HEVC_CA_DIV 0x0506005AU +/********Name=CLKSEL_CON91,Offset=0x46C********/ +#define CLK_RKVDEC0_CORE_DIV 0x0500005BU +/********Name=CLKSEL_CON93,Offset=0x474********/ +#define ACLK_RKVDEC1_ROOT_DIV 0x0502005DU +#define CLK_RKVDEC1_CA_DIV 0x0509005DU +/********Name=CLKSEL_CON94,Offset=0x478********/ +#define CLK_RKVDEC1_HEVC_CA_DIV 0x0500005EU +#define CLK_RKVDEC1_CORE_DIV 0x0507005EU +/********Name=CLKSEL_CON96,Offset=0x480********/ +#define ACLK_USB_ROOT_DIV 0x05000060U +/********Name=CLKSEL_CON98,Offset=0x488********/ +#define ACLK_VDPU_ROOT_DIV 0x05000062U +/********Name=CLKSEL_CON99,Offset=0x48C********/ +#define ACLK_JPEG_DECODER_ROOT_DIV 0x05000063U +#define CLK_IEP2P0_CORE_DIV 0x05070063U +/********Name=PMU1CLKSEL_CON00,Offset=0x300********/ +#define CLK_MATRIX_PMU1_50M_SRC_DIV 0x04000000U +#define CLK_MATRIX_PMU1_100M_SRC_DIV 0x03040000U +#define CLK_MATRIX_PMU1_200M_SRC_DIV 0x03070000U +#define CLK_MATRIX_PMU1_300M_SRC_DIV 0x050A0000U +/********Name=PMU1CLKSEL_CON01,Offset=0x304********/ +#define CLK_MATRIX_PMU1_400M_SRC_DIV 0x05000001U +/********Name=PMU1CLKSEL_CON02,Offset=0x308********/ +#define CLK_PMU_CM0_RTC_DIV 0x05000002U +/********Name=PMU1CLKSEL_CON03,Offset=0x30C********/ +#define CLK_UART0_SRC_DIV 0x05070003U +/********Name=PMU1CLKSEL_CON04,Offset=0x310********/ +#define CLK_UART0_FRAC_DIV 0x20000004U +/********Name=PMU1CLKSEL_CON05,Offset=0x314********/ +#define CLK_I2S1_8CH_TX_SRC_DIV 0x05020005U +/********Name=PMU1CLKSEL_CON06,Offset=0x318********/ +#define CLK_I2S1_8CH_TX_FRAC_DIV 0x20000006U +/********Name=PMU1CLKSEL_CON07,Offset=0x31C********/ +#define CLK_I2S1_8CH_RX_SRC_DIV 0x05020007U +/********Name=PMU1CLKSEL_CON08,Offset=0x320********/ +#define CLK_I2S1_8CH_RX_FRAC_DIV 0x20000008U +/********Name=PMU1CLKSEL_CON09,Offset=0x324********/ +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_DIV 0x05050009U +/********Name=PMU1CLKSEL_CON12,Offset=0x330********/ +#define CLK_HDPTX0_REF_XTAL_DIV 0x0506000CU +/********Name=PMU1CLKSEL_CON14,Offset=0x338********/ +#define CLK_REF_MIPI_DCPHY0_DIV 0x0700000EU +#define CLK_OTGPHY_U3_0_DIV 0x0509000EU +/********Name=PMU1CLKSEL_CON15,Offset=0x33C********/ +#define CLK_CR_PARA_DIV 0x0500000FU +/********Name=PMU1CLKSEL_CON17,Offset=0x344********/ +/********Name=PMU1SCLKSEL_CON00,Offset=0x300********/ +/********Name=PMU1SCLKSEL_CON02,Offset=0x308********/ +#define XIN_OSC0_DIV_DIV 0x20000001U + +/********Name=CLKSEL_CON00,Offset=0x300********/ +#define CLK_MATRIX_50M_SRC_SEL 0x01050000U +#define CLK_MATRIX_50M_SRC_SEL_CLK_CPLL_MUX 0U +#define CLK_MATRIX_100M_SRC_SEL 0x010B0000U +#define CLK_MATRIX_100M_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON01,Offset=0x304********/ +#define CLK_MATRIX_150M_SRC_SEL 0x01050001U +#define CLK_MATRIX_150M_SRC_SEL_CLK_CPLL_MUX 0U +#define CLK_MATRIX_200M_SRC_SEL 0x010B0001U +#define CLK_MATRIX_200M_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON02,Offset=0x308********/ +#define CLK_MATRIX_250M_SRC_SEL 0x01050002U +#define CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX 0U +#define CLK_MATRIX_300M_SRC_SEL 0x010B0002U +#define CLK_MATRIX_300M_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON03,Offset=0x30C********/ +#define CLK_MATRIX_350M_SRC_SEL 0x01050003U +#define CLK_MATRIX_350M_SRC_SEL_CLK_SPLL_MUX 0U +#define CLK_MATRIX_400M_SRC_SEL 0x010B0003U +#define CLK_MATRIX_400M_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON04,Offset=0x310********/ +#define CLK_MATRIX_450M_SRC_SEL 0x01050004U +#define CLK_MATRIX_450M_SRC_SEL_CLK_CPLL_MUX 0U +#define CLK_MATRIX_500M_SRC_SEL 0x010B0004U +#define CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON05,Offset=0x314********/ +#define CLK_MATRIX_600M_SRC_SEL 0x01050005U +#define CLK_MATRIX_600M_SRC_SEL_CLK_CPLL_MUX 0U +#define CLK_MATRIX_650M_SRC_SEL 0x010B0005U +#define CLK_MATRIX_650M_SRC_SEL_CLK_LPLL_MUX 0U +/********Name=CLKSEL_CON06,Offset=0x318********/ +#define CLK_MATRIX_700M_SRC_SEL 0x01050006U +#define CLK_MATRIX_700M_SRC_SEL_CLK_SPLL_MUX 0U +#define CLK_MATRIX_800M_SRC_SEL 0x010B0006U +#define CLK_MATRIX_800M_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON07,Offset=0x31C********/ +#define CLK_MATRIX_1000M_SRC_SEL 0x02050007U +#define CLK_MATRIX_1000M_SRC_SEL_CLK_V0PLL_MUX 0U +#define CLK_MATRIX_1200M_SRC_SEL 0x010C0007U +#define CLK_MATRIX_1200M_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON08,Offset=0x320********/ +#define ACLK_TOP_ROOT_SEL 0x02050008U +#define ACLK_TOP_ROOT_SEL_CLK_AUPLL_MUX 0U +#define PCLK_TOP_ROOT_SEL 0x02070008U +#define PCLK_TOP_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_LOW_TOP_ROOT_SEL 0x010E0008U +#define ACLK_LOW_TOP_ROOT_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON09,Offset=0x324********/ +#define ACLK_TOP_M300_ROOT_SEL 0x02000009U +#define ACLK_TOP_M300_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_TOP_M500_ROOT_SEL 0x02020009U +#define ACLK_TOP_M500_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_TOP_M400_ROOT_SEL 0x02040009U +#define ACLK_TOP_M400_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_TOP_S200_ROOT_SEL 0x02060009U +#define ACLK_TOP_S200_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_TOP_S400_ROOT_SEL 0x02080009U +#define ACLK_TOP_S400_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON10,Offset=0x328********/ +#define CLK_TESTOUT_TOP_SEL 0x0306000AU +#define CLK_TESTOUT_TOP_SEL_CLK_DEEPSLOW 0U +#define CLK_TESTOUT_SEL 0x0309000AU +#define CLK_TESTOUT_SEL_CLK_TESTOUT_DDR23 0U +#define CLK_TESTOUT_GRP0_SEL 0x030C000AU +#define CLK_TESTOUT_GRP0_SEL_CLK_TESTOUT_NPU 0U +/********Name=CLKSEL_CON100,Offset=0x490********/ +#define CLK_RGA2_CORE_SEL 0x03050064U +#define CLK_RGA2_CORE_SEL_CLK_SPLL_MUX 0U +#define CLK_RGA3_0_CORE_SEL 0x030D0064U +#define CLK_RGA3_0_CORE_SEL_CLK_SPLL_MUX 0U +/********Name=CLKSEL_CON102,Offset=0x498********/ +#define HCLK_RKVENC0_ROOT_SEL 0x02000066U +#define HCLK_RKVENC0_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_RKVENC0_ROOT_SEL 0x02070066U +#define ACLK_RKVENC0_ROOT_SEL_CLK_NPLL_MUX 0U +#define CLK_RKVENC0_CORE_SEL 0x020E0066U +#define CLK_RKVENC0_CORE_SEL_CLK_NPLL_MUX 0U +/********Name=CLKSEL_CON104,Offset=0x4A0********/ +#define HCLK_RKVENC1_ROOT_SEL 0x02000068U +#define HCLK_RKVENC1_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_RKVENC1_ROOT_SEL 0x02070068U +#define ACLK_RKVENC1_ROOT_SEL_CLK_NPLL_MUX 0U +#define CLK_RKVENC1_CORE_SEL 0x020E0068U +#define CLK_RKVENC1_CORE_SEL_CLK_NPLL_MUX 0U +/********Name=CLKSEL_CON106,Offset=0x4A8********/ +#define ACLK_VI_ROOT_SEL 0x0305006AU +#define ACLK_VI_ROOT_SEL_CLK_SPLL_MUX 0U +#define HCLK_VI_ROOT_SEL 0x0208006AU +#define HCLK_VI_ROOT_SEL_XIN_OSC0_FUNC 0U +#define PCLK_VI_ROOT_SEL 0x020A006AU +#define PCLK_VI_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON107,Offset=0x4AC********/ +#define DCLK_VICAP_SEL 0x0105006BU +#define DCLK_VICAP_SEL_CLK_CPLL_MUX 0U +#define CLK_ISP0_CORE_SEL 0x020B006BU +#define CLK_ISP0_CORE_SEL_CLK_SPLL_MUX 0U +/********Name=CLKSEL_CON108,Offset=0x4B0********/ +#define CLK_FISHEYE0_CORE_SEL 0x0205006CU +#define CLK_FISHEYE0_CORE_SEL_CLK_SPLL_MUX 0U +#define CLK_FISHEYE1_CORE_SEL 0x020C006CU +#define CLK_FISHEYE1_CORE_SEL_CLK_SPLL_MUX 0U +#define ICLK_CSIHOST01_SEL 0x020E006CU +#define ICLK_CSIHOST01_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON110,Offset=0x4B8********/ +#define ACLK_VOP_ROOT_SEL 0x0305006EU +#define ACLK_VOP_ROOT_SEL_CLK_SPLL_MUX 0U +#define ACLK_VOP_LOW_ROOT_SEL 0x0208006EU +#define ACLK_VOP_LOW_ROOT_SEL_XIN_OSC0_FUNC 0U +#define HCLK_VOP_ROOT_SEL 0x020A006EU +#define HCLK_VOP_ROOT_SEL_XIN_OSC0_FUNC 0U +#define PCLK_VOP_ROOT_SEL 0x020C006EU +#define PCLK_VOP_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON111,Offset=0x4BC********/ +#define DCLK_VOP0_SRC_SEL 0x0207006FU +#define DCLK_VOP0_SRC_SEL_CLK_AUPLL_MUX 0U +#define DCLK_VOP1_SRC_SEL 0x020E006FU +#define DCLK_VOP1_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON112,Offset=0x4C0********/ +#define DCLK_VOP2_SRC_SEL 0x02050070U +#define DCLK_VOP2_SRC_SEL_CLK_AUPLL_MUX 0U +#define DCLK_VOP0_SEL 0x02070070U +#define DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL1_O 0U +#define DCLK_VOP1_SEL 0x02090070U +#define DCLK_VOP1_SEL_CLK_HDMIPHY_PIXEL1_O 0U +#define DCLK_VOP2_SEL 0x020B0070U +#define DCLK_VOP2_SEL_CLK_HDMIPHY_PIXEL1_O 0U +/********Name=CLKSEL_CON113,Offset=0x4C4********/ +#define DCLK_VOP3_SEL 0x02070071U +#define DCLK_VOP3_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON114,Offset=0x4C8********/ +#define CLK_DSIHOST0_SEL 0x02070072U +#define CLK_DSIHOST0_SEL_CLK_SPLL_MUX 0U +/********Name=CLKSEL_CON115,Offset=0x4CC********/ +#define CLK_DSIHOST1_SEL 0x02070073U +#define CLK_DSIHOST1_SEL_CLK_SPLL_MUX 0U +#define ACLK_VOP_SUB_SRC_SEL 0x01090073U +#define ACLK_VOP_SUB_SRC_SEL_ACLK_VOP_DIV2_SRC 0U +/********Name=CLKSEL_CON116,Offset=0x4D0********/ +#define ACLK_VO0_ROOT_SEL 0x01050074U +#define ACLK_VO0_ROOT_SEL_CLK_CPLL_MUX 0U +#define HCLK_VO0_ROOT_SEL 0x02060074U +#define HCLK_VO0_ROOT_SEL_XIN_OSC0_FUNC 0U +#define HCLK_VO0_S_ROOT_SEL 0x02080074U +#define HCLK_VO0_S_ROOT_SEL_XIN_OSC0_FUNC 0U +#define PCLK_VO0_ROOT_SEL 0x020A0074U +#define PCLK_VO0_ROOT_SEL_XIN_OSC0_FUNC 0U +#define PCLK_VO0_S_ROOT_SEL 0x020C0074U +#define PCLK_VO0_S_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON117,Offset=0x4D4********/ +/********Name=CLKSEL_CON118,Offset=0x4D8********/ +#define CLK_I2S4_8CH_TX_SRC_SEL 0x01050076U +#define CLK_I2S4_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON119,Offset=0x4DC********/ +/********Name=CLKSEL_CON120,Offset=0x4E0********/ +#define MCLK_I2S4_8CH_TX_SEL 0x02000078U +#define MCLK_I2S4_8CH_TX_SEL_XIN_OSC0_HALF 0U +#define I2S4_8CH_MCLKOUT_SEL 0x01020078U +#define I2S4_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +#define CLK_I2S8_8CH_TX_SRC_SEL 0x01080078U +#define CLK_I2S8_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON121,Offset=0x4E4********/ +/********Name=CLKSEL_CON122,Offset=0x4E8********/ +#define MCLK_I2S8_8CH_TX_SEL 0x0200007AU +#define MCLK_I2S8_8CH_TX_SEL_XIN_OSC0_HALF 0U +#define I2S8_8CH_MCLKOUT_SEL 0x0102007AU +#define I2S8_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +#define CLK_SPDIF2_DP0_SRC_SEL 0x0108007AU +#define CLK_SPDIF2_DP0_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON123,Offset=0x4EC********/ +/********Name=CLKSEL_CON124,Offset=0x4F0********/ +#define MCLK_4X_SPDIF2_DP0_SEL 0x0200007CU +#define MCLK_4X_SPDIF2_DP0_SEL_XIN_OSC0_HALF 0U +#define CLK_SPDIF5_DP1_SRC_SEL 0x0107007CU +#define CLK_SPDIF5_DP1_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON125,Offset=0x4F4********/ +/********Name=CLKSEL_CON126,Offset=0x4F8********/ +#define MCLK_4X_SPDIF5_DP1_SEL 0x0200007EU +#define MCLK_4X_SPDIF5_DP1_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON128,Offset=0x500********/ +#define ACLK_HDCP1_ROOT_SEL 0x02050080U +#define ACLK_HDCP1_ROOT_SEL_CLK_HDMITRX_REFSRC 0U +#define ACLK_HDMIRX_ROOT_SEL 0x010C0080U +#define ACLK_HDMIRX_ROOT_SEL_CLK_CPLL_MUX 0U +#define HCLK_VO1_ROOT_SEL 0x020D0080U +#define HCLK_VO1_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON129,Offset=0x504********/ +#define HCLK_VO1_S_ROOT_SEL 0x02000081U +#define HCLK_VO1_S_ROOT_SEL_XIN_OSC0_FUNC 0U +#define PCLK_VO1_ROOT_SEL 0x02020081U +#define PCLK_VO1_ROOT_SEL_XIN_OSC0_FUNC 0U +#define PCLK_VO1_S_ROOT_SEL 0x02040081U +#define PCLK_VO1_S_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_I2S7_8CH_RX_SRC_SEL 0x010B0081U +#define CLK_I2S7_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON130,Offset=0x508********/ +/********Name=CLKSEL_CON131,Offset=0x50C********/ +#define MCLK_I2S7_8CH_RX_SEL 0x02000083U +#define MCLK_I2S7_8CH_RX_SEL_XIN_OSC0_HALF 0U +#define I2S7_8CH_MCLKOUT_SEL 0x01020083U +#define I2S7_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON133,Offset=0x514********/ +#define CLK_HDMITX0_EARC_SEL 0x01060085U +#define CLK_HDMITX0_EARC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON136,Offset=0x520********/ +#define CLK_HDMITX1_EARC_SEL 0x01060088U +#define CLK_HDMITX1_EARC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON138,Offset=0x528********/ +#define CLK_HDMIRX_AUD_SRC_SEL 0x0108008AU +#define CLK_HDMIRX_AUD_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON139,Offset=0x52C********/ +/********Name=CLKSEL_CON140,Offset=0x530********/ +#define CLK_HDMIRX_AUD_SEL 0x0100008CU +#define CLK_HDMIRX_AUD_SEL_CLK_HDMIRX_AUD_FRAC 0U +#define CLK_EDP0_200M_SEL 0x0201008CU +#define CLK_EDP0_200M_SEL_XIN_OSC0_FUNC 0U +#define CLK_EDP1_200M_SEL 0x0203008CU +#define CLK_EDP1_200M_SEL_XIN_OSC0_FUNC 0U +#define CLK_I2S5_8CH_TX_SRC_SEL 0x010A008CU +#define CLK_I2S5_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON141,Offset=0x534********/ +/********Name=CLKSEL_CON142,Offset=0x538********/ +#define MCLK_I2S5_8CH_TX_SEL 0x0200008EU +#define MCLK_I2S5_8CH_TX_SEL_XIN_OSC0_HALF 0U +/********Name=CLKSEL_CON144,Offset=0x540********/ +#define I2S5_8CH_MCLKOUT_SEL 0x01020090U +#define I2S5_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +#define CLK_I2S6_8CH_TX_SRC_SEL 0x01080090U +#define CLK_I2S6_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON145,Offset=0x544********/ +/********Name=CLKSEL_CON146,Offset=0x548********/ +#define MCLK_I2S6_8CH_TX_SEL 0x02000092U +#define MCLK_I2S6_8CH_TX_SEL_XIN_OSC0_HALF 0U +#define CLK_I2S6_8CH_RX_SRC_SEL 0x01070092U +#define CLK_I2S6_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON147,Offset=0x54C********/ +/********Name=CLKSEL_CON148,Offset=0x550********/ +#define MCLK_I2S6_8CH_RX_SEL 0x02000094U +#define MCLK_I2S6_8CH_RX_SEL_XIN_OSC0_HALF 0U +#define I2S6_8CH_MCLKOUT_SEL 0x02020094U +#define I2S6_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +#define CLK_SPDIF3_SRC_SEL 0x01090094U +#define CLK_SPDIF3_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON149,Offset=0x554********/ +/********Name=CLKSEL_CON15,Offset=0x33C********/ +#define MCLK_GMAC0_OUT_SEL 0x0107000FU +#define MCLK_GMAC0_OUT_SEL_CLK_CPLL_MUX 0U +#define REFCLKO25M_ETH0_OUT_SEL 0x010F000FU +#define REFCLKO25M_ETH0_OUT_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON150,Offset=0x558********/ +#define MCLK_SPDIF3_SEL 0x02000096U +#define MCLK_SPDIF3_SEL_XIN_OSC0_HALF 0U +#define CLK_SPDIF4_SRC_SEL 0x01070096U +#define CLK_SPDIF4_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON151,Offset=0x55C********/ +/********Name=CLKSEL_CON152,Offset=0x560********/ +#define MCLK_SPDIF4_SEL 0x02000098U +#define MCLK_SPDIF4_SEL_XIN_OSC0_HALF 0U +#define MCLK_SPDIFRX0_SEL 0x02070098U +#define MCLK_SPDIFRX0_SEL_CLK_AUPLL_MUX 0U +#define MCLK_SPDIFRX1_SEL 0x020E0098U +#define MCLK_SPDIFRX1_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON153,Offset=0x564********/ +#define MCLK_SPDIFRX2_SEL 0x02050099U +#define MCLK_SPDIFRX2_SEL_CLK_AUPLL_MUX 0U +#define CLK_I2S9_8CH_RX_SRC_SEL 0x010C0099U +#define CLK_I2S9_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON154,Offset=0x568********/ +/********Name=CLKSEL_CON155,Offset=0x56C********/ +#define MCLK_I2S9_8CH_RX_SEL 0x0200009BU +#define MCLK_I2S9_8CH_RX_SEL_XIN_OSC0_HALF 0U +#define CLK_I2S10_8CH_RX_SRC_SEL 0x0108009BU +#define CLK_I2S10_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON156,Offset=0x570********/ +/********Name=CLKSEL_CON157,Offset=0x574********/ +#define MCLK_I2S10_8CH_RX_SEL 0x0200009DU +#define MCLK_I2S10_8CH_RX_SEL_XIN_OSC0_HALF 0U +#define CLK_HDMITRX_REFSRC_SEL 0x0107009DU +#define CLK_HDMITRX_REFSRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON158,Offset=0x578********/ +#define CLK_GPU_SRC_T_SEL 0x0305009EU +#define CLK_GPU_SRC_T_SEL_CLK_SPLL_MUX 0U +#define CLK_TESTOUT_GPU_SEL 0x010D009EU +#define CLK_TESTOUT_GPU_SEL_CLK_GPU_PVTPLL 0U +#define CLK_GPU_SRC_SEL 0x010E009EU +#define CLK_GPU_SRC_SEL_CLK_GPU_PVTPLL 0U +/********Name=CLKSEL_CON159,Offset=0x57C********/ +/********Name=CLKSEL_CON16,Offset=0x340********/ +#define REFCLKO25M_ETH1_OUT_SEL 0x01070010U +#define REFCLKO25M_ETH1_OUT_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON160,Offset=0x580********/ +/********Name=CLKSEL_CON161,Offset=0x584********/ +#define PCLK_GPU_ROOT_SEL 0x020000A1U +#define PCLK_GPU_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_GPU_PVTPLL_SEL 0x010200A1U +#define CLK_GPU_PVTPLL_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON163,Offset=0x58C********/ +#define ACLK_AV1_ROOT_SEL 0x020500A3U +#define ACLK_AV1_ROOT_SEL_CLK_AUPLL_MUX 0U +#define PCLK_AV1_ROOT_SEL 0x020700A3U +#define PCLK_AV1_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON165,Offset=0x594********/ +#define ACLK_CENTER_ROOT_SEL 0x020000A5U +#define ACLK_CENTER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_CENTER_LOW_ROOT_SEL 0x020200A5U +#define ACLK_CENTER_LOW_ROOT_SEL_XIN_OSC0_FUNC 0U +#define HCLK_CENTER_ROOT_SEL 0x020400A5U +#define HCLK_CENTER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define PCLK_CENTER_ROOT_SEL 0x020600A5U +#define PCLK_CENTER_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_CENTER_S200_ROOT_SEL 0x020800A5U +#define ACLK_CENTER_S200_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_CENTER_S400_ROOT_SEL 0x020A00A5U +#define ACLK_CENTER_S400_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_DDR_TIMER_ROOT_SEL 0x010C00A5U +#define CLK_DDR_TIMER_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +/********Name=CLKSEL_CON166,Offset=0x598********/ +#define CLK_DDR_CM0_RTC_SEL 0x010500A6U +#define CLK_DDR_CM0_RTC_SEL_CLK_DEEPSLOW 0U +/********Name=CLKSEL_CON17,Offset=0x344********/ +#define CLK_CIFOUT_OUT_SEL 0x02080011U +#define CLK_CIFOUT_OUT_SEL_CLK_SPLL_MUX 0U +/********Name=CLKSEL_CON170,Offset=0x5A8********/ +#define ACLK_VO1USB_TOP_ROOT_SEL 0x010500AAU +#define ACLK_VO1USB_TOP_ROOT_SEL_CLK_CPLL_MUX 0U +#define HCLK_VO1USB_TOP_ROOT_SEL 0x020600AAU +#define HCLK_VO1USB_TOP_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON172,Offset=0x5B0********/ +#define HCLK_SDIO_ROOT_SEL 0x020000ACU +#define HCLK_SDIO_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CCLK_SRC_SDIO_SEL 0x020800ACU +#define CCLK_SRC_SDIO_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON174,Offset=0x5B8********/ +#define ACLK_RGA3_ROOT_SEL 0x020500AEU +#define ACLK_RGA3_ROOT_SEL_CLK_AUPLL_MUX 0U +#define HCLK_RGA3_ROOT_SEL 0x020700AEU +#define HCLK_RGA3_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_RGA3_1_CORE_SEL 0x020E00AEU +#define CLK_RGA3_1_CORE_SEL_CLK_SPLL_MUX 0U +/********Name=CLKSEL_CON176,Offset=0x5C0********/ +/********Name=CLKSEL_CON177,Offset=0x5C4********/ +#define CLK_REF_PIPE_PHY0_SEL 0x010600B1U +#define CLK_REF_PIPE_PHY0_SEL_CLK_REF_PIPE_PHY0_PLL_SRC 0U +#define CLK_REF_PIPE_PHY1_SEL 0x010700B1U +#define CLK_REF_PIPE_PHY1_SEL_CLK_REF_PIPE_PHY1_PLL_SRC 0U +#define CLK_REF_PIPE_PHY2_SEL 0x010800B1U +#define CLK_REF_PIPE_PHY2_SEL_CLK_REF_PIPE_PHY2_PLL_SRC 0U +/********Name=CLKSEL_CON18,Offset=0x348********/ +#define CLK_MIPI_CAMARAOUT_M0_SEL 0x02080012U +#define CLK_MIPI_CAMARAOUT_M0_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON19,Offset=0x34C********/ +#define CLK_MIPI_CAMARAOUT_M1_SEL 0x02080013U +#define CLK_MIPI_CAMARAOUT_M1_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON20,Offset=0x350********/ +#define CLK_MIPI_CAMARAOUT_M2_SEL 0x02080014U +#define CLK_MIPI_CAMARAOUT_M2_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON21,Offset=0x354********/ +#define CLK_MIPI_CAMARAOUT_M3_SEL 0x02080015U +#define CLK_MIPI_CAMARAOUT_M3_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON22,Offset=0x358********/ +#define CLK_MIPI_CAMARAOUT_M4_SEL 0x02080016U +#define CLK_MIPI_CAMARAOUT_M4_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON24,Offset=0x360********/ +#define HCLK_AUDIO_ROOT_SEL 0x02000018U +#define HCLK_AUDIO_ROOT_SEL_XIN_OSC0_FUNC 0U +#define PCLK_AUDIO_ROOT_SEL 0x02020018U +#define PCLK_AUDIO_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_I2S0_8CH_TX_SRC_SEL 0x01090018U +#define CLK_I2S0_8CH_TX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON25,Offset=0x364********/ +/********Name=CLKSEL_CON26,Offset=0x368********/ +#define MCLK_I2S0_8CH_TX_SEL 0x0200001AU +#define MCLK_I2S0_8CH_TX_SEL_XIN_OSC0_HALF 0U +#define CLK_I2S0_8CH_RX_SRC_SEL 0x0107001AU +#define CLK_I2S0_8CH_RX_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON27,Offset=0x36C********/ +/********Name=CLKSEL_CON28,Offset=0x370********/ +#define MCLK_I2S0_8CH_RX_SEL 0x0200001CU +#define MCLK_I2S0_8CH_RX_SEL_XIN_OSC0_HALF 0U +#define I2S0_8CH_MCLKOUT_SEL 0x0202001CU +#define I2S0_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +#define CLK_I2S2_2CH_SRC_SEL 0x0109001CU +#define CLK_I2S2_2CH_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON29,Offset=0x374********/ +/********Name=CLKSEL_CON30,Offset=0x378********/ +#define MCLK_I2S2_2CH_SEL 0x0200001EU +#define MCLK_I2S2_2CH_SEL_XIN_OSC0_HALF 0U +#define I2S2_2CH_MCLKOUT_SEL 0x0102001EU +#define I2S2_2CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +#define CLK_I2S3_2CH_SRC_SEL 0x0108001EU +#define CLK_I2S3_2CH_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON31,Offset=0x37C********/ +/********Name=CLKSEL_CON32,Offset=0x380********/ +#define MCLK_I2S3_2CH_SEL 0x02000020U +#define MCLK_I2S3_2CH_SEL_XIN_OSC0_HALF 0U +#define I2S3_2CH_MCLKOUT_SEL 0x01020020U +#define I2S3_2CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +#define CLK_SPDIF0_SRC_SEL 0x01080020U +#define CLK_SPDIF0_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON33,Offset=0x384********/ +/********Name=CLKSEL_CON34,Offset=0x388********/ +#define MCLK_SPDIF0_SEL 0x02000022U +#define MCLK_SPDIF0_SEL_XIN_OSC0_HALF 0U +#define CLK_SPDIF1_SRC_SEL 0x01070022U +#define CLK_SPDIF1_SRC_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON35,Offset=0x38C********/ +/********Name=CLKSEL_CON36,Offset=0x390********/ +#define MCLK_SPDIF1_SEL 0x02000024U +#define MCLK_SPDIF1_SEL_XIN_OSC0_HALF 0U +#define MCLK_PDM1_SEL 0x02070024U +#define MCLK_PDM1_SEL_CLK_AUPLL_MUX 0U +/********Name=CLKSEL_CON38,Offset=0x398********/ +#define ACLK_BUS_ROOT_SEL 0x01050026U +#define ACLK_BUS_ROOT_SEL_CLK_CPLL_MUX 0U +#define CLK_I2C1_SEL 0x01060026U +#define CLK_I2C1_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_I2C2_SEL 0x01070026U +#define CLK_I2C2_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_I2C3_SEL 0x01080026U +#define CLK_I2C3_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_I2C4_SEL 0x01090026U +#define CLK_I2C4_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_I2C5_SEL 0x010A0026U +#define CLK_I2C5_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_I2C6_SEL 0x010B0026U +#define CLK_I2C6_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_I2C7_SEL 0x010C0026U +#define CLK_I2C7_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_I2C8_SEL 0x010D0026U +#define CLK_I2C8_SEL_CLK_MATRIX_100M_SRC 0U +/********Name=CLKSEL_CON39,Offset=0x39C********/ +#define CLK_CAN0_SEL 0x01050027U +#define CLK_CAN0_SEL_CLK_CPLL_MUX 0U +#define CLK_CAN1_SEL 0x010B0027U +#define CLK_CAN1_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON40,Offset=0x3A0********/ +#define CLK_CAN2_SEL 0x01050028U +#define CLK_CAN2_SEL_CLK_CPLL_MUX 0U +#define CLK_SARADC_SEL 0x010E0028U +#define CLK_SARADC_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON41,Offset=0x3A4********/ +#define CLK_TSADC_SEL 0x01080029U +#define CLK_TSADC_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART1_SRC_SEL 0x010E0029U +#define CLK_UART1_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON42,Offset=0x3A8********/ +/********Name=CLKSEL_CON43,Offset=0x3AC********/ +#define SCLK_UART1_SEL 0x0200002BU +#define SCLK_UART1_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART2_SRC_SEL 0x0107002BU +#define CLK_UART2_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON44,Offset=0x3B0********/ +/********Name=CLKSEL_CON45,Offset=0x3B4********/ +#define SCLK_UART2_SEL 0x0200002DU +#define SCLK_UART2_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART3_SRC_SEL 0x0107002DU +#define CLK_UART3_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON46,Offset=0x3B8********/ +/********Name=CLKSEL_CON47,Offset=0x3BC********/ +#define SCLK_UART3_SEL 0x0200002FU +#define SCLK_UART3_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART4_SRC_SEL 0x0107002FU +#define CLK_UART4_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON48,Offset=0x3C0********/ +/********Name=CLKSEL_CON49,Offset=0x3C4********/ +#define SCLK_UART4_SEL 0x02000031U +#define SCLK_UART4_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART5_SRC_SEL 0x01070031U +#define CLK_UART5_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON50,Offset=0x3C8********/ +/********Name=CLKSEL_CON51,Offset=0x3CC********/ +#define SCLK_UART5_SEL 0x02000033U +#define SCLK_UART5_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART6_SRC_SEL 0x01070033U +#define CLK_UART6_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON52,Offset=0x3D0********/ +/********Name=CLKSEL_CON53,Offset=0x3D4********/ +#define SCLK_UART6_SEL 0x02000035U +#define SCLK_UART6_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART7_SRC_SEL 0x01070035U +#define CLK_UART7_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON54,Offset=0x3D8********/ +/********Name=CLKSEL_CON55,Offset=0x3DC********/ +#define SCLK_UART7_SEL 0x02000037U +#define SCLK_UART7_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART8_SRC_SEL 0x01070037U +#define CLK_UART8_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON56,Offset=0x3E0********/ +/********Name=CLKSEL_CON57,Offset=0x3E4********/ +#define SCLK_UART8_SEL 0x02000039U +#define SCLK_UART8_SEL_XIN_OSC0_FUNC 0U +#define CLK_UART9_SRC_SEL 0x01070039U +#define CLK_UART9_SRC_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON58,Offset=0x3E8********/ +/********Name=CLKSEL_CON59,Offset=0x3EC********/ +#define SCLK_UART9_SEL 0x0200003BU +#define SCLK_UART9_SEL_XIN_OSC0_FUNC 0U +#define CLK_SPI0_SEL 0x0202003BU +#define CLK_SPI0_SEL_XIN_OSC0_FUNC 0U +#define CLK_SPI1_SEL 0x0204003BU +#define CLK_SPI1_SEL_XIN_OSC0_FUNC 0U +#define CLK_SPI2_SEL 0x0206003BU +#define CLK_SPI2_SEL_XIN_OSC0_FUNC 0U +#define CLK_SPI3_SEL 0x0208003BU +#define CLK_SPI3_SEL_XIN_OSC0_FUNC 0U +#define CLK_SPI4_SEL 0x020A003BU +#define CLK_SPI4_SEL_XIN_OSC0_FUNC 0U +#define CLK_PWM1_SEL 0x020C003BU +#define CLK_PWM1_SEL_XIN_OSC0_FUNC 0U +#define CLK_PWM2_SEL 0x020E003BU +#define CLK_PWM2_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON60,Offset=0x3F0********/ +#define CLK_PWM3_SEL 0x0200003CU +#define CLK_PWM3_SEL_XIN_OSC0_FUNC 0U +#define CLK_BUS_TIMER_ROOT_SEL 0x0102003CU +#define CLK_BUS_TIMER_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define DBCLK_GPIO1_SEL 0x0108003CU +#define DBCLK_GPIO1_SEL_CLK_DEEPSLOW 0U +#define DBCLK_GPIO2_SEL 0x010E003CU +#define DBCLK_GPIO2_SEL_CLK_DEEPSLOW 0U +/********Name=CLKSEL_CON61,Offset=0x3F4********/ +#define DBCLK_GPIO3_SEL 0x0105003DU +#define DBCLK_GPIO3_SEL_CLK_DEEPSLOW 0U +#define DBCLK_GPIO4_SEL 0x010B003DU +#define DBCLK_GPIO4_SEL_CLK_DEEPSLOW 0U +/********Name=CLKSEL_CON62,Offset=0x3F8********/ +#define DCLK_DECOM_SEL 0x0105003EU +#define DCLK_DECOM_SEL_CLK_SPLL_MUX 0U +/********Name=CLKSEL_CON63,Offset=0x3FC********/ +#define CLK_TESTOUT_DDR01_SEL 0x0106003FU +#define CLK_TESTOUT_DDR01_SEL_CLK_DFI_CH1 0U +/********Name=CLKSEL_CON65,Offset=0x404********/ +#define CLK_TESTOUT_DDR23_SEL 0x01060041U +#define CLK_TESTOUT_DDR23_SEL_CLK_DFI_CH3 0U +/********Name=CLKSEL_CON67,Offset=0x40C********/ +#define ACLK_ISP1_ROOT_SEL 0x02050043U +#define ACLK_ISP1_ROOT_SEL_CLK_SPLL_MUX 0U +#define HCLK_ISP1_ROOT_SEL 0x02070043U +#define HCLK_ISP1_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_ISP1_CORE_SEL 0x020E0043U +#define CLK_ISP1_CORE_SEL_CLK_SPLL_MUX 0U +/********Name=CLKSEL_CON73,Offset=0x424********/ +#define HCLK_RKNN_ROOT_SEL 0x02000049U +#define HCLK_RKNN_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_RKNN_DSU0_SRC_T_SEL 0x03070049U +#define CLK_RKNN_DSU0_SRC_T_SEL_CLK_SPLL_MUX 0U +#define CLK_TESTOUT_NPU_SEL 0x010F0049U +#define CLK_TESTOUT_NPU_SEL_CLK_NPU_PVTPLL 0U +/********Name=CLKSEL_CON74,Offset=0x428********/ +#define CLK_RKNN_DSU0_SEL 0x0100004AU +#define CLK_RKNN_DSU0_SEL_CLK_NPU_PVTPLL 0U +#define PCLK_NPUTOP_ROOT_SEL 0x0201004AU +#define PCLK_NPUTOP_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_NPUTIMER_ROOT_SEL 0x0103004AU +#define CLK_NPUTIMER_ROOT_SEL_CLK_MATRIX_100M_SRC 0U +#define CLK_NPU_PVTPLL_SEL 0x0104004AU +#define CLK_NPU_PVTPLL_SEL_XIN_OSC0_FUNC 0U +#define HCLK_NPU_CM0_ROOT_SEL 0x0205004AU +#define HCLK_NPU_CM0_ROOT_SEL_XIN_OSC0_FUNC 0U +#define CLK_NPU_CM0_RTC_SEL 0x010C004AU +#define CLK_NPU_CM0_RTC_SEL_CLK_DEEPSLOW 0U +/********Name=CLKSEL_CON77,Offset=0x434********/ +#define HCLK_NVM_ROOT_SEL 0x0200004DU +#define HCLK_NVM_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_NVM_ROOT_SEL 0x0107004DU +#define ACLK_NVM_ROOT_SEL_CLK_CPLL_MUX 0U +#define CCLK_EMMC_SEL 0x020E004DU +#define CCLK_EMMC_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON78,Offset=0x438********/ +#define BCLK_EMMC_SEL 0x0105004EU +#define BCLK_EMMC_SEL_CLK_CPLL_MUX 0U +#define SCLK_SFC_SEL 0x020C004EU +#define SCLK_SFC_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON80,Offset=0x440********/ +#define PCLK_PHP_ROOT_SEL 0x02000050U +#define PCLK_PHP_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_PCIE_ROOT_SEL 0x01070050U +#define ACLK_PCIE_ROOT_SEL_CLK_CPLL_MUX 0U +#define ACLK_PHP_ROOT_SEL 0x010D0050U +#define ACLK_PHP_ROOT_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON81,Offset=0x444********/ +#define CLK_GMAC0_PTP_REF_SEL 0x01060051U +#define CLK_GMAC0_PTP_REF_SEL_CLK_GMAC0_PTPREFO 0U +#define CLK_GMAC1_PTP_REF_SEL 0x010D0051U +#define CLK_GMAC1_PTP_REF_SEL_CLK_GMAC1_PTPREFO 0U +/********Name=CLKSEL_CON82,Offset=0x448********/ +#define CLK_RXOOB0_SEL 0x01070052U +#define CLK_RXOOB0_SEL_CLK_CPLL_MUX 0U +#define CLK_RXOOB1_SEL 0x010F0052U +#define CLK_RXOOB1_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON83,Offset=0x44C********/ +#define CLK_RXOOB2_SEL 0x01070053U +#define CLK_RXOOB2_SEL_CLK_CPLL_MUX 0U +#define CLK_GMAC_125M_CRU_I_SEL 0x010F0053U +#define CLK_GMAC_125M_CRU_I_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON84,Offset=0x450********/ +#define CLK_GMAC_50M_CRU_I_SEL 0x01070054U +#define CLK_GMAC_50M_CRU_I_SEL_CLK_CPLL_MUX 0U +#define CLK_UTMI_OTG2_SEL 0x020C0054U +#define CLK_UTMI_OTG2_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON85,Offset=0x454********/ +/********Name=CLKSEL_CON89,Offset=0x464********/ +#define HCLK_RKVDEC0_ROOT_SEL 0x02000059U +#define HCLK_RKVDEC0_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_RKVDEC0_ROOT_SEL 0x02070059U +#define ACLK_RKVDEC0_ROOT_SEL_CLK_SPLL_MUX 0U +#define ACLK_RKVDEC_CCU_SEL 0x020E0059U +#define ACLK_RKVDEC_CCU_SEL_CLK_SPLL_MUX 0U +/********Name=CLKSEL_CON90,Offset=0x468********/ +#define CLK_RKVDEC0_CA_SEL 0x0105005AU +#define CLK_RKVDEC0_CA_SEL_CLK_CPLL_MUX 0U +#define CLK_RKVDEC0_HEVC_CA_SEL 0x020B005AU +#define CLK_RKVDEC0_HEVC_CA_SEL_CLK_MATRIX_1000M_SRC 0U +/********Name=CLKSEL_CON91,Offset=0x46C********/ +#define CLK_RKVDEC0_CORE_SEL 0x0105005BU +#define CLK_RKVDEC0_CORE_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON93,Offset=0x474********/ +#define HCLK_RKVDEC1_ROOT_SEL 0x0200005DU +#define HCLK_RKVDEC1_ROOT_SEL_XIN_OSC0_FUNC 0U +#define ACLK_RKVDEC1_ROOT_SEL 0x0207005DU +#define ACLK_RKVDEC1_ROOT_SEL_CLK_NPLL_MUX 0U +#define CLK_RKVDEC1_CA_SEL 0x010E005DU +#define CLK_RKVDEC1_CA_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON94,Offset=0x478********/ +#define CLK_RKVDEC1_HEVC_CA_SEL 0x0205005EU +#define CLK_RKVDEC1_HEVC_CA_SEL_CLK_MATRIX_1000M_SRC 0U +#define CLK_RKVDEC1_CORE_SEL 0x010C005EU +#define CLK_RKVDEC1_CORE_SEL_CLK_CPLL_MUX 0U +/********Name=CLKSEL_CON96,Offset=0x480********/ +#define ACLK_USB_ROOT_SEL 0x01050060U +#define ACLK_USB_ROOT_SEL_CLK_CPLL_MUX 0U +#define HCLK_USB_ROOT_SEL 0x02060060U +#define HCLK_USB_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON98,Offset=0x488********/ +#define ACLK_VDPU_ROOT_SEL 0x02050062U +#define ACLK_VDPU_ROOT_SEL_CLK_AUPLL_MUX 0U +#define ACLK_VDPU_LOW_ROOT_SEL 0x02070062U +#define ACLK_VDPU_LOW_ROOT_SEL_XIN_OSC0_FUNC 0U +#define HCLK_VDPU_ROOT_SEL 0x02090062U +#define HCLK_VDPU_ROOT_SEL_XIN_OSC0_FUNC 0U +/********Name=CLKSEL_CON99,Offset=0x48C********/ +#define ACLK_JPEG_DECODER_ROOT_SEL 0x02050063U +#define ACLK_JPEG_DECODER_ROOT_SEL_CLK_SPLL_MUX 0U +#define CLK_IEP2P0_CORE_SEL 0x010C0063U +#define CLK_IEP2P0_CORE_SEL_CLK_CPLL_MUX 0U + +/********Name=PMU1CLKSEL_CON00,Offset=0x300********/ +#define CLK_MATRIX_PMU1_300M_SRC_SEL 0x010F0000U +#define CLK_MATRIX_PMU1_300M_SRC_SEL_XIN_OSC0_FUNC 0U +/********Name=PMU1CLKSEL_CON01,Offset=0x304********/ +#define CLK_MATRIX_PMU1_400M_SRC_SEL 0x01050001U +#define CLK_MATRIX_PMU1_400M_SRC_SEL_XIN_OSC0_FUNC 0U +#define HCLK_PMU1_ROOT_I_SEL 0x02060001U +#define HCLK_PMU1_ROOT_I_SEL_XIN_OSC0_FUNC 0U +#define PCLK_PMU1_ROOT_I_SEL 0x02080001U +#define PCLK_PMU1_ROOT_I_SEL_XIN_OSC0_FUNC 0U +#define HCLK_PMU_CM0_ROOT_I_SEL 0x020A0001U +#define HCLK_PMU_CM0_ROOT_I_SEL_XIN_OSC0_FUNC 0U +/********Name=PMU1CLKSEL_CON02,Offset=0x308********/ +#define CLK_PMU_CM0_RTC_SEL 0x01050002U +#define CLK_PMU_CM0_RTC_SEL_CLK_DEEPSLOW 0U +#define TCLK_PMU1WDT_SEL 0x01060002U +#define TCLK_PMU1WDT_SEL_CLK_DEEPSLOW 0U +#define CLK_PMU1TIMER_ROOT_SEL 0x02070002U +#define CLK_PMU1TIMER_ROOT_SEL_CLK_MATRIX_PMU1_100M_SRC 0U +#define CLK_PMU1PWM_SEL 0x02090002U +#define CLK_PMU1PWM_SEL_XIN_OSC0_FUNC 0U +/********Name=PMU1CLKSEL_CON03,Offset=0x30C********/ +#define CLK_I2C0_SEL 0x01060003U +#define CLK_I2C0_SEL_CLK_MATRIX_PMU1_100M_SRC 0U +/********Name=PMU1CLKSEL_CON04,Offset=0x310********/ +/********Name=PMU1CLKSEL_CON05,Offset=0x314********/ +#define SCLK_UART0_SEL 0x02000005U +#define SCLK_UART0_SEL_XIN_OSC0_FUNC 0U +/********Name=PMU1CLKSEL_CON06,Offset=0x318********/ +/********Name=PMU1CLKSEL_CON07,Offset=0x31C********/ +#define MCLK_I2S1_8CH_TX_SEL 0x02000007U +#define MCLK_I2S1_8CH_TX_SEL_XIN_OSC0_HALF 0U +/********Name=PMU1CLKSEL_CON08,Offset=0x320********/ +/********Name=PMU1CLKSEL_CON09,Offset=0x324********/ +#define MCLK_I2S1_8CH_RX_SEL 0x02000009U +#define MCLK_I2S1_8CH_RX_SEL_XIN_OSC0_HALF 0U +#define I2S1_8CH_MCLKOUT_SEL 0x02020009U +#define I2S1_8CH_MCLKOUT_SEL_XIN_OSC0_HALF 0U +#define MCLK_PDM0_SEL 0x01040009U +#define MCLK_PDM0_SEL_CLK_MATRIX_PMU1_200M_SRC 0U +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_SEL 0x010A0009U +#define CLK_USBDP_COMBO_PHY0_REF_XTAL_SEL_CLK_PPLL 0U +/********Name=PMU1CLKSEL_CON12,Offset=0x330********/ +#define CLK_HDPTX0_REF_XTAL_SEL 0x010B000CU +#define CLK_HDPTX0_REF_XTAL_SEL_CLK_PPLL 0U +/********Name=PMU1CLKSEL_CON14,Offset=0x338********/ +#define CLK_REF_MIPI_DCPHY0_SEL 0x0207000EU +#define CLK_REF_MIPI_DCPHY0_SEL_CLK_SPLL_MUX 0U +#define CLK_OTGPHY_U3_0_SEL 0x010E000EU +#define CLK_OTGPHY_U3_0_SEL_CLK_PPLL 0U +/********Name=PMU1CLKSEL_CON15,Offset=0x33C********/ +#define CLK_CR_PARA_SEL 0x0205000FU +#define CLK_CR_PARA_SEL_CLK_SPLL_MUX 0U +/********Name=PMU1CLKSEL_CON17,Offset=0x344********/ +#define DBCLK_GPIO0_SEL 0x01000011U +#define DBCLK_GPIO0_SEL_CLK_DEEPSLOW 0U + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __RK3588_H */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/RK3588RegsPeri.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/RK3588RegsPeri.h new file mode 100644 index 0000000..3cf9fe2 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/RK3588RegsPeri.h @@ -0,0 +1,13 @@ +/** @file +* +* Copyright (c) 2021, Rockchip Ltd. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + +#ifndef __RK3588_REGS_PERI_H__ +#define __RK3588_REGS_PERI_H__ + + +#endif /* __RK3588_REGS_PERI_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/ScmiDefinitions.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/ScmiDefinitions.h new file mode 100644 index 0000000..9b17fde --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/ScmiDefinitions.h @@ -0,0 +1,55 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2024, Rockchip, Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __RK3588_SCMI_DEFINITIONS_H__ +#define __RK3588_SCMI_DEFINITIONS_H__ + +#define SCMI_CLK_CPUL 0 +#define SCMI_CLK_DSU 1 +#define SCMI_CLK_CPUB01 2 +#define SCMI_CLK_CPUB23 3 +#define SCMI_CLK_DDR 4 +#define SCMI_CLK_GPU 5 +#define SCMI_CLK_NPU 6 +#define SCMI_CLK_SBUS 7 +#define SCMI_PCLK_SBUS 8 +#define SCMI_CCLK_SD 9 +#define SCMI_DCLK_SD 10 +#define SCMI_ACLK_SECURE_NS 11 +#define SCMI_HCLK_SECURE_NS 12 +#define SCMI_TCLK_WDT 13 +#define SCMI_KEYLADDER_CORE 14 +#define SCMI_KEYLADDER_RNG 15 +#define SCMI_ACLK_SECURE_S 16 +#define SCMI_HCLK_SECURE_S 17 +#define SCMI_PCLK_SECURE_S 18 +#define SCMI_CRYPTO_RNG 19 +#define SCMI_CRYPTO_CORE 20 +#define SCMI_CRYPTO_PKA 21 +#define SCMI_SPLL 22 +#define SCMI_HCLK_SD 23 +#define SCMI_CRYPTO_RNG_S 24 +#define SCMI_CRYPTO_CORE_S 25 +#define SCMI_CRYPTO_PKA_S 26 +#define SCMI_A_CRYPTO_S 27 +#define SCMI_H_CRYPTO_S 28 +#define SCMI_P_CRYPTO_S 29 +#define SCMI_A_KEYLADDER_S 30 +#define SCMI_H_KEYLADDER_S 31 +#define SCMI_P_KEYLADDER_S 32 +#define SCMI_TRNG_S 33 +#define SCMI_H_TRNG_S 34 +#define SCMI_P_OTPC_S 35 +#define SCMI_OTPC_S 36 +#define SCMI_OTP_PHY 37 +#define SCMI_OTPC_AUTO_RD 38 +#define SCMI_OTPC_ARB 39 +#define SCMI_CCLK_EMMC 40 + +#endif // __RK3588_SCMI_DEFINITIONS_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Soc.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Soc.h new file mode 100644 index 0000000..8c1ec31 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/Soc.h @@ -0,0 +1,86 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __SOC_H +#define __SOC_H +#ifdef __cplusplus + extern "C" { +#endif +#define uint8_t UINT8 +#define uint16_t UINT16 +#define uint32_t UINT32 +#define uint64_t UINT64 +#define HAL_ASSERT ASSERT +#define HAL_CPUDelayUs MicroSecondDelay +#define __WEAK +#define HAL_DivU64 DivU64x32 +/* IO definitions (access restrictions to peripheral registers) */ +/*!< brief Defines 'read only' permissions */ +#ifdef __cplusplus + #define __I volatile +#else + #define __I volatile const +#endif +/*!< brief Defines 'write only' permissions */ +#define __O volatile +/*!< brief Defines 'read / write' permissions */ +#define __IO volatile + +/**< Write the register */ +#define WRITE_REG(REG, VAL) ((*(volatile uint32_t *)&(REG)) = (VAL)) +/**< Read the register */ +#define READ_REG(REG) ((*(volatile const uint32_t *)&(REG))) +#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ +#include "RK3588.h" +#define RK3588_PERIPH_BASE 0xF0000000 +#define RK3588_PERIPH_SZ 0x10000000 + +#define I2C_BASE(id) ((id == 0) ? 0xFD880000 : \ + (id <= 5) ? (0xFEA90000 + ((id - 1) * 0x10000)) : \ + (id <= 8) ? (0xFEC80000 + ((id - 6) * 0x10000)) : 0) +#define I2C_COUNT 9 + +/******************************************CRU*******************************************/ +#define PLL_INPUT_OSC_RATE (24 * 1000 * 1000) + +typedef enum { + PLL_LPLL = 0, + PLL_B0PLL, + PLL_B1PLL, + PLL_CPLL, + PLL_GPLL, + PLL_NPLL, + PLL_V0PLL, + PLL_PPLL, + PLL_AUPLL, + CCLK_EMMC, + SCLK_SFC, + CCLK_SRC_SDIO, + BCLK_EMMC, + CLK_REF_PIPE_PHY0, + CLK_REF_PIPE_PHY1, + CLK_REF_PIPE_PHY2, + DCLK_VOP2_SRC, + CLK_I2S0_8CH_TX_SRC, + MCLK_I2S0_8CH_TX, + MCLK_I2S1_8CH_TX, + CLK_COUNT +} RK3588_CLOCK_IDS; + +typedef enum { + RESET_COUNT = 0 +} RK3588_RESET_IDS; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __SOC_H */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h new file mode 100644 index 0000000..d7166de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h @@ -0,0 +1,97 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __VARSTORE_DATA_H__ +#define __VARSTORE_DATA_H__ + +#define CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT 0 +#define CPU_PERF_CLUSTER_CLOCK_PRESET_MIN 1 +#define CPU_PERF_CLUSTER_CLOCK_PRESET_MAX 2 +#define CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM 3 +typedef struct { + UINT32 Preset; +} CPU_PERF_CLUSTER_CLOCK_PRESET_VARSTORE_DATA; + +typedef struct { + UINT32 Mhz; +} CPU_PERF_CLUSTER_CLOCK_CUSTOM_VARSTORE_DATA; + +#define CPU_PERF_CLUSTER_VOLTAGE_MODE_AUTO 0 +#define CPU_PERF_CLUSTER_VOLTAGE_MODE_CUSTOM 1 +typedef struct { + UINT32 Mode; +} CPU_PERF_CLUSTER_VOLTAGE_MODE_VARSTORE_DATA; + +typedef struct { + UINT32 Microvolts; +} CPU_PERF_CLUSTER_VOLTAGE_CUSTOM_VARSTORE_DATA; + +#define COMBO_PHY_MODE_UNCONNECTED 0 +#define COMBO_PHY_MODE_PCIE 1 +#define COMBO_PHY_MODE_SATA 2 +#define COMBO_PHY_MODE_USB3 3 +typedef struct { + UINT32 Mode; +} COMBO_PHY_MODE_VARSTORE_DATA; + +#define PCIE30_STATE_DISABLED 0 +#define PCIE30_STATE_ENABLED 1 +typedef struct { + UINT32 State; +} PCIE30_STATE_VARSTORE_DATA; + +#define PCIE30_PHY_MODE_AGGREGATION 4 +#define PCIE30_PHY_MODE_NANBNB 0 +#define PCIE30_PHY_MODE_NANBBI 1 +#define PCIE30_PHY_MODE_NABINB 2 +#define PCIE30_PHY_MODE_NABIBI 3 +typedef struct { + UINT8 Mode; +} PCIE30_PHY_MODE_VARSTORE_DATA; + +#define CONFIG_TABLE_MODE_ACPI 0x00000001 +#define CONFIG_TABLE_MODE_FDT 0x00000002 +#define CONFIG_TABLE_MODE_ACPI_FDT 0x00000003 +typedef struct { + UINT32 Mode; +} CONFIG_TABLE_MODE_VARSTORE_DATA; + +#define ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV 0x00000001 +#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6 0x00000002 +#define ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON 0x00000004 +#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV 0x00000003 +#define ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON 0x00000006 +typedef struct { + UINT32 Mode; +} ACPI_PCIE_ECAM_COMPAT_MODE_VARSTORE_DATA; + +typedef struct { + UINT8 State; +} FDT_SUPPORT_OVERRIDES_VARSTORE_DATA; + +#define COOLING_FAN_STATE_DISABLED 0 +#define COOLING_FAN_STATE_ENABLED 1 +typedef struct { + UINT32 State; +} COOLING_FAN_STATE_VARSTORE_DATA; + +typedef struct { + UINT32 Percentage; +} COOLING_FAN_SPEED_VARSTORE_DATA; + +#define USBDP_PHY_USB3_STATE_DISABLED 0 +#define USBDP_PHY_USB3_STATE_ENABLED 1 +typedef struct { + UINT32 State; +} USBDP_PHY_USB3_STATE_VARSTORE_DATA; + +typedef struct { + UINT64 Value; +} DEBUG_SERIAL_PORT_BAUD_RATE_VARSTORE_DATA; + +#endif // __VARSTORE_DATA_H__ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/DwcSdhciPlatformLib/DwcSdhciPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/DwcSdhciPlatformLib/DwcSdhciPlatformLib.c new file mode 100644 index 0000000..685da37 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/DwcSdhciPlatformLib/DwcSdhciPlatformLib.c @@ -0,0 +1,63 @@ +/** @file + * + * DwcSdhciDxe platform helper library. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include + +#define NS_CRU_BASE 0xFD7C0000 +#define CRU_CLKSEL_CON77 0x0434 + +#define EMMC_CLOCK_BASE (NS_CRU_BASE + CRU_CLKSEL_CON77) + +EFI_STATUS +EFIAPI +DwcSdhciSetClockRate ( + IN UINTN Frequency + ) +{ + UINT32 CClkEmmcSel, Div; + + if (Frequency >= 200000000) { + CClkEmmcSel = 0; + Div = 6; + } else if (Frequency >= 150000000) { + CClkEmmcSel = 0; + Div = 8; + } else if (Frequency >= 100000000) { + CClkEmmcSel = 0; + Div = 12; + } else if (Frequency >= 50000000) { + CClkEmmcSel = 0; + Div = 24; + } else if (Frequency >= 24000000) { + CClkEmmcSel = 2; + Div = 1; + } else { /* 375KHZ*/ + CClkEmmcSel = 2; + Div = 64; + } + + MmioWrite32(EMMC_CLOCK_BASE, ((( 0x3 << 14 )|( 0x3F << 8 )) << 16 ) | + ( CClkEmmcSel << 14 ) | + (( Div - 1 ) << 8)); + + return EFI_SUCCESS; +} + +VOID +EFIAPI +DwcSdhciSetIoMux ( + VOID + ) +{ + SdhciEmmcIoMux (); +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/DwcSdhciPlatformLib/DwcSdhciPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/DwcSdhciPlatformLib/DwcSdhciPlatformLib.inf new file mode 100644 index 0000000..cf867a0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/DwcSdhciPlatformLib/DwcSdhciPlatformLib.inf @@ -0,0 +1,28 @@ +#/** @file +# +# DwcSdhciDxe platform helper library. +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = DwcSdhciPlatformLib + FILE_GUID = a3d2126b-6110-4bc5-8b96-c95ac9858b04 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = DwcSdhciPlatformLib + +[Sources] + DwcSdhciPlatformLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + IoLib + RockchipPlatformLib diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.c new file mode 100644 index 0000000..f156184 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.c @@ -0,0 +1,339 @@ +/** @file + * + * RK3588 GPIO Library. + * + * Copyright (c) 2021, Jared McNeill + * Copyright (c) 2023, Molly Sophia + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ +#include +#include +#include +#include +#include + +#define GRF_GPIO_IOMUX_REG(Pin) (((Pin) / 4) * 4) +#define GRF_GPIO_IOMUX_SHIFT(Pin) (((Pin) % 4) * 4) +#define GRF_GPIO_IOMUX_MASK(Pin) (0xFU << (GRF_GPIO_IOMUX_SHIFT(Pin) + 16)) + +#define GRF_GPIO_P_REG(Pin) (((Pin) / 8) * 4) +#define GRF_GPIO_P_SHIFT(Pin) (((Pin) % 8) * 2) +#define GRF_GPIO_P_MASK(Pin) (0x3U << (GRF_GPIO_P_SHIFT (Pin) + 16)) + +#define GRF_GPIO_DS_REG(Pin) (((Pin) / 4) * 4) +#define GRF_GPIO_DS_SHIFT(Pin) (((Pin) % 4) * 4) +#define GRF_GPIO_DS_MASK(Pin) (0xFFU << (GRF_GPIO_DS_SHIFT (Pin) + 16)) + +#define GRF_GPIO_IE_REG(Pin) (((Pin) / 8) * 4) +#define GRF_GPIO_IE_SHIFT(Pin) (((Pin) % 8) * 2) +#define GRF_GPIO_IE_MASK(Pin) (0x3U << (GRF_GPIO_IE_SHIFT (Pin) + 16)) + +#define GPIO_SWPORT_DR(Pin) ((Pin) < 16 ? 0x0000 : 0x0004) +#define GPIO_SWPORT_DDR(Pin) ((Pin) < 16 ? 0x0008 : 0x000C) + +#define GPIO_WRITE_MASK(Pin) (1U << (((Pin) % 16) + 16)) +#define GPIO_VALUE_MASK(Pin, Value) ((UINT32)Value << ((Pin) % 16)) + +#define GPIO_EXT_PORT 0x0070 + +#define GPIO_NGROUPS 5 + +#define PMU1_IOC_BASE (0xFD5F0000U) +#define PMU2_IOC_BASE (PMU1_IOC_BASE + 0x4000) +#define BUS_IOC_BASE (PMU1_IOC_BASE + 0x8000) +#define VCCIO1_4_IOC_BASE (PMU1_IOC_BASE + 0x9000) +#define VCCIO3_5_IOC_BASE (PMU1_IOC_BASE + 0xA000) +#define VCCIO2_IOC_BASE (PMU1_IOC_BASE + 0xB000) +#define VCCIO6_IOC_BASE (PMU1_IOC_BASE + 0xC000) +#define EMMC_IOC_BASE (PMU1_IOC_BASE + 0xD000) + +typedef struct { + UINT8 Group; + UINT8 Pin; + EFI_PHYSICAL_ADDRESS Addr; +} GPIO_REG; + +STATIC GPIO_REG mDsReg[] = { + {0, GPIO_PIN_PA0, PMU1_IOC_BASE + 0x0010}, + {0, GPIO_PIN_PA4, PMU1_IOC_BASE + 0x0014}, + {0, GPIO_PIN_PB0, PMU1_IOC_BASE + 0x0018}, + {0, GPIO_PIN_PB4, PMU2_IOC_BASE + 0x0014}, + {0, GPIO_PIN_PC0, PMU2_IOC_BASE + 0x0018}, + {0, GPIO_PIN_PC4, PMU2_IOC_BASE + 0x001C}, + {0, GPIO_PIN_PD0, PMU2_IOC_BASE + 0x0020}, + {0, GPIO_PIN_PD4, PMU2_IOC_BASE + 0x0024}, + {1, GPIO_PIN_PA0, VCCIO1_4_IOC_BASE + 0x0020}, + {1, GPIO_PIN_PA4, VCCIO1_4_IOC_BASE + 0x0024}, + {1, GPIO_PIN_PB0, VCCIO1_4_IOC_BASE + 0x0028}, + {1, GPIO_PIN_PB4, VCCIO1_4_IOC_BASE + 0x002C}, + {1, GPIO_PIN_PC0, VCCIO1_4_IOC_BASE + 0x0030}, + {1, GPIO_PIN_PC4, VCCIO1_4_IOC_BASE + 0x0034}, + {1, GPIO_PIN_PD0, VCCIO1_4_IOC_BASE + 0x0038}, + {1, GPIO_PIN_PD4, VCCIO1_4_IOC_BASE + 0x003C}, + {2, GPIO_PIN_PA0, EMMC_IOC_BASE + 0x0040}, + {2, GPIO_PIN_PA4, VCCIO3_5_IOC_BASE + 0x0044}, + {2, GPIO_PIN_PB0, VCCIO3_5_IOC_BASE + 0x0048}, + {2, GPIO_PIN_PB4, VCCIO3_5_IOC_BASE + 0x004C}, + {2, GPIO_PIN_PC0, VCCIO3_5_IOC_BASE + 0x0050}, + {2, GPIO_PIN_PC4, VCCIO3_5_IOC_BASE + 0x0054}, + {2, GPIO_PIN_PD0, EMMC_IOC_BASE + 0x0058}, + {2, GPIO_PIN_PD4, EMMC_IOC_BASE + 0x005C}, + {3, GPIO_PIN_PA0, VCCIO3_5_IOC_BASE + 0x0060}, + {3, GPIO_PIN_PA4, VCCIO3_5_IOC_BASE + 0x0064}, + {3, GPIO_PIN_PB0, VCCIO3_5_IOC_BASE + 0x0068}, + {3, GPIO_PIN_PB4, VCCIO3_5_IOC_BASE + 0x006C}, + {3, GPIO_PIN_PC0, VCCIO3_5_IOC_BASE + 0x0070}, + {3, GPIO_PIN_PC4, VCCIO3_5_IOC_BASE + 0x0074}, + {3, GPIO_PIN_PD0, VCCIO3_5_IOC_BASE + 0x0078}, + {3, GPIO_PIN_PD4, VCCIO3_5_IOC_BASE + 0x007C}, + {4, GPIO_PIN_PA0, VCCIO6_IOC_BASE + 0x0080}, + {4, GPIO_PIN_PA4, VCCIO6_IOC_BASE + 0x0084}, + {4, GPIO_PIN_PB0, VCCIO6_IOC_BASE + 0x0088}, + {4, GPIO_PIN_PB4, VCCIO6_IOC_BASE + 0x008C}, + {4, GPIO_PIN_PC0, VCCIO6_IOC_BASE + 0x0090}, + {4, GPIO_PIN_PC2, VCCIO3_5_IOC_BASE + 0x0090}, + {4, GPIO_PIN_PC4, VCCIO3_5_IOC_BASE + 0x0094}, + {4, GPIO_PIN_PD0, VCCIO2_IOC_BASE + 0x0098}, +}; + +STATIC GPIO_REG mPullReg[] = { + {0, GPIO_PIN_PA0, PMU1_IOC_BASE + 0x0020}, + {0, GPIO_PIN_PB0, PMU1_IOC_BASE + 0x0024}, + {0, GPIO_PIN_PB5, PMU2_IOC_BASE + 0x0028}, + {0, GPIO_PIN_PC0, PMU2_IOC_BASE + 0x002C}, + {0, GPIO_PIN_PD0, PMU2_IOC_BASE + 0x0030}, + {1, GPIO_PIN_PA0, VCCIO1_4_IOC_BASE + 0x0110}, + {1, GPIO_PIN_PB0, VCCIO1_4_IOC_BASE + 0x0114}, + {1, GPIO_PIN_PC0, VCCIO1_4_IOC_BASE + 0x0118}, + {1, GPIO_PIN_PD0, VCCIO1_4_IOC_BASE + 0x011C}, + {2, GPIO_PIN_PA0, EMMC_IOC_BASE + 0x0120}, + {2, GPIO_PIN_PA4, VCCIO3_5_IOC_BASE + 0x0120}, + {2, GPIO_PIN_PB0, VCCIO3_5_IOC_BASE + 0x0124}, + {2, GPIO_PIN_PC0, VCCIO3_5_IOC_BASE + 0x0128}, + {2, GPIO_PIN_PD0, EMMC_IOC_BASE + 0x012C}, + {3, GPIO_PIN_PA0, VCCIO3_5_IOC_BASE + 0x0130}, + {3, GPIO_PIN_PB0, VCCIO3_5_IOC_BASE + 0x0134}, + {3, GPIO_PIN_PC0, VCCIO3_5_IOC_BASE + 0x0138}, + {3, GPIO_PIN_PD0, VCCIO3_5_IOC_BASE + 0x013C}, + {4, GPIO_PIN_PA0, VCCIO6_IOC_BASE + 0x0140}, + {4, GPIO_PIN_PB0, VCCIO6_IOC_BASE + 0x0144}, + {4, GPIO_PIN_PC0, VCCIO6_IOC_BASE + 0x0148}, + {4, GPIO_PIN_PC2, VCCIO3_5_IOC_BASE + 0x0148}, + {4, GPIO_PIN_PD0, VCCIO2_IOC_BASE + 0x014C}, +}; + +STATIC GPIO_REG mIEReg[] = { + {0, GPIO_PIN_PA0, PMU1_IOC_BASE + 0x0028}, + {0, GPIO_PIN_PB0, PMU1_IOC_BASE + 0x002C}, + {0, GPIO_PIN_PB5, PMU2_IOC_BASE + 0x0034}, + {0, GPIO_PIN_PC0, PMU2_IOC_BASE + 0x0038}, + {0, GPIO_PIN_PD0, PMU2_IOC_BASE + 0x003C}, + {1, GPIO_PIN_PA0, VCCIO1_4_IOC_BASE + 0x0180}, + {1, GPIO_PIN_PB0, VCCIO1_4_IOC_BASE + 0x0184}, + {1, GPIO_PIN_PC0, VCCIO1_4_IOC_BASE + 0x0188}, + {1, GPIO_PIN_PD0, VCCIO1_4_IOC_BASE + 0x018C}, + {2, GPIO_PIN_PA0, EMMC_IOC_BASE + 0x0190}, + {2, GPIO_PIN_PA4, VCCIO3_5_IOC_BASE + 0x0190}, + {2, GPIO_PIN_PB0, VCCIO3_5_IOC_BASE + 0x0194}, + {2, GPIO_PIN_PC0, VCCIO3_5_IOC_BASE + 0x0198}, + {2, GPIO_PIN_PD0, EMMC_IOC_BASE + 0x019C}, + {3, GPIO_PIN_PA0, VCCIO3_5_IOC_BASE + 0x01A0}, + {3, GPIO_PIN_PB0, VCCIO3_5_IOC_BASE + 0x01A4}, + {3, GPIO_PIN_PC0, VCCIO3_5_IOC_BASE + 0x01A8}, + {3, GPIO_PIN_PD0, VCCIO3_5_IOC_BASE + 0x01AC}, + {4, GPIO_PIN_PA0, VCCIO6_IOC_BASE + 0x01B0}, + {4, GPIO_PIN_PB0, VCCIO6_IOC_BASE + 0x01B4}, + {4, GPIO_PIN_PC0, VCCIO6_IOC_BASE + 0x01B8}, + {4, GPIO_PIN_PC2, VCCIO3_5_IOC_BASE + 0x01B8}, + {4, GPIO_PIN_PD0, VCCIO2_IOC_BASE + 0x01BC}, +}; + +#define GPIO_BASE(n) ((n) == 0 ? 0xFD8A0000UL : (0xFEC20000UL + ((n) - 1) * 0x10000)) + +VOID +GpioPinSetDirection ( + IN UINT8 Group, + IN UINT8 Pin, + IN GPIO_PIN_DIRECTION Direction + ) +{ + DEBUG((DEBUG_INFO, "GpioPinSetDirection Group:%d Pin:%d Direction:%d\n", + Group, Pin, Direction)); + MmioWrite32 (GPIO_BASE (Group) + GPIO_SWPORT_DDR (Pin), + GPIO_WRITE_MASK (Pin) | GPIO_VALUE_MASK (Pin, Direction)); +} + +VOID +GpioPinWrite ( + IN UINT8 Group, + IN UINT8 Pin, + IN BOOLEAN Value + ) +{ + DEBUG((DEBUG_VERBOSE, "GpioPinWrite Group:%d Pin:%d Value:%d\n", + Group, Pin, Value)); + MmioWrite32 (GPIO_BASE (Group) + GPIO_SWPORT_DR (Pin), + GPIO_WRITE_MASK (Pin) | GPIO_VALUE_MASK (Pin, Value)); +} + +BOOLEAN +GpioPinRead ( + IN UINT8 Group, + IN UINT8 Pin + ) +{ + CONST UINT32 Value = MmioRead32 (GPIO_BASE (Group) + GPIO_SWPORT_DR (Pin)); + return (Value & GPIO_VALUE_MASK (Pin, 1)) != 0; +} + +BOOLEAN +GpioPinReadActual ( + IN UINT8 Group, + IN UINT8 Pin + ) +{ + CONST UINT32 Value = MmioRead32 (GPIO_BASE (Group) + GPIO_EXT_PORT); + return (Value & (1 << Pin)) != 0; +} + +VOID +GpioPinSetFunction ( + IN UINT8 Group, + IN UINT8 Pin, + IN UINT8 Function + ) +{ + ASSERT (Group < GPIO_NGROUPS); + + EFI_PHYSICAL_ADDRESS Reg; + UINT32 Value = GRF_GPIO_IOMUX_MASK (Pin) | ((UINT32)Function << GRF_GPIO_IOMUX_SHIFT (Pin)); + + DEBUG ((DEBUG_INFO, "GpioPinSetFunction Group:%d Pin:%d Function:%d\n", Group, Pin, Function)); + + if(Group == 0) { + if(Pin >= GPIO_PIN_PB4) { + if(Function >= 8) { + Reg = PMU2_IOC_BASE - 0xC + GRF_GPIO_IOMUX_REG(Pin); + Value = GRF_GPIO_IOMUX_MASK (Pin) | ((UINT32)8 << GRF_GPIO_IOMUX_SHIFT (Pin)); + MmioWrite32(Reg, Value); + + Reg = BUS_IOC_BASE + GRF_GPIO_IOMUX_REG(Pin); + Value = GRF_GPIO_IOMUX_MASK (Pin) | ((UINT32)Function << GRF_GPIO_IOMUX_SHIFT (Pin)); + MmioWrite32(Reg, Value); + } else { + Reg = PMU2_IOC_BASE - 0xC + GRF_GPIO_IOMUX_REG(Pin); + Value = GRF_GPIO_IOMUX_MASK (Pin) | ((UINT32)Function << GRF_GPIO_IOMUX_SHIFT (Pin)); + MmioWrite32(Reg, Value); + + Reg = BUS_IOC_BASE + GRF_GPIO_IOMUX_REG(Pin); + Value = GRF_GPIO_IOMUX_MASK (Pin); + MmioWrite32(Reg, Value); + } + DEBUG ((DEBUG_VERBOSE, "Reg - Value: 0x%lX = 0x%08X\n", Reg, Value)); + return; + } else { + Reg = PMU1_IOC_BASE + GRF_GPIO_IOMUX_REG(Pin); + } + } else { + Reg = BUS_IOC_BASE + Group * 0x20 + GRF_GPIO_IOMUX_REG(Pin); + } + + DEBUG ((DEBUG_VERBOSE, "Reg - Value: 0x%lX = 0x%08X\n", Reg, Value)); + MmioWrite32 (Reg, Value); +} + +VOID +GpioPinSetPull ( + IN UINT8 Group, + IN UINT8 Pin, + IN GPIO_PIN_PULL Pull + ) +{ + ASSERT (Group < GPIO_NGROUPS); + + INTN Idx; + EFI_PHYSICAL_ADDRESS Reg; + CONST UINT32 Value = GRF_GPIO_P_MASK (Pin) | ((UINT32)Pull << GRF_GPIO_P_SHIFT (Pin)); + + for(Idx = ARRAY_SIZE(mPullReg) - 1; Idx >= 0; Idx--) { + if(Group == mPullReg[Idx].Group && Pin >= mPullReg[Idx].Pin) { + Reg = mPullReg[Idx].Addr + GRF_GPIO_P_REG(Pin - mPullReg[Idx].Pin); + } + } + + DEBUG ((DEBUG_INFO, "GpioPinSetPull Group:%d Pin:%d Pull:%d\n", Group, Pin, Pull)); + DEBUG ((DEBUG_VERBOSE, "Reg - Value: 0x%lX = 0x%08X\n", Reg, Value)); + + MmioWrite32 (Reg, Value); +} + +VOID +GpioPinSetDrive ( + IN UINT8 Group, + IN UINT8 Pin, + IN GPIO_PIN_DRIVE Drive + ) +{ + ASSERT (Group < GPIO_NGROUPS); + + INTN Idx; + EFI_PHYSICAL_ADDRESS Reg; + CONST UINT32 Value = GRF_GPIO_DS_MASK (Pin) | ((UINT32)Drive << GRF_GPIO_DS_SHIFT (Pin)); + + for(Idx = ARRAY_SIZE(mDsReg) - 1; Idx >= 0; Idx--) { + if(Group == mDsReg[Idx].Group && Pin >= mDsReg[Idx].Pin) { + Reg = mDsReg[Idx].Addr + GRF_GPIO_DS_REG(Pin - mDsReg[Idx].Pin); + } + } + + DEBUG ((DEBUG_INFO, "GpioPinSetDrive Group:%d Pin:%d Drive:%d\n", Group, Pin, Drive)); + DEBUG ((DEBUG_VERBOSE, "Reg - Value: 0x%lX = 0x%08X\n", Reg, Value)); + + MmioWrite32 (Reg, Value); +} + +VOID +GpioPinSetInput ( + IN UINT8 Group, + IN UINT8 Pin, + IN GPIO_PIN_INPUT_ENABLE InputEnable + ) +{ + ASSERT (Group < GPIO_NGROUPS); + + INTN Idx; + EFI_PHYSICAL_ADDRESS Reg; + CONST UINT32 Value = GRF_GPIO_IE_MASK (Pin) | ((UINT32)InputEnable << GRF_GPIO_IE_SHIFT (Pin)); + + for(Idx = ARRAY_SIZE(mIEReg) - 1; Idx >= 0; Idx--) { + if(Group == mIEReg[Idx].Group && Pin >= mIEReg[Idx].Pin) { + Reg = mIEReg[Idx].Addr + GRF_GPIO_IE_REG(Pin - mIEReg[Idx].Pin); + } + } + + DEBUG ((DEBUG_INFO, "GpioPinSetInput Group:%d Pin:%d InputEnable:%d\n", Group, Pin, InputEnable)); + DEBUG ((DEBUG_VERBOSE, "Reg - Value: 0x%lX = 0x%08X\n", Reg, Value)); + + MmioWrite32 (Reg, Value); +} + +VOID +GpioSetIomuxConfig ( + IN CONST GPIO_IOMUX_CONFIG *Configs, + IN UINT32 NumConfigs + ) +{ + UINT32 Index; + + for (Index = 0; Index < NumConfigs; Index++) { + CONST GPIO_IOMUX_CONFIG *Mux = &Configs[Index]; + DEBUG ((DEBUG_INFO, "GPIO: IOMUX for pin '%a'\n", Mux->Name)); + GpioPinSetFunction (Mux->Group, Mux->Pin, Mux->Function); + GpioPinSetPull (Mux->Group, Mux->Pin, Mux->Pull); + if (Mux->Drive != GPIO_PIN_DRIVE_DEFAULT) { + GpioPinSetDrive (Mux->Group, Mux->Pin, Mux->Drive); + } + } +} \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf new file mode 100644 index 0000000..9cb1305 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf @@ -0,0 +1,35 @@ +#/** @file +# +# RK3566/RK3568 GPIO Library. +# +# Copyright (c) 2021, Jared McNeill +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = GpioLib + FILE_GUID = FD6DFA94-101B-4DE3-8F55-D4CC1E1E642A + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = GpioLib + +[Sources] + GpioLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + +[FixedPcd] + +[Guids] diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.c new file mode 100644 index 0000000..6583960 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.c @@ -0,0 +1,164 @@ +/** @file + * + * Copyright (c) 2021, Andrei Warkentin + * Copyright (c) 2011-2015, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +STATIC +VOID +InitMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable + ) +{ + RETURN_STATUS Status; + + //Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() the MMU Page Table + // resides in DRAM (even at the top of DRAM as it is the first permanent memory allocation) + Status = ArmConfigureMmu (MemoryTable, NULL, NULL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n")); + } +} + +STATIC +VOID +AddBasicMemoryRegion ( + IN ARM_MEMORY_REGION_DESCRIPTOR *Desc +) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + Desc->PhysicalBase, + Desc->Length + ); +} + +STATIC +VOID +AddRuntimeServicesRegion ( + IN ARM_MEMORY_REGION_DESCRIPTOR *Desc +) +{ + AddBasicMemoryRegion (Desc); + + BuildMemoryAllocationHob ( + Desc->PhysicalBase, + Desc->Length, + EfiRuntimeServicesData + ); +} + +STATIC +VOID +AddUnmappedMemoryRegion ( + IN ARM_MEMORY_REGION_DESCRIPTOR *Desc + ) +{ + // Do nothing +} + +STATIC +VOID +AddReservedMemoryRegion ( + IN ARM_MEMORY_REGION_DESCRIPTOR *Desc + ) +{ + AddBasicMemoryRegion (Desc); + + BuildMemoryAllocationHob ( + Desc->PhysicalBase, + Desc->Length, + EfiReservedMemoryType + ); +} + +void (*AddRegion[]) (IN ARM_MEMORY_REGION_DESCRIPTOR *Desc) = { + AddUnmappedMemoryRegion, + AddBasicMemoryRegion, + AddRuntimeServicesRegion, + AddReservedMemoryRegion, + }; + +/*++ + +Routine Description: + + + +Arguments: + + FileHandle - Handle of the file being invoked. + PeiServices - Describes the list of possible PEI Services. + +Returns: + + Status - EFI_SUCCESS if the boot mode could be set + +--*/ +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + RK3588_MEMORY_REGION_INFO *MemoryInfo; + UINTN Index; + + DEBUG ((DEBUG_INFO, "%s\n", __FUNCTION__)); + + // Get Virtual Memory Map from the Platform Library + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + // Get additional info not provided by MemoryTable + Rk3588PlatformGetVirtualMemoryInfo (&MemoryInfo); + + // Register each memory region + for (Index = 0; MemoryTable[Index].Length != 0; Index++) { + ASSERT (MemoryInfo[Index].Type < ARRAY_SIZE (AddRegion)); + DEBUG ((DEBUG_INFO, "%s:\n" + "\tPhysicalBase: 0x%lX\n" + "\tVirtualBase: 0x%lX\n" + "\tLength: 0x%lX\n", + MemoryInfo[Index].Name, + MemoryTable[Index].PhysicalBase, + MemoryTable[Index].VirtualBase, + MemoryTable[Index].Length)); + AddRegion[MemoryInfo[Index].Type] (&MemoryTable[Index]); + } + + // Build Memory Allocation Hob + InitMmu (MemoryTable); + + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { + // Optional feature that helps prevent EFI memory map fragmentation. + BuildMemoryTypeInformationHob (); + } + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf new file mode 100644 index 0000000..f0bd07e --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf @@ -0,0 +1,45 @@ +#/** @file +# +# Copyright (c) 2021, Andrei Warkentin +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = MemoryInitPeiLib + FILE_GUID = 4bbc9c10-a100-43fb-8311-332ba497d1b4 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM + +[Sources] + MemoryInitPeiLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + DebugLib + HobLib + ArmMmuLib + ArmPlatformLib + +[Guids] + gEfiMemoryTypeInformationGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[Depex] + TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.c new file mode 100644 index 0000000..79a3d81 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.c @@ -0,0 +1,98 @@ +/** @file + * + * RK3588 OTP Library. + * + * Copyright (c) 2022, Jared McNeill + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include + +#define OTP_BASE 0xfecc0000 + +#define RK3588_OTPC_AUTO_CTRL (OTP_BASE + 0x0004) +#define RK3588_ADDR_SHIFT 16 +#define RK3588_BURST_SHIFT 8 +#define RK3588_OTPC_AUTO_EN (OTP_BASE + 0x0008) +#define RK3588_AUTO_EN BIT0 +#define RK3588_OTPC_DOUT0 (OTP_BASE + 0x0020) +#define RK3588_OTPC_INT_ST (OTP_BASE + 0x0084) +#define RK3588_RD_DONE BIT1 + +#define RK3588_BLOCK_SIZE 4 +#define RK3588_NO_SECURE_OFFSET 0x300 + +VOID +OtpRead ( + IN UINT16 Offset, + IN UINT16 Length, + OUT UINT8 *Data + ) +{ + UINT32 Addr; + UINT16 AddrOffset; + UINT16 BytesRemaining; + UINT32 Value; + UINTN Retry; + + Addr = (Offset / RK3588_BLOCK_SIZE) + RK3588_NO_SECURE_OFFSET; + AddrOffset = Offset % RK3588_BLOCK_SIZE; + BytesRemaining = Length; + Retry = 100000; + + while (BytesRemaining > 0) { + MmioWrite32 (RK3588_OTPC_AUTO_CTRL, Addr << RK3588_ADDR_SHIFT | 1 << RK3588_BURST_SHIFT); + MmioWrite32 (RK3588_OTPC_AUTO_EN, RK3588_AUTO_EN); + while ((MmioRead32 (RK3588_OTPC_INT_ST) & RK3588_RD_DONE) == 0) { + MicroSecondDelay (1); + if (--Retry == 0) { + DEBUG ((DEBUG_WARN, "OTP read timeout!\n")); + break; + } + } + MmioWrite32 (RK3588_OTPC_INT_ST, RK3588_RD_DONE); + + Value = MmioRead32 (RK3588_OTPC_DOUT0); + + while (AddrOffset < RK3588_BLOCK_SIZE && BytesRemaining > 0) { + *Data++ = (Value >> (8 * AddrOffset)) & 0xFF; + AddrOffset++; + BytesRemaining--; + } + + AddrOffset = 0; + Addr++; + } +} + +VOID +OtpReadCpuCode ( + OUT UINT16 *CpuCode + ) +{ + OtpRead (0x02, 0x2, (UINT8*)CpuCode); +} + +VOID +OtpReadId ( + OUT UINT8 Id[16] + ) +{ + OtpRead (0x07, 0x10, Id); +} + +VOID +OtpReadCpuVersion ( + OUT UINT8 *Version + ) +{ + OtpRead (0x1c, 0x1, Version); +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf new file mode 100644 index 0000000..c5b03e2 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf @@ -0,0 +1,35 @@ +#/** @file +# +# RK3588 OTP Library. +# +# Copyright (c) 2022, Jared McNeill +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = OtpLib + FILE_GUID = 412C6116-58A9-4512-B98E-0EF837D1D622 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = OtpLib + +[Sources] + OtpLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + TimerLib + +[Guids] diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.c new file mode 100755 index 0000000..8dbfef4 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.c @@ -0,0 +1,117 @@ +/** @file + * + * RK3588 PCIe PHY Library. + * + * Copyright (c) 2023, David Gwynne + * Copyright (c) 2023, Jared McNeill + * Copyright (c) 2023, Molly Sophia + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCIE30_PHY_GRF 0xfd5b8000 +/* PCIEPHY_GRF */ +#define GRF_PCIE30_PHY_CON(n) (PCIE30_PHY_GRF + 0x0000 + (n) * 0x4) /* 0 .. 9 */ +#define GRF_PCIE30_PHY_STATUS(n) (PCIE30_PHY_GRF + 0x0080 + (n) * 0x4) /* 0 .. 2 */ +#define GRF_PCIE30_PHY_PRT0_CON(n) (PCIE30_PHY_GRF + 0x0100 + (n) * 0x4) /* 0 .. 39 */ +/* CON1 and CON9 */ +#define GRF_PCIE30PHY_DA_OCM_MASK BIT15 +#define GRF_PCIE30PHY_DA_OCM BIT15 +/* CON5 */ +#define GRF_PCIE30PHY_LANE0_LINK_NUM_SHIFT 0 +#define GRF_PCIE30PHY_LANE0_LINK_NUM_MASK (0xfU << GRF_PCIE30PHY_LANE0_LINK_NUM_SHIFT) +/* CON6 */ +#define GRF_PCIE30PHY_LANE1_LINK_NUM_SHIFT 0 +#define GRF_PCIE30PHY_LANE1_LINK_NUM_MASK (0xfU << GRF_PCIE30PHY_LANE1_LINK_NUM_SHIFT) + +/* STATUS0 */ +#define GRF_PCIE30PHY_SRAM_INIT_DONE BIT14 + +#define SOFTRST_INDEX 27 +#define SOFTRST_BIT 14 + +STATIC +VOID +GrfUpdateRegister ( + IN EFI_PHYSICAL_ADDRESS Reg, + IN UINT32 Mask, + IN UINT32 Val + ) +{ + ASSERT ((Mask & ~0xFFFF) == 0); + ASSERT ((Val & ~0xFFFF) == 0); + ASSERT ((Mask & Val) == Val); + + MmioWrite32 (Reg, (Mask << 16) | Val); +} + +EFI_STATUS +Pcie30PhyInit ( + VOID + ) +{ + // UINTN Retry; + + DEBUG ((DEBUG_INFO, "PCIe30: PHY init\n")); + DEBUG ((DEBUG_INFO, "PCIe30: PHY mode %d\n", PcdGet8(PcdPcie30PhyMode))); + + // MicroSecondDelay(100000); + + /* Disable power domain */ + MmioWrite32(0xFD8D8150, 0x1 << 23 | 0x1 << 21); // PD_PCIE & PD_PHP + + /* Phy mode: from pcd Pcie30PhyMode */ + MmioWrite32(GRF_PCIE30_PHY_CON(0), (0x7 << 16) | PcdGet8(PcdPcie30PhyMode)); + + MmioWrite32(0xFD7C8A00, (0x1 << 10) | (0x1 << 26)); + + /* Deassert PCIe PMA output clamp mode */ + MmioWrite32(GRF_PCIE30_PHY_CON(0), (0x1 << 8) | (0x1 << 24)); + + /* Deassert PHY Reset */ + MmioWrite32(0xFD7C8A00, (0x1 << 26)); + + // /* Enable clocks */ + // PmuCruEnableClock (2, 13); + // PmuCruEnableClock (2, 14); + // CruEnableClock (33, 8); + + // /* Assert reset */ + // CruAssertSoftReset (SOFTRST_INDEX, SOFTRST_BIT); + // gBS->Stall (1000); + + // MicroSecondDelay (1); + + // GrfUpdateRegister (GRF_PCIE30_PHY_CON (9), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM); + // GrfUpdateRegister (GRF_PCIE30_PHY_CON (5), GRF_PCIE30PHY_LANE0_LINK_NUM_MASK, PCIE30PHY_LANE0_LINK_NUM); + // GrfUpdateRegister (GRF_PCIE30_PHY_CON (6), GRF_PCIE30PHY_LANE1_LINK_NUM_MASK, PCIE30PHY_LANE1_LINK_NUM); + // GrfUpdateRegister (GRF_PCIE30_PHY_CON (1), GRF_PCIE30PHY_DA_OCM_MASK, GRF_PCIE30PHY_DA_OCM); + + // /* De-assert reset */ + // CruDeassertSoftReset (SOFTRST_INDEX, SOFTRST_BIT); + + // for (Retry = 500; Retry > 0; Retry--) { + // MicroSecondDelay (100); + + // if ((MmioRead32 (GRF_PCIE30_PHY_STATUS (0)) & GRF_PCIE30PHY_SRAM_INIT_DONE) != 0) { + // break; + // } + // } + // if (Retry == 0) { + // DEBUG ((DEBUG_WARN, "PCIe30: Failed to enable PCIe 3.0 PHY\n")); + // return EFI_TIMEOUT; + // } + + DEBUG ((DEBUG_INFO, "PCIe30: PHY init complete\n")); + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.inf new file mode 100755 index 0000000..84e1874 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# RK3588 PCIe 3.0 PHY Library. +# +# Copyright (c) 2023, Jared McNeill +# Copyright (c) 2023, Molly Sophia +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = Pcie30PhyLib + FILE_GUID = FF2358C0-1F45-4A8F-971F-891FFDE25C81 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = Pcie30PhyLib + +[Sources] + Pcie30PhyLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + BaseLib + DebugLib + IoLib + TimerLib + CruLib + +[FixedPcd] + +[Pcd] + gRK3588TokenSpaceGuid.PcdPcie30PhyMode + +[Guids] diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf new file mode 100644 index 0000000..c6fa162 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf @@ -0,0 +1,73 @@ +#/** @file +# +# Copyright (c) 2021, Jared McNeill +# Copyright (c) 2017-2021, Andrei Warkentin +# Copyright (c) 2014-2016, Linaro Limited. All rights reserved. +# Copyright (c) 2011-2019, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformLib + FILE_GUID = ADAB50A9-04BE-4B17-9CBF-17B781B3CB00 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib|SEC PEIM + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + Silicon/Rockchip/RockchipPkg.dec + +[LibraryClasses] + ArmLib + BaseVariableLib + FdtLib + IoLib + MemoryAllocationLib + PcdLib + PrintLib + SdramLib + SerialPortLib + +[Sources.common] + Rk3588.c + Rk3588Mem.c + +[Sources.AARCH64] + Rk3588Helper.S + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + gArmTokenSpaceGuid.PcdFvSize + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[PatchPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + +[Ppis] + gArmMpCoreInfoPpiGuid + +[Guids] + gRK3588DxeFormSetGuid diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588.c new file mode 100644 index 0000000..d991409 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588.c @@ -0,0 +1,120 @@ +/** @file + * + * Copyright (c) 2014-2016, Linaro Limited. All rights reserved. + * Copyright (c) 2014, Red Hat, Inc. + * Copyright (c) 2011-2013, ARM Limited. All rights reserved. + * + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include + +#include + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + This function is called by PrePeiCore, in the SEC phase. +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + EFI_STATUS Status; + UINTN Size; + UINT64 BaudRate; + + Size = sizeof (UINT64); + Status = BaseGetVariable ( + L"DebugSerialPortBaudRate", + &gRK3588DxeFormSetGuid, + NULL, + &Size, + &BaudRate + ); + if (EFI_ERROR (Status) || BaudRate == 0) { + return RETURN_SUCCESS; + } + + DEBUG ((DEBUG_INFO, "%a: Setting baud rate to %lu\n", __func__, BaudRate)); + + PatchPcdSet64 (PcdUartDefaultBaudRate, BaudRate); + SerialPortInitialize (); + + return RETURN_SUCCESS; +} + +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ +} + +STATIC ARM_CORE_INFO mRk3588InfoTable[] = { + { 0x0, 0x000 }, // Cluster 0, Core 0 + { 0x0, 0x100 }, // Cluster 0, Core 1 + { 0x0, 0x200 }, // Cluster 0, Core 2 + { 0x0, 0x300 }, // Cluster 0, Core 3 + { 0x0, 0x400 }, // Cluster 0, Core 4 + { 0x0, 0x500 }, // Cluster 0, Core 5 + { 0x0, 0x600 }, // Cluster 0, Core 6 + { 0x0, 0x700 }, // Cluster 0, Core 7 +}; + +STATIC +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + // Only support one cluster + *CoreCount = sizeof (mRk3588InfoTable) / sizeof (ARM_CORE_INFO); + *ArmCoreTable = mRk3588InfoTable; + + return EFI_SUCCESS; +} + +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { + PrePeiCoreGetMpCoreInfo +}; +STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof (mPlatformPpiTable); + *PpiList = mPlatformPpiTable; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Helper.S b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Helper.S new file mode 100644 index 0000000..74862b8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Helper.S @@ -0,0 +1,45 @@ +/** @file + * + * Copyright (c) 2020-2021, Andrei Warkentin + * Copyright (c) 2019-2020, Pete Batard + * Copyright (c) 2016, Linaro Limited. All rights reserved. + * Copyright (c) 2011-2020, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include + +ASM_FUNC (ArmPlatformPeiBootAction) + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC (ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC (ArmPlatformIsPrimaryCore) + mov x0, #1 + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +// With this function: CorePos = (ClusterId * 4) + CoreId +ASM_FUNC (ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Mem.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Mem.c new file mode 100644 index 0000000..b8b67e0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/PlatformLib/Rk3588Mem.c @@ -0,0 +1,192 @@ +/** @file + * + * Copyright (c) 2021, Jared McNeill + * Copyright (c) 2017-2021, Andrey Warkentin + * Copyright (c) 2019, Pete Batard + * Copyright (c) 2014, Linaro Limited. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include + +UINT64 mSystemMemoryBase = FixedPcdGet64 (PcdSystemMemoryBase); +STATIC UINT64 mSystemMemorySize = FixedPcdGet64 (PcdSystemMemorySize); + +// The total number of descriptors, including the final "end-of-table" descriptor. +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 12 + +STATIC BOOLEAN VirtualMemoryInfoInitialized = FALSE; +STATIC RK3588_MEMORY_REGION_INFO VirtualMemoryInfo[MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS]; + +#define VariablesBase FixedPcdGet64(PcdFlashNvStorageVariableBase64) + +#define VariablesSize (FixedPcdGet32(PcdFlashNvStorageVariableSize) + \ + FixedPcdGet32(PcdFlashNvStorageFtwWorkingSize) + \ + FixedPcdGet32(PcdFlashNvStorageFtwSpareSize)) + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU + on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR + describing a Physical-to-Virtual Memory + mapping. This array must be ended by a + zero-filled entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + mSystemMemorySize = SdramGetMemorySize (); + DEBUG ((DEBUG_INFO, "RAM: 0x%ll08X (Size 0x%ll08X)\n", mSystemMemoryBase, mSystemMemorySize)); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages + (EFI_SIZE_TO_PAGES (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + // + // TF-A Region + // Must be unmapped for the shared memory to retain its attributes. + // + VirtualMemoryTable[Index].PhysicalBase = 0x00000000; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = 0x200000; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + VirtualMemoryInfo[Index].Type = RK3588_MEM_UNMAPPED_REGION; + VirtualMemoryInfo[Index++].Name = L"TF-A + Shared Memory"; + + // Firmware Volume + VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdFvBaseAddress); + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdFvSize); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + VirtualMemoryInfo[Index].Type = RK3588_MEM_RESERVED_REGION; + VirtualMemoryInfo[Index++].Name = L"UEFI FV"; + + // Variable Volume + VirtualMemoryTable[Index].PhysicalBase = VariablesBase; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = VariablesSize; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + VirtualMemoryInfo[Index].Type = RK3588_MEM_RUNTIME_REGION; + VirtualMemoryInfo[Index++].Name = L"Variable Store"; + + // Base System RAM (< OP-TEE) + VirtualMemoryTable[Index].PhysicalBase = VariablesBase + VariablesSize; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = MIN (mSystemMemorySize, 0x08400000 - VirtualMemoryTable[Index].PhysicalBase); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + VirtualMemoryInfo[Index].Type = RK3588_MEM_BASIC_REGION; + VirtualMemoryInfo[Index++].Name = L"System RAM (< OP-TEE)"; + + // OP-TEE Region + VirtualMemoryTable[Index].PhysicalBase = 0x08400000; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = 0x1000000; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + VirtualMemoryInfo[Index].Type = RK3588_MEM_RESERVED_REGION; + VirtualMemoryInfo[Index++].Name = L"OP-TEE"; + + // Base System RAM (< 4GB) + VirtualMemoryTable[Index].PhysicalBase = 0x08400000 + 0x1000000; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = MIN (mSystemMemorySize, 0xF0000000 - VirtualMemoryTable[Index].PhysicalBase); + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + VirtualMemoryInfo[Index].Type = RK3588_MEM_BASIC_REGION; + VirtualMemoryInfo[Index++].Name = L"System RAM (< 4GB)"; + + // MMIO + VirtualMemoryTable[Index].PhysicalBase = 0xF0000000; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = 0x10000000; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + VirtualMemoryInfo[Index].Type = RK3588_MEM_UNMAPPED_REGION; + VirtualMemoryInfo[Index++].Name = L"MMIO"; + + if (mSystemMemorySize > 0x100000000UL) { + // Base System RAM >= 4GB + VirtualMemoryTable[Index].PhysicalBase = 0x100000000; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = mSystemMemorySize - 0x100000000; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + VirtualMemoryInfo[Index].Type = RK3588_MEM_BASIC_REGION; + VirtualMemoryInfo[Index++].Name = L"System RAM >= 4GB"; + } + + // MMIO > 32GB + VirtualMemoryTable[Index].PhysicalBase = 0x0000000900000000UL; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = 0x0000000141400000UL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + VirtualMemoryInfo[Index].Type = RK3588_MEM_UNMAPPED_REGION; + VirtualMemoryInfo[Index++].Name = L"MMIO > 32GB"; + + if (mSystemMemoryBase + mSystemMemorySize > 0x3fc000000UL) { + // Bad memory range 1 + VirtualMemoryTable[Index].PhysicalBase = 0x3fc000000; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = 0x500000; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + VirtualMemoryInfo[Index].Type = RK3588_MEM_RESERVED_REGION; + VirtualMemoryInfo[Index++].Name = L"BAD1"; + + // Bad memory range 2 + VirtualMemoryTable[Index].PhysicalBase = 0x3fff00000; + VirtualMemoryTable[Index].VirtualBase = VirtualMemoryTable[Index].PhysicalBase; + VirtualMemoryTable[Index].Length = 0x100000; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + VirtualMemoryInfo[Index].Type = RK3588_MEM_RESERVED_REGION; + VirtualMemoryInfo[Index++].Name = L"BAD2"; + } + + // End of Table + VirtualMemoryTable[Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index++].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT(Index <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap = VirtualMemoryTable; + VirtualMemoryInfoInitialized = TRUE; +} + +/** + Return additional memory info not populated by the above call. + + This call should follow the one to ArmPlatformGetVirtualMemoryMap (). + +**/ +VOID +Rk3588PlatformGetVirtualMemoryInfo ( + IN RK3588_MEMORY_REGION_INFO** MemoryInfo + ) +{ + ASSERT (VirtualMemoryInfo != NULL); + + if (!VirtualMemoryInfoInitialized) { + DEBUG ((DEBUG_ERROR, + "ArmPlatformGetVirtualMemoryMap must be called before Rk3588PlatformGetVirtualMemoryInfo.\n")); + return; + } + + *MemoryInfo = VirtualMemoryInfo; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c new file mode 100755 index 0000000..b38baa0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.c @@ -0,0 +1,655 @@ +/** @file + + Copyright 2017, 2020 NXP + Copyright 2021-2023, Jared McNeill + Copyright 2023, Molly Sophia + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PciHostBridgeInit.h" + +/* APB Registers */ +#define PCIE_CLIENT_GENERAL_CON 0x0000 +#define DEVICE_TYPE_SHIFT 4 +#define DEVICE_TYPE_MASK (0xFU << DEVICE_TYPE_SHIFT) +#define DEVICE_TYPE_RC (4 << DEVICE_TYPE_SHIFT) +#define LINK_REQ_RST_GRT BIT3 +#define LTSSM_ENABLE BIT2 +#define PCIE_CLIENT_INTR_MASK_LEGACY 0x001C +#define PCIE_CLIENT_POWER_CON 0x002C +#define APP_CLK_REQ_N BIT0 +#define CLK_REQ_N_BYPASS BIT12 +#define CLK_REQ_N_CON BIT13 +#define PCIE_CLIENT_GENERAL_DEBUG_INIT 0x0104 +#define PCIE_CLIENT_HOT_RESET_CTRL 0x0180 +#define APP_LSSTM_ENABLE_ENHANCE BIT4 +#define PCIE_CLIENT_LTSSM_STATUS 0x0300 +#define RDLH_LINK_UP BIT17 +#define SMLH_LINK_UP BIT16 +#define SMLH_LTSSM_STATE_MASK 0x3f +#define SMLH_LTSSM_STATE_LINK_UP 0x11 + +/* DBI Registers */ +#define PCI_COMMAND 0x0004 +#define PCI_DEVICE_CLASS 0x000A +#define PCI_BAR0 0x0010 +#define PCI_BAR1 0x0014 +#define PCIE_LINK_CAPABILITY 0x007C +#define PCIE_LINK_STATUS 0x0080 +#define LINK_STATUS_WIDTH_SHIFT 20 +#define LINK_STATUS_WIDTH_MASK (0xFU << LINK_STATUS_WIDTH_SHIFT) +#define LINK_STATUS_SPEED_SHIFT 16 +#define LINK_STATUS_SPEED_MASK (0xFU << LINK_STATUS_SPEED_SHIFT) +#define PCIE_LINK_CTL_2 0x00A0 +#define PL_PORT_LINK_CTRL_OFF 0x0710 +#define LINK_CAPABLE_SHIFT 16 +#define LINK_CAPABLE_MASK (0x3FU << LINK_CAPABLE_SHIFT) +#define FAST_LINK_MODE BIT7 +#define DLL_LINK_EN BIT5 +#define PL_GEN2_CTRL_OFF 0x080C +#define DIRECT_SPEED_CHANGE BIT17 +#define NUM_OF_LANES_SHIFT 8 +#define NUM_OF_LANES_MASK (0x1FU << NUM_OF_LANES_SHIFT) +#define PL_MISC_CONTROL_1_OFF 0x08BC +#define DBI_RO_WR_EN BIT0 + +#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 + +/* ATU Registers */ +#define ATU_CAP_BASE 0x300000 +#define IATU_REGION_CTRL_OUTBOUND(n) (ATU_CAP_BASE + ((n) << 9)) +#define IATU_REGION_CTRL_INBOUND(n) (ATU_CAP_BASE + ((n) << 9) + 0x100) +#define IATU_REGION_CTRL_1_OFF 0x000 +#define IATU_TYPE_MEM 0 +#define IATU_TYPE_IO 2 +#define IATU_TYPE_CFG0 4 +#define IATU_TYPE_CFG1 5 +#define IATU_REGION_CTRL_2_OFF 0x004 +#define IATU_ENABLE BIT31 +#define IATU_CFG_SHIFT_MODE BIT28 +#define IATU_LWR_BASE_ADDR_OFF 0x008 +#define IATU_UPPER_BASE_ADDR_OFF 0x00C +#define IATU_LIMIT_ADDR_OFF 0x010 +#define IATU_LWR_TARGET_ADDR_OFF 0x014 +#define IATU_UPPER_TARGET_ADDR_OFF 0x018 + +BOOLEAN +IsPcieNumEnabled( + UINTN PcieNum + ) +{ + BOOLEAN Enabled = FALSE; + + /* + * According to TRM Part 1 6.19.2 PCIe3PHY_GRF_CMN_CON0, + * if pcie l4(PCIE30X4) bifurcation enabled (phymode & 0b01), pcie3phy lane 1 is connected to 1l0 + * if pcie l2(PCIE30X2) bifurcation enabled (phymode & 0b10), pcie3phy lane 3 is connected to 1l1 + */ + switch (PcieNum) + { + case PCIE_SEGMENT_PCIE30X4: + Enabled = (FixedPcdGetBool (PcdPcie30Supported) && PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED); + break; + + case PCIE_SEGMENT_PCIE30X2: + Enabled = (PcdGet8 (PcdPcie30PhyMode) != PCIE30_PHY_MODE_AGGREGATION); + break; + + case PCIE_SEGMENT_PCIE20L0: + Enabled = (PcdGet32(PcdComboPhy1Mode) == COMBO_PHY_MODE_PCIE); + break; + + case PCIE_SEGMENT_PCIE20L1: + Enabled = (PcdGet32(PcdComboPhy2Mode) == COMBO_PHY_MODE_PCIE); + break; + + case PCIE_SEGMENT_PCIE20L2: + Enabled = (PcdGet32(PcdComboPhy0Mode) == COMBO_PHY_MODE_PCIE); + break; + + default: + break; + } + + return Enabled; +} + +STATIC CONST GPIO_IOMUX_CONFIG mPcie30x1_0_IomuxConfigs[][3] = { + { + { "pcie30x1_0_clkreqnm0", 0, GPIO_PIN_PC0, 12, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_0_wakenm0", 0, GPIO_PIN_PC4, 12, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_0_perstnm0", 0, GPIO_PIN_PC5, 12, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + }, + { + { "pcie30x1_0_clkreqnm1", 4, GPIO_PIN_PA3, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_0_wakenm1", 4, GPIO_PIN_PA4, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_0_perstnm1", 4, GPIO_PIN_PA5, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + }, + { + { "pcie30x1_0_clkreqnm2", 1, GPIO_PIN_PB5, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_0_wakenm2", 1, GPIO_PIN_PB3, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_0_perstnm2", 1, GPIO_PIN_PB4, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + }, +}; + +STATIC CONST GPIO_IOMUX_CONFIG mPcie30x1_1_IomuxConfigs[][3] = { + { + { "pcie30x1_1_clkreqnm0", 0, GPIO_PIN_PB5, 12, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_1_wakenm0", 0, GPIO_PIN_PB6, 12, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_1_perstnm0", 0, GPIO_PIN_PB7, 12, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + }, + { + { "pcie30x1_1_clkreqnm1", 4, GPIO_PIN_PA0, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_1_wakenm1", 4, GPIO_PIN_PA1, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_1_perstnm1", 4, GPIO_PIN_PA2, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + }, + { + { "pcie30x1_1_clkreqnm2", 1, GPIO_PIN_PA0, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_1_wakenm2", 1, GPIO_PIN_PA1, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie30x1_1_perstnm2", 1, GPIO_PIN_PA7, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + }, +}; + +STATIC CONST GPIO_IOMUX_CONFIG mPcie20x1_2_IomuxConfigs[][3] = { + { + { "pcie20x1_2_clkreqnm0", 3, GPIO_PIN_PC7, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie20x1_2_wakenm0", 3, GPIO_PIN_PD0, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie20x1_2_perstnm0", 3, GPIO_PIN_PD1, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + }, + { + { "pcie20x1_2_clkreqnm1", 4, GPIO_PIN_PB7, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie20x1_2_wakenm1", 4, GPIO_PIN_PC0, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + { "pcie20x1_2_perstnm1", 4, GPIO_PIN_PC1, 4, GPIO_PIN_PULL_NONE, GPIO_PIN_DRIVE_DEFAULT }, + }, +}; + +STATIC BOOLEAN PcieSupportClkreq[NUM_PCIE_CONTROLLER] = { + FALSE, FALSE, FALSE, FALSE, FALSE +}; + +VOID +PciePinmuxInit( + UINTN PcieNum, + UINTN MuxNum + ) +{ + ASSERT(PcieNum < NUM_PCIE_CONTROLLER); + switch(PcieNum) { + case PCIE_SEGMENT_PCIE20L0: + ASSERT(MuxNum < 3); + GpioSetIomuxConfig(&mPcie30x1_0_IomuxConfigs[MuxNum][0], 3); + break; + case PCIE_SEGMENT_PCIE20L1: + ASSERT(MuxNum < 3); + GpioSetIomuxConfig(&mPcie30x1_1_IomuxConfigs[MuxNum][0], 3); + break; + case PCIE_SEGMENT_PCIE20L2: + ASSERT(MuxNum < 2); + GpioSetIomuxConfig(&mPcie20x1_2_IomuxConfigs[MuxNum][0], 3); + break; + + default: + return; + } + PcieSupportClkreq[PcieNum] = TRUE; +} + +STATIC +VOID +PciSetupClocks ( + IN UINTN Segment + ) +{ + MmioWrite32(0xFD7C8800, (0x1 << 17)|(0x1 << 25)); // pclk_phptop_cru_en + MmioWrite32(0xFD7C0880, 0xffff0000); //CRU_GATE_CON32 + switch(Segment) { + case PCIE_SEGMENT_PCIE30X4: + MmioWrite32(0xFD7C8A00, (0x1 << 24)|(0x1 << 26)); //PHPTOPCRU_SOFTRST_CON00 + MmioWrite32(0xFD7C8800, (0x1 << 24)); //PHPTOPCRU_GATE_CON00 + MmioWrite32(0xFD7C0A80, (0x1 << 29)); //CRU_SOFTRST_CON32:resetn_pcie_4l_power_up + MmioWrite32(0xFD7C089c, (0x1 << 16)); //CRU_GATE_CON39:clk_pcie_4l_pipe_en + MmioWrite32(0xFD7C0888, (0x1 << 17)); //CRU_GATE_CON34:clk_pcie_4l_aux_en + MmioWrite32(0xFD7C0884, (0x1 << 28)|(0x1 << 23)|(0x1 << 18)); //CRU_GATE_CON33:pclk_pcie_4l_en,aclk_pcie_4l_slv_en,aclk_pcie_4l_mstr_en + break; + case PCIE_SEGMENT_PCIE30X2: + MmioWrite32(0xFD7C0A80, (0x1 << 30)); //CRU_SOFTRST_CON32:resetn_pcie_2l_power_up + MmioWrite32(0xFD7C089c, (0x1 << 17)); //CRU_GATE_CON39:clk_pcie_2l_pipe_en + MmioWrite32(0xFD7C0888, (0x1 << 18)); //CRU_GATE_CON34:clk_pcie_2l_aux_en + MmioWrite32(0xFD7C0884, (0x1 << 29)|(0x1 << 24)|(0x1 << 19)); //CRU_GATE_CON33:pclk_pcie_2l_en,aclk_pcie_2l_slv_en,aclk_pcie_2l_mstr_en + break; + case PCIE_SEGMENT_PCIE20L2: //phy0 + MmioWrite32(0xFD7C8A00, (0x1 << 21)|(0x1 << 18)); //PHPTOPCRU_SOFTRST_CON00 + MmioWrite32(0xFD7C8800, (0x1 << 21)|(0x1 << 18)); //PHPTOPCRU_GATE_CON00 + MmioWrite32(0xFD7C0A84, (0x1 << 17)); //CRU_SOFTRST_CON33:resetn_pcie_1l2_power_up + MmioWrite32(0xFD7C0898, (0x1 << 29)); //CRU_GATE_CON38:clk_pcie_1l2_pipe_en + MmioWrite32(0xFD7C0888, (0x1 << 21)|(0x1 << 16)); //CRU_GATE_CON34:clk_pcie_1l2_aux_en,pclk_pcie_1l2_en + MmioWrite32(0xFD7C0884, (0x1 << 27)|(0x1 << 22)); //CRU_GATE_CON33:aclk_pcie_1l2_slv_en,aclk_pcie_1l2_mstr_en + break; + case PCIE_SEGMENT_PCIE20L0: //phy1 + MmioWrite32(0xFD7C8A00, (0x1 << 22)|(0x1 << 19)); //PHPTOPCRU_SOFTRST_CON00 + MmioWrite32(0xFD7C8800, (0x1 << 22)|(0x1 << 19)); //PHPTOPCRU_GATE_CON00 + MmioWrite32(0xFD7C0A80, (0x1 << 31)); //CRU_SOFTRST_CON32:resetn_pcie_1l0_power_up + MmioWrite32(0xFD7C0898, (0x1 << 30)); //CRU_GATE_CON38:clk_pcie_1l0_pipe_en + MmioWrite32(0xFD7C0888, (0x1 << 19)); //CRU_GATE_CON34:clk_pcie_1l0_aux_en + MmioWrite32(0xFD7C0884, (0x1 << 30)|(0x1 << 25)|(0x1 << 20)); //CRU_GATE_CON33:pclk_pcie_1l0_en,aclk_pcie_1l0_slv_en,aclk_pcie_1l0_mstr_en + break; + case PCIE_SEGMENT_PCIE20L1: //phy2 + MmioWrite32(0xFD7C8A00, (0x1 << 23)|(0x1 << 20)); //PHPTOPCRU_SOFTRST_CON00 + MmioWrite32(0xFD7C8800, (0x1 << 23)|(0x1 << 20)); //PHPTOPCRU_GATE_CON00 + MmioWrite32(0xFD7C0A84, (0x1 << 16)); //CRU_SOFTRST_CON33:resetn_pcie_1l1_power_up + MmioWrite32(0xFD7C0898, (0x1 << 31)); //CRU_GATE_CON38:clk_pcie_1l1_pipe_en + MmioWrite32(0xFD7C0888, (0x1 << 20)); //CRU_GATE_CON34:clk_pcie_1l1_aux_en + MmioWrite32(0xFD7C0884, (0x1 << 31)|(0x1 << 26)|(0x1 << 21)); //CRU_GATE_CON33:pclk_pcie_1l1_en,aclk_pcie_1l1_slv_en,aclk_pcie_1l1_mstr_en + break; + default: + break; + } + +} + +STATIC +VOID +PciSetRcMode ( + IN UINTN Segment, + IN EFI_PHYSICAL_ADDRESS ApbBase + ) +{ + MmioWrite32 (ApbBase + PCIE_CLIENT_INTR_MASK_LEGACY, 0xFFFF0000); + MmioWrite32 (ApbBase + PCIE_CLIENT_HOT_RESET_CTRL, + (APP_LSSTM_ENABLE_ENHANCE << 16) | APP_LSSTM_ENABLE_ENHANCE); + + if(PcieSupportClkreq[Segment]) { + MmioWrite32 (ApbBase + PCIE_CLIENT_POWER_CON, (APP_CLK_REQ_N << 16) | APP_CLK_REQ_N); + } else { + MmioWrite32 (ApbBase + PCIE_CLIENT_POWER_CON, APP_CLK_REQ_N << 16); + MmioWrite32 (ApbBase + PCIE_CLIENT_POWER_CON, ((CLK_REQ_N_BYPASS|CLK_REQ_N_CON) << 16) | CLK_REQ_N_BYPASS); + // Maybe also disable PCIE L1SS capabilities here? + } + MmioWrite32 (ApbBase + PCIE_CLIENT_GENERAL_CON, + (DEVICE_TYPE_MASK << 16) | DEVICE_TYPE_RC); +} + +STATIC +VOID +PciSetupBars ( + IN EFI_PHYSICAL_ADDRESS DbiBase + ) +{ + MmioWrite16 (DbiBase + PCI_DEVICE_CLASS, (PCI_CLASS_BRIDGE << 8) | PCI_CLASS_BRIDGE_P2P); + + // Disable BAR0 + BAR1 of root port as they're invalid. + MmioWrite32 (DbiBase + PCIE_TYPE0_HDR_DBI2_OFFSET + PCI_BAR0, 0x0); + MmioWrite32 (DbiBase + PCIE_TYPE0_HDR_DBI2_OFFSET + PCI_BAR1, 0x0); +} + +STATIC +VOID +PciDirectSpeedChange ( + IN EFI_PHYSICAL_ADDRESS DbiBase + ) +{ + DEBUG ((DEBUG_INIT, "PCIe: SetupBars: Speed change\n")); + /* Initiate a speed change to Gen2 or Gen3 after the link is initialized as Gen1 speed. */ + MmioOr32 (DbiBase + PL_GEN2_CTRL_OFF, DIRECT_SPEED_CHANGE); +} + +STATIC +VOID +PciSetupLinkSpeed ( + IN EFI_PHYSICAL_ADDRESS DbiBase, + IN UINT32 Speed, + IN UINT32 NumLanes + ) +{ + /* Select target link speed */ + MmioAndThenOr32 (DbiBase + PCIE_LINK_CTL_2, ~0xFU, Speed); + MmioAndThenOr32 (DbiBase + PCIE_LINK_CAPABILITY, ~0xFU, Speed); + + /* Disable fast link mode, select number of lanes, and enable link initialization */ + MmioAndThenOr32 (DbiBase + PL_PORT_LINK_CTRL_OFF, + ~(LINK_CAPABLE_MASK | FAST_LINK_MODE), + DLL_LINK_EN | (((NumLanes * 2) - 1) << LINK_CAPABLE_SHIFT)); + + /* Select link width */ + MmioAndThenOr32 (DbiBase + PL_GEN2_CTRL_OFF, ~NUM_OF_LANES_MASK, + NumLanes << NUM_OF_LANES_SHIFT); +} + +STATIC +VOID +PciGetLinkSpeedWidth ( + IN EFI_PHYSICAL_ADDRESS DbiBase, + OUT UINT32 *Speed, + OUT UINT32 *Width + ) +{ + UINT32 Val; + + Val = MmioRead32 (DbiBase + PCIE_LINK_STATUS); + *Speed = (Val & LINK_STATUS_SPEED_MASK) >> LINK_STATUS_SPEED_SHIFT; + *Width = (Val & LINK_STATUS_WIDTH_MASK) >> LINK_STATUS_WIDTH_SHIFT; +} + +STATIC +VOID +PciPrintLinkSpeedWidth ( + IN UINT32 Speed, + IN UINT32 Width + ) +{ + char LinkSpeedBuf[6]; + + switch (Speed) { + case 0: + AsciiStrCpyS (LinkSpeedBuf, sizeof (LinkSpeedBuf) - 1, "1.25"); + break; + case 1: + AsciiStrCpyS (LinkSpeedBuf, sizeof (LinkSpeedBuf) - 1, "2.5"); + break; + case 2: + AsciiStrCpyS (LinkSpeedBuf, sizeof (LinkSpeedBuf) - 1, "5.0"); + break; + case 3: + AsciiStrCpyS (LinkSpeedBuf, sizeof (LinkSpeedBuf) - 1, "8.0"); + break; + case 4: + AsciiStrCpyS (LinkSpeedBuf, sizeof (LinkSpeedBuf) - 1, "16.0"); + break; + default: + AsciiSPrint (LinkSpeedBuf, sizeof (LinkSpeedBuf), "%u.%u", + (Speed * 25) / 10, (Speed * 25) % 10); + break; + } + DEBUG ((DEBUG_INIT, "PCIe: Link up (x%u, %a GT/s)\n", Width, LinkSpeedBuf)); +} + +STATIC +VOID +PciEnableLtssm ( + IN EFI_PHYSICAL_ADDRESS ApbBase, + IN BOOLEAN Enable + ) +{ + UINT32 Val; + + Val = (LINK_REQ_RST_GRT | LTSSM_ENABLE) << 16; + Val |= LINK_REQ_RST_GRT; + if (Enable) { + Val |= LTSSM_ENABLE; + } + + MmioWrite32 (ApbBase + PCIE_CLIENT_GENERAL_CON, Val); +} + +STATIC +BOOLEAN +PciIsLinkUp ( + IN EFI_PHYSICAL_ADDRESS ApbBase + ) +{ + STATIC UINT32 LastVal = 0xFFFFFFFF; + UINT32 Val; + + Val = MmioRead32 (ApbBase + PCIE_CLIENT_LTSSM_STATUS); + if (Val != LastVal) { + DEBUG ((DEBUG_INIT, "PCIe: PciIsLinkUp(): LTSSM_STATUS=0x%08X\n", Val)); + LastVal = Val; + } + + if ((Val & RDLH_LINK_UP) == 0) { + return FALSE; + } + if ((Val & SMLH_LINK_UP) == 0) { + return FALSE; + } + + return (Val & SMLH_LTSSM_STATE_MASK) == SMLH_LTSSM_STATE_LINK_UP; +} + +STATIC +VOID +PciSetupAtu ( + IN EFI_PHYSICAL_ADDRESS DbiBase, + IN UINT32 Index, + IN UINT32 Type, + IN UINT64 CpuBase, + IN UINT64 BusBase, + IN UINT64 Length + ) +{ + UINT32 Ctrl2Off = IATU_ENABLE; + + if (Type == IATU_TYPE_CFG0 || Type == IATU_TYPE_CFG1) { + Ctrl2Off |= IATU_CFG_SHIFT_MODE; + } + + MmioWrite32 (DbiBase + IATU_REGION_CTRL_OUTBOUND (Index) + IATU_LWR_BASE_ADDR_OFF, + (UINT32)CpuBase); + MmioWrite32 (DbiBase + IATU_REGION_CTRL_OUTBOUND (Index) + IATU_UPPER_BASE_ADDR_OFF, + (UINT32)(CpuBase >> 32)); + MmioWrite32 (DbiBase + IATU_REGION_CTRL_OUTBOUND (Index) + IATU_LIMIT_ADDR_OFF, + (UINT32)(CpuBase + Length - 1)); + MmioWrite32 (DbiBase + IATU_REGION_CTRL_OUTBOUND (Index) + IATU_LWR_TARGET_ADDR_OFF, + (UINT32)BusBase); + MmioWrite32 (DbiBase + IATU_REGION_CTRL_OUTBOUND (Index) + IATU_UPPER_TARGET_ADDR_OFF, + (UINT32)(BusBase >> 32)); + MmioWrite32 (DbiBase + IATU_REGION_CTRL_OUTBOUND (Index) + IATU_REGION_CTRL_1_OFF, + Type); + MmioWrite32 (DbiBase + IATU_REGION_CTRL_OUTBOUND (Index) + IATU_REGION_CTRL_2_OFF, + Ctrl2Off); + + gBS->Stall (10000); +} + +STATIC +VOID +PciValidateCfg0 ( + IN UINT32 Segment, + IN EFI_PHYSICAL_ADDRESS Cfg0Base + ) +{ + EFI_STATUS Status; + + // + // Check if the downstream device appears mirrored (due to 64 KB iATU granularity) + // and needs to have config acesses shifted for single device ECAM mode in ACPI. + // + // Warning: + // Bus hang ups have been observed when doing CFG0 cycles to 01:01.0 (+0x8000) + // for some devices that have working filtering and aren't mirrored (e.g. VIA VL805). + // + // Checking 01:01.0 before 01:00.0 and then never again seems fine, at least for UEFI. + // In single-device ECAM mode, an OS is going to scan the entire affected bus again, so + // there's still a risk of locking up the system, but we can't do anything about it. + // + if (MmioRead32 (Cfg0Base + 0x8000) == 0xffffffff + && MmioRead32 (Cfg0Base) != 0xffffffff) { + Status = PcdSet32S (PcdPcieEcamCompliantSegmentsMask, + PcdGet32 (PcdPcieEcamCompliantSegmentsMask) | (1 << Segment)); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "PCIe: Working CFG0 TLP filtering for connected device!\n")); + } +} + +#define NUM_SEGMENTS 5 +#define NUM_MODES 5 + +STATIC struct { + UINT32 Speed; + UINT32 Width; +} LinkSpeedWidthMap[NUM_MODES][NUM_SEGMENTS] = { + /* NANBNB */ { + { 3, 2 }, + { 3, 2 }, + { 2, 1 }, + { 2, 1 }, + { 2, 1 }, + }, + /* NANBBI */ { + { 3, 1 }, + { 3, 2 }, + { 3, 1 }, + { 2, 1 }, + { 2, 1 }, + }, + /* NABINB */ { + { 3, 2 }, + { 3, 1 }, + { 2, 1 }, + { 3, 1 }, + { 2, 1 }, + }, + /* NABIBI */ { + { 3, 1 }, + { 3, 1 }, + { 3, 1 }, + { 3, 1 }, + { 2, 1 }, + }, + /* AGGREGATION */ { + { 3, 4 }, + { 0, 0 }, + { 2, 1 }, + { 2, 1 }, + { 2, 1 }, + }, +}; + +EFI_STATUS +InitializePciHost ( + UINT32 Segment + ) +{ + EFI_PHYSICAL_ADDRESS ApbBase = PCIE_APB_BASE (Segment); + EFI_PHYSICAL_ADDRESS DbiBase = PCIE_DBI_BASE (Segment); + EFI_PHYSICAL_ADDRESS PcieBase = PCIE_CFG_BASE (Segment); + UINTN Retry; + UINT32 LinkSpeed; + UINT32 LinkWidth; + UINT64 Cfg0Base; + UINT64 Cfg0Size; + UINT64 Cfg1Base; + UINT64 Cfg1Size; + UINT64 PciIoBase; + UINT64 PciIoSize; + UINT8 Pcie30PhyMode; + + Pcie30PhyMode = PcdGet8 (PcdPcie30PhyMode); + if (Pcie30PhyMode >= NUM_MODES) { + /* If one modified this to some strange value, this will make all things about to work */ + DEBUG ((DEBUG_WARN, "PCIe: Invalid PCIe 3.0 PHY mode %u, use NANBNB(x2x2)\n", Pcie30PhyMode)); + Pcie30PhyMode = PCIE30_PHY_MODE_NANBNB; + } + if (Segment >= NUM_SEGMENTS) { + DEBUG ((DEBUG_WARN, "PCIe: Invalid segment %u\n", Segment)); + return EFI_INVALID_PARAMETER; + } + + LinkSpeed = LinkSpeedWidthMap[Pcie30PhyMode][Segment].Speed; + LinkWidth = LinkSpeedWidthMap[Pcie30PhyMode][Segment].Width; + if (LinkSpeed == 0 || LinkWidth == 0) { + /* should never here */ + DEBUG ((DEBUG_WARN, "PCIe: Segment %u not enabled\n", Segment)); + return EFI_UNSUPPORTED; + } + + /* Log settings */ + DEBUG ((DEBUG_INIT, "\nPCIe: Segment %u\n", Segment)); + DEBUG ((DEBUG_INIT, "PCIe: PciExpressBaseAddress 0x%lx\n", PcieBase)); + DEBUG ((DEBUG_INIT, "PCIe: ApbBase 0x%lx\n", ApbBase)); + DEBUG ((DEBUG_INIT, "PCIe: DbiBase 0x%lx\n", DbiBase)); + DEBUG ((DEBUG_INIT, "PCIe: NumLanes %u\n", LinkWidth)); + DEBUG ((DEBUG_INIT, "PCIe: LinkSpeed %u\n", LinkSpeed)); + + PcieIoInit(Segment); + PciePowerEn(Segment, TRUE); + gBS->Stall (100000); + + if (Segment == PCIE_SEGMENT_PCIE30X4 || Segment == PCIE_SEGMENT_PCIE30X2) { + /* Configure PCIe 3.0 PHY */ + Pcie30PhyInit (); + } + + /* Combo PHY for PCIe 2.0 is configured earlier by RK3588Dxe */ + + DEBUG ((DEBUG_INIT, "PCIe: Setup clocks\n")); + PciSetupClocks (Segment); + + DEBUG ((DEBUG_INIT, "PCIe: Switching to RC mode\n")); + PciSetRcMode (Segment, ApbBase); + + /* Allow writing RO registers through the DBI */ + DEBUG ((DEBUG_INIT, "PCIe: Enabling DBI access\n")); + MmioOr32 (DbiBase + PL_MISC_CONTROL_1_OFF, DBI_RO_WR_EN); + + DEBUG ((DEBUG_INIT, "PCIe: Setup BARs\n")); + PciSetupBars (DbiBase); + + DEBUG ((DEBUG_INIT, "PCIe: Setup iATU\n")); + Cfg0Base = SIZE_1MB; + Cfg0Size = SIZE_64KB; + Cfg1Base = SIZE_2MB; + Cfg1Size = 0x10000000UL - (SIZE_2MB + SIZE_64KB); + PciIoBase = 0x2FFF0000UL; + PciIoSize = SIZE_64KB; + + PciSetupAtu (DbiBase, 0, IATU_TYPE_CFG0, PcieBase + Cfg0Base, Cfg0Base, Cfg0Size); + PciSetupAtu (DbiBase, 1, IATU_TYPE_CFG1, PcieBase + Cfg1Base, Cfg1Base, Cfg1Size); + PciSetupAtu (DbiBase, 2, IATU_TYPE_IO, PcieBase + PciIoBase, 0, PciIoSize); + + DEBUG ((DEBUG_INIT, "PCIe: Set link speed\n")); + PciSetupLinkSpeed (DbiBase, LinkSpeed, LinkWidth); + PciDirectSpeedChange (DbiBase); + + /* Disallow writing RO registers through the DBI */ + MmioAnd32 (DbiBase + PL_MISC_CONTROL_1_OFF, ~DBI_RO_WR_EN); + + DEBUG ((DEBUG_INIT, "PCIe: Assert reset\n")); + PciePeReset(Segment, TRUE); + + DEBUG ((DEBUG_INIT, "PCIe: Start LTSSM\n")); + + PciEnableLtssm (ApbBase, TRUE); + + gBS->Stall (100000); + DEBUG ((DEBUG_INIT, "PCIe: Deassert reset\n")); + PciePeReset(Segment, FALSE); + + /* Wait for link up */ + DEBUG ((DEBUG_INIT, "PCIe: Waiting for link up...\n")); + for (Retry = 20; Retry != 0; Retry--) { + if (PciIsLinkUp (ApbBase)) { + break; + } + gBS->Stall (100000); + } + if (Retry == 0) { + DEBUG ((DEBUG_WARN, "PCIe: Link up timeout!\n")); + return EFI_TIMEOUT; + } + + PciGetLinkSpeedWidth (DbiBase, &LinkSpeed, &LinkWidth); + PciPrintLinkSpeedWidth (LinkSpeed, LinkWidth); + + PciValidateCfg0 (Segment, PcieBase + Cfg0Base); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.h new file mode 100755 index 0000000..0c9da37 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeInit.h @@ -0,0 +1,18 @@ +/** @file + + Copyright 2021-2023, Jared McNeill + Copyright 2023, Molly Sophia + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PCIHOSTBRIDGEINIT_H__ +#define PCIHOSTBRIDGEINIT_H__ + +EFI_STATUS +InitializePciHost ( + UINT32 Segment + ); + +#endif /* PCIHOSTBRIDGEINIT_H__ */ \ No newline at end of file diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeLib.c new file mode 100755 index 0000000..fa0cba5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/PciHostBridgeLib.c @@ -0,0 +1,295 @@ +/** @file + PCI Host Bridge Library instance for Rockchip Rk3588 + + Copyright (c) 2023, Molly Sophia + Copyright (c) 2021, Jared McNeill + Copyright (c) 2016, Linaro Ltd. All rights reserved.
    + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "PciHostBridgeInit.h" + + +#pragma pack(1) +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; +#pragma pack () + +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + PCIE_SEGMENT_PCIE30X4 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + PCIE_SEGMENT_PCIE30X2 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + PCIE_SEGMENT_PCIE20L0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + PCIE_SEGMENT_PCIE20L1 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)sizeof (ACPI_HID_DEVICE_PATH), + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) + } + }, + EISA_PNP_ID (0x0A08), // PCIe + PCIE_SEGMENT_PCIE20L2 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + }, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { + L"Mem", L"I/O", L"Bus" +}; + +PCI_ROOT_BRIDGE mPciRootBridges[NUM_PCIE_CONTROLLER]; + +/** + Return all the root bridge instances in an array. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances in an array. + The array should be passed into PciHostBridgeFreeRootBridges() + when it's not used. +**/ +PCI_ROOT_BRIDGE * +EFIAPI +PciHostBridgeGetRootBridges ( + UINTN *Count + ) +{ + EFI_STATUS Status; + UINTN Idx; + UINTN Loop; + + for(Idx = 0, Loop = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) { + if(IsPcieNumEnabled(Idx) == FALSE) + continue; + + Status = InitializePciHost(Idx); + if (EFI_ERROR (Status)) + continue; + + mPciRootBridges[Loop].Segment = Idx; + mPciRootBridges[Loop].Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | + EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | + EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \ + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \ + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + mPciRootBridges[Loop].Attributes = mPciRootBridges[Loop].Supports; + mPciRootBridges[Loop].DmaAbove4G = TRUE; + mPciRootBridges[Loop].NoExtendedConfigSpace = FALSE; + mPciRootBridges[Loop].ResourceAssigned = FALSE; + mPciRootBridges[Loop].AllocationAttributes = EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | + EFI_PCI_HOST_BRIDGE_MEM64_DECODE; + + mPciRootBridges[Loop].Bus.Base = 0; + mPciRootBridges[Loop].Bus.Limit = PCIE_BUS_LIMIT; + + mPciRootBridges[Loop].Io.Base = PCIE_IO_BASE; + mPciRootBridges[Loop].Io.Limit = mPciRootBridges[Loop].Io.Base + PCIE_IO_SIZE - 1; + mPciRootBridges[Loop].Io.Translation = MAX_UINT64 - PCIE_IO_XLATE(Idx) + 1; + + mPciRootBridges[Loop].Mem.Base = PCIE_MEM_BASE(Idx); + mPciRootBridges[Loop].Mem.Limit = mPciRootBridges[Loop].Mem.Base + PCIE_MEM_SIZE - 1; + + mPciRootBridges[Loop].MemAbove4G.Base = PCIE_MEM64_BASE(Idx); + mPciRootBridges[Loop].MemAbove4G.Limit = mPciRootBridges[Loop].MemAbove4G.Base + PCIE_MEM64_SIZE - 1; + + mPciRootBridges[Loop].PMem.Base = MAX_UINT64; + mPciRootBridges[Loop].PMem.Limit = 0; + mPciRootBridges[Loop].PMemAbove4G.Base = MAX_UINT64; + mPciRootBridges[Loop].PMemAbove4G.Limit = 0; + mPciRootBridges[Loop].DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Idx]; + + DEBUG((DEBUG_INFO, "0x%llx 0x%llx 0x%llx\n", mPciRootBridges[Loop].Mem.Base, mPciRootBridges[Loop].MemAbove4G.Base,mPciRootBridges[Loop].Io.Translation)); + Loop++; + } + + *Count = Loop; + if(Loop == 0) return NULL; + + return mPciRootBridges; +} + +/** + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). + + @param Bridges The root bridge instances array. + @param Count The count of the array. +**/ +VOID +EFIAPI +PciHostBridgeFreeRootBridges ( + PCI_ROOT_BRIDGE *Bridges, + UINTN Count + ) +{ + // FreePool (Bridges); +} + +/** + Inform the platform that the resource conflict happens. + + @param HostBridgeHandle Handle of the Host Bridge. + @param Configuration Pointer to PCI I/O and PCI memory resource + descriptors. The Configuration contains the resources + for all the root bridges. The resource for each root + bridge is terminated with END descriptor and an + additional END is appended indicating the end of the + entire resources. The resource descriptor field + values follow the description in + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + .SubmitResources(). +**/ +VOID +EFIAPI +PciHostBridgeResourceConflict ( + EFI_HANDLE HostBridgeHandle, + VOID *Configuration + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; + UINTN RootBridgeIndex; + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); + + RootBridgeIndex = 0; + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { + ASSERT (Descriptor->ResType < + (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / + sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) + ) + ); + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], + Descriptor->AddrLen, Descriptor->AddrRangeMax + )); + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, + ((Descriptor->SpecificFlag & + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE + ) != 0) ? L" (Prefetchable)" : L"" + )); + } + } + // + // Skip the END descriptor for root bridge + // + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 + ); + } +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/Rk3588PciHostBridgeLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/Rk3588PciHostBridgeLib.inf new file mode 100755 index 0000000..133a3ad --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/Rk3588PciHostBridgeLib.inf @@ -0,0 +1,56 @@ +## @file +# PCI Host Bridge Library instance for Rockchip RK356x +# +# Copyright (c) 2016, Linaro Ltd. All rights reserved.
    +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Rk3588PciHostBridgeLib + FILE_GUID = 643CA097-12B2-4B84-AF76-FF478D3D45C3 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciHostBridgeLib + +# +# The following information is for reference only and not required by the build +# tools. +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources] + PciHostBridgeLib.c + PciHostBridgeInit.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + DebugLib + DevicePathLib + MemoryAllocationLib + CruLib + GpioLib + Pcie30PhyLib + +[FixedPcd] + gRK3588TokenSpaceGuid.PcdPcie30Supported + +[Pcd] + gRK3588TokenSpaceGuid.PcdComboPhy0Mode + gRK3588TokenSpaceGuid.PcdComboPhy1Mode + gRK3588TokenSpaceGuid.PcdComboPhy2Mode + + gRK3588TokenSpaceGuid.PcdPcie30State + gRK3588TokenSpaceGuid.PcdPcie30PhyMode + + gRK3588TokenSpaceGuid.PcdPcieEcamCompliantSegmentsMask diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/PciSegmentLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/PciSegmentLib.c new file mode 100755 index 0000000..95d566a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/PciSegmentLib.c @@ -0,0 +1,1415 @@ +/** @file + PCI Segment Library for Rockchip RK356x + + Copyright (c) 2023, Molly Sophia + Copyright (c) 2021, Jared McNeill + Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.
    + Copyright (c) 2017, Linaro, Ltd. All rights reserved.
    + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include + +typedef enum { + PciCfgWidthUint8 = 0, + PciCfgWidthUint16, + PciCfgWidthUint32, + PciCfgWidthMax +} PCI_CFG_WIDTH; + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63 + + @param A The address to validate. + @param M Additional bits to assert to be zero. + +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ + ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0) + +#define GET_SEG_NUM(Address) ((Address >> 32) & 0xFFFF) +#define GET_BUS_NUM(Address) ((Address >> 20) & 0xFF) +#define GET_DEV_NUM(Address) ((Address >> 15) & 0x1F) +#define GET_FUNC_NUM(Address) ((Address >> 12) & 0x07) +#define GET_REG_NUM(Address) ((Address) & 0xFFF) + +STATIC +UINT64 +PciSegmentLibGetConfigBase ( + IN UINT64 Address + ) +{ + UINT16 Segment; + UINT8 Bus; + UINT16 Device; + + Segment = GET_SEG_NUM (Address); + Bus = GET_BUS_NUM (Address); + Device = GET_DEV_NUM (Address); + + ASSERT (Segment < NUM_PCIE_CONTROLLER); + + // DEBUG ((DEBUG_ERROR, "PciSegmentLibGetConfigBase: Address=0x%lX, Bus=%d, Segment=%d\n", + // Address, Bus, Segment)); + + // Ignore more than one device on bus 0 and 1 to hide duplicates/ghosts. + if (Device > 0 && (Bus == 0 || Bus == 1)) { + return 0xffffffff; + } + + // The root port is not part of the main config space. + if(Bus == 0) { + return PCIE_DBI_BASE (Segment); + } + + // Here starts the not-quite-compliant ECAM space. + return PCIE_CFG_BASE (Segment); +} + +/** + Internal worker function to read a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param Width The width of data to read + + @return The value read from the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibReadWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width + ) +{ + UINT64 Base; + + Base = PciSegmentLibGetConfigBase (Address); + + if(Base == 0xFFFFFFFF) + return Base; + + // DEBUG ((DEBUG_ERROR, "PciSegmentLibReadWorker: Address=0x%lX, Base=0x%lX, Width=%u\n", + // Address, Base, Width)); + + switch (Width) { + case PciCfgWidthUint8: + return MmioRead8 (Base + (UINT32)Address); + case PciCfgWidthUint16: + return MmioRead16 (Base + (UINT32)Address); + case PciCfgWidthUint32: + return MmioRead32 (Base + (UINT32)Address); + default: + ASSERT (FALSE); + } + + return 0; +} + +/** + Internal worker function to writes a PCI configuration register. + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + @param Width The width of data to write + @param Data The value to write. + + @return The value written to the PCI configuration register. + +**/ +STATIC +UINT32 +PciSegmentLibWriteWorker ( + IN UINT64 Address, + IN PCI_CFG_WIDTH Width, + IN UINT32 Data + ) +{ + UINT64 Base; + + Base = PciSegmentLibGetConfigBase (Address); + + if(Base == 0xFFFFFFFF) + return Base; + + // DEBUG ((DEBUG_ERROR, "PciSegmentLibWriteWorker: Address=0x%lX, Base=0x%lX, Width=%u\n", + // Address, Base, Width)); + + switch (Width) { + case PciCfgWidthUint8: + MmioWrite8 (Base + (UINT32)Address, Data); + break; + case PciCfgWidthUint16: + MmioWrite16 (Base + (UINT32)Address, Data); + break; + case PciCfgWidthUint32: + MmioWrite32 (Base + (UINT32)Address, Data); + break; + default: + ASSERT (FALSE); + } + + return Data; +} + +/** + Register a PCI device so PCI configuration registers may be accessed after + SetVirtualAddressMap(). + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Bus, Device, Function and + Register. + + @retval RETURN_SUCCESS The PCI device was registered for runtime access. + @retval RETURN_UNSUPPORTED An attempt was made to call this function + after ExitBootServices(). + @retval RETURN_UNSUPPORTED The resources required to access the PCI device + at runtime could not be mapped. + @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to + complete the registration. + +**/ +RETURN_STATUS +EFIAPI +PciSegmentRegisterForRuntimeAccess ( + IN UINTN Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + return RETURN_UNSUPPORTED; +} + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, + and Register. + + @return The 8-bit PCI configuration register specified by Address. + +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8); +} + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value); +} + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentOr8 ( + IN UINT64 Address, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAnd8 ( + IN UINT64 Address, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData)); +} + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, + followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAndThenOr8 ( + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in an 8-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldRead8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 8-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldWrite8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value) + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 8-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData) + ); +} + +/** + Reads a bit field in an 8-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 8-bit register. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND between the read result and the value specified by AndData, and + writes the result to the 8-bit PCI configuration register specified by + Address. The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are + serialized. Extra left bits in AndData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAnd8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData) + ); +} + +/** + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 8-bit port. + + Reads the 8-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 8-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..7. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..7. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentBitFieldAndThenOr8 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 ( + Address, + BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData) + ); +} + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16); +} + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value); +} + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 16-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentOr16 ( + IN UINT64 Address, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData)); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAnd16 ( + IN UINT64 Address, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData)); +} + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, + followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAndThenOr16 ( + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData)); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 16-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldRead16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 16-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldWrite16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value) + ); +} + +/** + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData) + ); +} + +/** + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, + and writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param StartBit The ordinal of the least significant bit in the bit field. + The ordinal of the least significant bit in a byte is bit 0. + @param EndBit The ordinal of the most significant bit in the bit field. + The ordinal of the most significant bit in a byte is bit 7. + @param AndData The value to AND with the read value from the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAnd16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData) + ); +} + +/** + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 16-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 15, then ASSERT(). + If EndBit is greater than 15, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..15. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..15. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentBitFieldAndThenOr16 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 ( + Address, + BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData) + ); +} + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Address. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, + and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibReadWorker (Address, PciCfgWidthUint32); +} + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, + Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value); +} + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentOr32 ( + IN UINT64 Address, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, + and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAnd32 ( + IN UINT64 Address, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); +} + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, + followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, Function, + and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAndThenOr32 ( + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData); +} + +/** + Reads a bit field of a PCI configuration register. + + Reads the bit field in a 32-bit PCI configuration register. The bit field is + specified by the StartBit and the EndBit. The value of the bit field is + returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + + @param Address The PCI configuration register to read. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + + @return The value of the bit field read from the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldRead32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit + ) +{ + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); +} + +/** + Writes a bit field to a PCI configuration register. + + Writes Value to the bit field of the PCI configuration register. The bit + field is specified by the StartBit and the EndBit. All other bits in the + destination PCI configuration register are preserved. The new value of the + 32-bit register is returned. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param Value The new value of the bit field. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldWrite32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value) + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and + writes the result back to the bit field in the 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise OR between the read result and the value specified by + OrData, and writes the result to the 32-bit PCI configuration register + specified by Address. The value written to the PCI configuration register is + returned. This function must guarantee that all PCI read and write operations + are serialized. Extra left bits in OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData) + ); +} + +/** + Reads a bit field in a 32-bit PCI configuration register, performs a bitwise + AND, and writes the result back to the bit field in the 32-bit register. + + + Reads the 32-bit PCI configuration register specified by Address, performs a bitwise + AND between the read result and the value specified by AndData, and writes the result + to the 32-bit PCI configuration register specified by Address. The value written to + the PCI configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in AndData are stripped. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAnd32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData) + ); +} + +/** + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a + bitwise OR, and writes the result back to the bit field in the + 32-bit port. + + Reads the 32-bit PCI configuration register specified by Address, performs a + bitwise AND followed by a bitwise OR between the read result and + the value specified by AndData, and writes the result to the 32-bit PCI + configuration register specified by Address. The value written to the PCI + configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in both AndData and + OrData are stripped. + + If any reserved bits in Address are set, then ASSERT(). + If StartBit is greater than 31, then ASSERT(). + If EndBit is greater than 31, then ASSERT(). + If EndBit is less than StartBit, then ASSERT(). + If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT(). + + @param Address The PCI configuration register to write. + @param StartBit The ordinal of the least significant bit in the bit field. + Range 0..31. + @param EndBit The ordinal of the most significant bit in the bit field. + Range 0..31. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the result of the AND operation. + + @return The value written back to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentBitFieldAndThenOr32 ( + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 ( + Address, + BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData) + ); +} + +/** + Reads a range of PCI configuration registers into a caller supplied buffer. + + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment, Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); + + if (Size == 0) { + return Size; + } + + ASSERT (Buffer != NULL); + + // + // Save Size for return + // + ReturnValue = Size; + + if ((StartAddress & BIT0) != 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); + StartAddress += sizeof (UINT8); + Size -= sizeof (UINT8); + Buffer = (UINT8*)Buffer + 1; + } + + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + while (Size >= sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); + StartAddress += sizeof (UINT32); + Size -= sizeof (UINT32); + Buffer = (UINT32*)Buffer + 1; + } + + if (Size >= sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + if (Size >= sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress); + } + + return ReturnValue; +} + + +/** + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment, Bus, + Device, Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to write. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); + ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000); + + if (Size == 0) { + return 0; + } + + ASSERT (Buffer != NULL); + + // + // Save Size for return + // + ReturnValue = Size; + + if ((StartAddress & BIT0) != 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + StartAddress += sizeof (UINT8); + Size -= sizeof (UINT8); + Buffer = (UINT8*)Buffer + 1; + } + + if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) { + // + // Write a word if StartAddress is word aligned + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + while (Size >= sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); + StartAddress += sizeof (UINT32); + Size -= sizeof (UINT32); + Buffer = (UINT32*)Buffer + 1; + } + + if (Size >= sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress += sizeof (UINT16); + Size -= sizeof (UINT16); + Buffer = (UINT16*)Buffer + 1; + } + + if (Size >= sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer); + } + + return ReturnValue; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/Rk3588PciSegmentLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/Rk3588PciSegmentLib.inf new file mode 100755 index 0000000..5e748c0 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/Rk3588PciSegmentLib.inf @@ -0,0 +1,41 @@ +## @file +# Instance of PCI Segment Library based on PCI Library. +# +# PCI Segment Library that layers on top of the PCI Library +# +# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
    +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Rk3588PciSegmentLib + MODULE_UNI_FILE = Rk3588PciSegmentLib.uni + FILE_GUID = 5EDF4444-F65F-4CE8-9CC6-25CBFD488FAD + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciSegmentLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + BaseLib + PciLib + DebugLib + +[FixedPcd] diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/Rk3588PciSegmentLib.uni b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/Rk3588PciSegmentLib.uni new file mode 100755 index 0000000..dae73de --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/Rk3588PciSegmentLib.uni @@ -0,0 +1,16 @@ +// /** @file +// Instance of PCI Segment Library based on PCI Library. +// +// PCI Segment Library that layers on top of the PCI Library which only +// supports segment 0 PCI configuration access. +// +// Copyright (c) 2016, Intel Corporation. All rights reserved.
    +// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI Segment Library based on PCI Library." + +#string STR_MODULE_DESCRIPTION #language en-US "PCI Segment Library that layers on top of the PCI Library." diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RkSdmmcPlatformLib/RkSdmmcPlatformLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RkSdmmcPlatformLib/RkSdmmcPlatformLib.c new file mode 100644 index 0000000..c0f68f8 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RkSdmmcPlatformLib/RkSdmmcPlatformLib.c @@ -0,0 +1,66 @@ +/** @file + * + * RkSdmmcDxe platform helper library. + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SCMI_CCLK_SD 9 + +EFI_STATUS +EFIAPI +RkSdmmcSetClockRate ( + IN UINTN Frequency + ) +{ + EFI_STATUS Status; + SCMI_CLOCK_PROTOCOL *ClockProtocol; + EFI_GUID ClockProtocolGuid = ARM_SCMI_CLOCK_PROTOCOL_GUID; + + Status = gBS->LocateProtocol (&ClockProtocolGuid, + NULL, + (VOID **) &ClockProtocol); + ASSERT (!EFI_ERROR (Status)); + + Status = ClockProtocol->RateSet (ClockProtocol, SCMI_CCLK_SD, Frequency); + ASSERT (!EFI_ERROR (Status)); + + return Status; +} + +VOID +EFIAPI +RkSdmmcSetIoMux ( + VOID + ) +{ +#define SYS_GRF_SOC_CON6 (0xFD58C000 + 0x0318) + + // Clear force_jtag (SD slot is muxed with JTAG) + MmioWrite32(SYS_GRF_SOC_CON6, 0x40000000); + + GpioPinSetDirection (0, GPIO_PIN_PA4, GPIO_PIN_INPUT); + SdmmcIoMux (); +} + +RKSDMMC_CARD_PRESENCE_STATE +EFIAPI +RkSdmmcGetCardPresenceState ( + VOID + ) +{ + return GpioPinReadActual (0, GPIO_PIN_PA4) ? RkSdmmcCardNotPresent + : RkSdmmcCardPresent; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RkSdmmcPlatformLib/RkSdmmcPlatformLib.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RkSdmmcPlatformLib/RkSdmmcPlatformLib.inf new file mode 100644 index 0000000..89eb1eb --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RkSdmmcPlatformLib/RkSdmmcPlatformLib.inf @@ -0,0 +1,33 @@ +#/** @file +# +# RkSdmmcDxe platform helper library. +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = RkSdmmcPlatformLib + FILE_GUID = b9039d6e-6d84-4f32-bfc5-9c328ed3e660 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RkSdmmcPlatformLib + +[Sources] + RkSdmmcPlatformLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Rockchip/RockchipPkg.dec + Silicon/Rockchip/RK3588/RK3588.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + GpioLib + IoLib + RockchipPlatformLib diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon/RK3588CruLib.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon/RK3588CruLib.c new file mode 100644 index 0000000..e4c708b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon/RK3588CruLib.c @@ -0,0 +1,480 @@ +/** @file + * + * Copyright (c) 2024, Mario Bălănică + * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include "Include/Library/CruLib.h" +#include +/** @addtogroup RK_HAL_Driver + * @{ + */ + +/** @addtogroup CRU + * @{ + */ + +/** @defgroup CRU_Private_Definition Private Definition + * @{ + */ +/********************* Private MACRO Definition ******************************/ +/********************* Private Structure Definition **************************/ + +static struct PLL_CONFIG PLL_TABLE[] = { + /* _mhz, _refDiv, _fbDiv, _postdDv1, _postDiv2, _dsmpd, _frac */ + RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), + RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), + RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), + RK3588_PLL_RATE(100000000, 3, 400, 5, 0), + { /* sentinel */ }, +}; + +static struct PLL_SETUP LPLL = { + .conOffset0 = &(DSUCRU->LPLL_CON[0]), + .conOffset1 = &(DSUCRU->LPLL_CON[1]), + .conOffset2 = &(DSUCRU->LPLL_CON[2]), + .conOffset3 = &(DSUCRU->LPLL_CON[3]), + .conOffset6 = &(DSUCRU->LPLL_CON[6]), + .modeOffset = &(DSUCRU->MODE_CON00), + .modeShift = 0, + .lockShift = 15, + .modeMask = 0x3, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP B0PLL = { + .conOffset0 = &(BIGCORE0CRU->B0PLL_CON[0]), + .conOffset1 = &(BIGCORE0CRU->B0PLL_CON[1]), + .conOffset2 = &(BIGCORE0CRU->B0PLL_CON[2]), + .conOffset3 = &(BIGCORE0CRU->B0PLL_CON[3]), + .conOffset6 = &(BIGCORE0CRU->B0PLL_CON[6]), + .modeOffset = &(BIGCORE0CRU->MODE_CON00), + .modeShift = 0, + .lockShift = 15, + .modeMask = 0x3, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP B1PLL = { + .conOffset0 = &(BIGCORE1CRU->B1PLL_CON[0]), + .conOffset1 = &(BIGCORE1CRU->B1PLL_CON[1]), + .conOffset2 = &(BIGCORE1CRU->B1PLL_CON[2]), + .conOffset3 = &(BIGCORE1CRU->B1PLL_CON[3]), + .conOffset6 = &(BIGCORE1CRU->B1PLL_CON[6]), + .modeOffset = &(BIGCORE1CRU->MODE_CON00), + .modeShift = 0, + .lockShift = 15, + .modeMask = 0x3, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP CPLL = { + .conOffset0 = &(CRU->CPLL_CON[0]), + .conOffset1 = &(CRU->CPLL_CON[1]), + .conOffset2 = &(CRU->CPLL_CON[2]), + .conOffset3 = &(CRU->CPLL_CON[3]), + .conOffset6 = &(CRU->CPLL_CON[6]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 8, + .lockShift = 15, + .modeMask = 0x3 << 8, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP GPLL = { + .conOffset0 = &(CRU->GPLL_CON[0]), + .conOffset1 = &(CRU->GPLL_CON[1]), + .conOffset2 = &(CRU->GPLL_CON[2]), + .conOffset3 = &(CRU->GPLL_CON[3]), + .conOffset6 = &(CRU->GPLL_CON[6]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 2, + .lockShift = 15, + .modeMask = 0x3 << 2, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP NPLL = { + .conOffset0 = &(CRU->NPLL_CON[0]), + .conOffset1 = &(CRU->NPLL_CON[1]), + .conOffset2 = &(CRU->NPLL_CON[2]), + .conOffset3 = &(CRU->NPLL_CON[3]), + .conOffset6 = &(CRU->NPLL_CON[6]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 0, + .lockShift = 15, + .modeMask = 0x3 << 0, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP V0PLL = { + .conOffset0 = &(CRU->V0PLL_CON[0]), + .conOffset1 = &(CRU->V0PLL_CON[1]), + .conOffset2 = &(CRU->V0PLL_CON[2]), + .conOffset3 = &(CRU->V0PLL_CON[3]), + .conOffset6 = &(CRU->V0PLL_CON[6]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 4, + .lockShift = 15, + .modeMask = 0x3 << 4, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP AUPLL = { + .conOffset0 = &(CRU->AUPLL_CON[0]), + .conOffset1 = &(CRU->AUPLL_CON[1]), + .conOffset2 = &(CRU->AUPLL_CON[2]), + .conOffset3 = &(CRU->AUPLL_CON[3]), + .conOffset6 = &(CRU->AUPLL_CON[6]), + .modeOffset = &(CRU->MODE_CON00), + .modeShift = 6, + .lockShift = 15, + .modeMask = 0x3 << 6, + .rateTable = PLL_TABLE, +}; + +static struct PLL_SETUP PPLL = { + .conOffset0 = &(PHPTOPCRU->PPLL_CON[0]), + .conOffset1 = &(PHPTOPCRU->PPLL_CON[1]), + .conOffset2 = &(PHPTOPCRU->PPLL_CON[2]), + .conOffset3 = &(PHPTOPCRU->PPLL_CON[3]), + .conOffset6 = &(PHPTOPCRU->PPLL_CON[6]), + .lockShift = 15, + .rateTable = PLL_TABLE, +}; + +static CRU_CLOCK Clocks[CLK_COUNT] = { + CRU_CLOCK_INIT (CCLK_EMMC, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, CCLK_EMMC_SEL, + CRU_CLKSEL_CON_OFFSET, CCLK_EMMC_DIV, + CRU_CLKGATE_CON_OFFSET, CCLK_EMMC_GATE), + CRU_CLOCK_INIT (SCLK_SFC, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, SCLK_SFC_SEL, + CRU_CLKSEL_CON_OFFSET, SCLK_SFC_DIV, + CRU_CLKGATE_CON_OFFSET, SCLK_SFC_GATE), + CRU_CLOCK_INIT (CCLK_SRC_SDIO, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, CCLK_SRC_SDIO_SEL, + CRU_CLKSEL_CON_OFFSET, CCLK_SRC_SDIO_DIV, + CRU_CLKGATE_CON_OFFSET, CCLK_SRC_SDIO_GATE), + CRU_CLOCK_INIT (BCLK_EMMC, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, BCLK_EMMC_SEL, + CRU_CLKSEL_CON_OFFSET, BCLK_EMMC_DIV, + CRU_CLKGATE_CON_OFFSET, BCLK_EMMC_GATE), + CRU_CLOCK_INIT (CLK_REF_PIPE_PHY0, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, CLK_REF_PIPE_PHY0_SEL, + CRU_CLKSEL_CON_OFFSET, CLK_REF_PIPE_PHY0_PLL_SRC_DIV, + CRU_CLKGATE_CON_OFFSET, CLK_REF_PIPE_PHY0_PLL_SRC_GATE), + CRU_CLOCK_INIT (CLK_REF_PIPE_PHY1, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, CLK_REF_PIPE_PHY1_SEL, + CRU_CLKSEL_CON_OFFSET, CLK_REF_PIPE_PHY1_PLL_SRC_DIV, + CRU_CLKGATE_CON_OFFSET, CLK_REF_PIPE_PHY1_PLL_SRC_GATE), + CRU_CLOCK_INIT (CLK_REF_PIPE_PHY2, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, CLK_REF_PIPE_PHY2_SEL, + CRU_CLKSEL_CON_OFFSET, CLK_REF_PIPE_PHY2_PLL_SRC_DIV, + CRU_CLKGATE_CON_OFFSET, CLK_REF_PIPE_PHY2_PLL_SRC_GATE), + CRU_CLOCK_INIT (DCLK_VOP2_SRC, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, DCLK_VOP2_SRC_SEL, + CRU_CLKSEL_CON_OFFSET, DCLK_VOP2_SRC_DIV, + CRU_CLKGATE_CON_OFFSET, DCLK_VOP2_SRC_GATE), + CRU_CLOCK_INIT (CLK_I2S0_8CH_TX_SRC, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, CLK_I2S0_8CH_TX_SRC_SEL, + CRU_CLKSEL_CON_OFFSET, CLK_I2S0_8CH_TX_SRC_DIV, + CRU_CLKGATE_CON_OFFSET, CLK_I2S0_8CH_TX_GATE), + CRU_CLOCK_NODIV_INIT (MCLK_I2S0_8CH_TX, CRU_BASE, + CRU_CLKSEL_CON_OFFSET, MCLK_I2S0_8CH_TX_SEL, + CRU_CLKGATE_CON_OFFSET, MCLK_I2S0_8CH_TX_GATE), + CRU_CLOCK_NODIV_INIT (MCLK_I2S1_8CH_TX, PMU1CRU_BASE, + CRU_CLKSEL_CON_OFFSET, MCLK_I2S1_8CH_TX_SEL, + CRU_CLKGATE_CON_OFFSET, MCLK_I2S1_8CH_TX_GATE), +}; + +static CRU_RESET Resets[RESET_COUNT] = { + // TO-DO +}; + +/********************* Private Variable Definition ***************************/ + +static uint32_t s_lpllFreq; +static uint32_t s_cpllFreq = 1500 * 1000 * 1000; +static uint32_t s_gpllFreq = 1188 * 1000 * 1000; +static uint32_t s_npllFreq; +static uint32_t s_v0pllFreq; +static uint32_t s_ppllFreq; +static uint32_t s_aupllFreq; + +/********************* Private Function Definition ***************************/ + +/** @} */ +/********************* Public Function Definition ****************************/ + +CRU_CLOCK * +EFIAPI +HAL_CRU_ClkGetById(uint32_t clockId) +{ + ASSERT (clockId < CLK_COUNT); + if (clockId >= CLK_COUNT) { + return NULL; + } + return &Clocks[clockId]; +} + +CRU_RESET * +EFIAPI +HAL_CRU_RstGetById(uint32_t resetId) +{ + ASSERT (resetId < RESET_COUNT); + if (resetId >= RESET_COUNT) { + return NULL; + } + return &Resets[resetId]; +} + +/** + * @brief Get clk freq. + * @param clockId: CLOCK_Name id. + * @return rate. + * @attention these APIs allow direct use in the HAL layer. + */ +uint32_t +EFIAPI +HAL_CRU_ClkGetFreq(uint32_t clockId) +{ + uint32_t pRate = 0, freq; + + if (!s_cpllFreq) { + s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL); + } + + if (!s_v0pllFreq) { + s_v0pllFreq = HAL_CRU_GetPllV1Freq(&V0PLL); + } + + switch (clockId) { + case PLL_LPLL: + freq = HAL_CRU_GetPllV1Freq(&LPLL); + s_lpllFreq = freq; + + return freq; + case PLL_B0PLL: + freq = HAL_CRU_GetPllV1Freq(&B0PLL); + + return freq; + case PLL_B1PLL: + freq = HAL_CRU_GetPllV1Freq(&B1PLL); + + return freq; + case PLL_CPLL: + freq = HAL_CRU_GetPllV1Freq(&CPLL); + s_cpllFreq = freq; + + return freq; + case PLL_NPLL: + freq = HAL_CRU_GetPllV1Freq(&NPLL); + s_npllFreq = freq; + + return freq; + case PLL_V0PLL: + freq = HAL_CRU_GetPllV1Freq(&V0PLL); + s_v0pllFreq = freq; + + return freq; + case PLL_AUPLL: + freq = HAL_CRU_GetPllV1Freq(&AUPLL); + s_aupllFreq = freq; + + return freq; + case PLL_PPLL: + freq = HAL_CRU_GetPllV1Freq(&PPLL); + s_ppllFreq = freq; + + return freq; + case PLL_GPLL: + freq = HAL_CRU_GetPllV1Freq(&GPLL); + s_gpllFreq = freq; + + return s_gpllFreq; + case CCLK_EMMC: + case SCLK_SFC: + case CCLK_SRC_SDIO: + if (HAL_CRU_ClkGetMux(clockId) == 0) { + pRate = s_gpllFreq; + } else if (HAL_CRU_ClkGetMux(clockId) == 1) { + pRate = s_cpllFreq; + } else if (HAL_CRU_ClkGetMux(clockId) == 2) { + pRate = PLL_INPUT_OSC_RATE; + } + + return pRate / HAL_CRU_ClkGetDiv(clockId) ; + case BCLK_EMMC: + if (HAL_CRU_ClkGetMux(clockId) == 0) { + pRate = s_gpllFreq; + } else if (HAL_CRU_ClkGetMux(clockId) == 1) { + pRate = s_cpllFreq; + } + + return pRate / HAL_CRU_ClkGetDiv(clockId) ; + case CLK_REF_PIPE_PHY0: + case CLK_REF_PIPE_PHY1: + case CLK_REF_PIPE_PHY2: + if (HAL_CRU_ClkGetMux(clockId) == 0) { + return PLL_INPUT_OSC_RATE; + } else if (HAL_CRU_ClkGetMux(clockId) == 1) { + return s_ppllFreq / HAL_CRU_ClkGetDiv(clockId) ; + } + + case DCLK_VOP2_SRC: + ASSERT (HAL_CRU_ClkGetMux(clockId) == 2); + pRate = s_v0pllFreq; + break; + default: + break; + } + + freq = pRate / HAL_CRU_ClkGetDiv(clockId); + + return freq; +} + +#define RK3588_VOP_PLL_LIMIT_FREQ 600000000 + +/** + * @brief Set clk freq. + * @param clockId: CLOCK_Name id. + * @param rate: clk rate. + * @return HAL_Status. + * @attention these APIs allow direct use in the HAL layer. + */ +HAL_Status +EFIAPI +HAL_CRU_ClkSetFreq(uint32_t clockId, uint32_t rate) +{ + HAL_Status error = HAL_OK; + uint32_t mux = 0, div = 0, pRate = 0; + + if (!s_cpllFreq) { + s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL); + } + + if (!s_v0pllFreq) { + s_v0pllFreq = HAL_CRU_GetPllV1Freq(&V0PLL); + } + + switch (clockId) { + case PLL_LPLL: + error = HAL_CRU_SetPllV1Freq(&LPLL, rate); + s_lpllFreq = HAL_CRU_GetPllV1Freq(&LPLL); + + return error; + case PLL_B0PLL: + error = HAL_CRU_SetPllV1Freq(&B0PLL, rate); + + return error; + case PLL_B1PLL: + error = HAL_CRU_SetPllV1Freq(&B1PLL, rate); + + return error; + case PLL_CPLL: + error = HAL_CRU_SetPllV1Freq(&CPLL, rate); + s_cpllFreq = HAL_CRU_GetPllV1Freq(&CPLL); + + return error; + case PLL_PPLL: + error = HAL_CRU_SetPllV1Freq(&PPLL, rate); + s_ppllFreq = HAL_CRU_GetPllV1Freq(&PPLL); + + return error; + case PLL_GPLL: + error = HAL_CRU_SetPllV1Freq(&GPLL, rate); + DEBUG ((DEBUG_INIT, "GPLL set rate: %d %x\n", rate, error)); + s_gpllFreq = HAL_CRU_GetPllV1Freq(&GPLL); + return error; + case PLL_NPLL: + error = HAL_CRU_SetPllV1Freq(&NPLL, rate); + s_npllFreq = HAL_CRU_GetPllV1Freq(&NPLL); + + return error; + case PLL_AUPLL: + error = HAL_CRU_SetPllV1Freq(&AUPLL, rate); + s_aupllFreq = HAL_CRU_GetPllV1Freq(&AUPLL); + + return error; + case PLL_V0PLL: + error = HAL_CRU_SetPllV1Freq(&V0PLL, rate); + s_v0pllFreq = HAL_CRU_GetPllV1Freq(&V0PLL); + + return error; + + case CCLK_EMMC: + case SCLK_SFC: + case CCLK_SRC_SDIO: + if (PLL_INPUT_OSC_RATE % rate == 0) { + pRate = PLL_INPUT_OSC_RATE; + mux = 2; + } else if (s_cpllFreq % rate == 0){ + pRate = s_cpllFreq; + mux = 1; + } else { + pRate = s_gpllFreq; + mux = 0; + } + break; + case BCLK_EMMC: + if (s_cpllFreq % rate == 0){ + pRate = s_cpllFreq; + mux = 1; + } else { + pRate = s_gpllFreq; + mux = 0; + } + break; + + case CLK_REF_PIPE_PHY0: + case CLK_REF_PIPE_PHY1: + case CLK_REF_PIPE_PHY2: + if (rate == PLL_INPUT_OSC_RATE) { + HAL_CRU_ClkSetMux(clockId, 0); + HAL_CRU_ClkSetDiv(clockId, 0); + } else { + div = HAL_DIV_ROUND_UP(s_ppllFreq, rate); + HAL_CRU_ClkSetDiv(clockId, div); + HAL_CRU_ClkSetMux(clockId, 1); + } + return HAL_OK; + + case DCLK_VOP2_SRC: + HAL_CRU_ClkSetMux(clockId, 2); + + if (s_v0pllFreq >= RK3588_VOP_PLL_LIMIT_FREQ && s_v0pllFreq % rate == 0) { + div = HAL_DIV_ROUND_UP(s_v0pllFreq, rate); + HAL_CRU_ClkSetDiv(clockId, div); + } else { + div = HAL_DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate); + HAL_CRU_ClkSetDiv(clockId, div); + error = HAL_CRU_ClkSetFreq(PLL_V0PLL, div * rate); + } + return error; + default: + break; + } + + div = HAL_DIV_ROUND_UP(pRate, rate); + + HAL_CRU_ClkSetMux(clockId, mux); + HAL_CRU_ClkSetDiv(clockId, div); + + return HAL_OK; +} +/** @} */ + +/** @} */ + +/** @} */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec new file mode 100644 index 0000000..2c2c56b --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.dec @@ -0,0 +1,98 @@ +## @file +# +# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010019 + PACKAGE_NAME = RK3588 + PACKAGE_GUID = 26e6ce4a-45e7-11ec-9726-f42a7dcb925d + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gRK3588TokenSpaceGuid = { 0x32594b40, 0x45e7, 0x11ec, { 0xbb, 0xc1, 0xf4, 0x2a, 0x7d, 0xcb, 0x92, 0x5d } } + gRK3588DxeFormSetGuid = { 0x10f41c33, 0xa468, 0x42cd, { 0x85, 0xee, 0x70, 0x43, 0x21, 0x3f, 0x73, 0xa3 } } + +[PcdsFixedAtBuild] + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|0|UINT32|0x00010001 + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|0|UINT32|0x00010002 + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|0|UINT32|0x00010003 + + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE|BOOLEAN|0x00010101 + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE|BOOLEAN|0x00010102 + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE|BOOLEAN|0x00010103 + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|0|UINT32|0x00010104 + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|0|UINT32|0x00010105 + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|0|UINT32|0x00010106 + + gRK3588TokenSpaceGuid.PcdPcie30Supported|FALSE|BOOLEAN|0x00010201 + gRK3588TokenSpaceGuid.PcdPcie30PhyModeDefault|4|UINT8|0x00010202 + + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault|0|UINT32|0x00010301 + + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|FALSE|BOOLEAN|0x10401 + + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|FALSE|BOOLEAN|0x00010501 + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|FALSE|BOOLEAN|0x00010502 + gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x0 }|VOID*|0x00010503 + gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 }|VOID*|0x00010504 + + gRK3588TokenSpaceGuid.PcdGmac0Supported|FALSE|BOOLEAN|0x00010601 + gRK3588TokenSpaceGuid.PcdGmac1Supported|FALSE|BOOLEAN|0x00010602 + gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0|UINT8|0x00010603 + gRK3588TokenSpaceGuid.PcdGmac0RxDelay|0|UINT8|0x00010604 + gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0|UINT8|0x00010605 + gRK3588TokenSpaceGuid.PcdGmac1RxDelay|0|UINT8|0x00010606 + + gRK3588TokenSpaceGuid.PcdI2S0Supported|FALSE|BOOLEAN|0x00010701 + gRK3588TokenSpaceGuid.PcdI2S1Supported|FALSE|BOOLEAN|0x00010702 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|0|UINT32|0x00000001 + gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|0|UINT32|0x00000002 + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|0|UINT32|0x00000003 + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|0|UINT32|0x00000004 + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|0|UINT32|0x00000005 + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|0|UINT32|0x00000006 + gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|0|UINT32|0x00000007 + gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|0|UINT32|0x00000008 + gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|0|UINT32|0x00000009 + gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|0|UINT32|0x0000000A + gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|0|UINT32|0x0000000B + gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|0|UINT32|0x0000000C + + gRK3588TokenSpaceGuid.PcdComboPhy0Mode|0|UINT32|0x00000101 + gRK3588TokenSpaceGuid.PcdComboPhy1Mode|0|UINT32|0x00000102 + gRK3588TokenSpaceGuid.PcdComboPhy2Mode|0|UINT32|0x00000103 + + gRK3588TokenSpaceGuid.PcdPcie30State|0|UINT32|0x00000201 + gRK3588TokenSpaceGuid.PcdPcie30PhyMode|0|UINT8|0x00000202 + + gRK3588TokenSpaceGuid.PcdConfigTableMode|0|UINT32|0x00000300 + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatMode|0|UINT32|0x00000301 + gRK3588TokenSpaceGuid.PcdFdtSupportOverrides|0|UINT8|0x00000351 + + gRK3588TokenSpaceGuid.PcdCoolingFanState|0|UINT32|0x00000401 + gRK3588TokenSpaceGuid.PcdCoolingFanSpeed|0|UINT32|0x00000402 + + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Usb3State|0|UINT32|0x00000501 + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Usb3State|0|UINT32|0x00000502 + +[PcdsDynamicEx] + gRK3588TokenSpaceGuid.PcdPcieEcamCompliantSegmentsMask|0|UINT32|0x20000001 diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf new file mode 100644 index 0000000..5452655 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588.fdf @@ -0,0 +1,178 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.NOR_FLASH_IMAGE] +BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x00800000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x800 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ +0x00200000|0x00500000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = BL33_AP_UEFI + +# NV_VARIABLE_STORE +0x007C0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + +# NV_FTW_WORKING header +0x007D0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + +# NV_FTW_WORKING data +0x007E0000|0x00010000 +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + # + # Prioritized components, ignoring dependency expressions + # + APRIORI DXE { +!include Silicon/Rockchip/FvMainAprioriDxe.fdf.inc + } + + # + # Common components + # +!include Silicon/Rockchip/FvMainModules.fdf.inc + + # + # General platform manager + # + INF Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf + + # + # PCI Support + # +!if $(RK3588_PCIE_ENABLE) == TRUE + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + INF EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf +!endif + + # + # USB/DP PHY Driver + # + INF Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.inf + + # + # GMAC Init Driver + # + INF Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf + + # + # ACPI Support + # + INF Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + # Device Tree Support + # + INF Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf + + # + # Custom platform components + # +!include $(RK_PLATFORM_FVMAIN_MODULES) + +[FV.BL33_AP_UEFI] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + # + # Common PEI components + # +!include Silicon/Rockchip/FvCompactModules.fdf.inc + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +!include Silicon/Rockchip/FvRules.fdf.inc diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc new file mode 100644 index 0000000..985206a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Base.dsc.inc @@ -0,0 +1,374 @@ +## @file +# +# Copyright (c) 2014-2018, Linaro Limited. All rights reserved. +# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + DEFINE CONFIG_NO_DEBUGLIB = FALSE + + # + # Shared Defines + # - must be kept in sync with their associated headers + # - values must be hexadecimal if used in byte array PCDs + # + + # + # Silicon/Rockchip/RK3588/Include/VarStoreData.h + # + DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT = 0 + DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MIN = 1 + DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_MAX = 2 + DEFINE CPU_PERF_CLUSTER_CLOCK_PRESET_CUSTOM = 3 + + DEFINE COMBO_PHY_MODE_UNCONNECTED = 0 + DEFINE COMBO_PHY_MODE_PCIE = 1 + DEFINE COMBO_PHY_MODE_SATA = 2 + DEFINE COMBO_PHY_MODE_USB3 = 3 + + DEFINE COOLING_FAN_STATE_DISABLED = 0 + DEFINE COOLING_FAN_STATE_ENABLED = 1 + + DEFINE USBDP_PHY_USB3_STATE_DISABLED = 0 + DEFINE USBDP_PHY_USB3_STATE_ENABLED = 1 + + DEFINE CONFIG_TABLE_MODE_ACPI = 0x00000001 + DEFINE CONFIG_TABLE_MODE_FDT = 0x00000002 + DEFINE CONFIG_TABLE_MODE_ACPI_FDT = 0x00000003 + + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_SINGLE_DEV = 0x00000001 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6 = 0x00000002 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_GRAVITON = 0x00000004 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV = 0x00000003 + DEFINE ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_GRAVITON = 0x00000006 + + # + # Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/CpuPerformance.h + # + DEFINE SCMI_CLK_CPUL = 0x0 + DEFINE SCMI_CLK_CPUB01 = 0x2 + DEFINE SCMI_CLK_CPUB23 = 0x3 + + # + # Default peripheral support flags + # +!ifndef RK_STATUS_LED_ENABLE + DEFINE RK_STATUS_LED_ENABLE = TRUE +!endif +!ifndef RK_NOR_FLASH_ENABLE + DEFINE RK_NOR_FLASH_ENABLE = TRUE +!endif +!ifndef RK_860X_REGULATOR_ENABLE + DEFINE RK_860X_REGULATOR_ENABLE = TRUE +!endif +!ifndef RK_SD_ENABLE + DEFINE RK_SD_ENABLE = TRUE +!endif +!ifndef RK_EMMC_ENABLE + DEFINE RK_EMMC_ENABLE = TRUE +!endif +!ifndef RK_AHCI_ENABLE + DEFINE RK_AHCI_ENABLE = TRUE +!endif +!ifndef RK_DW_HDMI_QP_ENABLE + DEFINE RK_DW_HDMI_QP_ENABLE = TRUE +!endif + + # + # RK3588-specific flags + # +!ifndef RK3588_PCIE_ENABLE + DEFINE RK3588_PCIE_ENABLE = TRUE +!endif + + # + # Base platform description + # +!include Silicon/Rockchip/Rockchip.dsc.inc + +################################################################################ +# +# Library Class section - list of all common Library Classes needed by RK3588 platforms. +# +################################################################################ + +[LibraryClasses.common] + # ACPI helpers + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf + + # Debug UART library + SerialPortLib|Silicon/Rockchip/Library/Dw8250SerialPortLib/DebugDw8250SerialPortLib.inf + + # SoC and memory descriptors + ArmPlatformLib|Silicon/Rockchip/RK3588/Library/PlatformLib/PlatformLib.inf + + # PCI Support +!if $(RK3588_PCIE_ENABLE) == TRUE + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciSegmentLib|Silicon/Rockchip/RK3588/Library/Rk3588PciSegmentLib/Rk3588PciSegmentLib.inf + PciHostBridgeLib|Silicon/Rockchip/RK3588/Library/Rk3588PciHostBridgeLib/Rk3588PciHostBridgeLib.inf + Pcie30PhyLib|Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.inf +!endif + + # RkSdmmcDxe dependencies + RkSdmmcPlatformLib|Silicon/Rockchip/RK3588/Library/RkSdmmcPlatformLib/RkSdmmcPlatformLib.inf + + # DwcSdhciDxe dependencies + DwcSdhciPlatformLib|Silicon/Rockchip/RK3588/Library/DwcSdhciPlatformLib/DwcSdhciPlatformLib.inf + + # Other SoC-specific libraries + OtpLib|Silicon/Rockchip/RK3588/Library/OtpLib/OtpLib.inf + GpioLib|Silicon/Rockchip/RK3588/Library/GpioLib/GpioLib.inf + +[LibraryClasses.common.SEC] + MemoryInitPeiLib|Silicon/Rockchip/RK3588/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf + +################################################################################################### +# BuildOptions Section - Define the module specific tool chain flags that should be used as +# the default flags for a module. These flags are appended to any +# standard flags that are defined by the build process. +################################################################################################### + +[BuildOptions] + GCC:*_*_*_PLATFORM_FLAGS = -I$(WORKSPACE)/Silicon/Rockchip/RK3588/Include -I$(WORKSPACE)/Silicon/Rockchip/Include + +################################################################################ +# +# Pcd Section - list of all common EDK II PCD Entries used by RK3588 platforms. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # System Memory (1GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 + + # RK3588 CPU profile + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + gArmPlatformTokenSpaceGuid.PcdClusterCount|1 + + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdProcessorName|"Rockchip RK3588 variant" + gRockchipTokenSpaceGuid.PcdPlatformName|"Generic RK3588 platform" + gRockchipTokenSpaceGuid.PcdMemoryVendorName|"TBD" + + # I2C + gRockchipTokenSpaceGuid.PcdI2cClockFrequency|198000000 + gRockchipTokenSpaceGuid.PcdI2cBaudRate|100000 + gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ UINT32(550000), UINT32(550000) } + gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ UINT32(1050000), UINT32(1050000) } + + # UART2 - Serial Terminal + DEFINE SERIAL_BASE = 0xFEB50000 # UART2 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|$(SERIAL_BASE) + gHisiTokenSpaceGuid.PcdSerialPortSendDelay|500000 + gHisiTokenSpaceGuid.PcdUartClkInHz|24000000 + + # SPI - SPI2 for test + gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0xFEB20000 + + # NOR FLASH + gRockchipTokenSpaceGuid.FspiBaseAddr|0xFE2B0000 + + # CRU + gRockchipTokenSpaceGuid.CruBaseAddr|0xFD7C0000 + + # + # ARM General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0xfe600000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xfe600000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfe680000 + + # GUID of the UI app + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + + # + # DesignWare SD Controller (MSHC) + # + gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress|0xfe2c0000 + + # + # DesignWare SD/eMMC Controller (SDHCI) + # + gRockchipTokenSpaceGuid.PcdDwcSdhciBaseAddress|0xfe2e0000 + + # + # USB2 EHCI + OHCI companion controllers + # + gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0xfc800000 + gRockchipTokenSpaceGuid.PcdNumEhciController|2 + gRockchipTokenSpaceGuid.PcdEhciSize|0x40000 + gRockchipTokenSpaceGuid.PcdOhciSize|0x40000 + + # + # DWC3 controller + # + gRockchipTokenSpaceGuid.PcdDwc3Size|0x400000 + + # + # Display + # + gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0x00000001 + gRockchipTokenSpaceGuid.PcdEdpId|0x00000000 #edp0 + #gRockchipTokenSpaceGuid.PcdEdpId|0x00000001 #edp1 + gRockchipTokenSpaceGuid.PcdHdmiId|0x00000000 #hdmi0 + #gRockchipTokenSpaceGuid.PcdHdmiId|0x00000001 #hdmi1 + gRockchipTokenSpaceGuid.PcdHdmiDDCI2CPinMux|0x00000000 #hdmitx_i2c_m0 + + # + # CPU Performance default values + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT) + + # + # Cooling Fan definitions + # + gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|FALSE + + # + # PCIe/SATA/USB Combo PIPE PHY support flags and default values + # + gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|FALSE + gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED) + gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED) + gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_UNCONNECTED) + + # + # PCI Express 3.0 support flags and default values + # + gRK3588TokenSpaceGuid.PcdPcie30Supported|FALSE + gRK3588TokenSpaceGuid.PcdPcie30PhyModeDefault|4 # AGGREGATION + + # + # ACPI support flags and default values + # + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault|$(ACPI_PCIE_ECAM_COMPAT_MODE_NXPMX6_SINGLE_DEV) + +[PcdsPatchableInModule] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|1500000 + +[PcdsDynamicDefault.common] + # + # Display + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 + +[PcdsDynamicHii.common.DEFAULT] + # + # CPU Performance + # + gRK3588TokenSpaceGuid.PcdCPULClusterClockPreset|L"CpuPerf_CPULClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault + gRK3588TokenSpaceGuid.PcdCPULClusterClockCustom|L"CpuPerf_CPULClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|1800 + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPreset|L"CpuPerf_CPUB01ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault + gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockCustom|L"CpuPerf_CPUB01ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400 + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPreset|L"CpuPerf_CPUB23ClusterClockPreset"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault + gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockCustom|L"CpuPerf_CPUB23ClusterClockCustom"|gRK3588DxeFormSetGuid|0x0|2400 + gRK3588TokenSpaceGuid.PcdCPULClusterVoltageMode|L"CpuPerf_CPULClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0 + gRK3588TokenSpaceGuid.PcdCPULClusterVoltageCustom|L"CpuPerf_CPULClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|950000 + gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageMode|L"CpuPerf_CPUB01ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0 + gRK3588TokenSpaceGuid.PcdCPUB01ClusterVoltageCustom|L"CpuPerf_CPUB01ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000 + gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageMode|L"CpuPerf_CPUB23ClusterVoltageMode"|gRK3588DxeFormSetGuid|0x0|0 + gRK3588TokenSpaceGuid.PcdCPUB23ClusterVoltageCustom|L"CpuPerf_CPUB23ClusterVoltageCustom"|gRK3588DxeFormSetGuid|0x0|1000000 + + # + # PCIe/SATA/USB Combo PIPE PHY + # + gRK3588TokenSpaceGuid.PcdComboPhy0Mode|L"ComboPhy0Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault + gRK3588TokenSpaceGuid.PcdComboPhy1Mode|L"ComboPhy1Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault + gRK3588TokenSpaceGuid.PcdComboPhy2Mode|L"ComboPhy2Mode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault + + # + # PCI Express 3.0 + # + gRK3588TokenSpaceGuid.PcdPcie30State|L"Pcie30State"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdPcie30Supported + gRK3588TokenSpaceGuid.PcdPcie30PhyMode|L"Pcie30PhyMode"|gRK3588DxeFormSetGuid|0x0|4 # AGGREGATION + + # + # ACPI / Device Tree + # + gRK3588TokenSpaceGuid.PcdConfigTableMode|L"ConfigTableMode"|gRK3588DxeFormSetGuid|0x0|$(CONFIG_TABLE_MODE_ACPI) + gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatMode|L"AcpiPcieEcamCompatMode"|gRK3588DxeFormSetGuid|0x0|gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault + gRK3588TokenSpaceGuid.PcdFdtSupportOverrides|L"FdtSupportOverrides"|gRK3588DxeFormSetGuid|0x0|FALSE + + # + # Cooling Fan + # + gRK3588TokenSpaceGuid.PcdCoolingFanState|L"CoolingFanState"|gRK3588DxeFormSetGuid|0x0|1 + gRK3588TokenSpaceGuid.PcdCoolingFanSpeed|L"CoolingFanSpeed"|gRK3588DxeFormSetGuid|0x0|50 + + # + # USB/DP PHY + # + gRK3588TokenSpaceGuid.PcdUsbDpPhy0Usb3State|L"UsbDpPhy0Usb3State"|gRK3588DxeFormSetGuid|0x0|$(USBDP_PHY_USB3_STATE_ENABLED) + gRK3588TokenSpaceGuid.PcdUsbDpPhy1Usb3State|L"UsbDpPhy1Usb3State"|gRK3588DxeFormSetGuid|0x0|$(USBDP_PHY_USB3_STATE_ENABLED) + +################################################################################ +# +# Components Section - list of all common EDK II Modules needed by RK3588 platforms. +# +################################################################################ +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePi/PeiUniCore.inf { + + # Full UART library + SerialPortLib|Silicon/Rockchip/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf + } + + # General platform manager + Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf + + # + # PCI Support + # +!if $(RK3588_PCIE_ENABLE) == TRUE + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + EmbeddedPkg/Drivers/NonCoherentIoMmuDxe/NonCoherentIoMmuDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf +!endif + + # + # USB/DP PHY Driver + # + Silicon/Rockchip/RK3588/Drivers/UsbDpPhyDxe/UsbDpPhyDxe.inf + + # + # GMAC Init Driver + # + Silicon/Rockchip/RK3588/Drivers/GmacPlatformDxe/GmacPlatformDxe.inf + + # + # ACPI Support + # + Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf + + # + # Device Tree Support + # + Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc new file mode 100644 index 0000000..41872f5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc @@ -0,0 +1,29 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +!include Silicon/Rockchip/RK3588/RK3588Base.dsc.inc + +################################################################################ +# +# Pcd Section - list of all common EDK II PCD Entries used by RK3588 platforms. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdProcessorName|"Rockchip RK3588" + + # + # DWC3 controller + # + gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfc400000), UINT32(0xfcd00000) } + + # + # PCI Express 3.0 support flags and default values + # + gRK3588TokenSpaceGuid.PcdPcie30Supported|TRUE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc new file mode 100644 index 0000000..3e64a03 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc @@ -0,0 +1,29 @@ +## @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +!include Silicon/Rockchip/RK3588/RK3588Base.dsc.inc + +################################################################################ +# +# Pcd Section - list of all common EDK II PCD Entries used by RK3588S platforms. +# +################################################################################ + +[PcdsFixedAtBuild.common] + # SMBIOS platform config + gRockchipTokenSpaceGuid.PcdProcessorName|"Rockchip RK3588S" + + # + # DWC3 controller + # + gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ UINT32(0xfc000000), UINT32(0xfcd00000) } + + # + # PCI Express 3.0 support flags and default values + # + gRK3588TokenSpaceGuid.PcdPcie30Supported|FALSE diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc new file mode 100644 index 0000000..3c6ebaf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/Rockchip.dsc.inc @@ -0,0 +1,795 @@ +## @file +# +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error + # + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x80000047 + + # + # Modules that can get too noisy on the DEBUG_INFO channel + # are excluded from it in the DEBUG_PRINT_INFO_MODULE_EXCLUDE + # bitmask below. + # + DEFINE DEBUG_MODULE_DXEMAIN = 0x00000010 + DEFINE DEBUG_MODULE_USBBUSDXE = 0x00000020 + DEFINE DEBUG_MODULE_PARTITIONDXE = 0x00000040 + DEFINE DEBUG_MODULE_SNPDXE = 0x00000100 + DEFINE DEBUG_MODULE_MNPDXE = 0x00000200 + + DEFINE DEBUG_PRINT_INFO_MODULE_EXCLUDE = 0x00000370 + + DEFINE DEBUG_PRINT_ERROR_LEVEL_NO_INFO = $(DEBUG_PRINT_ERROR_LEVEL) & ~0x00000040 + + # + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 + # +!if $(TARGET) == RELEASE + DEFINE DEBUG_PROPERTY_MASK = 0x00 +!else + DEFINE DEBUG_PROPERTY_MASK = 0x0f +!endif + +################################################################################ +# +# Library Class section - list of all common Library Classes needed by Rockchip platforms. +# +################################################################################ + +!include MdePkg/MdeLibs.dsc.inc + +[LibraryClasses.common] +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + + # UiApp dependencies + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + + # BDS dependencies + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + PlatformBootManagerLib|Silicon/Rockchip/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + + # USB Requirements + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + + # SCMI Mailbox Transport Layer + ArmMtlLib|Silicon/Rockchip/Library/RkMtlLib/RkMtlLib.inf + + # SMC/HVC dependencies + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf + ArmMonitorLib|ArmPkg/Library/ArmMonitorLib/ArmMonitorLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) == TRUE + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootVariableLib.inf + SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf + PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/PlatformPKProtectionLibVarPolicy.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf +!endif + + # VariableRuntimeDxe Requirements + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf + + # RTC dependencies + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + + DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf + + # + # Allow dynamic PCDs + # + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # UART libraries + # SerialPortLib|Silicon/Rockchip/Library/SerialPortLib/SerialPortLib.inf # Modified + # UartLib|Silicon/Rockchip/Library/SerialPortLib/UartLib.inf + + # Runtime reset helper + ResetSystemLib|Silicon/Rockchip/Library/ResetSystemLib/ResetSystemLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scripts accessing system memory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf + + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + + # Flattened Device Tree (FDT) access library + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + + NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverableDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf + + # UEFI Shell dependencies + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + RngLib|MdeModulePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf + ArmTrngLib|ArmPkg/Library/ArmTrngLib/ArmTrngLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf + EdkiiSystemCapsuleLib|SignedCapsulePkg/Library/EdkiiSystemCapsuleLib/EdkiiSystemCapsuleLib.inf + IniParsingLib|SignedCapsulePkg/Library/IniParsingLib/IniParsingLib.inf + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf + #PlatformFlashAccessLib|Silicon/Rockchip/Library/PlatformFlashAccessLib/PlatformFlashAccessLibDxe.inf + + ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.inf + + # + # It is not possible to prevent the ARM compiler for generic intrinsic functions. + # This library provides the instrinsic functions generate by a given compiler. + # And NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + + # RkSdmmcDxe dependencies + RkSdmmcPlatformLib|Silicon/Rockchip/Library/RkSdmmcPlatformLibNull/RkSdmmcPlatformLibNull.inf + + # DwcSdhciDxe dependencies + DwcSdhciPlatformLib|Silicon/Rockchip/Library/DwcSdhciPlatformLibNull/DwcSdhciPlatformLibNull.inf + + # + # Rockchip libraries + # + RkAtagsLib|Silicon/Rockchip/Library/RkAtagsLib/RkAtagsLib.inf + SdramLib|Silicon/Rockchip/Library/SdramLib/SdramLib.inf + CruLib|Silicon/Rockchip/Library/CruLib/CruLib.inf + SpiLib|Silicon/Rockchip/Library/SpiLib/SpiLib.inf + RK806|Silicon/Rockchip/Library/SpiLib/RK806.inf + PWMLib|Silicon/Rockchip/Library/PWMLib/PWMLib.inf + RockchipDisplayLib|Silicon/Rockchip/Library/DisplayLib/RockchipDisplayLib.inf + + BaseVariableLib|Silicon/Rockchip/Library/BaseVariableLib/BaseVariableLib.inf + +[LibraryClasses.common.SEC] + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + + ## Fixed compile error after upgrade to 14.10 + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER,LibraryClasses.common.UEFI_APPLICATION] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +!ifndef CONFIG_NO_DEBUGLIB + DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf +!endif +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf +!endif + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf +FspiLib|Silicon/Rockchip/Library/FspiLib/FspiLib.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + +[LibraryClasses.AARCH64] + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + +################################################################################################### +# BuildOptions Section - Define the module specific tool chain flags that should be used as +# the default flags for a module. These flags are appended to any +# standard flags that are defined by the build process. +################################################################################################### + +[BuildOptions] +# RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG + *_*_*_CC_FLAGS = -DDEFAULT_DARK + GCC:*_*_AARCH64_CC_FLAGS = -Wno-error=uninitialized -Wno-error=stringop-overflow -Wno-error=unused-function -Wno-error=unused-variable + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000 + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 + +################################################################################ +# +# Pcd Section - list of all common EDK II PCD Entries used by Rockchip platforms. +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE + + # If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + +[PcdsFixedAtBuild.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" + + # + # IO is mapped to memory space, so we use the same size of + # PcdPrePiCpuMemorySize + # + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|$(DEBUG_PROPERTY_MASK) + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL) + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 +!if $(SECURE_BOOT_ENABLE) == TRUE + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500 +!else + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 +!endif + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + # Set timer interrupt to be triggerred in 1ms to avoid missing + # serial terminal input characters. + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000 + gArmTokenSpaceGuid.PcdVFPEnabled|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32 + + # + # Variable store - default values + # + #gRockchipTokenSpaceGuid.PcdSpiMemoryBase|0xF9000000 + #gRockchipTokenSpaceGuid.PcdSpiMemoryMapped|TRUE + #gRockchipTokenSpaceGuid.PcdSpiVariableOffset|0x3C0000 + #gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + #gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + #gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + +!if $(SECURE_BOOT_ENABLE) == TRUE + # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 # Variable: L"Timeout" + +################################################################################ +# +# Components Section - list of all common EDK II Modules needed by Rockchip platforms. +# +# Should match the components declared in FvCompactModules and FvMainModules. +# +################################################################################ +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePi/PeiUniCore.inf + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + + +!if $(DEBUG_PRINT_INFO_MODULE_EXCLUDE) & $(DEBUG_MODULE_DXEMAIN) + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL_NO_INFO) +!endif + } + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf + SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf { + +!if $(RK_RTC8563_ENABLE) == TRUE + RealTimeClockLib|Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf +!else + RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf +!endif + } + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + SecurityPkg/RandomNumberGenerator/RngDxe/RngDxe.inf + SecurityPkg/Hash2DxeCrypto/Hash2DxeCrypto.inf + + # + # Status LED support + # +!if $(RK_STATUS_LED_ENABLE) == TRUE + Silicon/Rockchip/Drivers/StatusLedDxe/StatusLedDxe.inf +!endif + + # + # Non-volatile FVB support + # +!if $(RK_NOR_FLASH_ENABLE) == TRUE + Silicon/Rockchip/Drivers/NorFlashDxe/NorFlashDxe.inf +!endif + Silicon/Rockchip/Drivers/RkFvbDxe/RkFvbDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + # + # Multiple Console IO support + # + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Arm GIC + # + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + # + # Timer + # + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # SCMI Support + # + ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf + + # + # ACPI Support + # + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|$(DEBUG_PROPERTY_MASK) & ~0x04 + } + MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + + # + # SMBIOS Support + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + Silicon/Rockchip/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf + + # + # I2C Bus & Devices + # + MdeModulePkg/Bus/I2c/I2cDxe/I2cDxe.inf + Silicon/Rockchip/Drivers/I2c/I2cDxe/I2cDxe.inf +!if $(RK_860X_REGULATOR_ENABLE) == TRUE + Silicon/Rockchip/Drivers/I2c/Rk860xRegulatorDxe/Rk860xRegulatorDxe.inf +!endif +!if $(RK_RTC8563_ENABLE) == TRUE + Silicon/Rockchip/Drivers/Rtc8563PlatformDxe/Rtc8563PlatformDxe.inf +!endif +!if $(RK_PCA9555_ENABLE) == TRUE + Silicon/Rockchip/Drivers/Pca9555Dxe/Pca9555Dxe.inf +!endif + # Silicon/Rockchip/Drivers/I2c/I2cDemoDxe/I2cDemoDxe.inf + + # + # Display Support + # + Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf + # Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf +!if $(RK_DW_HDMI_QP_ENABLE) == TRUE + Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf +!endif + Silicon/Rockchip/Library/DisplayLib/DwDpLib.inf + Silicon/Rockchip/Library/DisplayLib/DwMipiDsi2Lib.inf + Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf + + # + # USB Support + # + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf + + # USB controllers installer + Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf + + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf { + +!if $(DEBUG_PRINT_INFO_MODULE_EXCLUDE) & $(DEBUG_MODULE_USBBUSDXE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL_NO_INFO) +!endif + } + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + MdeModulePkg/Bus/Usb/UsbMouseAbsolutePointerDxe/UsbMouseAbsolutePointerDxe.inf + + # + # PCI Support + # + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # + # SD/eMMC upper layer drivers + # +!if $(RK_SD_ENABLE) == TRUE || $(RK_EMMC_ENABLE) == TRUE + MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf + MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf +!endif + + # + # SD Support + # +!if $(RK_SD_ENABLE) == TRUE + Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.inf + Silicon/Rockchip/Drivers/RkSdmmcDxe/RkSdmmcDxe.inf +!endif + + # + # eMMC Support + # +!if $(RK_EMMC_ENABLE) == TRUE + MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf + Silicon/Rockchip/Drivers/DwcSdhciDxe/DwcSdhciDxe.inf +!endif + + # + # AHCI Support + # +!if $(RK_AHCI_ENABLE) == TRUE + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf { + +!if $(DEBUG_PRINT_INFO_MODULE_EXCLUDE) & $(DEBUG_MODULE_PARTITIONDXE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL_NO_INFO) +!endif + } + FatPkg/EnhancedFatDxe/Fat.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # RAM Disk Support + # + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf + + # + # UEFI Network Stack + # +!include NetworkPkg/Network.dsc.inc + +!if $(NETWORK_ENABLE) == TRUE + +!if $(NETWORK_SNP_ENABLE) == TRUE + NetworkPkg/SnpDxe/SnpDxe.inf { + +!if $(DEBUG_PRINT_INFO_MODULE_EXCLUDE) & $(DEBUG_MODULE_SNPDXE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL_NO_INFO) +!endif + } +!endif + + NetworkPkg/MnpDxe/MnpDxe.inf { + +!if $(DEBUG_PRINT_INFO_MODULE_EXCLUDE) & $(DEBUG_MODULE_MNPDXE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL_NO_INFO) +!endif + } + + # + # Realtek PCIe UNDI Driver + # + Drivers/Realtek/Bus/Pcie/PcieNetworking/RtkUndiDxe.inf + + # + # Realtek USB UNDI Driver + # + Drivers/Realtek/Bus/Usb/UsbNetworking/RtkUsbUndiDxe.inf + + # + # AX88772 Ethernet Driver for Apple Ethernet Adapter + # + Drivers/ASIX/Bus/Usb/UsbNetworking/Ax88772c/Ax88772c.inf +!endif + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + NULL|Silicon/Rockchip/Library/PlatformBootDescriptionLib/PlatformBootDescriptionLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + + # + # UEFI applications + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf + NULL|Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } +!ifdef $(INCLUDE_TFTP_COMMAND) + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + # I2C Demo application + # Silicon/Rockchip/Applications/I2cDemoTest/I2cDemoTest.inf + + # SPI Flash Cmd application + # Silicon/Rockchip/Applications/SpiTool/SpiFlashCmd.inf diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RockchipPkg.dec b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RockchipPkg.dec new file mode 100644 index 0000000..440d6ae --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Rockchip/RockchipPkg.dec @@ -0,0 +1,96 @@ +## @file +# +# Copyright (c) 2021-2022, Rockchip Limited. All rights reserved. +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = RockchipPkg + PACKAGE_GUID = 633b6754-2c95-11ec-b78c-f42a7dcb925d + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[Protocols] + gUniNorFlashProtocolGuid = { 0x86F305EA, 0xDFAC, 0x4A6B, { 0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA } } + gRockchipI2cDemoProtocolGuid = { 0x71954bda, 0x60d3, 0x4ef8, { 0x8e, 0x3c, 0x0e, 0x33, 0x9f, 0x3b, 0xc2, 0x2b } } + gRk860xRegulatorProtocolGuid = { 0xb9ef9018, 0x2096, 0x4bf5, { 0x94, 0xb2, 0x70, 0x32, 0xb9, 0xa9, 0xa4, 0x29 } } + gRockchipCrtcProtocolGuid = { 0xC128406A, 0x99D9, 0x11EC, { 0x99, 0x27, 0xF4, 0x2A, 0x7D, 0xCB, 0x92, 0x5D } } + gRockchipConnectorProtocolGuid = { 0x50439CB6, 0x9B85, 0x11EC, { 0x95, 0x73, 0xF4, 0x2A, 0x7D, 0xCB, 0x92, 0x5D } } + gOhciDeviceProtocolGuid = { 0x54bce5e6, 0xbaae, 0x488a, { 0x82, 0x67, 0xc0, 0x85, 0x7f, 0xb4, 0xe8, 0x05 } } + gRockchipI2cMasterProtocolGuid = { 0x7b4af789, 0x43d2, 0x44a5, { 0xa0, 0xb3, 0x3f, 0xa5, 0xde, 0xd7, 0xa1, 0x27 } } + gRockchipPlatformConfigAppliedProtocolGuid = { 0xdf0e9b10, 0xcbd6, 0x496f, { 0x83, 0xd6, 0xef, 0xbb, 0x96, 0x9c, 0xe5, 0x3d } } + gDpPhyProtocolGuid = { 0xb4bcf881, 0xc8b3, 0x46d7, { 0xaf, 0xbe, 0x5a, 0x2d, 0x94, 0x9d, 0x93, 0xc3 } } + gPca95xxProtocolGuid = { 0x7e91391b, 0xa23c, 0x4a51, { 0x9d, 0xf7, 0xf6, 0x74, 0xef, 0x1d, 0x51, 0x1b } } + gRockchipDsiPanelProtocolGuid = { 0x07a5d05c, 0x3216, 0x49fc, { 0xb4, 0x22, 0x28, 0x9d, 0x38, 0xd5, 0xdf, 0x7e } } + +[Guids] + gRockchipTokenSpaceGuid = { 0xc620b83a, 0x3175, 0x11ec, { 0x95, 0xb4, 0xf4, 0x2a, 0x7d, 0xcb, 0x92, 0x5d } } + gShellSfHiiGuid = { 0x03a67756, 0x8cde, 0x4638, { 0x82, 0x34, 0x4a, 0x0f, 0x6d, 0x58, 0x81, 0x39 } } + gShellI2cDemoHiiGuid = { 0xb2f4c714, 0x147f, 0x4ff7, { 0x82, 0x1b, 0xce, 0x7b, 0x91, 0x7f, 0x5f, 0x2f } } + gRockchipEventResetGuid = { 0x4ecbd617, 0xc2a6, 0x4d4c, { 0x80, 0x4e, 0x53, 0x38, 0x3b, 0x98, 0x7d, 0x75 } } + gRockchipEventPlatformBmAfterConsoleGuid = { 0xf1272c11, 0xb418, 0x40ca, { 0x88, 0x26, 0x11, 0x94, 0xd7, 0xb7, 0x30, 0x4a } } + +[PcdsFixedAtBuild] + gRockchipTokenSpaceGuid.PcdProcessorName|"Unknown"|VOID*|0x00000001 + gRockchipTokenSpaceGuid.PcdPlatformName|"Unknown"|VOID*|0x00000002 + gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Unknown"|VOID*|0x00000003 + gRockchipTokenSpaceGuid.PcdBoardName|"Unknown"|VOID*|0x00000004 + gRockchipTokenSpaceGuid.PcdBoardVendorName|"Unknown"|VOID*|0x00000005 + gRockchipTokenSpaceGuid.PcdProductUrl|"Unknown"|VOID*|0x00000006 + gRockchipTokenSpaceGuid.PcdMemoryVendorName|"Unknown"|VOID*|0x00000007 + gRockchipTokenSpaceGuid.PcdFamilyName|"Unknown"|VOID*|0x00000008 + gRockchipTokenSpaceGuid.PcdDeviceTreeName|"Unknown"|VOID*|0x00000009 + + gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x0 }|VOID*|0x02000001 + gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }|VOID*|0x02000002 + gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ 0x0 }|VOID*|0x02000003 + gRockchipTokenSpaceGuid.PcdI2cClockFrequency|0|UINT32|0x02000004 + gRockchipTokenSpaceGuid.PcdI2cBaudRate|0|UINT32|0x02000005 + gRockchipTokenSpaceGuid.PcdI2cDemoAddresses|{ 0x0 }|VOID*|0x02000007 + gRockchipTokenSpaceGuid.PcdI2cDemoBuses|{ 0x0 }|VOID*|0x02000008 + gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x0 }|VOID*|0x02000009 + gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0 }|VOID*|0x0200000A + gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ 0x0 }|VOID*|0x0200000B + gRockchipTokenSpaceGuid.PcdRk860xRegulatorMinVoltages|{ 0x0 }|VOID*|0x0200000C + gRockchipTokenSpaceGuid.PcdRk860xRegulatorMaxVoltages|{ 0x0 }|VOID*|0x0200000D + gRockchipTokenSpaceGuid.PcdRtc8563Bus|0|UINT8|0x0200000E + + gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress|0x0|UINT32|0x40000030 + gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken|FALSE|BOOLEAN|0x40000031 + + gRockchipTokenSpaceGuid.PcdDwcSdhciBaseAddress|0x0|UINT32|0x40000035 + gRockchipTokenSpaceGuid.PcdDwcSdhciForceHighSpeed|FALSE|BOOLEAN|0x40000036 + gRockchipTokenSpaceGuid.PcdDwcSdhciDisableHs400|FALSE|BOOLEAN|0x40000037 + + gRockchipTokenSpaceGuid.SpiRK806BaseAddr|0|UINT32|0x21200002 + + gRockchipTokenSpaceGuid.PcdEhciBaseAddress|0|UINT32|0x50000060 + gRockchipTokenSpaceGuid.PcdNumEhciController|0|UINT32|0x50000061 + gRockchipTokenSpaceGuid.PcdEhciSize|0|UINT32|0x50000062 + gRockchipTokenSpaceGuid.PcdOhciSize|0|UINT32|0x50000063 + + gRockchipTokenSpaceGuid.PcdDwc3BaseAddresses|{ 0x0 }|VOID*|0x50000069 + gRockchipTokenSpaceGuid.PcdDwc3Size|0|UINT32|0x50000071 + + gRockchipTokenSpaceGuid.FspiBaseAddr|0|UINT64|0x21200003 + gRockchipTokenSpaceGuid.CruBaseAddr|0|UINT64|0x21200008 + + gRockchipTokenSpaceGuid.PcdNvStoragePreferSpiFlash|FALSE|BOOLEAN|0x21200009 + + gRockchipTokenSpaceGuid.PcdLcdPixelFormat|0|UINT32|0x32000001 + gRockchipTokenSpaceGuid.PcdEdpId|0|UINT32|0x32000003 + gRockchipTokenSpaceGuid.PcdHdmiId|0|UINT32|0x32000004 + gRockchipTokenSpaceGuid.PcdHdmiDDCI2CPinMux|0|UINT32|0x32000005 + + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase|0x0010f000|UINT64|0x00001000 + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize|0x100|UINT32|0x00001001 + gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSmcId|0x82000010|UINT32|0x00010002 + + gRockchipTokenSpaceGuid.PcdPca9555Address|0|UINT8|0x03000001 + gRockchipTokenSpaceGuid.PcdPca9555Bus|0|UINT8|0x03000002 diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/DesignWarePkg.dec b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/DesignWarePkg.dec new file mode 100644 index 0000000..9354ebf --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/DesignWarePkg.dec @@ -0,0 +1,25 @@ +#/** @file +# Framework Module Development Environment Industry Standards +# +# This Package provides headers and libraries that conform to EFI/PI Industry standards. +# Copyright (c) 2007-2021, Intel Corporation. All rights reserved. +# Copyright (c) 2012-2014, ARM Ltd. All rights reserved. +# Copyright (c) 2018, Linaro. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +#**/ + +[Defines] + DEC_SPECIFICATION = 0x00010019 + PACKAGE_NAME = DesignWarePkg + PACKAGE_GUID = e73097ce-1fe2-41a6-a930-3136bc6d23ef + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[Guids.common] + gDwMmcHcNonDiscoverableDeviceGuid = { 0x971ab768, 0xd733, 0x41be, { 0xac, 0x9e, 0x82, 0x36, 0x10, 0x94, 0xc9, 0x3c }} + +[Protocols.common] + gPlatformDwMmcProtocolGuid = { 0x1d6dfde5, 0x76a7, 0x4404, { 0x85, 0x74, 0x7a, 0xdf, 0x1a, 0x8a, 0xa2, 0x0d }} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/ComponentName.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/ComponentName.c new file mode 100644 index 0000000..7076963 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/ComponentName.c @@ -0,0 +1,207 @@ +/** @file + UEFI Component Name(2) protocol implementation for Designware SD/MMC host + controller driver. + + Copyright (c) 2015-2021, Intel Corporation. All rights reserved. + Copyright (c) 2018, Linaro Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "DwMmcHcDxe.h" + +// +// EFI Component Name Protocol +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL gDwMmcHcComponentName = { + DwMmcHcComponentNameGetDriverName, + DwMmcHcComponentNameGetControllerName, + "eng" +}; + +// +// EFI Component Name 2 Protocol +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL gDwMmcHcComponentName2 = { + (EFI_COMPONENT_NAME2_GET_DRIVER_NAME) DwMmcHcComponentNameGetDriverName, + (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME) DwMmcHcComponentNameGetControllerName, + "en" +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mDwMmcHcDriverNameTable[] = { + { "eng;en", L"Designware Sd/Mmc Host Controller Driver" }, + { NULL , NULL } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mDwMmcHcControllerNameTable[] = { + { "eng;en", L"Designware Sd/Mmc Host Controller" }, + { NULL , NULL } +}; + +/** + Retrieves a Unicode string that is the user readable name of the driver. + + This function retrieves the user readable name of a driver in the form of a + Unicode string. If the driver specified by This has a user readable name in + the language specified by Language, then a pointer to the driver name is + returned in DriverName, and EFI_SUCCESS is returned. If the driver specified + by This does not support the language specified by Language, + then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified + in RFC 4646 or ISO 639-2 language code format. + + @param DriverName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + driver specified by This in the language + specified by Language. + + @retval EFI_SUCCESS The Unicode string for the Driver specified by + This and the language specified by Language was + returned in DriverName. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER DriverName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcComponentNameGetDriverName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ) +{ + return LookupUnicodeString2 ( + Language, + This->SupportedLanguages, + mDwMmcHcDriverNameTable, + DriverName, + (BOOLEAN)(This == &gDwMmcHcComponentName) + ); +} + +/** + Retrieves a Unicode string that is the user readable name of the controller + that is being managed by a driver. + + This function retrieves the user readable name of the controller specified by + ControllerHandle and ChildHandle in the form of a Unicode string. If the + driver specified by This has a user readable name in the language specified by + Language, then a pointer to the controller name is returned in ControllerName, + and EFI_SUCCESS is returned. If the driver specified by This is not currently + managing the controller specified by ControllerHandle and ChildHandle, + then EFI_UNSUPPORTED is returned. If the driver specified by This does not + support the language specified by Language, then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param ControllerHandle[in] The handle of a controller that the driver + specified by This is managing. This handle + specifies the controller whose name is to be + returned. + + @param ChildHandle[in] The handle of the child controller to retrieve + the name of. This is an optional parameter that + may be NULL. It will be NULL for device + drivers. It will also be NULL for a bus drivers + that wish to retrieve the name of the bus + controller. It will not be NULL for a bus + driver that wishes to retrieve the name of a + child controller. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified in + RFC 4646 or ISO 639-2 language code format. + + @param ControllerName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + controller specified by ControllerHandle and + ChildHandle in the language specified by + Language from the point of view of the driver + specified by This. + + @retval EFI_SUCCESS The Unicode string for the user readable name in + the language specified by Language for the + driver specified by This was returned in + DriverName. + + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid + EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER ControllerName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This is not currently + managing the controller specified by + ControllerHandle and ChildHandle. + + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcComponentNameGetControllerName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle, OPTIONAL + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ) +{ + EFI_STATUS Status; + + if (Language == NULL || ControllerName == NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // This is a device driver, so ChildHandle must be NULL. + // + if (ChildHandle != NULL) { + return EFI_UNSUPPORTED; + } + + // + // Make sure this driver is currently managing ControllerHandle + // + Status = EfiTestManagedDevice ( + ControllerHandle, + gDwMmcHcDriverBinding.DriverBindingHandle, + &gEfiPciIoProtocolGuid + ); + if (EFI_ERROR (Status)) { + return Status; + } + + return LookupUnicodeString2 ( + Language, + This->SupportedLanguages, + mDwMmcHcControllerNameTable, + ControllerName, + (BOOLEAN)(This == &gDwMmcHcComponentName) + ); +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.c new file mode 100644 index 0000000..ff6d75a --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.c @@ -0,0 +1,1294 @@ +/** @file + This driver is used to manage Designware SD/MMC host controller. + + It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. + + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved. + Copyright (C) 2016 Marvell International Ltd. All rigths reserved. + Copyright (C) 2018, Linaro Ltd. All rigths reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "DwMmcHcDxe.h" + +// +// Driver Global Variables +// +EFI_DRIVER_BINDING_PROTOCOL gDwMmcHcDriverBinding = { + DwMmcHcDriverBindingSupported, + DwMmcHcDriverBindingStart, + DwMmcHcDriverBindingStop, + 0x10, + NULL, + NULL +}; + +// +// Template for Designware SD/MMC host controller private data. +// +DW_MMC_HC_PRIVATE_DATA gDwMmcHcTemplate = { + DW_MMC_HC_PRIVATE_SIGNATURE, // Signature + NULL, // ControllerHandle + 0x0, // Mmio base address + { // PassThru + sizeof (UINT32), + DwMmcPassThruPassThru, + DwMmcPassThruGetNextSlot, + DwMmcPassThruBuildDevicePath, + DwMmcPassThruGetSlotNumber, + DwMmcPassThruResetDevice + }, + NULL, // PlatformDwMmc + 0, // PreviousSlot + NULL, // TimerEvent + NULL, // ConnectEvent + // Queue + INITIALIZE_LIST_HEAD_VARIABLE (gDwMmcHcTemplate.Queue), + { // Slot + {0, UnknownSlot, 0, 0, 0} + }, + { // Capability + {0} + }, + { // MaxCurrent + 0 + }, + 0 // ControllerVersion +}; + +SD_DEVICE_PATH mSdDpTemplate = { + { + MESSAGING_DEVICE_PATH, + MSG_SD_DP, + { + (UINT8) (sizeof (SD_DEVICE_PATH)), + (UINT8) ((sizeof (SD_DEVICE_PATH)) >> 8) + } + }, + 0 +}; + +EMMC_DEVICE_PATH mEmmcDpTemplate = { + { + MESSAGING_DEVICE_PATH, + MSG_EMMC_DP, + { + (UINT8) (sizeof (EMMC_DEVICE_PATH)), + (UINT8) ((sizeof (EMMC_DEVICE_PATH)) >> 8) + } + }, + 0 +}; + +// +// Prioritized function list to detect card type. +// User could add other card detection logic here. +// +DWMMC_CARD_TYPE_DETECT_ROUTINE mCardTypeDetectRoutineTable[] = { + EmmcIdentification, + SdCardIdentification, + NULL +}; + +/** + The entry point for SD host controller driver, used to install this driver on the ImageHandle. + + @param[in] ImageHandle The firmware allocated handle for this driver image. + @param[in] SystemTable Pointer to the EFI system table. + + @retval EFI_SUCCESS Driver loaded. + @retval other Driver not loaded. + +**/ +EFI_STATUS +EFIAPI +InitializeDwMmcHcDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = EfiLibInstallDriverBindingComponentName2 ( + ImageHandle, + SystemTable, + &gDwMmcHcDriverBinding, + ImageHandle, + &gDwMmcHcComponentName, + &gDwMmcHcComponentName2 + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Call back function when the timer event is signaled. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the + Event. + +**/ +VOID +EFIAPI +ProcessAsyncTaskList ( + IN EFI_EVENT Event, + IN VOID* Context + ) +{ + DW_MMC_HC_PRIVATE_DATA *Private; + LIST_ENTRY *Link; + DW_MMC_HC_TRB *Trb; + EFI_STATUS Status; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + BOOLEAN InfiniteWait; + EFI_EVENT TrbEvent; + + Private = (DW_MMC_HC_PRIVATE_DATA *)Context; + + // + // Check if the first entry in the async I/O queue is done or not. + // + Status = EFI_SUCCESS; + Trb = NULL; + Link = GetFirstNode (&Private->Queue); + if (!IsNull (&Private->Queue, Link)) { + Trb = DW_MMC_HC_TRB_FROM_THIS (Link); + if (!Private->Slot[Trb->Slot].MediaPresent) { + Status = EFI_NO_MEDIA; + goto Done; + } + if (!Trb->Started) { + // + // Check whether the cmd/data line is ready for transfer. + // + Status = DwMmcCheckTrbEnv (Private, Trb); + if (!EFI_ERROR (Status)) { + Trb->Started = TRUE; + Status = DwMmcExecTrb (Private, Trb); + if (EFI_ERROR (Status)) { + goto Done; + } + } else { + goto Done; + } + } + Status = DwMmcCheckTrbResult (Private, Trb); + } + +Done: + if ((Trb != NULL) && (Status == EFI_NOT_READY)) { + Packet = Trb->Packet; + if (Packet->Timeout == 0) { + InfiniteWait = TRUE; + } else { + InfiniteWait = FALSE; + } + if ((!InfiniteWait) && (Trb->Timeout-- == 0)) { + RemoveEntryList (Link); + Trb->Packet->TransactionStatus = EFI_TIMEOUT; + TrbEvent = Trb->Event; + DwMmcFreeTrb (Trb); + DEBUG (( + DEBUG_VERBOSE, + "ProcessAsyncTaskList(): Signal Event %p EFI_TIMEOUT\n", + TrbEvent + )); + gBS->SignalEvent (TrbEvent); + return; + } + } + if ((Trb != NULL) && (Status != EFI_NOT_READY)) { + RemoveEntryList (Link); + Trb->Packet->TransactionStatus = Status; + TrbEvent = Trb->Event; + DwMmcFreeTrb (Trb); + DEBUG (( + DEBUG_VERBOSE, + "ProcessAsyncTaskList(): Signal Event %p with %r\n", + TrbEvent, + Status + )); + gBS->SignalEvent (TrbEvent); + } + return; +} + +/** + Sd removable device enumeration callback function when the timer event is signaled. + + @param[in] Event The Event this notify function registered to. + @param[in] Context Pointer to the context data registered to the + Event. + +**/ +VOID +EFIAPI +DwMmcHcEnumerateDevice ( + IN EFI_EVENT Event, + IN VOID* Context + ) +{ + DW_MMC_HC_PRIVATE_DATA *Private; + EFI_STATUS Status; + BOOLEAN MediaPresent; + BOOLEAN MediaChanged; + UINT32 RoutineNum; + DWMMC_CARD_TYPE_DETECT_ROUTINE *Routine; + UINTN Index; + LIST_ENTRY *Link; + LIST_ENTRY *NextLink; + DW_MMC_HC_TRB *Trb; + EFI_TPL OldTpl; + + Private = (DW_MMC_HC_PRIVATE_DATA *)Context; + + if ((Private->Slot[0].Enable) && + (Private->Slot[0].SlotType == RemovableSlot)) { + Status = DwMmcHcCardDetect ( + Private->DevBase, + Private->ControllerHandle, + 0, + &MediaPresent + ); + + MediaChanged = Private->Slot[0].MediaPresent != MediaPresent; + + if (MediaChanged && !MediaPresent) { + DEBUG (( + DEBUG_INFO, + "DwMmcHcEnumerateDevice: device disconnected at %p\n", + Private->DevBase + )); + Private->Slot[0].MediaPresent = FALSE; + // + // Signal all async task events at the slot with EFI_NO_MEDIA status. + // + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + for (Link = GetFirstNode (&Private->Queue); + !IsNull (&Private->Queue, Link); + Link = NextLink) { + NextLink = GetNextNode (&Private->Queue, Link); + Trb = DW_MMC_HC_TRB_FROM_THIS (Link); + if (Trb->Slot == 0) { + RemoveEntryList (Link); + Trb->Packet->TransactionStatus = EFI_NO_MEDIA; + gBS->SignalEvent (Trb->Event); + DwMmcFreeTrb (Trb); + } + } + gBS->RestoreTPL (OldTpl); + // + // Notify the upper layer the connect state change through + // ReinstallProtocolInterface. + // + gBS->ReinstallProtocolInterface ( + Private->ControllerHandle, + &gEfiSdMmcPassThruProtocolGuid, + &Private->PassThru, + &Private->PassThru + ); + } + if (MediaChanged && MediaPresent) { + DEBUG (( + DEBUG_INFO, + "DwMmcHcEnumerateDevice: device connected at %p\n", + Private->DevBase + )); + // + // Initialize slot and start identification process for the new + // attached device + // + Status = DwMmcHcInitHost (Private->DevBase, Private->Capability[0]); + if (EFI_ERROR (Status)) { + return; + } + // + // Reset the specified slot of the SD/MMC Pci Host Controller + // + Status = DwMmcHcReset (Private->DevBase, Private->Capability[0]); + if (EFI_ERROR (Status)) { + return; + } + + Private->Slot[0].MediaPresent = TRUE; + RoutineNum = sizeof (mCardTypeDetectRoutineTable) / + sizeof (DWMMC_CARD_TYPE_DETECT_ROUTINE); + for (Index = 0; Index < RoutineNum; Index++) { + Routine = &mCardTypeDetectRoutineTable[Index]; + if (*Routine != NULL) { + Status = (*Routine) (Private); + if (!EFI_ERROR (Status)) { + break; + } + } + } + // + // This card doesn't get initialized correctly. + // + if (Index == RoutineNum) { + return; + } + + // + // Notify the upper layer the connect state change through + // ReinstallProtocolInterface. + // + gBS->ReinstallProtocolInterface ( + Private->ControllerHandle, + &gEfiSdMmcPassThruProtocolGuid, + &Private->PassThru, + &Private->PassThru + ); + } + } + + return; +} + +/** + Reset the specified SD/MMC host controller and enable all interrupts. + + @param[in] DevBase The Mmio Device Base Address. + + @retval EFI_SUCCESS The software reset executes successfully. + @retval Others The software reset fails. + +**/ +EFI_STATUS +DwMmcHcReset ( + IN UINTN DevBase, + IN DW_MMC_HC_SLOT_CAP Capability + ) +{ + EFI_STATUS Status; + UINT32 BlkSize; + + // + // Enable all interrupt after reset all. + // + Status = DwMmcHcEnableInterrupt (DevBase); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "DwMmcHcReset: enable interrupts fail: %r\n", Status)); + return Status; + } + Status = DwMmcHcInitTimeoutCtrl (DevBase); + if (EFI_ERROR (Status)) { + return Status; + } + + BlkSize = DW_MMC_BLOCK_SIZE; + MmioWrite32 (DevBase + DW_MMC_BLKSIZ, BlkSize); + + Status = DwMmcHcInitClockFreq (DevBase, Capability); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = DwMmcHcSetBusWidth (DevBase, FALSE, 1); + + return Status; +} + +/** + Tests to see if this driver supports a given controller. If a child device + is provided, it further tests to see if this driver supports creating a + handle for the specified child device. + + This function checks to see if the driver specified by This supports the + device specified by ControllerHandle. Drivers will typically use the device + path attached to ControllerHandle and/or the services from the bus I/O + abstraction attached to ControllerHandle to determine if the driver supports + ControllerHandle. This function may be called many times during platform + initialization. In order to reduce boot times, the tests performed by this + function must be very small, and take as little time as possible to execute. + This function must not change the state of any hardware devices, and this + function must be aware that the device specified by ControllerHandle may + already be managed by the same driver or a different driver. This function + must match its calls to AllocatePages() with FreePages(), AllocatePool() with + FreePool(), and OpenProtocol() with CloseProtocol(). Since ControllerHandle + may have been previously started by the same driver, if a protocol is already + in the opened state, then it must not be closed with CloseProtocol(). This is + required to guarantee the state of ControllerHandle is not modified by this + function. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL + instance. + @param[in] ControllerHandle The handle of the controller to test. This + handle must support a protocol interface that + supplies an I/O abstraction to the driver. + @param[in] RemainingDevicePath A pointer to the remaining portion of a + device path. This parameter is ignored by + device drivers, and is optional for bus + drivers. For bus drivers, if this parameter + is not NULL, then the bus driver must deter- + mine if the bus controller specified by + ControllerHandle and the child controller + specified by RemainingDevicePath are both + supported by this bus driver. + + @retval EFI_SUCCESS The device specified by ControllerHandle and + RemainingDevicePath is supported by the + driver specified by This. + @retval EFI_ALREADY_STARTED The device specified by ControllerHandle and + RemainingDevicePath is already being managed + by the driver specified by This. + @retval EFI_ACCESS_DENIED The device specified by ControllerHandle and + RemainingDevicePath is already being managed + by a different driver or an application that + requires exclusive access. + Currently not implemented. + @retval EFI_UNSUPPORTED The device specified by ControllerHandle and + RemainingDevicePath is not supported by the + driver specified by This. +**/ +EFI_STATUS +EFIAPI +DwMmcHcDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath; + NON_DISCOVERABLE_DEVICE *Dev; + PLATFORM_DW_MMC_PROTOCOL *PlatformDwMmc; + + ParentDevicePath = NULL; + + Status = gBS->LocateProtocol ( + &gPlatformDwMmcProtocolGuid, + NULL, + (VOID **) &PlatformDwMmc + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = gBS->OpenProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + (VOID *) &ParentDevicePath, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + // + // EFI_ALREADY_STARTED is also an error. + // + return Status; + } + // + // Close the protocol because we don't use it here. + // + gBS->CloseProtocol ( + Controller, + &gEfiDevicePathProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + // + // Now test the EdkiiNonDiscoverableDeviceProtocol. + // + Status = gBS->OpenProtocol ( + Controller, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + (VOID **) &Dev, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if (CompareGuid (Dev->Type, &gDwMmcHcNonDiscoverableDeviceGuid)) { + Status = EFI_SUCCESS; + } else { + Status = EFI_UNSUPPORTED; + } + + gBS->CloseProtocol ( + Controller, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + This->DriverBindingHandle, + Controller + ); + return Status; +} + +/** + Starts a device controller or a bus controller. + + The Start() function is designed to be invoked from the EFI boot service + ConnectController(). + As a result, much of the error checking on the parameters to Start() has + been moved into this + common boot service. It is legal to call Start() from other locations, + but the following calling restrictions must be followed or the system + behavior will not be deterministic. + 1. ControllerHandle must be a valid EFI_HANDLE. + 2. If RemainingDevicePath is not NULL, then it must be a pointer to a + naturally aligned EFI_DEVICE_PATH_PROTOCOL. + 3. Prior to calling Start(), the Supported() function for the driver + specified by This must have been called with the same calling parameters, + and Supported() must have returned EFI_SUCCESS. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL + instance. + @param[in] ControllerHandle The handle of the controller to start. This + handle must support a protocol interface + that supplies an I/O abstraction to the + driver. + @param[in] RemainingDevicePath A pointer to the remaining portion of a + device path. This parameter is ignored by + device drivers, and is optional for bus + drivers. + For a bus driver, if this parameter is NULL, + then handles for all the children of + Controller are created by this driver. + If this parameter is not NULL and the first + Device Path Node is not the End of Device + Path Node, then only the handle for the + child device specified by the first Device + Path Node of RemainingDevicePath is created + by this driver. + If the first Device Path Node of + RemainingDevicePath is the End of Device Path + Node, no child handle is created by this + driver. + + @retval EFI_SUCCESS The device was started. + @retval EFI_DEVICE_ERROR The device could not be started due to a + device error. Currently not implemented. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a + lack of resources. + @retval Others The driver failded to start the device. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ) +{ + EFI_STATUS Status; + DW_MMC_HC_PRIVATE_DATA *Private; + + NON_DISCOVERABLE_DEVICE *Dev; + + BOOLEAN MediaPresent; + DWMMC_CARD_TYPE_DETECT_ROUTINE *Routine; + UINT8 Index; + UINT32 RoutineNum; + PLATFORM_DW_MMC_PROTOCOL *PlatformDwMmc; + + Status = gBS->LocateProtocol ( + &gPlatformDwMmcProtocolGuid, + NULL, + (VOID **) &PlatformDwMmc + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "err %d", __LINE__)); + return Status; + } + + Status = gBS->OpenProtocol ( + Controller, + &gEdkiiNonDiscoverableDeviceProtocolGuid, + (VOID **) &Dev, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_BY_DRIVER + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "err %d", __LINE__)); + return Status; + } + + Private = AllocateCopyPool (sizeof (DW_MMC_HC_PRIVATE_DATA), &gDwMmcHcTemplate); + if (Private == NULL) { + DEBUG ((DEBUG_ERROR, "err %d", __LINE__)); + Status = EFI_OUT_OF_RESOURCES; + goto Done; + } + + Private->ControllerHandle = Controller; + Private->DevBase = Dev->Resources[0].AddrRangeMin; + Private->PlatformDwMmc = PlatformDwMmc; + InitializeListHead (&Private->Queue); + + Status = Private->PlatformDwMmc->GetCapability (Controller, 0, &Private->Capability[0]); + + if (EFI_ERROR (Status)) { + goto Done; + } + + if (Private->Capability[0].BaseClkFreq == 0) { + goto Done; + } + + DumpCapabilityReg (0, &Private->Capability[0]); + + Status = DwMmcHcCardDetect (Private->DevBase, Controller, 0, &Private->Slot[0].MediaPresent); + + // + // Initialize slot and start identification process for the new attached device + // + Status = DwMmcHcInitHost (Private->DevBase, Private->Capability[0]); + if (EFI_ERROR (Status)) { + goto Done; + } + + // + // Reset HC + // + Status = DwMmcHcReset (Private->DevBase, Private->Capability[0]); + if (EFI_ERROR (Status)) { + goto Done; + } + + Private->Slot[0].SlotType = Private->Capability[0].SlotType; + Private->Slot[0].CardType = Private->Capability[0].CardType; + Private->Slot[0].Enable = TRUE; + + RoutineNum = sizeof (mCardTypeDetectRoutineTable) / sizeof (DWMMC_CARD_TYPE_DETECT_ROUTINE); + for (Index = 0; Index < RoutineNum; Index++) { + Routine = &mCardTypeDetectRoutineTable[Index]; + if (*Routine != NULL) { + Status = (*Routine) (Private); + if (!EFI_ERROR (Status)) { + break; + } + } + } + + // + // Start the asynchronous I/O monitor + // + Status = gBS->CreateEvent ( + EVT_TIMER | EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + ProcessAsyncTaskList, + Private, + &Private->TimerEvent + ); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = gBS->SetTimer (Private->TimerEvent, TimerPeriodic, DW_MMC_HC_ASYNC_TIMER); + if (EFI_ERROR (Status)) { + goto Done; + } + + // + // Start the Sd removable device connection enumeration + // + Status = gBS->CreateEvent ( + EVT_TIMER | EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + DwMmcHcEnumerateDevice, + Private, + &Private->ConnectEvent + ); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = gBS->SetTimer (Private->ConnectEvent, TimerPeriodic, DW_MMC_HC_ENUM_TIMER); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Controller, + &gEfiSdMmcPassThruProtocolGuid, + &(Private->PassThru), + NULL + ); + + DEBUG ((DEBUG_INFO, "DwMmcHcDriverBindingStart: %r End on %x\n", Status, Controller)); + +Done: + if (EFI_ERROR (Status)) { + if ((Private != NULL) && (Private->TimerEvent != NULL)) { + gBS->CloseEvent (Private->TimerEvent); + } + + if ((Private != NULL) && (Private->ConnectEvent != NULL)) { + gBS->CloseEvent (Private->ConnectEvent); + } + + if (Private != NULL) { + FreePool (Private); + } + } + + return Status; +} + +/** + Stops a device controller or a bus controller. + + The Stop() function is designed to be invoked from the EFI boot service + DisconnectController(). + As a result, much of the error checking on the parameters to Stop() has been + moved into this common boot service. It is legal to call Stop() from other + locations, but the following calling restrictions must be followed or the + system behavior will not be deterministic. + 1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous + call to this same driver's Start() function. + 2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid + EFI_HANDLE. In addition, all of these handles must have been created in + this driver's Start() function, and the Start() function must have called + OpenProtocol() on ControllerHandle with an Attribute of + EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL + instance. + @param[in] ControllerHandle A handle to the device being stopped. The handle + must support a bus specific I/O protocol for the + driver to use to stop the device. + @param[in] NumberOfChildren The number of child device handles in + ChildHandleBuffer. + @param[in] ChildHandleBuffer An array of child handles to be freed. May be + NULL if NumberOfChildren is 0. + + @retval EFI_SUCCESS The device was stopped. + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device + error. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ) +{ + EFI_STATUS Status; + EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru; + DW_MMC_HC_PRIVATE_DATA *Private; + LIST_ENTRY *Link; + LIST_ENTRY *NextLink; + DW_MMC_HC_TRB *Trb; + + DEBUG ((DEBUG_INFO, "DwMmcHcDriverBindingStop: Start\n")); + + Status = gBS->OpenProtocol ( + Controller, + &gEfiSdMmcPassThruProtocolGuid, + (VOID**) &PassThru, + This->DriverBindingHandle, + Controller, + EFI_OPEN_PROTOCOL_GET_PROTOCOL + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (PassThru); + // + // Close Non-Blocking timer and free Task list. + // + if (Private->TimerEvent != NULL) { + gBS->CloseEvent (Private->TimerEvent); + Private->TimerEvent = NULL; + } + if (Private->ConnectEvent != NULL) { + gBS->CloseEvent (Private->ConnectEvent); + Private->ConnectEvent = NULL; + } + // + // As the timer is closed, there is no needs to use TPL lock to + // protect the critical region "queue". + // + for (Link = GetFirstNode (&Private->Queue); + !IsNull (&Private->Queue, Link); + Link = NextLink) { + NextLink = GetNextNode (&Private->Queue, Link); + RemoveEntryList (Link); + Trb = DW_MMC_HC_TRB_FROM_THIS (Link); + Trb->Packet->TransactionStatus = EFI_ABORTED; + gBS->SignalEvent (Trb->Event); + DwMmcFreeTrb (Trb); + } + + // + // Uninstall Block I/O protocol from the device handle + // + Status = gBS->UninstallProtocolInterface ( + Controller, + &gEfiSdMmcPassThruProtocolGuid, + &(Private->PassThru) + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + gBS->CloseProtocol ( + Controller, + &gEfiPciIoProtocolGuid, + This->DriverBindingHandle, + Controller + ); + + FreePool (Private); + + DEBUG ((DEBUG_INFO, "DwMmcHcDriverBindingStop: End with %r\n", Status)); + + return Status; +} + +/** + Sends SD command to an SD card that is attached to the SD controller. + + The PassThru() function sends the SD command specified by Packet to the SD + card specified by Slot. + + If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned. + + If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is + returned. + + If Slot is not in a valid range for the SD controller, then + EFI_INVALID_PARAMETER is returned. + + If Packet defines a data command but both InDataBuffer and OutDataBuffer are + NULL, EFI_INVALID_PARAMETER is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Slot The slot number of the SD card to send the + command to. + @param[in,out] Packet A pointer to the SD command data structure. + @param[in] Event If Event is NULL, blocking I/O is performed. If + Event is not NULL, then nonblocking I/O is + performed, and Event will be signaled when the + Packet completes. + + @retval EFI_SUCCESS The SD Command Packet was sent by the host. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send + the SD command Packet. + @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is + invalid. + @retval EFI_INVALID_PARAMETER Packet defines a data command but both + InDataBuffer and OutDataBuffer are NULL. + @retval EFI_NO_MEDIA SD Device not present in the Slot. + @retval EFI_UNSUPPORTED The command described by the SD Command Packet + is not supported by the host controller. + @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength + exceeds the limit supported by SD card + ( i.e. if the number of bytes exceed the Last + LBA). + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruPassThru ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ) +{ + EFI_STATUS Status; + DW_MMC_HC_PRIVATE_DATA *Private; + DW_MMC_HC_TRB *Trb; + EFI_TPL OldTpl; + + if ((This == NULL) || (Packet == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->SdMmcCmdBlk == NULL) || (Packet->SdMmcStatusBlk == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) { + return EFI_INVALID_PARAMETER; + } + + if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) { + return EFI_INVALID_PARAMETER; + } + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (This); + + if (!Private->Slot[Slot].Enable) { + return EFI_INVALID_PARAMETER; + } + + if (!Private->Slot[Slot].MediaPresent) { + return EFI_NO_MEDIA; + } + + Trb = DwMmcCreateTrb (Private, Slot, Packet, Event); + if (Trb == NULL) { + return EFI_OUT_OF_RESOURCES; + } + // + // Immediately return for async I/O. + // + if (Event != NULL) { + return EFI_SUCCESS; + } + + // + // Wait async I/O list is empty before execute sync I/O operation. + // + while (TRUE) { + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + if (IsListEmpty (&Private->Queue)) { + gBS->RestoreTPL (OldTpl); + break; + } + gBS->RestoreTPL (OldTpl); + } + + Status = DwMmcWaitTrbEnv (Private, Trb); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = DwMmcExecTrb (Private, Trb); + if (EFI_ERROR (Status)) { + goto Done; + } + + Status = DwMmcWaitTrbResult (Private, Trb); + if (EFI_ERROR (Status)) { + goto Done; + } + +Done: + if (Trb != NULL) { + DwMmcFreeTrb (Trb); + } + + return Status; +} + +/** + Used to retrieve next slot numbers supported by the SD controller. The + function returns information about all available slots (populated or + not-populated). + + The GetNextSlot() function retrieves the next slot number on an SD controller. + If on input Slot is 0xFF, then the slot number of the first slot on the SD + controller is returned. + + If Slot is a slot number that was returned on a previous call to + GetNextSlot(), then the slot number of the next slot on the SD controller is + returned. + + If Slot is not 0xFF and Slot was not returned on a previous call to + GetNextSlot(), EFI_INVALID_PARAMETER is returned. + + If Slot is the slot number of the last slot on the SD controller, then + EFI_NOT_FOUND is returned. + + @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL + instance. + @param[in,out] Slot On input, a pointer to a slot number on the SD + controller. + On output, a pointer to the next slot number on + the SD controller. + An input value of 0xFF retrieves the first slot + number on the SD controller. + + @retval EFI_SUCCESS The next slot number on the SD controller was + returned in Slot. + @retval EFI_NOT_FOUND There are no more slots on this SD controller. + @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a + previous call to GetNextSlot(). + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruGetNextSlot ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN OUT UINT8 *Slot + ) +{ + DW_MMC_HC_PRIVATE_DATA *Private; + + if ((This == NULL) || (Slot == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (This); + + if (*Slot == 0xFF) { + if (Private->Slot[0].Enable) { + *Slot = 0; + Private->PreviousSlot = 0; + return EFI_SUCCESS; + } + return EFI_NOT_FOUND; + } else if (*Slot == Private->PreviousSlot) { + return EFI_NOT_FOUND; + } else { + return EFI_INVALID_PARAMETER; + } +} + +/** + Used to allocate and build a device path node for an SD card on the SD + controller. + + The BuildDevicePath() function allocates and builds a single device node + for the SD card specified by Slot. + + If the SD card specified by Slot is not present on the SD controller, then + EFI_NOT_FOUND is returned. + + If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. + + If there are not enough resources to allocate the device path node, then + EFI_OUT_OF_RESOURCES is returned. + + Otherwise, DevicePath is allocated with the boot service AllocatePool(), + the contents of DevicePath are initialized to describe the SD card specified + by Slot, and EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL + instance. + @param[in] Slot Specifies the slot number of the SD card for + which a device path node is to be allocated and + built. + @param[in,out] DevicePath A pointer to a single device path node that + describes the SD card specified by Slot. This + function is responsible for allocating the + buffer DevicePath with the boot service + AllocatePool(). It is the caller's responsi- + bility to free DevicePath when the caller is + finished with DevicePath. + + @retval EFI_SUCCESS The device path node that describes the SD card + specified by Slot was allocated and returned in + DevicePath. + @retval EFI_NOT_FOUND The SD card specified by Slot does not exist on + the SD controller. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate + DevicePath. + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruBuildDevicePath ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ) +{ + DW_MMC_HC_PRIVATE_DATA *Private; + SD_DEVICE_PATH *SdNode; + EMMC_DEVICE_PATH *EmmcNode; + + if ((This == NULL) || (DevicePath == NULL) || (Slot >= DW_MMC_HC_MAX_SLOT)) { + return EFI_INVALID_PARAMETER; + } + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (This); + + if ((!Private->Slot[Slot].Enable) || (!Private->Slot[Slot].MediaPresent)) { + return EFI_NOT_FOUND; + } + + if (Private->Slot[Slot].CardType == SdCardType) { + SdNode = AllocateCopyPool (sizeof (SD_DEVICE_PATH), &mSdDpTemplate); + if (SdNode == NULL) { + return EFI_OUT_OF_RESOURCES; + } + SdNode->SlotNumber = Slot; + + *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) SdNode; + } else if (Private->Slot[Slot].CardType == EmmcCardType) { + EmmcNode = AllocateCopyPool (sizeof (EMMC_DEVICE_PATH), &mEmmcDpTemplate); + if (EmmcNode == NULL) { + return EFI_OUT_OF_RESOURCES; + } + EmmcNode->SlotNumber = Slot; + + *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *) EmmcNode; + } else { + // + // Currently we only support SD and EMMC two device nodes. + // + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + This function retrieves an SD card slot number based on the input device path. + + The GetSlotNumber() function retrieves slot number for the SD card specified + by the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is + returned. + + If DevicePath is not a device path node type that the SD Pass Thru driver + supports, EFI_UNSUPPORTED is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] DevicePath A pointer to the device path node that describes + a SD card on the SD controller. + @param[out] Slot On return, points to the slot number of an SD + card on the SD controller. + + @retval EFI_SUCCESS SD card slot number is returned in Slot. + @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL. + @retval EFI_UNSUPPORTED DevicePath is not a device path node type that + the SD Pass Thru driver supports. + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruGetSlotNumber ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT8 *Slot + ) +{ + DW_MMC_HC_PRIVATE_DATA *Private; + SD_DEVICE_PATH *SdNode; + EMMC_DEVICE_PATH *EmmcNode; + UINT8 SlotNumber; + + if ((This == NULL) || (DevicePath == NULL) || (Slot == NULL)) { + return EFI_INVALID_PARAMETER; + } + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (This); + + // + // Check whether the DevicePath belongs to SD_DEVICE_PATH or EMMC_DEVICE_PATH + // + if ((DevicePath->Type != MESSAGING_DEVICE_PATH) || + ((DevicePath->SubType != MSG_SD_DP) && + (DevicePath->SubType != MSG_EMMC_DP)) || + (DevicePathNodeLength(DevicePath) != sizeof(SD_DEVICE_PATH)) || + (DevicePathNodeLength(DevicePath) != sizeof(EMMC_DEVICE_PATH))) { + return EFI_UNSUPPORTED; + } + + if (DevicePath->SubType == MSG_SD_DP) { + SdNode = (SD_DEVICE_PATH *) DevicePath; + SlotNumber = SdNode->SlotNumber; + } else { + EmmcNode = (EMMC_DEVICE_PATH *) DevicePath; + SlotNumber = EmmcNode->SlotNumber; + } + + if (SlotNumber >= DW_MMC_HC_MAX_SLOT) { + return EFI_NOT_FOUND; + } + + if (Private->Slot[SlotNumber].Enable) { + *Slot = SlotNumber; + return EFI_SUCCESS; + } else { + return EFI_NOT_FOUND; + } +} + +/** + Resets an SD card that is connected to the SD controller. + + The ResetDevice() function resets the SD card specified by Slot. + + If this SD controller does not support a device reset operation, + EFI_UNSUPPORTED is returned. + + If Slot is not in a valid slot number for this SD controller, + EFI_INVALID_PARAMETER is returned. + + If the device reset operation is completed, EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Slot Specifies the slot number of the SD card to be + reset. + + @retval EFI_SUCCESS The SD card specified by Slot was reset. + @retval EFI_UNSUPPORTED The SD controller does not support a device + reset operation. + @retval EFI_INVALID_PARAMETER Slot number is invalid. + @retval EFI_NO_MEDIA SD Device not present in the Slot. + @retval EFI_DEVICE_ERROR The reset command failed due to a device error + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruResetDevice ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot + ) +{ + DW_MMC_HC_PRIVATE_DATA *Private; + LIST_ENTRY *Link; + LIST_ENTRY *NextLink; + DW_MMC_HC_TRB *Trb; + EFI_TPL OldTpl; + + if (This == NULL) { + return EFI_INVALID_PARAMETER; + } + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (This); + + if (!Private->Slot[Slot].Enable) { + return EFI_INVALID_PARAMETER; + } + + if (!Private->Slot[Slot].MediaPresent) { + return EFI_NO_MEDIA; + } + + // + // Free all async I/O requests in the queue + // + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + + for (Link = GetFirstNode (&Private->Queue); + !IsNull (&Private->Queue, Link); + Link = NextLink) { + NextLink = GetNextNode (&Private->Queue, Link); + RemoveEntryList (Link); + Trb = DW_MMC_HC_TRB_FROM_THIS (Link); + Trb->Packet->TransactionStatus = EFI_ABORTED; + gBS->SignalEvent (Trb->Event); + DwMmcFreeTrb (Trb); + } + + gBS->RestoreTPL (OldTpl); + + return EFI_SUCCESS; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.h new file mode 100644 index 0000000..101bc92 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.h @@ -0,0 +1,810 @@ +/** @file + + Provides some data structure definitions used by the Designware SD/MMC + host controller driver. + + Copyright (c) 2015, Intel Corporation. All rights reserved. + Copyright (C) 2018, Linaro Ltd. All rigths reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DW_MMC_HC_DXE_H_ +#define _DW_MMC_HC_DXE_H_ + +#include + +#include + +#include +#include +#include +#include +#include + +#include "DwMmcHci.h" + +extern EFI_COMPONENT_NAME_PROTOCOL gDwMmcHcComponentName; +extern EFI_COMPONENT_NAME2_PROTOCOL gDwMmcHcComponentName2; +extern EFI_DRIVER_BINDING_PROTOCOL gDwMmcHcDriverBinding; + +#define DW_MMC_HC_PRIVATE_SIGNATURE SIGNATURE_32 ('d', 'w', 's', 'd') + +#define DW_MMC_HC_PRIVATE_FROM_THIS(a) \ + CR(a, DW_MMC_HC_PRIVATE_DATA, PassThru, DW_MMC_HC_PRIVATE_SIGNATURE) + +// +// Generic time out value, 1 microsecond as unit. +// +#define DW_MMC_HC_GENERIC_TIMEOUT (1 * 1000 * 1000) + +// +// SD/MMC async transfer timer interval, set by experience. +// The unit is 100us, takes 1ms as interval. +// +#define DW_MMC_HC_ASYNC_TIMER EFI_TIMER_PERIOD_MILLISECONDS(1) +// +// SD/MMC removable device enumeration timer interval, set by experience. +// The unit is 100us, takes 100ms as interval. +// +#define DW_MMC_HC_ENUM_TIMER EFI_TIMER_PERIOD_MILLISECONDS(100) + +typedef struct { + BOOLEAN Enable; + EFI_SD_MMC_SLOT_TYPE SlotType; + BOOLEAN MediaPresent; + BOOLEAN Initialized; + SD_MMC_CARD_TYPE CardType; +} DW_MMC_HC_SLOT; + +typedef struct { + UINTN Signature; + + EFI_HANDLE ControllerHandle; + + // Mmio base address + UINTN DevBase; + + EFI_SD_MMC_PASS_THRU_PROTOCOL PassThru; + + PLATFORM_DW_MMC_PROTOCOL *PlatformDwMmc; + // + // The field is used to record the previous slot in GetNextSlot(). + // + UINT8 PreviousSlot; + // + // For Non-blocking operation. + // + EFI_EVENT TimerEvent; + // + // For Sd removable device enumeration. + // + EFI_EVENT ConnectEvent; + LIST_ENTRY Queue; + + DW_MMC_HC_SLOT Slot[DW_MMC_HC_MAX_SLOT]; + DW_MMC_HC_SLOT_CAP Capability[DW_MMC_HC_MAX_SLOT]; + UINT64 MaxCurrent[DW_MMC_HC_MAX_SLOT]; + + UINT32 ControllerVersion; +} DW_MMC_HC_PRIVATE_DATA; + +#define DW_MMC_HC_TRB_SIG SIGNATURE_32 ('D', 'T', 'R', 'B') + +// +// TRB (Transfer Request Block) contains information for the cmd request. +// +typedef struct { + UINT32 Signature; + LIST_ENTRY TrbList; + + UINT8 Slot; + UINT16 BlockSize; + + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + VOID *Data; + UINT32 DataLen; + BOOLEAN Read; + EFI_PHYSICAL_ADDRESS DataPhy; + VOID *DataMap; + DW_MMC_HC_TRANSFER_MODE Mode; + + EFI_EVENT Event; + BOOLEAN Started; + UINT64 Timeout; + + DW_MMC_HC_DMA_DESC_LINE *DmaDesc; + EFI_PHYSICAL_ADDRESS DmaDescPhy; + UINT32 DmaDescPages; + VOID *DmaMap; + + BOOLEAN UseFifo; + BOOLEAN UseBE; // Big-endian + + DW_MMC_HC_PRIVATE_DATA *Private; +} DW_MMC_HC_TRB; + +#define DW_MMC_HC_TRB_FROM_THIS(a) \ + CR(a, DW_MMC_HC_TRB, TrbList, DW_MMC_HC_TRB_SIG) + +// +// Task for Non-blocking mode. +// +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + + UINT8 Slot; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + BOOLEAN IsStart; + EFI_EVENT Event; + UINT64 RetryTimes; + BOOLEAN InfiniteWait; + VOID *Map; + VOID *MapAddress; +} DW_MMC_HC_QUEUE; + +// +// Prototypes +// +/** + Execute card identification procedure. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + + @retval EFI_SUCCESS The card is identified correctly. + @retval Others The card can't be identified. + +**/ +typedef +EFI_STATUS +(*DWMMC_CARD_TYPE_DETECT_ROUTINE) ( + IN DW_MMC_HC_PRIVATE_DATA *Private + ); + +/** + Sends SD command to an SD card that is attached to the SD controller. + + The PassThru() function sends the SD command specified by Packet to the SD + card specified by Slot. + + If Packet is successfully sent to the SD card, then EFI_SUCCESS is returned. + + If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is + returned. + + If Slot is not in a valid range for the SD controller, then + EFI_INVALID_PARAMETER is returned. + + If Packet defines a data command but both InDataBuffer and OutDataBuffer are + NULL, EFI_INVALID_PARAMETER is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Slot The slot number of the SD card to send the + command to. + @param[in,out] Packet A pointer to the SD command data structure. + @param[in] Event If Event is NULL, blocking I/O is performed. If + Event is not NULL, then nonblocking I/O is + performed, and Event will be signaled when the + Packet completes. + + @retval EFI_SUCCESS The SD Command Packet was sent by the host. + @retval EFI_DEVICE_ERROR A device error occurred while attempting to send + the SD command Packet. + @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is + invalid. + @retval EFI_INVALID_PARAMETER Packet defines a data command but both + InDataBuffer and OutDataBuffer are NULL. + @retval EFI_NO_MEDIA SD Device not present in the Slot. + @retval EFI_UNSUPPORTED The command described by the SD Command Packet + is not supported by the host controller. + @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength + exceeds the limit supported by SD card ( i.e. if + the number of bytes exceed the Last LBA). + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruPassThru ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + IN OUT EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet, + IN EFI_EVENT Event OPTIONAL + ); + +/** + Used to retrieve next slot numbers supported by the SD controller. The + function returns information about all available slots (populated or + not-populated). + + The GetNextSlot() function retrieves the next slot number on an SD controller. + If on input Slot is 0xFF, then the slot number of the first slot on the SD + controller is returned. + + If Slot is a slot number that was returned on a previous call to + GetNextSlot(), then the slot number of the next slot on the SD controller is + returned. + + If Slot is not 0xFF and Slot was not returned on a previous call to + GetNextSlot(), EFI_INVALID_PARAMETER is returned. + + If Slot is the slot number of the last slot on the SD controller, then + EFI_NOT_FOUND is returned. + + @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL + instance. + @param[in,out] Slot On input, a pointer to a slot number on the SD + controller. + On output, a pointer to the next slot number on + the SD controller. + An input value of 0xFF retrieves the first slot + number on the SD controller. + + @retval EFI_SUCCESS The next slot number on the SD controller was + returned in Slot. + @retval EFI_NOT_FOUND There are no more slots on this SD controller. + @retval EFI_INVALID_PARAMETER Slot is not 0xFF and Slot was not returned on a + previous call to GetNextSlot(). + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruGetNextSlot ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN OUT UINT8 *Slot + ); + +/** + Used to allocate and build a device path node for an SD card on the SD + controller. + + The BuildDevicePath() function allocates and builds a single device node + for the SD + card specified by Slot. + + If the SD card specified by Slot is not present on the SD controller, then + EFI_NOT_FOUND is returned. + + If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. + + If there are not enough resources to allocate the device path node, then + EFI_OUT_OF_RESOURCES is returned. + + Otherwise, DevicePath is allocated with the boot service AllocatePool(), the + contents of DevicePath are initialized to describe the SD card specified by + Slot, and EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL + instance. + @param[in] Slot Specifies the slot number of the SD card for + which a device path node is to be allocated and + built. + @param[in,out] DevicePath A pointer to a single device path node that + describes the SD card specified by Slot. This + function is responsible for allocating the + buffer DevicePath with the boot service + AllocatePool(). It is the caller's responsibi- + lity to free DevicePath when the caller is + finished with DevicePath. + + @retval EFI_SUCCESS The device path node that describes the SD card + specified by Slot was allocated and returned in + DevicePath. + @retval EFI_NOT_FOUND The SD card specified by Slot does not exist on + the SD controller. + @retval EFI_INVALID_PARAMETER DevicePath is NULL. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate + DevicePath. + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruBuildDevicePath ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot, + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath + ); + +/** + This function retrieves an SD card slot number based on the input device path. + + The GetSlotNumber() function retrieves slot number for the SD card specified + by the DevicePath node. If DevicePath is NULL, EFI_INVALID_PARAMETER is + returned. + + If DevicePath is not a device path node type that the SD Pass Thru driver + supports, EFI_UNSUPPORTED is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] DevicePath A pointer to the device path node that describes + a SD card on the SD controller. + @param[out] Slot On return, points to the slot number of an SD + card on the SD controller. + + @retval EFI_SUCCESS SD card slot number is returned in Slot. + @retval EFI_INVALID_PARAMETER Slot or DevicePath is NULL. + @retval EFI_UNSUPPORTED DevicePath is not a device path node type that + the SD Pass Thru driver supports. + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruGetSlotNumber ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT UINT8 *Slot + ); + +/** + Resets an SD card that is connected to the SD controller. + + The ResetDevice() function resets the SD card specified by Slot. + + If this SD controller does not support a device reset operation, + EFI_UNSUPPORTED is returned. + + If Slot is not in a valid slot number for this SD controller, + EFI_INVALID_PARAMETER is returned. + + If the device reset operation is completed, EFI_SUCCESS is returned. + + @param[in] This A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Slot Specifies the slot number of the SD card to be + reset. + + @retval EFI_SUCCESS The SD card specified by Slot was reset. + @retval EFI_UNSUPPORTED The SD controller does not support a device + reset operation. + @retval EFI_INVALID_PARAMETER Slot number is invalid. + @retval EFI_NO_MEDIA SD Device not present in the Slot. + @retval EFI_DEVICE_ERROR The reset command failed due to a device error + +**/ +EFI_STATUS +EFIAPI +DwMmcPassThruResetDevice ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *This, + IN UINT8 Slot + ); + +// +// Driver model protocol interfaces +// +/** + Tests to see if this driver supports a given controller. If a child device is + provided, it further tests to see if this driver supports creating a handle + for the specified child device. + + This function checks to see if the driver specified by This supports the + device specified by ControllerHandle. Drivers will typically use the device + path attached to ControllerHandle and/or the services from the bus I/O + abstraction attached to ControllerHandle to determine if the driver supports + ControllerHandle. This function may be called many times during platform + initialization. In order to reduce boot times, the tests performed by this + function must be very small, and take as little time as possible to execute. + This function must not change the state of any hardware devices, and this + function must be aware that the device specified by ControllerHandle may + already be managed by the same driver or a different driver. This function + must match its calls to AllocatePages() with FreePages(), AllocatePool() with + FreePool(), and OpenProtocol() with CloseProtocol(). + Since ControllerHandle may have been previously started by the same driver, if + a protocol is already in the opened state, then it must not be closed with + CloseProtocol(). This is required to guarantee the state of ControllerHandle + is not modified by this function. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL + instance. + @param[in] ControllerHandle The handle of the controller to test. This + handle must support a protocol interface that + supplies an I/O abstraction to the driver. + @param[in] RemainingDevicePath A pointer to the remaining portion of a + device path. This parameter is ignored by + device drivers, and is optional for bus + drivers. For bus drivers, if this parameter + is not NULL, then the bus driver must deter- + mine if the bus controller specified by + ControllerHandle and the child controller + specified by RemainingDevicePath are both + supported by this bus driver. + + @retval EFI_SUCCESS The device specified by ControllerHandle and + RemainingDevicePath is supported by the + driver specified by This. + @retval EFI_ALREADY_STARTED The device specified by ControllerHandle and + RemainingDevicePath is already being managed + by the driver specified by This. + @retval EFI_ACCESS_DENIED The device specified by ControllerHandle and + RemainingDevicePath is already being managed + by a different driver or an application that + requires exclusive access. + Currently not implemented. + @retval EFI_UNSUPPORTED The device specified by ControllerHandle and + RemainingDevicePath is not supported by the + driver specified by This. +**/ +EFI_STATUS +EFIAPI +DwMmcHcDriverBindingSupported ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ); + +/** + Starts a device controller or a bus controller. + + The Start() function is designed to be invoked from the EFI boot service + ConnectController(). + As a result, much of the error checking on the parameters to Start() has been + moved into this common boot service. It is legal to call Start() from other + locations, + but the following calling restrictions must be followed or the system behavior + will not be deterministic. + 1. ControllerHandle must be a valid EFI_HANDLE. + 2. If RemainingDevicePath is not NULL, then it must be a pointer to a natural- + ly aligned EFI_DEVICE_PATH_PROTOCOL. + 3. Prior to calling Start(), the Supported() function for the driver specified + by This must have been called with the same calling parameters, and + Supported() must have returned EFI_SUCCESS. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL + instance. + @param[in] ControllerHandle The handle of the controller to start. This + handle must support a protocol interface that + supplies an I/O abstraction to the driver. + @param[in] RemainingDevicePath A pointer to the remaining portion of a + device path. This parameter is ignored by + device drivers, and is optional for bus dri- + vers. For a bus driver, if this parameter is + NULL, then handles for all the children of + Controller are created by this driver. + If this parameter is not NULL and the first + Device Path Node is not the End of Device + Path Node, then only the handle for the + child device specified by the first Device + Path Node of RemainingDevicePath is created + by this driver. + If the first Device Path Node of + RemainingDevicePath is the End of Device Path + Node, no child handle is created by this + driver. + + @retval EFI_SUCCESS The device was started. + @retval EFI_DEVICE_ERROR The device could not be started due to a + device error. Currently not implemented. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a + lack of resources. + @retval Others The driver failded to start the device. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcDriverBindingStart ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath + ); + +/** + Stops a device controller or a bus controller. + + The Stop() function is designed to be invoked from the EFI boot service + DisconnectController(). + As a result, much of the error checking on the parameters to Stop() has been + moved into this common boot service. It is legal to call Stop() from other + locations, but the following calling restrictions must be followed or the + system behavior will not be deterministic. + 1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous + call to this same driver's Start() function. + 2. The first NumberOfChildren handles of ChildHandleBuffer must all be a valid + EFI_HANDLE. In addition, all of these handles must have been created in + this driver's Start() function, and the Start() function must have called + OpenProtocol() on ControllerHandle with an Attribute of + EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER. + + @param[in] This A pointer to the EFI_DRIVER_BINDING_PROTOCOL + instance. + @param[in] ControllerHandle A handle to the device being stopped. The handle + must support a bus specific I/O protocol for the + driver to use to stop the device. + @param[in] NumberOfChildren The number of child device handles in + ChildHandleBuffer. + @param[in] ChildHandleBuffer An array of child handles to be freed. May be + NULL if NumberOfChildren is 0. + + @retval EFI_SUCCESS The device was stopped. + @retval EFI_DEVICE_ERROR The device could not be stopped due to a device + error. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcDriverBindingStop ( + IN EFI_DRIVER_BINDING_PROTOCOL *This, + IN EFI_HANDLE Controller, + IN UINTN NumberOfChildren, + IN EFI_HANDLE *ChildHandleBuffer + ); + +// +// EFI Component Name Functions +// +/** + Retrieves a Unicode string that is the user readable name of the driver. + + This function retrieves the user readable name of a driver in the form of a + Unicode string. If the driver specified by This has a user readable name in + the language specified by Language, then a pointer to the driver name is + returned in DriverName, and EFI_SUCCESS is returned. If the driver specified + by This does not support the language specified by Language, + then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified + in RFC 4646 or ISO 639-2 language code format. + + @param DriverName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + driver specified by This in the language + specified by Language. + + @retval EFI_SUCCESS The Unicode string for the Driver specified by + This and the language specified by Language was + returned in DriverName. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER DriverName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcComponentNameGetDriverName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + +/** + Retrieves a Unicode string that is the user readable name of the controller + that is being managed by a driver. + + This function retrieves the user readable name of the controller specified by + ControllerHandle and ChildHandle in the form of a Unicode string. If the + driver specified by This has a user readable name in the language specified by + Language, then a pointer to the controller name is returned in ControllerName, + and EFI_SUCCESS is returned. If the driver specified by This is not currently + managing the controller specified by ControllerHandle and ChildHandle, + then EFI_UNSUPPORTED is returned. If the driver specified by This does not + support the language specified by Language, then EFI_UNSUPPORTED is returned. + + @param This[in] A pointer to the EFI_COMPONENT_NAME2_PROTOCOL or + EFI_COMPONENT_NAME_PROTOCOL instance. + + @param ControllerHandle[in] The handle of a controller that the driver + specified by This is managing. This handle + specifies the controller whose name is to be + returned. + + @param ChildHandle[in] The handle of the child controller to retrieve + the name of. This is an optional parameter that + may be NULL. It will be NULL for device + drivers. It will also be NULL for a bus drivers + that wish to retrieve the name of the bus + controller. It will not be NULL for a bus + driver that wishes to retrieve the name of a + child controller. + + @param Language[in] A pointer to a Null-terminated ASCII string + array indicating the language. This is the + language of the driver name that the caller is + requesting, and it must match one of the + languages specified in SupportedLanguages. The + number of languages supported by a driver is up + to the driver writer. Language is specified in + RFC 4646 or ISO 639-2 language code format. + + @param ControllerName[out] A pointer to the Unicode string to return. + This Unicode string is the name of the + controller specified by ControllerHandle and + ChildHandle in the language specified by + Language from the point of view of the driver + specified by This. + + @retval EFI_SUCCESS The Unicode string for the user readable name in + the language specified by Language for the + driver specified by This was returned in + DriverName. + + @retval EFI_INVALID_PARAMETER ControllerHandle is not a valid EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER ChildHandle is not NULL and it is not a valid + EFI_HANDLE. + + @retval EFI_INVALID_PARAMETER Language is NULL. + + @retval EFI_INVALID_PARAMETER ControllerName is NULL. + + @retval EFI_UNSUPPORTED The driver specified by This is not currently + managing the controller specified by + ControllerHandle and ChildHandle. + + @retval EFI_UNSUPPORTED The driver specified by This does not support + the language specified by Language. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcComponentNameGetControllerName ( + IN EFI_COMPONENT_NAME_PROTOCOL *This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle, OPTIONAL + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +/** + Create a new TRB for the SD/MMC cmd request. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Slot The slot number of the SD card to send the command + to. + @param[in] Packet A pointer to the SD command data structure. + @param[in] Event If Event is NULL, blocking I/O is performed. + If Event is not NULL, then nonblocking I/O is + performed, and Event will be signaled when the + Packet completes. + + @return Created Trb or NULL. + +**/ +DW_MMC_HC_TRB * +DwMmcCreateTrb ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet, + IN EFI_EVENT Event + ); + +/** + Free the resource used by the TRB. + + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + +**/ +VOID +DwMmcFreeTrb ( + IN DW_MMC_HC_TRB *Trb + ); + +/** + Check if the env is ready for execute specified TRB. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The env is ready for TRB execution. + @retval EFI_NOT_READY The env is not ready for TRB execution. + @retval Others Some erros happen. + +**/ +EFI_STATUS +DwMmcCheckTrbEnv ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ); + +/** + Wait for the env to be ready for execute specified TRB. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The env is ready for TRB execution. + @retval EFI_TIMEOUT The env is not ready for TRB execution in time. + @retval Others Some erros happen. + +**/ +EFI_STATUS +DwMmcWaitTrbEnv ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ); + +/** + Execute the specified TRB. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The TRB is sent to host controller successfully. + @retval Others Some erros happen when sending this request to the + host controller. + +**/ +EFI_STATUS +DwMmcExecTrb ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ); + +/** + Check the TRB execution result. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The TRB is executed successfully. + @retval EFI_NOT_READY The TRB is not completed for execution. + @retval Others Some erros happen when executing this request. + +**/ +EFI_STATUS +DwMmcCheckTrbResult ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ); + +/** + Wait for the TRB execution result. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The TRB is executed successfully. + @retval Others Some erros happen when executing this request. + +**/ +EFI_STATUS +DwMmcWaitTrbResult ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ); + +/** + Execute EMMC device identification procedure. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + + @retval EFI_SUCCESS There is a EMMC card. + @retval Others There is not a EMMC card. + +**/ +EFI_STATUS +EmmcIdentification ( + IN DW_MMC_HC_PRIVATE_DATA *Private + ); + +/** + Execute EMMC device identification procedure. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + + @retval EFI_SUCCESS There is a EMMC card. + @retval Others There is not a EMMC card. + +**/ +EFI_STATUS +SdCardIdentification ( + IN DW_MMC_HC_PRIVATE_DATA *Private + ); + +#endif /* _DW_MMC_HC_DXE_H_ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.inf b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.inf new file mode 100644 index 0000000..930a0a3 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHcDxe.inf @@ -0,0 +1,67 @@ +## @file +# DwSdMmcHcDxe driver is used to manage those host controllers which comply with +# Designware SD Host Controller. +# +# It will produce EFI_SD_MMC_PASS_THRU_PROTOCOL to allow sending SD/MMC/eMMC cmds +# to specified devices from upper layer. +# +# Copyright (c) 2015, Intel Corporation. All rights reserved. +# Copyright (C) 2016, Marvell International Ltd. All rights reserved. +# Copyright (c) 2018, Linaro Ltd. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = DwMmcHcDxe + MODULE_UNI_FILE = DwMmcHcDxe.uni + FILE_GUID = 9be4d260-208c-4efe-a524-0b5d3bf77f9d + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeDwMmcHcDxe + +[Sources] + ComponentName.c + DwMmcHcDxe.c + DwMmcHcDxe.h + DwMmcHci.c + DwMmcHci.h + EmmcDevice.c + SdDevice.c + +[Packages] + ArmPkg/ArmPkg.dec + Silicon/Synopsys/DesignWare/DesignWarePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + BaseLib + BaseMemoryLib + CacheMaintenanceLib + DebugLib + DevicePathLib + DmaLib + MemoryAllocationLib + TimerLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + +[Protocols] + gEdkiiNonDiscoverableDeviceProtocolGuid + gEfiDevicePathProtocolGuid ## TO_START + gEfiPciIoProtocolGuid ## TO_START + gEfiSdMmcPassThruProtocolGuid ## BY_START + gPlatformDwMmcProtocolGuid + +[Guids] + gDwMmcHcNonDiscoverableDeviceGuid + +[UserExtensions.TianoCore."ExtraFiles"] + DwMmcHcDxeExtra.uni diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHci.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHci.c new file mode 100644 index 0000000..6b122d5 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHci.c @@ -0,0 +1,1647 @@ +/** @file + This driver is used to manage Designware SD/MMC PCI host controllers. + + It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. + + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
    + Copyright (c) 2018, Linaro Ltd. All rights reserved.
    + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "DwMmcHcDxe.h" + +/** + Dump the content of SD/MMC host controller's Capability Register. + + @param[in] Slot The slot number of the SD card to send the + command to. + @param[in] Capability The buffer to store the capability data. + +**/ +VOID +DumpCapabilityReg ( + IN UINT8 Slot, + IN DW_MMC_HC_SLOT_CAP *Capability + ) +{ + // + // Dump Capability Data + // + DEBUG (( + DEBUG_INFO, + " == Slot [%d] Capability is 0x%x ==\n", + Slot, + Capability + )); + DEBUG (( + DEBUG_INFO, + " Base Clk Freq %dKHz\n", + Capability->BaseClkFreq + )); + DEBUG (( + DEBUG_INFO, + " BusWidth %d\n", + Capability->BusWidth + )); + DEBUG (( + DEBUG_INFO, + " HighSpeed Support %a\n", + Capability->HighSpeed ? "TRUE" : "FALSE" + )); + DEBUG (( + DEBUG_INFO, + " Voltage 1.8 %a\n", + Capability->Voltage18 ? "TRUE" : "FALSE" + )); + DEBUG (( + DEBUG_INFO, + " 64-bit Sys Bus %a\n", + Capability->SysBus64 ? "TRUE" : "FALSE" + )); + DEBUG ((DEBUG_INFO, " SlotType ")); + if (Capability->SlotType == 0x00) { + DEBUG ((DEBUG_INFO, "%a\n", "Removable Slot")); + } else if (Capability->SlotType == 0x01) { + DEBUG ((DEBUG_INFO, "%a\n", "Embedded Slot")); + } else if (Capability->SlotType == 0x02) { + DEBUG ((DEBUG_INFO, "%a\n", "Shared Bus Slot")); + } else { + DEBUG ((DEBUG_INFO, "%a\n", "Reserved")); + } + DEBUG (( + DEBUG_INFO, + " SDR50 Support %a\n", + Capability->Sdr50 ? "TRUE" : "FALSE" + )); + DEBUG (( + DEBUG_INFO, + " SDR104 Support %a\n", + Capability->Sdr104 ? "TRUE" : "FALSE" + )); + DEBUG (( + DEBUG_INFO, + " DDR50 Support %a\n", + Capability->Ddr50 ? "TRUE" : "FALSE" + )); + return; +} + +/** + Set all interrupt status bits in Normal and Error Interrupt Status Enable + register. + + @param[in] DevIo The DEVICE IO protocol instance. + + @retval EFI_SUCCESS The operation executes successfully. + @retval Others The operation fails. + +**/ +EFI_STATUS +DwMmcHcEnableInterrupt ( + UINTN DevBase + ) +{ + UINT32 IntStatus; + UINT32 IdIntEn; + UINT32 IdSts; + + // + // Enable all bits in Interrupt Mask Register + // + IntStatus = 0; + MmioWrite32 (DevBase + DW_MMC_INTMASK, IntStatus); + + // + // Clear status in Interrupt Status Register + // + IntStatus = ~0; + MmioWrite32 (DevBase + DW_MMC_RINTSTS, IntStatus); + + IdIntEn = ~0; + MmioWrite32 (DevBase + DW_MMC_IDINTEN, IdIntEn); + + IdSts = ~0; + MmioWrite32 (DevBase + DW_MMC_IDSTS, IdSts); + + return EFI_SUCCESS; +} + +EFI_STATUS +DwMmcHcGetCapability ( + IN UINTN DevBase, + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT DW_MMC_HC_SLOT_CAP *Capacity + ) +{ + PLATFORM_DW_MMC_PROTOCOL *PlatformDwMmc; + EFI_STATUS Status; + + if (Capacity == NULL) { + return EFI_INVALID_PARAMETER; + } + Status = gBS->LocateProtocol ( + &gPlatformDwMmcProtocolGuid, + NULL, + (VOID **) &PlatformDwMmc + ); + if (EFI_ERROR (Status)) { + return Status; + } + Status = PlatformDwMmc->GetCapability (Controller, Slot, Capacity); + return Status; +} + +/** + Detect whether there is a SD/MMC card attached at the specified SD/MMC host + controller slot. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command + to. + @param[out] MediaPresent The pointer to the media present boolean value. + + @retval EFI_SUCCESS There is no media change happened. + @retval EFI_MEDIA_CHANGED There is media change happened. + @retval Others The detection fails. + +**/ +EFI_STATUS +DwMmcHcCardDetect ( + IN UINTN DevBase, + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT BOOLEAN *MediaPresent + ) +{ + PLATFORM_DW_MMC_PROTOCOL *PlatformDwMmc; + EFI_STATUS Status; + + if (MediaPresent == NULL) { + return EFI_INVALID_PARAMETER; + } + Status = gBS->LocateProtocol ( + &gPlatformDwMmcProtocolGuid, + NULL, + (VOID **) &PlatformDwMmc + ); + if (EFI_ERROR (Status)) { + return Status; + } + *MediaPresent = PlatformDwMmc->CardDetect (Controller, Slot); + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +DwMmcHcUpdateClock ( + IN UINTN DevBase + ) +{ + UINT32 Cmd; + UINT32 IntStatus; + + Cmd = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY | + BIT_CMD_START; + MmioWrite32 (DevBase + DW_MMC_CMD, Cmd); + + while (1) { + Cmd = MmioRead32 (DevBase + DW_MMC_CMD); + + if (!(Cmd & CMD_START_BIT)) { + break; + } + + IntStatus = MmioRead32 (DevBase + DW_MMC_RINTSTS); + + if (IntStatus & DW_MMC_INT_HLE) { + DEBUG (( + DEBUG_ERROR, + "DwMmcHcUpdateClock: failed to update mmc clock frequency\n" + )); + return EFI_DEVICE_ERROR; + } + } + + return EFI_SUCCESS; +} + +/** + Stop SD/MMC card clock. + + @param[in] DevIo The DEVICE IO protocol instance. + + @retval EFI_SUCCESS Succeed to stop SD/MMC clock. + @retval Others Fail to stop SD/MMC clock. + +**/ +EFI_STATUS +DwMmcHcStopClock ( + IN UINTN DevBase + ) +{ + EFI_STATUS Status; + UINT32 ClkEna; + + // + // Disable MMC clock first + // + ClkEna = 0; + MmioWrite32 (DevBase + DW_MMC_CLKENA, ClkEna); + + Status = DwMmcHcUpdateClock (DevBase); + if (EFI_ERROR (Status)) { + return Status; + } + return Status; +} + +/** + SD/MMC card clock supply. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] ClockFreq The max clock frequency to be set. The unit is KHz. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The clock is supplied successfully. + @retval Others The clock isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcClockSupply ( + IN UINTN DevBase, + IN UINT64 ClockFreq, + IN DW_MMC_HC_SLOT_CAP Capability + ) +{ + EFI_STATUS Status; + UINT32 BaseClkFreq; + UINT32 SettingFreq; + UINT32 Divisor; + UINT32 Remainder; + UINT32 MmcStatus; + UINT32 ClkEna; + UINT32 ClkSrc; + + // + // Calculate a divisor for SD clock frequency + // + ASSERT (Capability.BaseClkFreq != 0); + + BaseClkFreq = Capability.BaseClkFreq; + if (ClockFreq == 0) { + return EFI_INVALID_PARAMETER; + } + + if (ClockFreq > BaseClkFreq) { + ClockFreq = BaseClkFreq; + } + + // + // Calculate the divisor of base frequency. + // + Divisor = 0; + SettingFreq = BaseClkFreq; + while (ClockFreq < SettingFreq) { + Divisor++; + + SettingFreq = BaseClkFreq / (2 * Divisor); + Remainder = BaseClkFreq % (2 * Divisor); + if ((ClockFreq == SettingFreq) && (Remainder == 0)) { + break; + } + if ((ClockFreq == SettingFreq) && (Remainder != 0)) { + SettingFreq ++; + } + } + + DEBUG (( + DEBUG_INFO, + "BaseClkFreq %dKHz Divisor %d ClockFreq %dKhz\n", + BaseClkFreq, + Divisor, + ClockFreq + )); + + // + // Wait until MMC is idle + // + do { + MmcStatus = MmioRead32 (DevBase + DW_MMC_STATUS); + } while (MmcStatus & DW_MMC_STS_DATA_BUSY); + + do { + Status = DwMmcHcStopClock (DevBase); + } while (EFI_ERROR (Status)); + + do { + ClkSrc = 0; + MmioWrite32 (DevBase + DW_MMC_CLKSRC, ClkSrc); + // + // Set clock divisor + // + MmioWrite32 (DevBase + DW_MMC_CLKDIV, Divisor); + // + // Enable MMC clock + // + ClkEna = 1; + MmioWrite32 (DevBase + DW_MMC_CLKENA, ClkEna); + + Status = DwMmcHcUpdateClock (DevBase); + } while (EFI_ERROR (Status)); + + return EFI_SUCCESS; +} + +/** + Set the SD/MMC bus width. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] IsDdr A boolean to indicate it's dual data rate or not. + @param[in] BusWidth The bus width used by the SD/MMC device, it must be + 1, 4 or 8. + + @retval EFI_SUCCESS The bus width is set successfully. + @retval Others The bus width isn't set successfully. + +**/ +EFI_STATUS +DwMmcHcSetBusWidth ( + IN UINTN DevBase, + IN BOOLEAN IsDdr, + IN UINT16 BusWidth + ) +{ + UINT32 Ctype; + UINT32 Uhs; + + switch (BusWidth) { + case 1: + Ctype = MMC_1BIT_MODE; + break; + case 4: + Ctype = MMC_4BIT_MODE; + break; + case 8: + Ctype = MMC_8BIT_MODE; + break; + default: + return EFI_INVALID_PARAMETER; + } + MmioWrite32 (DevBase + DW_MMC_CTYPE, Ctype); + + Uhs = MmioRead32 (DevBase + DW_MMC_UHSREG); + + if (IsDdr) { + Uhs |= UHS_DDR_MODE; + } else { + Uhs &= ~(UHS_DDR_MODE); + } + + MmioWrite32 (DevBase + DW_MMC_UHSREG, Uhs); + + return EFI_SUCCESS; +} + +/** + Supply SD/MMC card with lowest clock frequency at initialization. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The clock is supplied successfully. + @retval Others The clock isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcInitClockFreq ( + IN UINTN DevBase, + IN DW_MMC_HC_SLOT_CAP Capability + ) +{ + EFI_STATUS Status; + UINT32 InitFreq; + + // + // Calculate a divisor for SD clock frequency + // + if (Capability.BaseClkFreq == 0) { + // + // Don't support get Base Clock Frequency information via another method + // + return EFI_UNSUPPORTED; + } + // + // Supply 400KHz clock frequency at initialization phase. + // + InitFreq = DWMMC_INIT_CLOCK_FREQ; + Status = DwMmcHcClockSupply (DevBase, InitFreq, Capability); + if (EFI_ERROR (Status)) { + return Status; + } + MicroSecondDelay (100); + return Status; +} + +STATIC +EFI_STATUS +DwMmcHcWaitReset ( + IN UINTN DevBase, + IN UINT32 ResetValue + ) +{ + UINT32 Timeout; + UINT32 Data; + + MmioWrite32 (DevBase + DW_MMC_CTRL, ResetValue); + + Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + while (Timeout--) { + Data = MmioRead32 (DevBase + DW_MMC_CTRL); + if ((Data & DW_MMC_CTRL_RESET_ALL) == 0) { + return EFI_SUCCESS; + } + gBS->Stall (1); + } + + return EFI_TIMEOUT; +} + +/** + Supply SD/MMC card with maximum voltage at initialization. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The voltage is supplied successfully. + @retval Others The voltage isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcInitPowerVoltage ( + IN UINTN DevBase, + IN DW_MMC_HC_SLOT_CAP Capability + ) +{ + EFI_STATUS Status; + + MmioWrite32 (DevBase + DW_MMC_PWREN, 0x1); + + Status = DwMmcHcWaitReset (DevBase, DW_MMC_CTRL_RESET_ALL); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, + "DwMmcHcInitPowerVoltage: reset failed due to timeout")); + return Status; + } + + MmioWrite32 (DevBase + DW_MMC_CTRL, DW_MMC_CTRL_INT_EN); + + return EFI_SUCCESS; +} + +/** + Initialize the Timeout Control register with most conservative value at + initialization. + + @param[in] DevIo The DEVICE IO protocol instance. + + @retval EFI_SUCCESS The timeout control register is configured + successfully. + @retval Others The timeout control register isn't configured + successfully. + +**/ +EFI_STATUS +DwMmcHcInitTimeoutCtrl ( + IN UINTN DevBase + ) +{ + UINT32 Data; + + Data = ~0; + MmioWrite32 (DevBase + DW_MMC_TMOUT, Data); + + Data = 0x00FFFFFF; + MmioWrite32 (DevBase + DW_MMC_DEBNCE, Data); + + return EFI_SUCCESS; +} + +/** + Initial SD/MMC host controller with lowest clock frequency, max power and + max timeout value at initialization. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command + to. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The host controller is initialized successfully. + @retval Others The host controller isn't initialized successfully. + +**/ +EFI_STATUS +DwMmcHcInitHost ( + IN UINTN DevBase, + IN DW_MMC_HC_SLOT_CAP Capability + ) +{ + EFI_STATUS Status; + + Status = DwMmcHcInitPowerVoltage (DevBase, Capability); + if (EFI_ERROR (Status)) { + return Status; + } + return Status; +} + +EFI_STATUS +DwMmcHcStartDma ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + EFI_STATUS Status; + UINTN DevBase; + UINT32 Ctrl; + UINT32 Bmod; + UINT32 Timeout; + UINT32 Data; + +// DevIo = Trb->Private->DevIo; + DevBase = Trb->Private->DevBase; + + // + // Reset DMA + // + Status = DwMmcHcWaitReset (DevBase, DW_MMC_CTRL_DMA_RESET); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Timed out waiting for CTRL_DMA_RESET")); + return Status; + } + + Bmod = DW_MMC_IDMAC_SWRESET | MmioRead32 (DevBase + DW_MMC_BMOD); + + MmioWrite32 (DevBase + DW_MMC_BMOD, Bmod); + + // + // Select IDMAC + // + Ctrl = DW_MMC_CTRL_IDMAC_EN; + Ctrl |= MmioRead32 (DevBase + DW_MMC_CTRL); + MmioWrite32 (DevBase + DW_MMC_CTRL, Ctrl); + + // + // Enable IDMAC + // + Bmod = DW_MMC_IDMAC_ENABLE | DW_MMC_IDMAC_FB; + Bmod |= MmioRead32 (DevBase + DW_MMC_BMOD); + + MmioWrite32 (DevBase + DW_MMC_BMOD, Bmod); + + return EFI_SUCCESS; +} + +EFI_STATUS +DwMmcHcStopDma ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + UINTN DevBase; + UINT32 Ctrl; + UINT32 Bmod; + + DevBase = Trb->Private->DevBase; + + // + // Disable and reset IDMAC + // + Ctrl = MmioRead32 (DevBase + DW_MMC_CTRL); + Ctrl &= ~DW_MMC_CTRL_IDMAC_EN; + Ctrl |= DW_MMC_CTRL_DMA_RESET; + MmioWrite32 (DevBase + DW_MMC_CTRL, Ctrl); + + // + // Stop IDMAC + // + Bmod = MmioRead32 (DevBase + DW_MMC_BMOD); + Bmod &= ~(DW_MMC_BMOD_FB | DW_MMC_BMOD_DE); + Bmod |= DW_MMC_BMOD_SWR; + MmioWrite32 (DevBase + DW_MMC_BMOD, Bmod); + + return EFI_SUCCESS; +} + +/** + Build DMA descriptor table for transfer. + + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The DMA descriptor table is created successfully. + @retval Others The DMA descriptor table isn't created successfully. + +**/ +EFI_STATUS +BuildDmaDescTable ( + IN DW_MMC_HC_TRB *Trb + ) +{ + EFI_PHYSICAL_ADDRESS Data; + UINT64 DataLen; + UINT64 Entries; + UINT32 Index; + UINT64 Remaining; + UINTN TableSize; + UINTN DevBase; + EFI_STATUS Status; + UINTN Bytes; + UINTN Blocks; + DW_MMC_HC_DMA_DESC_LINE *DmaDesc; + UINT32 DmaDescPhy; + UINT32 Idsts; + UINT32 BytCnt; + UINT32 BlkSize; + + Data = Trb->DataPhy; + DataLen = Trb->DataLen; + DevBase = Trb->Private->DevBase; + // + // Only support 32bit DMA Descriptor Table + // + if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) { + return EFI_INVALID_PARAMETER; + } + // + // Address field shall be set on 32-bit boundary (Lower 2-bit is always set + // to 0) for 32-bit address descriptor table. + // + if ((Data & (BIT0 | BIT1)) != 0) { + DEBUG (( + DEBUG_INFO, + "The buffer [0x%x] to construct DMA desc is not aligned to 4 bytes!\n", + Data + )); + } + + Entries = (DataLen + DWMMC_DMA_BUF_SIZE - 1) / DWMMC_DMA_BUF_SIZE; + TableSize = Entries * sizeof (DW_MMC_HC_DMA_DESC_LINE); + Blocks = (DataLen + DW_MMC_BLOCK_SIZE - 1) / DW_MMC_BLOCK_SIZE; + + Trb->DmaDescPages = (UINT32)EFI_SIZE_TO_PAGES (Entries * DWMMC_DMA_BUF_SIZE); +/* Status = DevIo->AllocateBuffer ( + DevIo, + AllocateAnyPages, + EfiBootServicesData, + EFI_SIZE_TO_PAGES (TableSize), + (EFI_PHYSICAL_ADDRESS *)&Trb->DmaDesc + );*/ + Status = DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (TableSize), + (VOID *)&Trb->DmaDesc); + if (EFI_ERROR (Status)) { + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem (Trb->DmaDesc, TableSize); + Bytes = TableSize; + + Status = DmaMap (MapOperationBusMasterCommonBuffer, + (EFI_PHYSICAL_ADDRESS *)Trb->DmaDesc, + &Bytes, &Trb->DmaDescPhy, &Trb->DmaMap); +/* Status = DevIo->Map ( + DevIo, + EfiBusMasterCommonBuffer, + (EFI_PHYSICAL_ADDRESS *)Trb->DmaDesc, + &Bytes, + &Trb->DmaDescPhy, + &Trb->DmaMap + );*/ + + if (EFI_ERROR (Status) || (Bytes != TableSize)) { + // + // Map error or unable to map the whole RFis buffer into a contiguous + // region. + // +/* DevIo->FreeBuffer ( + DevIo, + EFI_SIZE_TO_PAGES (TableSize), + (EFI_PHYSICAL_ADDRESS)Trb->DmaDesc + );*/ + return EFI_OUT_OF_RESOURCES; + } + + if ((UINT64)(UINTN)Trb->DmaDescPhy > 0x100000000ul) { + // + // The DMA doesn't support 64bit addressing. + // + DmaUnmap (Trb->DmaMap); +/* DevIo->Unmap ( + DevIo, + Trb->DmaMap + );*/ + return EFI_DEVICE_ERROR; + } + + if (DataLen < DW_MMC_BLOCK_SIZE) { + BlkSize = DataLen; + BytCnt = DataLen; + Remaining = DataLen; + } else { + BlkSize = DW_MMC_BLOCK_SIZE; + BytCnt = DW_MMC_BLOCK_SIZE * Blocks; + Remaining = DW_MMC_BLOCK_SIZE * Blocks; + } + + MmioWrite32 (DevBase + DW_MMC_BLKSIZ, BlkSize); + MmioWrite32 (DevBase + DW_MMC_BYTCNT, BytCnt); + DmaDesc = Trb->DmaDesc; + for (Index = 0; Index < Entries; Index++, DmaDesc++) { + DmaDesc->Des0 = DW_MMC_IDMAC_DES0_OWN | DW_MMC_IDMAC_DES0_CH | + DW_MMC_IDMAC_DES0_DIC; + DmaDesc->Des1 = DW_MMC_IDMAC_DES1_BS1 (DWMMC_DMA_BUF_SIZE); + // + // Buffer Address + // + DmaDesc->Des2 = (UINT32)((UINTN)Trb->DataPhy + + (DWMMC_DMA_BUF_SIZE * Index)); + // + // Next Descriptor Address + // + DmaDesc->Des3 = (UINT32)((UINTN)Trb->DmaDescPhy + + sizeof (DW_MMC_HC_DMA_DESC_LINE) * (Index + 1)); + Remaining = Remaining - DWMMC_DMA_BUF_SIZE; + } + // + // First Descriptor + // + Trb->DmaDesc[0].Des0 |= DW_MMC_IDMAC_DES0_FS; + // + // Last Descriptor + // + Trb->DmaDesc[Entries - 1].Des0 &= ~(DW_MMC_IDMAC_DES0_CH | + DW_MMC_IDMAC_DES0_DIC); + Trb->DmaDesc[Entries - 1].Des0 |= DW_MMC_IDMAC_DES0_OWN | + DW_MMC_IDMAC_DES0_LD; + Trb->DmaDesc[Entries - 1].Des1 = DW_MMC_IDMAC_DES1_BS1 (Remaining + + DWMMC_DMA_BUF_SIZE); + // + // Set the next field of the Last Descriptor + // + Trb->DmaDesc[Entries - 1].Des3 = 0; + DmaDescPhy = (UINT32)Trb->DmaDescPhy; + + MmioWrite32 (DevBase + DW_MMC_DBADDR, DmaDescPhy); + + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + // + // Clear interrupts + // + Idsts = ~0; + MmioWrite32 (DevBase + DW_MMC_IDSTS, Idsts); + + return Status; +} + +EFI_STATUS +TransferFifo ( + IN DW_MMC_HC_TRB *Trb + ) +{ + UINTN DevBase; + UINT32 Data; + UINT32 Received; + UINT32 Count; + UINT32 Intsts; + UINT32 Sts; + UINT32 FifoCount; + UINT32 Index; /* count with bytes */ + UINT32 Ascending; + UINT32 Descending; + UINT32 Timeout; + + DevBase = Trb->Private->DevBase; + Received = 0; + Count = 0; + Index = 0; + Ascending = 0; + Descending = ((Trb->DataLen + 3) & ~3) - 4; + Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + do { + Intsts = MmioRead32 (DevBase + DW_MMC_RINTSTS); + + if (!Trb->Read && (Intsts & DW_MMC_INT_TXDR)) { + Sts = MmioRead32 (DevBase + DW_MMC_STATUS); + + while (!(DW_MMC_STS_FIFO_FULL(Sts)) + && (Received < Trb->DataLen) + && (Intsts & DW_MMC_INT_TXDR)) { + if (Trb->UseBE) { + Data = SwapBytes32 (*(UINT32 *)((UINTN)Trb->Data + Descending)); + Descending = Descending - 4; + } else { + Data = *(UINT32 *)((UINTN)Trb->Data + Ascending); + Ascending += 4; + } + Index += 4; + Received += 4; + + MmioWrite32 (DevBase + DW_MMC_FIFO_START, Data); + + Intsts = DW_MMC_INT_TXDR; + MmioWrite32 (DevBase + DW_MMC_RINTSTS, Intsts); + + Intsts = MmioRead32 (DevBase + DW_MMC_RINTSTS); + Sts = MmioRead32 (DevBase + DW_MMC_STATUS); + } + Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + goto Verify; + } + + if (Trb->Read && ((Intsts & DW_MMC_INT_RXDR) || + (Intsts & DW_MMC_INT_DTO))) { + Sts = MmioRead32 (DevBase + DW_MMC_STATUS); + // + // Convert to bytes + // + FifoCount = GET_STS_FIFO_COUNT (Sts) << 2; + if ((FifoCount == 0) && (Received < Trb->DataLen)) { + goto Verify; + } + Index = 0; + Count = (MIN (FifoCount, Trb->DataLen) + 3) & ~3; + while (Index < Count) { + Data = MmioRead32 (DevBase + DW_MMC_FIFO_START); + + if (Trb->UseBE) { + *(UINT32 *)((UINTN)Trb->Data + Descending) = SwapBytes32 (Data); + Descending = Descending - 4; + } else { + *(UINT32 *)((UINTN)Trb->Data + Ascending) = Data; + Ascending += 4; + } + Index += 4; + Received += 4; + } /* while */ + Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + } /* if */ + +Verify: + if (Intsts & DW_MMC_INT_DATA_ERR) { + DEBUG ((DEBUG_ERROR, "%a: Data error. CmdIndex=%d, IntStatus=%p\n", + __func__, Trb->Packet->SdMmcCmdBlk->CommandIndex, Intsts)); + return EFI_DEVICE_ERROR; + } + + if (Timeout < DW_MMC_HC_GENERIC_TIMEOUT) { + MicroSecondDelay(1); + } + + if (--Timeout == 0) { + DEBUG ((DEBUG_ERROR, "%a: Timed out. CmdIndex=%d, IntStatus=%p\n", + __func__, Trb->Packet->SdMmcCmdBlk->CommandIndex, Intsts)); + return EFI_TIMEOUT; + } + } while ((Received < Trb->DataLen)); + + return EFI_SUCCESS; +} + +/** + Create a new TRB for the SD/MMC cmd request. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Slot The slot number of the SD card to send the command + to. + @param[in] Packet A pointer to the SD command data structure. + @param[in] Event If Event is NULL, blocking I/O is performed. If + Event is not NULL, then nonblocking I/O is + performed, and Event will be signaled when the + Packet completes. + + @return Created Trb or NULL. + +**/ +DW_MMC_HC_TRB * +DwMmcCreateTrb ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 Slot, + IN EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet, + IN EFI_EVENT Event + ) +{ + DW_MMC_HC_TRB *Trb; + EFI_STATUS Status; + EFI_TPL OldTpl; + EFI_IO_OPERATION_TYPE Flag; + UINTN MapLength; + + Trb = AllocateZeroPool (sizeof (DW_MMC_HC_TRB)); + if (Trb == NULL) { + return NULL; + } + + Trb->Signature = DW_MMC_HC_TRB_SIG; + Trb->Slot = Slot; + Trb->BlockSize = 0x200; + Trb->Packet = Packet; + Trb->Event = Event; + Trb->Started = FALSE; + Trb->Timeout = Packet->Timeout; + Trb->Private = Private; + + if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) { + Trb->Data = Packet->InDataBuffer; + Trb->DataLen = Packet->InTransferLength; + Trb->Read = TRUE; + ZeroMem (Trb->Data, Trb->DataLen); + } else if (Packet->OutTransferLength && (Packet->OutDataBuffer != NULL)) { + Trb->Data = Packet->OutDataBuffer; + Trb->DataLen = Packet->OutTransferLength; + Trb->Read = FALSE; + } else if (!Packet->InTransferLength && !Packet->OutTransferLength) { + Trb->Data = NULL; + Trb->DataLen = 0; + } else { + goto Error; + } + + if (((Private->Slot[Trb->Slot].CardType == EmmcCardType) && + (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK)) || + ((Private->Slot[Trb->Slot].CardType == SdCardType) && + (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_TUNING_BLOCK))) { + Trb->Mode = SdMmcPioMode; + } else { + if (Trb->Read) { + Flag = EfiBusMasterWrite; + } else { + Flag = EfiBusMasterRead; + } + + if (Private->Slot[Trb->Slot].CardType == SdCardType) { + Trb->UseFifo = TRUE; + } else { + Trb->UseFifo = FALSE; + if (Trb->DataLen) { + MapLength = Trb->DataLen; + Status = DmaMap (Flag, Trb->Data, &MapLength, &Trb->DataPhy, &Trb->DataMap); +/* Status = DevIo->Map ( + DevIo, + Flag, + Trb->Data, + &MapLength, + &Trb->DataPhy, + &Trb->DataMap + );*/ + if (EFI_ERROR (Status) || (Trb->DataLen != MapLength)) { + Status = EFI_BAD_BUFFER_SIZE; + goto Error; + } + + Status = BuildDmaDescTable (Trb); + if (EFI_ERROR (Status)) { + DmaUnmap(Trb->DataMap); + goto Error; + } + Status = DwMmcHcStartDma (Private, Trb); + if (EFI_ERROR (Status)) { + DmaUnmap(Trb->DataMap); + goto Error; + } + } + } + } /* TuningBlock */ + + if (Event != NULL) { + OldTpl = gBS->RaiseTPL (TPL_NOTIFY); + InsertTailList (&Private->Queue, &Trb->TrbList); + gBS->RestoreTPL (OldTpl); + } + + return Trb; + +Error: + return NULL; +} + +/** + Free the resource used by the TRB. + + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + +**/ +VOID +DwMmcFreeTrb ( + IN DW_MMC_HC_TRB *Trb + ) +{ + if (Trb->DmaMap != NULL) { + DmaUnmap (Trb->DmaMap); + } + if (Trb->DataMap != NULL) { + DmaUnmap (Trb->DataMap); + } + FreePool (Trb); +} + +/** + Check if the env is ready for execute specified TRB. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The env is ready for TRB execution. + @retval EFI_NOT_READY The env is not ready for TRB execution. + @retval Others Some erros happen. + +**/ +EFI_STATUS +DwMmcCheckTrbEnv ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + return EFI_SUCCESS; +} + +/** + Wait for the env to be ready for execute specified TRB. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The env is ready for TRB execution. + @retval EFI_TIMEOUT The env is not ready for TRB execution in time. + @retval Others Some erros happen. + +**/ +EFI_STATUS +DwMmcWaitTrbEnv ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + EFI_STATUS Status; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + UINT64 Timeout; + BOOLEAN InfiniteWait; + + // + // Wait Command Complete Interrupt Status bit in Normal Interrupt Status + // Register + // + Packet = Trb->Packet; + Timeout = Packet->Timeout; + if (Timeout == 0) { + InfiniteWait = TRUE; + } else { + InfiniteWait = FALSE; + } + + while (InfiniteWait || (Timeout > 0)) { + // + // Check Trb execution result by reading Normal Interrupt Status register. + // + Status = DwMmcCheckTrbEnv (Private, Trb); + if (Status != EFI_NOT_READY) { + return Status; + } + // + // Stall for 1 microsecond. + // + gBS->Stall (1); + + Timeout--; + } + + return EFI_TIMEOUT; +} + +EFI_STATUS +DwEmmcExecTrb ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + UINTN DevBase; + UINT32 Cmd; + UINT32 MmcStatus; + UINT32 IntStatus; + UINT32 Argument; + UINT32 ErrMask; + UINT32 Timeout; + + Packet = Trb->Packet; + DevBase = Trb->Private->DevBase; + + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + // + // Wait until MMC is idle + // + do { + MmcStatus = MmioRead32 (DevBase + DW_MMC_STATUS); + } while (MmcStatus & DW_MMC_STS_DATA_BUSY); + + IntStatus = ~0; + MmioWrite32 (DevBase + DW_MMC_RINTSTS, IntStatus); + Cmd = CMD_INDEX (Packet->SdMmcCmdBlk->CommandIndex); + if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAc) || + (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc)) { + switch (Packet->SdMmcCmdBlk->CommandIndex) { + case EMMC_SET_RELATIVE_ADDR: + Cmd |= BIT_CMD_SEND_INIT; + break; + case EMMC_SEND_STATUS: + Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE; + break; + case EMMC_STOP_TRANSMISSION: + Cmd |= BIT_CMD_STOP_ABORT_CMD; + break; + } + if (Packet->InTransferLength) { + Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_DATA_EXPECTED | + BIT_CMD_READ; + } else if (Packet->OutTransferLength) { + Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_DATA_EXPECTED | + BIT_CMD_WRITE; + } + Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC; + } else { + switch (Packet->SdMmcCmdBlk->CommandIndex) { + case EMMC_GO_IDLE_STATE: + Cmd |= BIT_CMD_SEND_INIT; + break; + case EMMC_SEND_OP_COND: + Cmd |= BIT_CMD_RESPONSE_EXPECT; + break; + case EMMC_ALL_SEND_CID: + Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE | + BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT; + break; + } + } + switch (Packet->SdMmcCmdBlk->ResponseType) { + case SdMmcResponseTypeR2: + Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC | + BIT_CMD_LONG_RESPONSE; + break; + case SdMmcResponseTypeR3: + Cmd |= BIT_CMD_RESPONSE_EXPECT; + break; + } + Cmd |= BIT_CMD_USE_HOLD_REG | BIT_CMD_START; + + Argument = Packet->SdMmcCmdBlk->CommandArgument; + MmioWrite32 (DevBase + DW_MMC_CMDARG, Argument); + + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + + MmioWrite32 (DevBase + DW_MMC_CMD, Cmd); + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + + ErrMask = DW_MMC_INT_EBE | DW_MMC_INT_HLE | DW_MMC_INT_RTO | + DW_MMC_INT_RCRC | DW_MMC_INT_RE; + ErrMask |= DW_MMC_INT_DCRC | DW_MMC_INT_DRT | DW_MMC_INT_SBE; + do { + Timeout = 10000; + if (--Timeout == 0) { + break; + } + IntStatus = MmioRead32 (DevBase + DW_MMC_RINTSTS); + if (IntStatus & ErrMask) { + return EFI_DEVICE_ERROR; + } + if (Trb->DataLen && ((IntStatus & DW_MMC_INT_DTO) == 0)) { + // + // Transfer Not Done + // + MicroSecondDelay (10); + continue; + } + MicroSecondDelay (10); + } while (!(IntStatus & DW_MMC_INT_CMD_DONE)); + switch (Packet->SdMmcCmdBlk->ResponseType) { + case SdMmcResponseTypeR1: + case SdMmcResponseTypeR1b: + case SdMmcResponseTypeR3: + case SdMmcResponseTypeR4: + case SdMmcResponseTypeR5: + Packet->SdMmcStatusBlk->Resp0 = MmioRead32 (DevBase + DW_MMC_RESP0); + break; + case SdMmcResponseTypeR2: + Packet->SdMmcStatusBlk->Resp0 = MmioRead32 (DevBase + DW_MMC_RESP0); + Packet->SdMmcStatusBlk->Resp1 = MmioRead32 (DevBase + DW_MMC_RESP1); + Packet->SdMmcStatusBlk->Resp2 = MmioRead32 (DevBase + DW_MMC_RESP2); + Packet->SdMmcStatusBlk->Resp3 = MmioRead32 (DevBase + DW_MMC_RESP3); + break; + } + + // + // The workaround on EMMC_SEND_CSD is used to be compatible with SDHC. + // + if (Packet->SdMmcCmdBlk->CommandIndex == EMMC_SEND_CSD) { + { + UINT32 Buf[4]; + ZeroMem (Buf, sizeof (Buf)); + CopyMem ( + (UINT8 *)Buf, + (UINT8 *)&Packet->SdMmcStatusBlk->Resp0 + 1, + sizeof (Buf) - 1 + ); + CopyMem ( + (UINT8 *)&Packet->SdMmcStatusBlk->Resp0, + (UINT8 *)Buf, + sizeof (Buf) - 1 + ); + } + } + + return EFI_SUCCESS; +} + +EFI_STATUS +DwSdExecTrb ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + UINTN DevBase; + UINT32 Cmd; + UINT32 MmcStatus; + UINT32 IntStatus; + UINT32 Argument; + UINT32 ErrMask; + UINT32 Timeout; + UINT32 Idsts; + UINT32 BytCnt; + UINT32 BlkSize; + EFI_STATUS Status; + + Packet = Trb->Packet; + DevBase = Trb->Private->DevBase; + + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + // + // Wait until MMC is idle + // + do { + MmcStatus = MmioRead32 (DevBase + DW_MMC_STATUS); + } while (MmcStatus & DW_MMC_STS_DATA_BUSY); + + IntStatus = ~0; + MmioWrite32 (DevBase + DW_MMC_RINTSTS, IntStatus); + Cmd = CMD_INDEX (Packet->SdMmcCmdBlk->CommandIndex); + if ((Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAc) || + (Packet->SdMmcCmdBlk->CommandType == SdMmcCommandTypeAdtc)) { + switch (Packet->SdMmcCmdBlk->CommandIndex) { + case SD_SET_RELATIVE_ADDR: + Cmd |= BIT_CMD_SEND_INIT; + break; + case SD_STOP_TRANSMISSION: + Cmd |= BIT_CMD_STOP_ABORT_CMD; + break; + case SD_SEND_SCR: + Trb->UseBE = TRUE; + break; + } + if (Packet->InTransferLength) { + Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_DATA_EXPECTED | + BIT_CMD_READ; + } else if (Packet->OutTransferLength) { + Cmd |= BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_DATA_EXPECTED | + BIT_CMD_WRITE; + } + Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC | + BIT_CMD_SEND_AUTO_STOP; + } else { + switch (Packet->SdMmcCmdBlk->CommandIndex) { + case SD_GO_IDLE_STATE: + Cmd |= BIT_CMD_SEND_INIT; + break; + } + } + switch (Packet->SdMmcCmdBlk->ResponseType) { + case SdMmcResponseTypeR2: + Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC | + BIT_CMD_LONG_RESPONSE; + break; + case SdMmcResponseTypeR3: + Cmd |= BIT_CMD_RESPONSE_EXPECT; + break; + case SdMmcResponseTypeR1b: + case SdMmcResponseTypeR4: + case SdMmcResponseTypeR6: + case SdMmcResponseTypeR7: + Cmd |= BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC; + break; + } + Cmd |= BIT_CMD_USE_HOLD_REG | BIT_CMD_START; + + if (Trb->UseFifo == TRUE) { + BytCnt = Trb->Read ? Packet->InTransferLength : Packet->OutTransferLength; + MmioWrite32 (DevBase + DW_MMC_BYTCNT, BytCnt); + if (Trb->Read) { + if (Packet->InTransferLength > DW_MMC_BLOCK_SIZE) { + BlkSize = DW_MMC_BLOCK_SIZE; + } else { + BlkSize = Packet->InTransferLength; + } + } + else { + if (Packet->OutTransferLength > DW_MMC_BLOCK_SIZE) { + BlkSize = DW_MMC_BLOCK_SIZE; + } else { + BlkSize = Packet->OutTransferLength; + } + } + + MmioWrite32 (DevBase + DW_MMC_BLKSIZ, BlkSize); + + if (Trb->DataLen) { + Status = DwMmcHcWaitReset (DevBase, DW_MMC_CTRL_FIFO_RESET); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: FIFO reset timed out. CmdIndex=%d\n", + __func__, Packet->SdMmcCmdBlk->CommandIndex)); + } + } + } + + Argument = Packet->SdMmcCmdBlk->CommandArgument; + MmioWrite32 (DevBase + DW_MMC_CMDARG, Argument); + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + MmioWrite32 (DevBase + DW_MMC_CMD, Cmd); + ArmDataSynchronizationBarrier (); + ArmInstructionSynchronizationBarrier (); + + ErrMask = DW_MMC_INT_EBE | DW_MMC_INT_HLE | DW_MMC_INT_RTO | + DW_MMC_INT_RCRC | DW_MMC_INT_RE; + ErrMask |= DW_MMC_INT_DRT | DW_MMC_INT_SBE; + if (Packet->InTransferLength || Packet->OutTransferLength) { + ErrMask |= DW_MMC_INT_DCRC; + } + + Timeout = 10000; + do { + if (--Timeout == 0) { + break; + } + IntStatus = MmioRead32 (DevBase + DW_MMC_RINTSTS); + MicroSecondDelay (1); + } while (!(IntStatus & DW_MMC_INT_CMD_DONE)); + + if (IntStatus & ErrMask) { + DEBUG ((DEBUG_ERROR, "%a: Command error. CmdIndex=%d, IntStatus=%p\n", + __func__, Packet->SdMmcCmdBlk->CommandIndex, IntStatus)); + return EFI_DEVICE_ERROR; + } + + if (Trb->DataLen) { + if (Trb->UseFifo == TRUE) { + Status = TransferFifo (Trb); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + if (Packet->InTransferLength) { + do { + Idsts = MmioRead32 (DevBase + DW_MMC_IDSTS); + } while ((Idsts & DW_MMC_IDSTS_RI) == 0); + Status = DwMmcHcStopDma (Private, Trb); + if (EFI_ERROR (Status)) { + return Status; + } + } else if (Packet->OutTransferLength) { + do { + Idsts = MmioRead32 (DevBase + DW_MMC_IDSTS); + } while ((Idsts & DW_MMC_IDSTS_TI) == 0); + Status = DwMmcHcStopDma (Private, Trb); + if (EFI_ERROR (Status)) { + return Status; + } + } /* Packet->InTransferLength */ + } /* UseFifo */ + } /* Trb->DataLen */ + + switch (Packet->SdMmcCmdBlk->ResponseType) { + case SdMmcResponseTypeR1: + case SdMmcResponseTypeR1b: + case SdMmcResponseTypeR3: + case SdMmcResponseTypeR4: + case SdMmcResponseTypeR5: + case SdMmcResponseTypeR6: + case SdMmcResponseTypeR7: + Packet->SdMmcStatusBlk->Resp0 = MmioRead32 (DevBase + DW_MMC_RESP0); + break; + case SdMmcResponseTypeR2: + Packet->SdMmcStatusBlk->Resp0 = MmioRead32 (DevBase + DW_MMC_RESP0); + Packet->SdMmcStatusBlk->Resp1 = MmioRead32 (DevBase + DW_MMC_RESP1); + Packet->SdMmcStatusBlk->Resp2 = MmioRead32 (DevBase + DW_MMC_RESP2); + Packet->SdMmcStatusBlk->Resp3 = MmioRead32 (DevBase + DW_MMC_RESP3); + break; + } + + // + // The workaround on SD_SEND_CSD/CID is used to be compatible with SDHC. + // + if (Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_CSD + || Packet->SdMmcCmdBlk->CommandIndex == SD_SEND_CID) { + { + UINT32 Buf[4]; + ZeroMem (Buf, sizeof (Buf)); + CopyMem ( + (UINT8 *)Buf, + (UINT8 *)&Packet->SdMmcStatusBlk->Resp0 + 1, + sizeof (Buf) - 1 + ); + CopyMem ( + (UINT8 *)&Packet->SdMmcStatusBlk->Resp0, + (UINT8 *)Buf, + sizeof (Buf) - 1 + ); + } + } + + return EFI_SUCCESS; +} + +/** + Execute the specified TRB. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The TRB is sent to host controller successfully. + @retval Others Some erros happen when sending this request to the + host controller. + +**/ +EFI_STATUS +DwMmcExecTrb ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Slot; + + Slot = Trb->Slot; + if (Private->Slot[Slot].CardType == EmmcCardType) { + Status = DwEmmcExecTrb (Private, Trb); + } else if (Private->Slot[Slot].CardType == SdCardType) { + Status = DwSdExecTrb (Private, Trb); + } else { + ASSERT (0); + } + return Status; +} + +/** + Check the TRB execution result. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The TRB is executed successfully. + @retval EFI_NOT_READY The TRB is not completed for execution. + @retval Others Some erros happen when executing this request. + +**/ +EFI_STATUS +DwMmcCheckTrbResult ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + UINT32 Idsts; + UINTN DevBase; + UINT32 IntStatus; + + DevBase = Private->DevBase; + Packet = Trb->Packet; + if (Trb->UseFifo == TRUE) { + if (Trb->DataLen) { + IntStatus = MmioRead32 (DevBase + DW_MMC_RINTSTS); + // + // Check Auto CMD12 completion + // + if (!(IntStatus & DW_MMC_INT_ACD)) { + return EFI_NOT_READY; + } + + // + // Check data trans over + // + if (!(IntStatus & DW_MMC_INT_DTO)) { + return EFI_NOT_READY; + } + + // + // There will be some errors reported (SBE, HTO, DRT, DCRC, RCRC) + // depending on the command sent (read/write, single/multi block). + // + // Not sure why this happens (do we need to manually stop the command?), + // but it does not seem to affect operation in any way. + // All data is correctly transferred and the FIFO is empty by the time + // we reach this code path. + // + // Each transfer is validated in TransferFifo(), which would fail on any + // of the error states above and more. + // Interrupt status is cleared before a new command is issued, no need + // to do it here. + // + } + return EFI_SUCCESS; + } + if (Packet->InTransferLength) { + do { + Idsts = MmioRead32 (DevBase + DW_MMC_IDSTS); + } while ((Idsts & BIT1) == 0); + } else if (Packet->OutTransferLength) { + do { + Idsts = MmioRead32 (DevBase + DW_MMC_IDSTS); + } while ((Idsts & BIT0) == 0); + } else { + return EFI_SUCCESS; + } + Idsts = ~0; + MmioWrite32 (DevBase + DW_MMC_IDSTS, Idsts); + + return EFI_SUCCESS; +} + +/** + Wait for the TRB execution result. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + @param[in] Trb The pointer to the DW_MMC_HC_TRB instance. + + @retval EFI_SUCCESS The TRB is executed successfully. + @retval Others Some erros happen when executing this request. + +**/ +EFI_STATUS +DwMmcWaitTrbResult ( + IN DW_MMC_HC_PRIVATE_DATA *Private, + IN DW_MMC_HC_TRB *Trb + ) +{ + EFI_STATUS Status; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET *Packet; + UINT64 Timeout; + BOOLEAN InfiniteWait; + + Packet = Trb->Packet; + // + // Wait Command Complete Interrupt Status bit in Normal Interrupt Status + // Register + // + Timeout = Packet->Timeout; + if (Timeout == 0) { + InfiniteWait = TRUE; + } else { + InfiniteWait = FALSE; + } + + while (InfiniteWait || (Timeout > 0)) { + // + // Check Trb execution result by reading Normal Interrupt Status register. + // + Status = DwMmcCheckTrbResult (Private, Trb); + if (Status != EFI_NOT_READY) { + return Status; + } + // + // Stall for 1 microsecond. + // + gBS->Stall (1); + + Timeout--; + } + + return EFI_TIMEOUT; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHci.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHci.h new file mode 100644 index 0000000..9a7b4da --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/DwMmcHci.h @@ -0,0 +1,988 @@ +/** @file + + Provides some data structure definitions used by the SD/MMC host controller + driver. + + Copyright (c) 2015-2021, Intel Corporation. All rights reserved. + Copyright (c) 2018, Linaro Ltd. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DW_MMC_HCI_H_ +#define _DW_MMC_HCI_H_ + +#include +#include + +#include + +// +// SD Host Controller SlotInfo Register Offset +// +#define DW_MMC_HC_SLOT_OFFSET 0x40 + +#define DW_MMC_HC_MAX_SLOT 1 + +// +// SD Host Controller MMIO Register Offset +// +#define DW_MMC_CTRL 0x000 +#define DW_MMC_PWREN 0x004 +#define DW_MMC_CLKDIV 0x008 +#define DW_MMC_CLKSRC 0x00c +#define DW_MMC_CLKENA 0x010 +#define DW_MMC_TMOUT 0x014 +#define DW_MMC_CTYPE 0x018 +#define DW_MMC_BLKSIZ 0x01c +#define DW_MMC_BYTCNT 0x020 +#define DW_MMC_INTMASK 0x024 +#define DW_MMC_CMDARG 0x028 +#define DW_MMC_CMD 0x02c +#define DW_MMC_RESP0 0x030 +#define DW_MMC_RESP1 0x034 +#define DW_MMC_RESP2 0x038 +#define DW_MMC_RESP3 0x03c +#define DW_MMC_RINTSTS 0x044 +#define DW_MMC_STATUS 0x048 +#define DW_MMC_FIFOTH 0x04c +#define DW_MMC_GPIO 0x058 +#define DW_MMC_DEBNCE 0x064 +#define DW_MMC_USRID 0x068 +#define DW_MMC_VERID 0x06c +#define DW_MMC_HCON 0x070 +#define DW_MMC_UHSREG 0x074 +#define DW_MMC_BMOD 0x080 +#define DW_MMC_DBADDR 0x088 +#define DW_MMC_IDSTS 0x08c +#define DW_MMC_IDINTEN 0x090 +#define DW_MMC_DSCADDR 0x094 +#define DW_MMC_BUFADDR 0x098 +#define DW_MMC_CARDTHRCTL 0x100 +#define DW_MMC_UHSREG_EXT 0x108 +#define DW_MMC_ENABLE_SHIFT 0x110 +#define DW_MMC_FIFO_START 0x200 + +#define GET_IDSTS_DMAC_FSM(x) (((x) >> 13) & 0xf) +#define IDSTS_FSM_DMA_IDLE 0 +#define IDSTS_FSM_DMA_SUSPEND 1 +#define IDSTS_FSM_DESC_RD 2 +#define IDSTS_FSM_DESC_CHK 3 +#define IDSTS_FSM_DMA_RD_REQ_WAIT 4 +#define IDSTS_FSM_DMA_WR_REQ_WAIT 5 +#define IDSTS_FSM_DMA_RD 6 +#define IDSTS_FSM_DMA_WR 7 +#define IDSTS_FSM_DESC_CLOSE 8 +#define IDSTS_FSM_MASK 0xf + +#define CMD_UPDATE_CLK 0x80202000 +#define CMD_START_BIT (1 << 31) + +#define MMC_8BIT_MODE (1 << 16) +#define MMC_4BIT_MODE (1 << 0) +#define MMC_1BIT_MODE 0 + +#define DW_MMC_BLOCK_SIZE 512 + +#define CMD_INDEX_MASK 0x3F +#define BIT_CMD_RESPONSE_EXPECT (1 << 6) +#define BIT_CMD_LONG_RESPONSE (1 << 7) +#define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8) +#define BIT_CMD_DATA_EXPECTED (1 << 9) +#define BIT_CMD_READ (0 << 10) +#define BIT_CMD_WRITE (1 << 10) +#define BIT_CMD_BLOCK_TRANSFER (0 << 11) +#define BIT_CMD_STREAM_TRANSFER (1 << 11) +#define BIT_CMD_SEND_AUTO_STOP (1 << 12) +#define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) +#define BIT_CMD_STOP_ABORT_CMD (1 << 14) +#define BIT_CMD_SEND_INIT (1 << 15) +#define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21) +#define BIT_CMD_READ_CEATA_DEVICE (1 << 22) +#define BIT_CMD_CCS_EXPECTED (1 << 23) +#define BIT_CMD_ENABLE_BOOT (1 << 24) +#define BIT_CMD_EXPECT_BOOT_ACK (1 << 25) +#define BIT_CMD_DISABLE_BOOT (1 << 26) +#define BIT_CMD_MANDATORY_BOOT (0 << 27) +#define BIT_CMD_ALTERNATE_BOOT (1 << 27) +#define BIT_CMD_VOLT_SWITCH (1 << 28) +#define BIT_CMD_USE_HOLD_REG (1 << 29) +#define BIT_CMD_START (1 << 31) + +#define CMD_INDEX(x) ((x) & CMD_INDEX_MASK) + +#define DW_MMC_INT_EBE (1 << 15) /* End-bit Err */ +#define DW_MMC_INT_ACD (1 << 14) /* Auto command done */ +#define DW_MMC_INT_SBE (1 << 13) /* Start-bit Err */ +#define DW_MMC_INT_HLE (1 << 12) /* Hardware-lock Err */ +#define DW_MMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */ +#define DW_MMC_INT_HTO (1 << 10) /* Data starvation by host timeout */ +#define DW_MMC_INT_DRT (1 << 9) /* Data timeout */ +#define DW_MMC_INT_RTO (1 << 8) /* Response timeout */ +#define DW_MMC_INT_DCRC (1 << 7) /* Data CRC err */ +#define DW_MMC_INT_RCRC (1 << 6) /* Response CRC err */ +#define DW_MMC_INT_RXDR (1 << 5) /* Receive FIFO data request */ +#define DW_MMC_INT_TXDR (1 << 4) /* Transmit FIFO data request */ +#define DW_MMC_INT_DTO (1 << 3) /* Data trans over */ +#define DW_MMC_INT_CMD_DONE (1 << 2) /* Command done */ +#define DW_MMC_INT_RE (1 << 1) /* Response error */ + +#define DW_MMC_INT_DATA_ERR (DW_MMC_INT_EBE |\ + DW_MMC_INT_SBE |\ + DW_MMC_INT_HLE |\ + DW_MMC_INT_FRUN |\ + DW_MMC_INT_DCRC |\ + DW_MMC_INT_HTO |\ + DW_MMC_INT_DRT) + +#define DW_MMC_IDMAC_DES0_DIC (1 << 1) +#define DW_MMC_IDMAC_DES0_LD (1 << 2) +#define DW_MMC_IDMAC_DES0_FS (1 << 3) +#define DW_MMC_IDMAC_DES0_CH (1 << 4) +#define DW_MMC_IDMAC_DES0_ER (1 << 5) +#define DW_MMC_IDMAC_DES0_CES (1 << 30) +#define DW_MMC_IDMAC_DES0_OWN (1 << 31) +#define DW_MMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff) +#define DW_MMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13) +#define DW_MMC_IDMAC_SWRESET (1 << 0) +#define DW_MMC_IDMAC_FB (1 << 1) +#define DW_MMC_IDMAC_ENABLE (1 << 7) + +#define DW_MMC_CTRL_RESET (1 << 0) +#define DW_MMC_CTRL_FIFO_RESET (1 << 1) +#define DW_MMC_CTRL_DMA_RESET (1 << 2) +#define DW_MMC_CTRL_INT_EN (1 << 4) +#define DW_MMC_CTRL_DMA_EN (1 << 5) +#define DW_MMC_CTRL_IDMAC_EN (1 << 25) +#define DW_MMC_CTRL_RESET_ALL (DW_MMC_CTRL_RESET | DW_MMC_CTRL_FIFO_RESET | DW_MMC_CTRL_DMA_RESET) + +#define DW_MMC_STS_DATA_BUSY (1 << 9) +#define DW_MMC_STS_FIFO_COUNT(x) (((x) & 0x1fff) << 17) /* Number of filled locations in FIFO */ +#define GET_STS_FIFO_COUNT(x) (((x) >> 17) & 0x1fff) +#define DW_MMC_STS_FIFO_FULL(x) (((x) >> 3) & 1) + +#define DW_MMC_BMOD_SWR (1 << 0) /* Software Reset */ +#define DW_MMC_BMOD_FB (1 << 1) /* Fix Burst */ +#define DW_MMC_BMOD_DE (1 << 7) /* IDMAC Enable */ + +#define DW_MMC_IDSTS_TI (1 << 0) /* Transmit Interrupt */ +#define DW_MMC_IDSTS_RI (1 << 1) /* Receive Interrupt */ + +#define DW_MMC_FIFO_TWMARK(x) ((x) & 0xfff) +#define DW_MMC_FIFO_RWMARK(x) (((x) & 0x1ff) << 16) +#define DW_MMC_DMA_BURST_SIZE(x) (((x) & 0x7) << 28) + +#define DW_MMC_CARD_RD_THR(x) (((x) & 0xfff) << 16) +#define DW_MMC_CARD_RD_THR_EN (1 << 0) + +#define UHS_DDR_MODE (1 << 16) + +#define GENCLK_DIV 7 + +#define DW_MMC_GPIO_CLK_DIV(x) (((x) & 0xf) << 8) +#define DW_MMC_GPIO_USE_SAMPLE_DLY(x) (((x) & 1) << 13) +#define DW_MMC_GPIO_CLK_ENABLE BIT16 + +#define UHSEXT_SAMPLE_PHASE(x) (((x) & 0x1f) << 16) +#define UHSEXT_SAMPLE_DRVPHASE(x) (((x) & 0x1f) << 21) +#define UHSEXT_SAMPLE_DLY(x) (((x) & 0x1f) << 26) + +#define DWMMC_DMA_BUF_SIZE (512 * 8) +#define DWMMC_FIFO_THRESHOLD 16 + +#define DWMMC_INIT_CLOCK_FREQ 400 /* KHz */ + +// +// The transfer modes supported by SD Host Controller +// Simplified Spec 3.0 Table 1-2 +// +typedef enum { + SdMmcNoData, + SdMmcPioMode, + SdMmcSdmaMode, + SdMmcAdmaMode +} DW_MMC_HC_TRANSFER_MODE; + +// +// The maximum data length of each descriptor line +// +#define ADMA_MAX_DATA_PER_LINE 0x10000 + +typedef struct { + UINT32 Des0; + UINT32 Des1; + UINT32 Des2; + UINT32 Des3; +} DW_MMC_HC_DMA_DESC_LINE; + +#define SD_MMC_SDMA_BOUNDARY 512 * 1024 +#define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1)) + +typedef struct { + UINT8 FirstBar:3; // bit 0:2 + UINT8 Reserved:1; // bit 3 + UINT8 SlotNum:3; // bit 4:6 + UINT8 Reserved1:1; // bit 7 +} DW_MMC_HC_SLOT_INFO; + +/** + Dump the content of SD/MMC host controller's Capability Register. + + @param[in] Slot The slot number of the SD card to send the command to. + @param[in] Capability The buffer to store the capability data. + +**/ +VOID +DumpCapabilityReg ( + IN UINT8 Slot, + IN DW_MMC_HC_SLOT_CAP *Capability + ); + +#if 0 +/** + Read SlotInfo register from SD/MMC host controller pci config space. + + @param[in] PciIo The PCI IO protocol instance. + @param[out] FirstBar The buffer to store the first BAR value. + @param[out] SlotNum The buffer to store the supported slot number. + + @retval EFI_SUCCESS The operation succeeds. + @retval Others The operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcGetSlotInfo ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + OUT UINT8 *FirstBar, + OUT UINT8 *SlotNum + ); +#endif + +#ifdef DWMMC_PCI +/** + Read/Write specified SD/MMC host controller mmio register. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] BarIndex The BAR index of the standard PCI Configuration + header to use as the base address for the memory + operation to perform. + @param[in] Offset The offset within the selected BAR to start the + memory operation. + @param[in] Read A boolean to indicate it's read or write operation. + @param[in] Count The width of the mmio register in bytes. + Must be 1, 2 , 4 or 8 bytes. + @param[in, out] Data For read operations, the destination buffer to store + the results. For write operations, the source buffer + to write data from. The caller is responsible for + having ownership of the data buffer and ensuring its + size not less than Count bytes. + + @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid. + @retval EFI_SUCCESS The read/write operation succeeds. + @retval Others The read/write operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcRwMmio ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 BarIndex, + IN UINT32 Offset, + IN BOOLEAN Read, + IN UINT8 Count, + IN OUT VOID *Data + ); +#else +/** + Read/Write specified SD/MMC host controller mmio register. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Offset The offset within the selected BAR to start the + memory operation. + @param[in] Read A boolean to indicate it's read or write operation. + @param[in] Count The width of the mmio register in bytes. + Must be 1, 2 , 4 or 8 bytes. + @param[in, out] Data For read operations, the destination buffer to store + the results. For write operations, the source buffer + to write data from. The caller is responsible for + having ownership of the data buffer and ensuring its + size not less than Count bytes. + + @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid. + @retval EFI_SUCCESS The read/write operation succeeds. + @retval Others The read/write operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcRwMmio ( + IN UINTN DevBase, + IN UINT32 Offset, + IN BOOLEAN Read, + IN UINT8 Count, + IN OUT VOID *Data + ); +#endif + +#ifdef DWMMC_PCI +/** + Do OR operation with the value of the specified SD/MMC host controller mmio register. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] BarIndex The BAR index of the standard PCI Configuration + header to use as the base address for the memory + operation to perform. + @param[in] Offset The offset within the selected BAR to start the + memory operation. + @param[in] Count The width of the mmio register in bytes. + Must be 1, 2 , 4 or 8 bytes. + @param[in] OrData The pointer to the data used to do OR operation. + The caller is responsible for having ownership of + the data buffer and ensuring its size not less than + Count bytes. + + @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid. + @retval EFI_SUCCESS The OR operation succeeds. + @retval Others The OR operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcOrMmio ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 BarIndex, + IN UINT32 Offset, + IN UINT8 Count, + IN VOID *OrData + ); +#else +/** + Do OR operation with the value of the specified SD/MMC host controller mmio register. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] BarIndex The BAR index of the standard PCI Configuration + header to use as the base address for the memory + operation to perform. + @param[in] Offset The offset within the selected BAR to start the + memory operation. + @param[in] Count The width of the mmio register in bytes. + Must be 1, 2 , 4 or 8 bytes. + @param[in] OrData The pointer to the data used to do OR operation. + The caller is responsible for having ownership of + the data buffer and ensuring its size not less than + Count bytes. + + @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid. + @retval EFI_SUCCESS The OR operation succeeds. + @retval Others The OR operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcOrMmio ( + IN UINTN DevBase, + IN UINT32 Offset, + IN UINT8 Count, + IN VOID *OrData + ); +#endif + +#ifdef DWMMC_PCI +/** + Do AND operation with the value of the specified SD/MMC host controller mmio register. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] BarIndex The BAR index of the standard PCI Configuration + header to use as the base address for the memory + operation to perform. + @param[in] Offset The offset within the selected BAR to start the + memory operation. + @param[in] Count The width of the mmio register in bytes. + Must be 1, 2 , 4 or 8 bytes. + @param[in] AndData The pointer to the data used to do AND operation. + The caller is responsible for having ownership of + the data buffer and ensuring its size not less than + Count bytes. + + @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid. + @retval EFI_SUCCESS The AND operation succeeds. + @retval Others The AND operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcAndMmio ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 BarIndex, + IN UINT32 Offset, + IN UINT8 Count, + IN VOID *AndData + ); +#else +/** + Do AND operation with the value of the specified SD/MMC host controller mmio register. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Offset The offset within the selected BAR to start the + memory operation. + @param[in] Count The width of the mmio register in bytes. + Must be 1, 2 , 4 or 8 bytes. + @param[in] AndData The pointer to the data used to do AND operation. + The caller is responsible for having ownership of + the data buffer and ensuring its size not less than + Count bytes. + + @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid. + @retval EFI_SUCCESS The AND operation succeeds. + @retval Others The AND operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcAndMmio ( + IN UINTN DevBase, + IN UINT32 Offset, + IN UINT8 Count, + IN VOID *AndData + ); +#endif + +#ifdef DWMMC_PCI +/** + Wait for the value of the specified MMIO register set to the test value. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] BarIndex The BAR index of the standard PCI Configuration + header to use as the base address for the memory + operation to perform. + @param[in] Offset The offset within the selected BAR to start the + memory operation. + @param[in] Count The width of the mmio register in bytes. + Must be 1, 2, 4 or 8 bytes. + @param[in] MaskValue The mask value of memory. + @param[in] TestValue The test value of memory. + @param[in] Timeout The time out value for wait memory set, uses 1 + microsecond as a unit. + + @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout + range. + @retval EFI_SUCCESS The MMIO register has expected value. + @retval Others The MMIO operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcWaitMmioSet ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 BarIndex, + IN UINT32 Offset, + IN UINT8 Count, + IN UINT64 MaskValue, + IN UINT64 TestValue, + IN UINT64 Timeout + ); +#else +/** + Wait for the value of the specified MMIO register set to the test value. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Offset The offset within the selected BAR to start the + memory operation. + @param[in] Count The width of the mmio register in bytes. + Must be 1, 2, 4 or 8 bytes. + @param[in] MaskValue The mask value of memory. + @param[in] TestValue The test value of memory. + @param[in] Timeout The time out value for wait memory set, uses 1 + microsecond as a unit. + + @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout + range. + @retval EFI_SUCCESS The MMIO register has expected value. + @retval Others The MMIO operation fails. + +**/ +EFI_STATUS +EFIAPI +DwMmcHcWaitMmioSet ( + IN UINTN DevBase, + IN UINT32 Offset, + IN UINT8 Count, + IN UINT64 MaskValue, + IN UINT64 TestValue, + IN UINT64 Timeout + ); +#endif + +#ifdef DWMMC_PCI +/** + Software reset the specified SD/MMC host controller. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + + @retval EFI_SUCCESS The software reset executes successfully. + @retval Others The software reset fails. + +**/ +EFI_STATUS +DwMmcHcReset ( +fark + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#else +/** + Software reset the specified SD/MMC host controller. + + @param[in] DevIo The DEVICE IO protocol instance. + + @retval EFI_SUCCESS The software reset executes successfully. + @retval Others The software reset fails. + +**/ +EFI_STATUS +DwMmcHcReset ( + IN UINTN DevBase, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#endif + +#ifdef DWMMC_PCI +/** + Set all interrupt status bits in Normal and Error Interrupt Status Enable + register. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + + @retval EFI_SUCCESS The operation executes successfully. + @retval Others The operation fails. + +**/ +EFI_STATUS +DwMmcHcEnableInterrupt ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot + ); +#else +/** + Set all interrupt status bits in Normal and Error Interrupt Status Enable + register. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + + @retval EFI_SUCCESS The operation executes successfully. + @retval Others The operation fails. + +**/ +EFI_STATUS +DwMmcHcEnableInterrupt ( + IN UINTN DevBase + ); +#endif + +#ifdef DWMMC_PCI +/** + Get the capability data from the specified slot. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[out] Capability The buffer to store the capability data. + + @retval EFI_SUCCESS The operation executes successfully. + @retval Others The operation fails. + +**/ +EFI_STATUS +DwMmcHcGetCapability ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT DW_MMC_HC_SLOT_CAP *Capability + ); +#else +/** + Get the capability data from the specified slot. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[out] Capability The buffer to store the capability data. + + @retval EFI_SUCCESS The operation executes successfully. + @retval Others The operation fails. + +**/ +EFI_STATUS +DwMmcHcGetCapability ( + IN UINTN DevBase, + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT DW_MMC_HC_SLOT_CAP *Capability + ); +#endif + +#if 0 +/** + Get the maximum current capability data from the specified slot. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[out] MaxCurrent The buffer to store the maximum current capability data. + + @retval EFI_SUCCESS The operation executes successfully. + @retval Others The operation fails. + +**/ +EFI_STATUS +DwMmcHcGetMaxCurrent ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + OUT UINT64 *MaxCurrent + ); +#endif + +#ifdef DWMMC_PCI +/** + Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller + slot. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[out] MediaPresent The pointer to the media present boolean value. + + @retval EFI_SUCCESS There is no media change happened. + @retval EFI_MEDIA_CHANGED There is media change happened. + @retval Others The detection fails. + +**/ +EFI_STATUS +DwMmcHcCardDetect ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT BOOLEAN *MediaPresent + ); +#else +/** + Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller + slot. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[out] MediaPresent The pointer to the media present boolean value. + + @retval EFI_SUCCESS There is no media change happened. + @retval EFI_MEDIA_CHANGED There is media change happened. + @retval Others The detection fails. + +**/ +EFI_STATUS +DwMmcHcCardDetect ( + IN UINTN DevBase, + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT BOOLEAN *MediaPresent + ); +#endif + +#ifdef DWMMC_PCI +/** + Stop SD/MMC card clock. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + + @retval EFI_SUCCESS Succeed to stop SD/MMC clock. + @retval Others Fail to stop SD/MMC clock. + +**/ +EFI_STATUS +DwMmcHcStopClock ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot + ); + +/** + SD/MMC card clock supply. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[in] ClockFreq The max clock frequency to be set. The unit is KHz. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The clock is supplied successfully. + @retval Others The clock isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcClockSupply ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN UINT64 ClockFreq, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#else +/** + Stop SD/MMC card clock. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details. + + @param[in] DevIo The DEVICE IO protocol instance. + + @retval EFI_SUCCESS Succeed to stop SD/MMC clock. + @retval Others Fail to stop SD/MMC clock. + +**/ +EFI_STATUS +DwMmcHcStopClock ( + IN UINTN DevBase + ); + +/** + SD/MMC card clock supply. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] ClockFreq The max clock frequency to be set. The unit is KHz. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The clock is supplied successfully. + @retval Others The clock isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcClockSupply ( + IN UINTN DevBase, + IN UINT64 ClockFreq, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#endif + +#if 0 +/** + SD/MMC bus power control. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[in] PowerCtrl The value setting to the power control register. + + @retval TRUE There is a SD/MMC card attached. + @retval FALSE There is no a SD/MMC card attached. + +**/ +EFI_STATUS +DwMmcHcPowerControl ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN UINT8 PowerCtrl + ); +#endif + +#ifdef DWMMC_PCI +/** + Set the SD/MMC bus width. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8. + + @retval EFI_SUCCESS The bus width is set successfully. + @retval Others The bus width isn't set successfully. + +**/ +EFI_STATUS +DwMmcHcSetBusWidth ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN BOOLEAN IsDdr, + IN UINT16 BusWidth + ); +#else +/** + Set the SD/MMC bus width. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8. + + @retval EFI_SUCCESS The bus width is set successfully. + @retval Others The bus width isn't set successfully. + +**/ +EFI_STATUS +DwMmcHcSetBusWidth ( + IN UINTN DevBase, + IN BOOLEAN IsDdr, + IN UINT16 BusWidth + ); +#endif + +#ifdef DWMMC_PCI +/** + Supply SD/MMC card with lowest clock frequency at initialization. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The clock is supplied successfully. + @retval Others The clock isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcInitClockFreq ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#else +/** + Supply SD/MMC card with lowest clock frequency at initialization. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The clock is supplied successfully. + @retval Others The clock isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcInitClockFreq ( + IN UINTN DevBase, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#endif + +#ifdef DWMMC_PCI +/** + Supply SD/MMC card with maximum voltage at initialization. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The voltage is supplied successfully. + @retval Others The voltage isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcInitPowerVoltage ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#else +/** + Supply SD/MMC card with maximum voltage at initialization. + + Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The voltage is supplied successfully. + @retval Others The voltage isn't supplied successfully. + +**/ +EFI_STATUS +DwMmcHcInitPowerVoltage ( + IN UINTN DevBase, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#endif + +#ifdef DWMMC_PCI +/** + Initialize the Timeout Control register with most conservative value at initialization. + + Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + + @retval EFI_SUCCESS The timeout control register is configured successfully. + @retval Others The timeout control register isn't configured successfully. + +**/ +EFI_STATUS +DwMmcHcInitTimeoutCtrl ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot + ); +#else +/** + Initialize the Timeout Control register with most conservative value at initialization. + + Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + + @retval EFI_SUCCESS The timeout control register is configured successfully. + @retval Others The timeout control register isn't configured successfully. + +**/ +EFI_STATUS +DwMmcHcInitTimeoutCtrl ( + IN UINTN DevBase + ); +#endif + +#ifdef DWMMC_PCI +/** + Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value + at initialization. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] Slot The slot number of the SD card to send the command to. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The host controller is initialized successfully. + @retval Others The host controller isn't initialized successfully. + +**/ +EFI_STATUS +DwMmcHcInitHost ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 Slot, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#else +/** + Initial SD/MMC host controller with lowest clock frequency, max power and + max timeout value at initialization. + + @param[in] DevIo The DEVICE IO protocol instance. + @param[in] Capability The capability of the slot. + + @retval EFI_SUCCESS The host controller is initialized successfully. + @retval Others The host controller isn't initialized successfully. + +**/ +EFI_STATUS +DwMmcHcInitHost ( + IN UINTN DevBase, + IN DW_MMC_HC_SLOT_CAP Capability + ); +#endif + +#endif /* _DW_MMC_HCI_H_ */ diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/EmmcDevice.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/EmmcDevice.c new file mode 100644 index 0000000..2f3c550 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/EmmcDevice.c @@ -0,0 +1,1035 @@ +/** @file + This file provides some helper functions which are specific for EMMC device. + + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved. + Copyright (c) 2018, Linaro. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include + +#include "DwMmcHcDxe.h" + +#define EMMC_GET_STATE(x) (((x) >> 9) & 0xf) +#define EMMC_STATE_IDLE 0 +#define EMMC_STATE_READY 1 +#define EMMC_STATE_IDENT 2 +#define EMMC_STATE_STBY 3 +#define EMMC_STATE_TRAN 4 +#define EMMC_STATE_DATA 5 +#define EMMC_STATE_RCV 6 +#define EMMC_STATE_PRG 7 +#define EMMC_STATE_DIS 8 +#define EMMC_STATE_BTST 9 +#define EMMC_STATE_SLP 10 + +#define EMMC_CMD1_CAPACITY_LESS_THAN_2GB 0x00FF8080 // Capacity <= 2GB, byte addressing used +#define EMMC_CMD1_CAPACITY_GREATER_THAN_2GB 0x40FF8080 // Capacity > 2GB, 512-byte sector addressing used + +/** + Send command GO_IDLE_STATE (CMD0 with argument of 0x00000000) to the device to + make it go to Idle State. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Slot The slot number of the SD card to send the command + to. + + @retval EFI_SUCCESS The EMMC device is reset correctly. + @retval Others The device reset fails. + +**/ +EFI_STATUS +EmmcReset ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBc; + SdMmcCmdBlk.ResponseType = 0; + SdMmcCmdBlk.CommandArgument = 0; + + gBS->Stall (1000); + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SEND_OP_COND to the EMMC device to get the data of the OCR + register. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in, out] Argument On input, the argument of SEND_OP_COND is to send + to the device. + On output, the argument is the value of OCR + register. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcGetOcr ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN OUT UINT32 *Argument + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3; + SdMmcCmdBlk.CommandArgument = *Argument; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (!EFI_ERROR (Status)) { + // + // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12. + // + *Argument = SdMmcStatusBlk.Resp0; + } + + return Status; +} + +/** + Broadcast command ALL_SEND_CID to the bus to ask all the EMMC devices to send + the data of their CID registers. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcGetAllCid ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2; + SdMmcCmdBlk.CommandArgument = 0; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SET_RELATIVE_ADDR to the EMMC device to assign a Relative device + Address (RCA). + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address to be assigned. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSetRca ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SEND_CSD to the EMMC device to get the data of the CSD register. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of selected device. + @param[out] Csd The buffer to store the content of the CSD register. + Note the caller should ignore the lowest byte of + this buffer as the content of this byte is + meaningless even if the operation succeeds. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcGetCsd ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + OUT EMMC_CSD *Csd + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_SEND_CSD; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (!EFI_ERROR (Status)) { + // + // Copy 128bit data for CSD structure. + // + CopyMem ((VOID *)Csd + 1, &SdMmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1); + } + + return Status; +} + +/** + Send command SELECT_DESELECT_CARD to the EMMC device to select/deselect it. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of selected device. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSelect ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SEND_EXT_CSD to the EMMC device to get the data of the EXT_CSD + register. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[out] ExtCsd The buffer to store the content of the EXT_CSD + register. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcGetExtCsd ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + OUT EMMC_EXT_CSD *ExtCsd + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = 0x00000000; + + Packet.InDataBuffer = ExtCsd; + Packet.InTransferLength = sizeof (EMMC_EXT_CSD); + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + return Status; +} + +/** + Send command SWITCH to the EMMC device to switch the mode of operation of the + selected Device or modifies the EXT_CSD registers. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Access The access mode of SWTICH command. + @param[in] Index The offset of the field to be access. + @param[in] Value The value to be set to the specified field of + EXT_CSD register. + @param[in] CmdSet The value of CmdSet field of EXT_CSD register. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSwitch ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 Access, + IN UINT8 Index, + IN UINT8 Value, + IN UINT8 CmdSet + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_SWITCH; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b; + SdMmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | \ + (Value << 8) | CmdSet; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SEND_STATUS to the addressed EMMC device to get its status + register. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of addressed device. + @param[out] DevStatus The returned device status. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSendStatus ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + OUT UINT32 *DevStatus + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_SEND_STATUS; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (!EFI_ERROR (Status)) { + *DevStatus = SdMmcStatusBlk.Resp0; + } + + return Status; +} + +/** + Send command SEND_TUNING_BLOCK to the EMMC device for HS200 optimal sampling + point detection. + + It may be sent up to 40 times until the host finishes the tuning procedure. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] BusWidth The bus width to work. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSendTuningBlk ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 BusWidth + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + UINT8 TuningBlock[128]; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = 0; + + Packet.InDataBuffer = TuningBlock; + if (BusWidth == 8) { + Packet.InTransferLength = sizeof (TuningBlock); + } else { + Packet.InTransferLength = 64; + } + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Tunning the clock to get HS200 optimal sampling point. + + Command SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes + the tuning procedure. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8. + + @param[in] DevIo A pointer to the EFI_DEVICE_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] BusWidth The bus width to work. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcTuningClkForHs200 ( + IN UINTN DevBase, + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 BusWidth + ) +{ + return EFI_SUCCESS; +} + +/** + Switch the bus width to specified width. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.9. + + @param[in] DevIo A pointer to the EFI_DEVICE_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address to be assigned. + @param[in] IsDdr If TRUE, use dual data rate data simpling method. + Otherwise use single data rate data simpling method. + @param[in] BusWidth The bus width to be set, it could be 4 or 8. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSwitchBusWidth ( + IN UINTN DevBase, + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + IN BOOLEAN IsDdr, + IN UINT8 BusWidth + ) +{ + EFI_STATUS Status; + UINT8 Access; + UINT8 Index; + UINT8 Value; + UINT8 CmdSet; + UINT32 DevStatus; + + // + // Write Byte, the Value field is written into the byte pointed by Index. + // + Access = 0x03; + Index = OFFSET_OF (EMMC_EXT_CSD, BusWidth); + if (BusWidth == 1) { + Value = 0; + } else { + if (BusWidth == 4) { + Value = 1; + } else if (BusWidth == 8) { + Value = 2; + } else { + return EFI_INVALID_PARAMETER; + } + + if (IsDdr) { + Value += 4; + } + } + + CmdSet = 0; + Status = EmmcSwitch (PassThru, Access, Index, Value, CmdSet); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "EmmcSwitchBusWidth: Switch to bus width %d fails with %r\n", + BusWidth, + Status + )); + return Status; + } + + do { + Status = EmmcSendStatus (PassThru, Rca, &DevStatus); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "EmmcSwitchBusWidth: Send status fails with %r\n", + Status + )); + return Status; + } + // + // Check the switch operation is really successful or not. + // + } while ((DevStatus & 0xf) == EMMC_STATE_PRG); + + Status = DwMmcHcSetBusWidth (DevBase, IsDdr, BusWidth); + if (EFI_ERROR (Status)) { + return Status; + } + + return Status; +} + +/** + Switch the clock frequency to the specified value. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.6. + + @param[in] DevIo A pointer to the EFI_DEVICE_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address to be assigned. + @param[in] HsTiming The value to be written to HS_TIMING field of + EXT_CSD register. + @param[in] ClockFreq The max clock frequency to be set, the unit is MHz. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSwitchClockFreq ( + IN UINTN DevBase, + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + IN UINT8 HsTiming, + IN UINT32 ClockFreq + ) +{ + EFI_STATUS Status; + UINT8 Access; + UINT8 Index; + UINT8 Value; + UINT8 CmdSet; + UINT32 DevStatus; + DW_MMC_HC_PRIVATE_DATA *Private; + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (PassThru); + // + // Write Byte, the Value field is written into the byte pointed by Index. + // + Access = 0x03; + Index = OFFSET_OF (EMMC_EXT_CSD, HsTiming); + Value = HsTiming; + CmdSet = 0; + + Status = EmmcSwitch (PassThru, Access, Index, Value, CmdSet); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "EmmcSwitchClockFreq: Switch to hstiming %d fails with %r\n", + HsTiming, + Status + )); + return Status; + } + + Status = EmmcSendStatus (PassThru, Rca, &DevStatus); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "EmmcSwitchClockFreq: Send status fails with %r\n", + Status + )); + return Status; + } + // + // Check the switch operation is really successful or not. + // + if ((DevStatus & BIT7) != 0) { + DEBUG (( + DEBUG_ERROR, + "EmmcSwitchClockFreq: The switch operation fails as DevStatus 0x%08x\n", + DevStatus + )); + return EFI_DEVICE_ERROR; + } + // + // Convert the clock freq unit from MHz to KHz. + // + Status = DwMmcHcClockSupply (DevBase, ClockFreq * 1000, Private->Capability[0]); + + return Status; +} + +/** + Switch to the High Speed timing according to request. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8. + + @param[in] DevIo A pointer to the EFI_DEVICE_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address to be assigned. + @param[in] ClockFreq The max clock frequency to be set. + @param[in] IsDdr If TRUE, use dual data rate data simpling method. + Otherwise use single data rate data simpling method. + @param[in] BusWidth The bus width to be set, it could be 4 or 8. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSwitchToHighSpeed ( + IN UINTN DevBase, + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + IN UINT32 ClockFreq, + IN BOOLEAN IsDdr, + IN UINT8 BusWidth + ) +{ + EFI_STATUS Status; + UINT8 HsTiming; + + HsTiming = 1; + Status = EmmcSwitchClockFreq (DevBase, PassThru, Rca, HsTiming, ClockFreq); + if (EFI_ERROR (Status)) { + return Status; + } + Status = EmmcSwitchBusWidth (DevBase, PassThru, Rca, IsDdr, BusWidth); + if (EFI_ERROR (Status)) { + return Status; + } + return EFI_SUCCESS; +} + +/** + Switch to the HS200 timing according to request. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8. + + @param[in] DevIo A pointer to the EFI_DEVICE_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address to be assigned. + @param[in] ClockFreq The max clock frequency to be set. + @param[in] BusWidth The bus width to be set, it could be 4 or 8. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSwitchToHS200 ( + IN UINTN DevBase, + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + IN UINT32 ClockFreq, + IN UINT8 BusWidth + ) +{ + return EFI_SUCCESS; +} + +/** + Switch the high speed timing according to request. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8. + + @param[in] DevIo A pointer to the EFI_DEVICE_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address to be assigned. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +EmmcSetBusMode ( + IN UINTN DevBase, + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca + ) +{ + EFI_STATUS Status; + EMMC_CSD Csd; + EMMC_EXT_CSD ExtCsd; + UINT8 HsTiming; + BOOLEAN IsDdr; + UINT32 DevStatus; + UINT32 ClockFreq; + UINT8 BusWidth; + DW_MMC_HC_PRIVATE_DATA *Private; + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (PassThru); + ASSERT (Private->Capability[0].BaseClkFreq != 0); + + Status = EmmcGetCsd (PassThru, Rca, &Csd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetCsd fails with %r\n", Status)); + return Status; + } + + Status = EmmcSelect (PassThru, Rca); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: Select fails with %r\n", Status)); + return Status; + } + + do { + Status = EmmcSendStatus (PassThru, Rca, &DevStatus); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "EmmcSetBusMode: Get Status fails with %r\n", + Status + )); + return Status; + } + } while (EMMC_GET_STATE (DevStatus) != EMMC_STATE_TRAN); + + BusWidth = 1; + Status = EmmcSwitchBusWidth (DevBase, PassThru, Rca, FALSE, BusWidth); + if (EFI_ERROR (Status)) { + return Status; + } + + BusWidth = Private->Capability[0].BusWidth; + // + // Get Deivce_Type from EXT_CSD register. + // + Status = EmmcGetExtCsd (PassThru, &ExtCsd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetExtCsd fails with %r\n", Status)); + return Status; + } + + // + // Calculate supported bus speed/bus width/clock frequency. + // + HsTiming = 0; + IsDdr = FALSE; + ClockFreq = 0; + if (((ExtCsd.DeviceType & (BIT4 | BIT5)) != 0) && + (Private->Capability[0].Sdr104 != 0)) { + HsTiming = 2; + IsDdr = FALSE; + ClockFreq = 200; + } else if (((ExtCsd.DeviceType & (BIT2 | BIT3)) != 0) && + (Private->Capability[0].Ddr50 != 0)) { + HsTiming = 1; + IsDdr = TRUE; + ClockFreq = 52; + } else if (((ExtCsd.DeviceType & BIT1) != 0) && + (Private->Capability[0].HighSpeed != 0)) { + HsTiming = 1; + IsDdr = FALSE; + ClockFreq = 52; + } else if (((ExtCsd.DeviceType & BIT0) != 0) && + (Private->Capability[0].HighSpeed != 0)) { + HsTiming = 1; + IsDdr = FALSE; + ClockFreq = 26; + } + + if ((ClockFreq == 0) || (HsTiming == 0)) { + // + // Continue using default setting. + // + return EFI_SUCCESS; + } + + DEBUG (( + DEBUG_INFO, + "EmmcSetBusMode: HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", + HsTiming, + ClockFreq, + BusWidth, + IsDdr ? "TRUE" : "FALSE" + )); + + if (HsTiming == 2) { + // + // Execute HS200 timing switch procedure + // + Status = EmmcSwitchToHS200 (DevBase, PassThru, Rca, ClockFreq, BusWidth); + } else { + // + // Execute High Speed timing switch procedure + // + Status = EmmcSwitchToHighSpeed ( + DevBase, + PassThru, + Rca, + ClockFreq, + IsDdr, + BusWidth + ); + } + + DEBUG (( + DEBUG_INFO, + "EmmcSetBusMode: Switch to %a %r\n", + (HsTiming == 3) ? "HS400" : ((HsTiming == 2) ? "HS200" : "HighSpeed"), + Status + )); + + return Status; +} + +/** + Execute EMMC device identification procedure. + + Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. + + @param[in] Private A pointer to the DW_MMC_HC_PRIVATE_DATA instance. + + @retval EFI_SUCCESS There is a EMMC card. + @retval Others There is not a EMMC card. + +**/ +EFI_STATUS +EmmcIdentification ( + IN DW_MMC_HC_PRIVATE_DATA *Private + ) +{ + EFI_STATUS Status; + UINTN DevBase; + EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru; + UINT32 Ocr; + UINT16 Rca; + UINT32 DevStatus; + UINT32 Timeout; + + DevBase = Private->DevBase; + PassThru = &Private->PassThru; + + Status = EmmcReset (PassThru); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "EmmcIdentification: Executing Cmd0 fails with %r\n", + Status + )); + return Status; + } + + Timeout = 100; + do { + Ocr = EMMC_CMD1_CAPACITY_GREATER_THAN_2GB; + Status = EmmcGetOcr (PassThru, &Ocr); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "EmmcIdentification: Executing Cmd1 fails with %r\n", + Status + )); + return Status; + } + if (--Timeout <= 0) { + return EFI_DEVICE_ERROR; + } + MicroSecondDelay (100); + } while ((Ocr & BIT31) == 0); + + Status = EmmcGetAllCid (PassThru); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "EmmcIdentification: Executing Cmd2 fails with %r\n", + Status + )); + return Status; + } + // + // valid RCA starts from 1. + // Here we takes a simple formula to calculate the RCA. + // Don't support multiple devices on the slot, that is + // shared bus slot feature. + // + Rca = 1; + Status = EmmcSetRca (PassThru, Rca); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "EmmcIdentification: Executing Cmd3 fails with %r\n", + Status + )); + return Status; + } + // + // Enter Data Tranfer Mode. + // + DEBUG (( + DEBUG_INFO, + "EmmcIdentification: Found a EMMC device at RCA [%d]\n", + Rca + )); + Private->Slot[0].CardType = EmmcCardType; + + Status = EmmcSetBusMode (DevBase, PassThru, Rca); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Exit DATA Mode. + // + do { + Status = EmmcSendStatus (PassThru, Rca, &DevStatus); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "EmmcSwitchBusWidth: Send status fails with %r\n", + Status + )); + return Status; + } + } while ((DevStatus & 0xf) == EMMC_STATE_DATA); + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/SdDevice.c b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/SdDevice.c new file mode 100644 index 0000000..3523b90 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Drivers/DwMmcHcDxe/SdDevice.c @@ -0,0 +1,1110 @@ +/** @file + This file provides some helper functions which are specific for SD card + device. + + Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved. + Copyright (c) 2018, Linaro. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include "DwMmcHcDxe.h" + +/** + Send command GO_IDLE_STATE to the device to make it go to Idle State. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + + @retval EFI_SUCCESS The SD device is reset correctly. + @retval Others The device reset fails. + +**/ +EFI_STATUS +SdCardReset ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_GO_IDLE_STATE; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBc; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + //Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SEND_IF_COND to the device to inquiry the SD Memory Card + interface condition. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] SupplyVoltage The supplied voltage by the host. + @param[in] CheckPattern The check pattern to be sent to the device. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardVoltageCheck ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 SupplyVoltage, + IN UINT8 CheckPattern + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_SEND_IF_COND; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR7; + SdMmcCmdBlk.CommandArgument = (SupplyVoltage << 8) | CheckPattern; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + if (!EFI_ERROR (Status)) { + if (SdMmcStatusBlk.Resp0 != SdMmcCmdBlk.CommandArgument) { + return EFI_DEVICE_ERROR; + } + } + + return Status; +} + +/** + Send command SDIO_SEND_OP_COND to the device to see whether it is SDIO device. + + Refer to SDIO Simplified Spec 3 Section 3.2 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] VoltageWindow The supply voltage window. + @param[in] S18R The boolean to show if it should switch to 1.8v. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdioSendOpCond ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT32 VoltageWindow, + IN BOOLEAN S18R + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + UINT32 Switch; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SDIO_SEND_OP_COND; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR4; + + Switch = S18R ? BIT24 : 0; + + SdMmcCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SD_SEND_OP_COND to the device to see whether it is SDIO device. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of addressed device. + @param[in] VoltageWindow The supply voltage window. + @param[in] S18R The boolean to show if it should switch to 1.8v. + @param[in] Xpc The boolean to show if it should provide 0.36w + power control. + @param[in] Hcs The boolean to show if it support host capacity + info. + @param[out] Ocr The buffer to store returned OCR register value. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSendOpCond ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + IN UINT32 VoltageWindow, + IN BOOLEAN S18R, + IN BOOLEAN Xpc, + IN BOOLEAN Hcs, + OUT UINT32 *Ocr + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + UINT32 Switch; + UINT32 MaxPower; + UINT32 HostCapacity; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_APP_CMD; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + SdMmcCmdBlk.CommandIndex = SD_SEND_OP_COND; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR3; + + Switch = S18R ? BIT24 : 0; + MaxPower = Xpc ? BIT28 : 0; + HostCapacity = Hcs ? BIT30 : 0; + + SdMmcCmdBlk.CommandArgument = (VoltageWindow & 0xFFFFFF) | Switch | \ + MaxPower | HostCapacity; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (!EFI_ERROR (Status)) { + *Ocr = SdMmcStatusBlk.Resp0; + } + + return Status; +} + +/** + Broadcast command ALL_SEND_CID to the bus to ask all the SD devices to send + the data of their CID registers. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardAllSendCid ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_ALL_SEND_CID; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SET_RELATIVE_ADDR to the SD device to assign a Relative device + Address (RCA). + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[out] Rca The relative device address to assign. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSetRca ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + OUT UINT16 *Rca + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_SET_RELATIVE_ADDR; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeBcr; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR6; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (!EFI_ERROR (Status)) { + *Rca = (UINT16)(SdMmcStatusBlk.Resp0 >> 16); + } + + return Status; +} + +/** + Send command SEND_CSD to the SD device to get the data of the CSD register. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of selected device. + @param[out] Csd The buffer to store the content of the CSD register. + Note the caller should ignore the lowest byte of + this buffer as the content of this byte is meaning- + less even if the operation succeeds. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardGetCsd ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + OUT SD_CSD *Csd + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_SEND_CSD; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (!EFI_ERROR (Status)) { + CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (SD_CSD) - 1); + } + + return Status; +} + +/** + Send command SEND_CSD to the SD device to get the data of the CSD register. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of selected device. + @param[out] Scr The buffer to store the content of the SCR register. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardGetScr ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + OUT SD_SCR *Scr + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_APP_CMD; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + SdMmcCmdBlk.CommandIndex = SD_SEND_SCR; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + + Packet.InDataBuffer = Scr; + Packet.InTransferLength = sizeof (SD_SCR); + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SELECT_DESELECT_CARD to the SD device to select/deselect it. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of selected device. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSelect ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_SELECT_DESELECT_CARD; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + if (Rca != 0) { + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1b; + } + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command VOLTAGE_SWITCH to the SD device to switch the voltage of the + device. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardVoltageSwitch ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_VOLTAGE_SWITCH; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = 0; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SET_BUS_WIDTH to the SD device to set the bus width. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of addressed device. + @param[in] BusWidth The bus width to be set, it could be 1 or 4. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSetBusWidth ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + IN UINT8 BusWidth + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + UINT8 Value; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_APP_CMD; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + SdMmcCmdBlk.CommandIndex = SD_SET_BUS_WIDTH; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + + if (BusWidth == 1) { + Value = 0; + } else if (BusWidth == 4) { + Value = 2; + } else { + return EFI_INVALID_PARAMETER; + } + + SdMmcCmdBlk.CommandArgument = Value & 0x3; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + return Status; +} + +/** + Send command SWITCH_FUNC to the SD device to check switchable function or + switch card function. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] AccessMode The value for access mode group. + @param[in] CommandSystem The value for command set group. + @param[in] DriveStrength The value for drive length group. + @param[in] PowerLimit The value for power limit group. + @param[in] Mode Switch or check function. + @param[out] SwitchResp The return switch function status. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSwitch ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT8 AccessMode, + IN UINT8 CommandSystem, + IN UINT8 DriveStrength, + IN UINT8 PowerLimit, + IN BOOLEAN Mode, + OUT UINT8 *SwitchResp + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + UINT32 ModeValue; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_SWITCH_FUNC; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + + ModeValue = Mode ? BIT31 : 0; + SdMmcCmdBlk.CommandArgument = (AccessMode & 0xF) | \ + ((PowerLimit & 0xF) << 4) | \ + ((DriveStrength & 0xF) << 8) | \ + ((DriveStrength & 0xF) << 12) | \ + ModeValue; + + Packet.InDataBuffer = SwitchResp; + Packet.InTransferLength = 64; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Send command SEND_STATUS to the addressed SD device to get its status + register. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address of addressed device. + @param[out] DevStatus The returned device status. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSendStatus ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + OUT UINT32 *DevStatus + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_SEND_STATUS; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16; + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + if (!EFI_ERROR (Status)) { + *DevStatus = SdMmcStatusBlk.Resp0; + } + + return Status; +} + +/** + Send command SEND_TUNING_BLOCK to the SD device for HS200 optimal sampling + point detection. + + It may be sent up to 40 times until the host finishes the tuning procedure. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSendTuningBlk ( + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru + ) +{ + EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk; + EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk; + EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; + EFI_STATUS Status; + UINT8 TuningBlock[64]; + + ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); + ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); + ZeroMem (&Packet, sizeof (Packet)); + + Packet.SdMmcCmdBlk = &SdMmcCmdBlk; + Packet.SdMmcStatusBlk = &SdMmcStatusBlk; + Packet.Timeout = DW_MMC_HC_GENERIC_TIMEOUT; + + SdMmcCmdBlk.CommandIndex = SD_SEND_TUNING_BLOCK; + SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc; + SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1; + SdMmcCmdBlk.CommandArgument = 0; + + Packet.InDataBuffer = TuningBlock; + Packet.InTransferLength = sizeof (TuningBlock); + + Status = PassThru->PassThru (PassThru, 0, &Packet, NULL); + + return Status; +} + +/** + Switch the bus width to specified width. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 and + SD Host Controller Simplified Spec 3.0 section Figure 3-7 for details. + + @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address to be assigned. + @param[in] BusWidth The bus width to be set, it could be 4 or 8. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSwitchBusWidth ( + IN UINTN DevBase, + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + IN BOOLEAN IsDdr, + IN UINT8 BusWidth + ) +{ + EFI_STATUS Status; + UINT32 DevStatus; + + Status = SdCardSetBusWidth (PassThru, Rca, BusWidth); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardSwitchBusWidth: Switch to bus width %d fails with %r\n", + BusWidth, + Status + )); + return Status; + } + + Status = SdCardSendStatus (PassThru, Rca, &DevStatus); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardSwitchBusWidth: Send status fails with %r\n", + Status + )); + return Status; + } + // + // Check the switch operation is really successful or not. + // + if ((DevStatus >> 16) != 0) { + DEBUG (( + DEBUG_ERROR, + "SdCardSwitchBusWidth: The switch operation fails as DevStatus 0x%08x\n", + DevStatus + )); + return EFI_DEVICE_ERROR; + } + + Status = DwMmcHcSetBusWidth (DevBase, IsDdr, BusWidth); + + return Status; +} + +/** + Switch the high speed timing according to request. + + Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. + + @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL + instance. + @param[in] Rca The relative device address to be assigned. + @param[in] S18A The boolean to show if it's a UHS-I SD card. + @param[in] BusWidths The bus width of the SD card. + @param[in] SdVersion1 The boolean to show if it's a Version 1 SD card. + + @retval EFI_SUCCESS The operation is done correctly. + @retval Others The operation fails. + +**/ +EFI_STATUS +SdCardSetBusMode ( + IN UINTN DevBase, + IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, + IN UINT16 Rca, + IN BOOLEAN S18A, + IN UINT32 BusWidths, + IN BOOLEAN SdVersion1 + ) +{ + EFI_STATUS Status; + DW_MMC_HC_SLOT_CAP *Capability; + UINT32 ClockFreq; + UINT8 AccessMode; + UINT8 SwitchResp[64]; + DW_MMC_HC_PRIVATE_DATA *Private; + BOOLEAN IsDdr; + + Private = DW_MMC_HC_PRIVATE_FROM_THIS (PassThru); + + Capability = &Private->Capability[0]; + + if ((Capability->BusWidth == 1) || (Capability->BusWidth == 4)) { + BusWidths &= Capability[0].BusWidth; + } else { + DEBUG (( + DEBUG_ERROR, + "SdCardSetBusMode: BusWidths (%d) in capability are wrong\n", + Capability->BusWidth + )); + return EFI_INVALID_PARAMETER; + } + + if (BusWidths == 0) { + DEBUG (( + DEBUG_ERROR, + "SdCardSetBusMode: Get wrong BusWidths:%d\n", + BusWidths + )); + return EFI_INVALID_PARAMETER; + } + + if (Private->Capability[0].Ddr50) { + IsDdr = TRUE; + } else { + IsDdr = FALSE; + } + + Status = SdCardSwitchBusWidth (DevBase, PassThru, Rca, IsDdr, BusWidths); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardSetBusMode: Executing SdCardSwitchBusWidth fails with %r\n", + Status + )); + return Status; + } + + // + // Get the supported bus speed from SWITCH cmd return data group #1. + // SdVersion1 doesn't support the SWITCH cmd. + // + if (!SdVersion1) { + Status = SdCardSwitch (PassThru, 0xF, 0xF, 0xF, 0xF, FALSE, SwitchResp); + if (EFI_ERROR (Status)) { + return Status; + } + } + // + // Calculate supported bus speed/bus width/clock frequency by host and device + // capability. + // + ClockFreq = 0; + if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) { + ClockFreq = 208; + AccessMode = 3; + } else if (S18A && (Capability->Sdr50 != 0) && + ((SwitchResp[13] & BIT2) != 0)) { + ClockFreq = 100; + AccessMode = 2; + } else if (S18A && (Capability->Ddr50 != 0) && + ((SwitchResp[13] & BIT4) != 0)) { + ClockFreq = 50; + AccessMode = 4; + } else if ((SwitchResp[13] & BIT1) != 0) { + ClockFreq = 50; + AccessMode = 1; + } else { + ClockFreq = 25; + AccessMode = 0; + } + + // + // SdVersion1 doesn't support the SWITCH cmd. + // + if (!SdVersion1) { + Status = SdCardSwitch (PassThru, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp); + if (EFI_ERROR (Status)) { + return Status; + } + } + + if ((SwitchResp[16] & 0xF) != AccessMode) { + DEBUG (( + DEBUG_ERROR, + "SdCardSetBusMode: Switch to AccessMode %d ClockFreq %d fails! The Switch response is 0x%1x\n", + AccessMode, + ClockFreq, + SwitchResp[16] & 0xF + )); + return EFI_DEVICE_ERROR; + } + + DEBUG (( + DEBUG_INFO, + "SdCardSetBusMode: Switch to AccessMode %d ClockFreq %d \n", + AccessMode, + ClockFreq + )); + + Status = DwMmcHcClockSupply (DevBase, ClockFreq * 1000, *Capability); + if (EFI_ERROR (Status)) { + return Status; + } + + return Status; +} + +EFI_STATUS +SdCardIdentification ( + IN DW_MMC_HC_PRIVATE_DATA *Private + ) +{ + EFI_STATUS Status; + UINTN DevBase; + EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru; + UINT32 Ocr; + UINT16 Rca; + BOOLEAN Xpc; + BOOLEAN S18r; + UINT64 MaxCurrent; + SD_SCR Scr; + SD_CSD Csd; + BOOLEAN SdVersion1; + + DevBase = Private->DevBase; + PassThru = &Private->PassThru; + SdVersion1 = FALSE; + // + // 1. Send Cmd0 to the device + // + Status = SdCardReset (PassThru); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "SdCardIdentification: Executing Cmd0 fails with %r\n", + Status + )); + return Status; + } + MicroSecondDelay (10000); + // + // 2. Send Cmd8 to the device + // + Status = SdCardVoltageCheck (PassThru, 0x1, 0xFF); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "SdCardIdentification: Executing Cmd8 fails with %r\n", + Status + )); + SdVersion1 = TRUE; + } + // + // 3. Send Acmd41 with voltage window 0 to the device + // + Status = SdCardSendOpCond (PassThru, 0, 0, FALSE, FALSE, FALSE, &Ocr); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_INFO, + "SdCardIdentification: Executing SdCardSendOpCond fails with %r\n", + Status + )); + return EFI_DEVICE_ERROR; + } + + if (Private->Capability[0].Voltage33 != 0) { + // + // Support 3.3V + // + MaxCurrent = ((UINT32)Private->MaxCurrent[0] & 0xFF) * 4; + S18r = FALSE; + } else if (Private->Capability[0].Voltage30 != 0) { + // + // Support 3.0V + // + MaxCurrent = (((UINT32)Private->MaxCurrent[0] >> 8) & 0xFF) * 4; + S18r = FALSE; + } else if (Private->Capability[0].Voltage18 != 0) { + // + // Support 1.8V + // + MaxCurrent = (((UINT32)Private->MaxCurrent[0] >> 16) & 0xFF) * 4; + S18r = TRUE; + } else { + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + + if (MaxCurrent >= 150) { + Xpc = TRUE; + } else { + Xpc = FALSE; + } + + // + // 4. Repeatly send Acmd41 with supply voltage window to the device. + // Note here we only support the cards complied with SD physical + // layer simplified spec version 2.0 and version 3.0 and above. + // + do { + Status = SdCardSendOpCond (PassThru, 0, Ocr, S18r, Xpc, TRUE, &Ocr); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardIdentification: SdCardSendOpCond fails with %r Ocr %x, S18r %x, Xpc %x\n", + Status, + Ocr, + S18r, + Xpc + )); + return EFI_DEVICE_ERROR; + } + } while ((Ocr & BIT31) == 0); + + Status = SdCardAllSendCid (PassThru); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardIdentification: Executing SdCardAllSendCid fails with %r\n", + Status + )); + return Status; + } + + Status = SdCardSetRca (PassThru, &Rca); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardIdentification: Executing SdCardSetRca fails with %r\n", + Status + )); + return Status; + } + + Status = SdCardGetCsd (PassThru, Rca, &Csd); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardIdentification: Executing SdCardGetCsd fails with %r\n", + Status + )); + return Status; + } + + Status = SdCardSelect (PassThru, Rca); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardIdentification: Selecting card fails with %r\n", + Status + )); + return Status; + } + + Status = SdCardGetScr (PassThru, Rca, &Scr); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "SdCardIdentification: Executing SdCardGetScr fails with %r\n", + Status + )); + return Status; + } + + // + // Enter Data Tranfer Mode. + // + DEBUG ((DEBUG_INFO, "SdCardIdentification: Found a SD device\n")); + Private->Slot[0].CardType = SdCardType; + + Status = SdCardSetBusMode (DevBase, PassThru, Rca, S18r, Scr.SdBusWidths, SdVersion1); + if (EFI_ERROR (Status)) { + return Status; + } + + Private->Slot[0].Initialized = TRUE; + + return Status; +} diff --git a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Include/Protocol/PlatformDwMmc.h b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Include/Protocol/PlatformDwMmc.h new file mode 100644 index 0000000..eac05ff --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Silicon/Synopsys/DesignWare/Include/Protocol/PlatformDwMmc.h @@ -0,0 +1,73 @@ +/** @file + + Copyright (c) 2018, Linaro. All rights reserved. + Copyright (c) 2021, Intel Corporation. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PLATFORM_DW_MMC_H__ +#define __PLATFORM_DW_MMC_H__ + +typedef enum { + RemovableSlot, + EmbeddedSlot, + SharedBusSlot, + UnknownSlot +} EFI_SD_MMC_SLOT_TYPE; + +typedef enum { + UnknownCardType, + SdCardType, + SdioCardType, + MmcCardType, + EmmcCardType +} SD_MMC_CARD_TYPE; + +typedef struct { + UINT32 DefaultSpeed:1; // bit 0 + UINT32 HighSpeed:1; // bit 1 + UINT32 Sdr12:1; // bit 2 + UINT32 Sdr25:1; // bit 3 + UINT32 Sdr50:1; // bit 4 + UINT32 Sdr104:1; // bit 5 + UINT32 Ddr50:1; // bit 6 + UINT32 SysBus64:1; // bit 7 + UINT32 BusWidth:4; // bit 11:8 + UINT32 SlotType:2; // bit 13:12 + UINT32 CardType:3; // bit 16:14 + UINT32 Voltage18:1; // bit 17 + UINT32 Voltage30:1; // bit 18 + UINT32 Voltage33:1; // bit 19 + UINT32 BaseClkFreq; + EFI_HANDLE Controller; +} DW_MMC_HC_SLOT_CAP; + +// +// Protocol interface structure +// +typedef struct _PLATFORM_DW_MMC_PROTOCOL PLATFORM_DW_MMC_PROTOCOL; + +typedef +EFI_STATUS +(EFIAPI *PLATFORM_DW_MMC_GET_CAPABILITY) ( + IN EFI_HANDLE Controller, + IN UINT8 Slot, + OUT DW_MMC_HC_SLOT_CAP *Capability + ); + +typedef +BOOLEAN +(EFIAPI *PLATFORM_DW_MMC_CARD_DETECT) ( + IN EFI_HANDLE Controller, + IN UINT8 Slot + ); + +struct _PLATFORM_DW_MMC_PROTOCOL { + PLATFORM_DW_MMC_GET_CAPABILITY GetCapability; + PLATFORM_DW_MMC_CARD_DETECT CardDetect; +}; + +extern EFI_GUID gPlatformDwMmcProtocolGuid; + +#endif /* __PLATFORM_DW_MMC_H__ */ diff --git a/local/UEFI/edk2-rk3588-master/misc/extractbl31.py b/local/UEFI/edk2-rk3588-master/misc/extractbl31.py new file mode 100755 index 0000000..4a96807 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/misc/extractbl31.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# +# Script to extract PT_LOAD segments from bl31.elf. Derived from +# Rockchip's make_fit_atf.py + +import os +import sys + +# pip3 install pyelftools / apt install python3-pyelftools +from elftools.elf.elffile import ELFFile +from elftools.elf.sections import SymbolTableSection +from elftools.elf.segments import Segment, InterpSegment, NoteSegment + +ELF_SEG_P_TYPE='p_type' +ELF_SEG_P_PADDR='p_paddr' + +def generate_atf_binary(bl31_file_name): + with open(bl31_file_name, "rb") as bl31_file: + bl31 = ELFFile(bl31_file) + + num = bl31.num_segments() + for i in range(num): + seg = bl31.get_segment(i) + if ('PT_LOAD' == seg.__getitem__(ELF_SEG_P_TYPE)): + paddr = seg.__getitem__(ELF_SEG_P_PADDR) + file_name = 'bl31_0x%08x.bin' % paddr + with open(file_name, "wb") as atf: + atf.write(seg.data()); + +generate_atf_binary(sys.argv[1]) diff --git a/local/UEFI/edk2-rk3588-master/misc/repack.sh b/local/UEFI/edk2-rk3588-master/misc/repack.sh new file mode 100755 index 0000000..90a5a41 --- /dev/null +++ b/local/UEFI/edk2-rk3588-master/misc/repack.sh @@ -0,0 +1,34 @@ +#!/bin/bash + +# Used to pack any executable into a complete flash image + +function _fit_repack(){ + mkdir -p ${WORKSPACE}/unpack + + cp ${REPACK_FILE} ${WORKSPACE}/unpack/uboot + cp ${ROOTDIR}/misc/prebuilts/uboot_uefi.img ${WORKSPACE}/ + + pushd ${ROOTDIR}/../git/u-boot + ./scripts/fit-repack.sh -f ${WORKSPACE}/uboot_uefi.img -d ${WORKSPACE}/unpack/ + popd +} + +function _pack(){ + _fit_repack + + echo "****Build 8MB NOR FLASH IMAGE****" + + # FIT Image at 0x100000 + dd if=${WORKSPACE}/uboot_uefi.img of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024 + + cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/ + echo "Build done: RK3588_NOR_FLASH.img" +} + +ROOTDIR="$(realpath "$(dirname "$0")")/.." +cd "${ROOTDIR}"||exit 1 +REPACK_FILE=${1} +export ROOTDIR REPACK_FILE +WORKSPACE="${ROOTDIR}/workspace" + +_pack diff --git a/local/UEFI/edk2-rk3588-master/misc/rk3588_spi_nor_gpt.img b/local/UEFI/edk2-rk3588-master/misc/rk3588_spi_nor_gpt.img new file mode 100644 index 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+ type = "standalone"; + arch = "arm64"; + os = "U-Boot"; + compression = "none"; + load = <0x00200000>; + hash { + algo = "sha256"; + }; + }; + atf-1 { + description = "ARM Trusted Firmware"; + data = /incbin/("./bl31_0x00040000.bin"); + type = "firmware"; + arch = "arm64"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <0x00040000>; + hash { + algo = "sha256"; + }; + }; + atf-2 { + description = "ARM Trusted Firmware"; + data = /incbin/("./bl31_0x000f0000.bin"); + type = "firmware"; + arch = "arm64"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <0x000f0000>; + hash { + algo = "sha256"; + }; + }; + atf-3 { + description = "ARM Trusted Firmware"; + data = /incbin/("./bl31_0xff100000.bin"); + type = "firmware"; + arch = "arm64"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <0xff100000>; + hash { + algo = "sha256"; + }; + }; + optee { + description = "OP-TEE"; + data = /incbin/("./bl32.bin"); + type = "firmware"; + arch = "arm64"; + os = "op-tee"; + compression = "none"; + load = <0x8400000>; + hash { + algo = "sha256"; + }; + }; + fdt { + description = "UEFI dtb"; + data = /incbin/("./@DEVICE@.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + hash { + algo = "sha256"; + }; + }; + nvdata { + description = "UEFI Non-Volatile Data"; + data-position = <0x006C0000>; /* 0x007C0000 - 0x100000 FIT offset */ + data-size = <0x00030000>; /* NV_VARIABLE_STORE + NV_FTW_WORKING + NV_FTW_SPARE */ + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x007C0000>; + }; + }; + + configurations { + default = "conf"; + conf { + description = "@DEVICE@"; + rollback-index = <0x0>; + firmware = "atf-1"; + loadables = "uboot", "atf-2", "atf-3", "optee", "nvdata"; + fdt = "fdt"; + signature { + algo = "sha256,rsa2048"; + padding = "pss"; + key-name-hint = "dev"; + sign-images = "fdt", "firmware", "loadables"; + }; + }; + }; +}; diff --git a/local/UEFI/orangepi-5plus_UEFI_Release_v0.11.2.img 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