diff --git a/xml/raw/x86/Intel/AVX512.xml b/xml/raw/x86/Intel/AVX512_r22.xml similarity index 100% rename from xml/raw/x86/Intel/AVX512.xml rename to xml/raw/x86/Intel/AVX512_r22.xml diff --git a/xml/raw/x86/Intel/AVX512_r24.xml b/xml/raw/x86/Intel/AVX512_r24.xml new file mode 100644 index 0000000..5ac8038 --- /dev/null +++ b/xml/raw/x86/Intel/AVX512_r24.xml @@ -0,0 +1,25739 @@ + + + + + + + + + ADDPD--Add Packed Double-Precision Floating-Point Values. + + ADDPD + xmm1,xmm2/m128 + 66 0F 58 /r + + SSE2 + + Add packed double-precision floating-point values from xmm2/mem to xmm1 and store result in xmm1. + + + VADDPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 58 /r + + AVX + + Add packed double-precision floating-point values from xmm3/mem to xmm2 and store result in xmm1. + + + VADDPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 58 /r + + AVX + + Add packed double-precision floating-point values from ymm3/mem to ymm2 and store result in ymm1. + + + VADDPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 58 /r + + AVX512VL + AVX512F + + Add packed double-precision floating-point values from xmm3/m128/m64bcst to xmm2 and store result in xmm1 with writemask k1. + + + VADDPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 58 /r + + AVX512VL + AVX512F + + Add packed double-precision floating-point values from ymm3/m256/m64bcst to ymm2 and store result in ymm1 with writemask k1. + + + VADDPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F.W1 58 /r + + AVX512F + + Add packed double-precision floating-point values from zmm3/m512/m64bcst to zmm2 and store result in zmm1 with writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + ADDPS--Add Packed Single-Precision Floating-Point Values. + + ADDPS + xmm1,xmm2/m128 + 0F 58 /r + + SSE + + Add packed single-precision floating-point values from xmm2/m128 to xmm1 and store result in xmm1. + + + VADDPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 58 /r + + AVX + + Add packed single-precision floating-point values from xmm3/m128 to xmm2 and store result in xmm1. + + + VADDPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F.WIG 58 /r + + AVX + + Add packed single-precision floating-point values from ymm3/m256 to ymm2 and store result in ymm1. + + + VADDPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 58 /r + + AVX512VL + AVX512F + + Add packed single-precision floating-point values from xmm3/m128/m32bcst to xmm2 and store result in xmm1 with writemask k1. + + + VADDPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 58 /r + + AVX512VL + AVX512F + + Add packed single-precision floating-point values from ymm3/m256/m32bcst to ymm2 and store result in ymm1 with writemask k1. + + + VADDPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst {er} + EVEX.NDS.512.0F.W0 58 /r + + AVX512F + + Add packed single-precision floating-point values from zmm3/m512/m32bcst to zmm2 and store result in zmm1 with writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + ADDSD--Add Scalar Double-Precision Floating-Point Values. + + ADDSD + xmm1,xmm2/m64 + F2 0F 58 /r + + SSE2 + + Add the low double-precision floating-point value from xmm2/mem to xmm1 and store the result in xmm1. + + + VADDSD + xmm1,xmm2,xmm3/m64 + VEX.NDS.128.F2.0F.WIG 58 /r + + AVX + + Add the low double-precision floating-point value from xmm3/mem to xmm2 and store the result in xmm1. + + + VADDSD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.NDS.LIG.F2.0F.W1 58 /r + + AVX512F + + Add the low double-precision floating-point value from xmm3/m64 to xmm2 and store the result in xmm1 with writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + ADDSS--Add Scalar Single-Precision Floating-Point Values. + + ADDSS + xmm1,xmm2/m32 + F3 0F 58 /r + + SSE + + Add the low single-precision floating-point value from xmm2/mem to xmm1 and store the result in xmm1. + + + VADDSS + xmm1,xmm2,xmm3/m32 + VEX.NDS.128.F3.0F.WIG 58 /r + + AVX + + Add the low single-precision floating-point value from xmm3/mem to xmm2 and store the result in xmm1. + + + VADDSS + xmm1{k1}{z},xmm2,xmm3/m32{er} + EVEX.NDS.LIG.F3.0F.W0 58 /r + + AVX512F + + Add the low single-precision floating-point value from xmm3/m32 to xmm2 and store the result in xmm1with writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VALIGND/VALIGNQ--Align Doubleword/Quadword Vectors. + + VALIGND + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst,imm8 + EVEX.NDS.128.66.0F3A.W0 03 /r ib + + AVX512VL + AVX512F + + Shift right and merge vectors xmm2 and xmm3/m128/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in xmm1, under writemask. + + + VALIGNQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst,imm8 + EVEX.NDS.128.66.0F3A.W1 03 /r ib + + AVX512VL + AVX512F + + Shift right and merge vectors xmm2 and xmm3/m128/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in xmm1, under writemask. + + + VALIGND + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.66.0F3A.W0 03 /r ib + + AVX512VL + AVX512F + + Shift right and merge vectors ymm2 and ymm3/m256/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in ymm1, under writemask. + + + VALIGNQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F3A.W1 03 /r ib + + AVX512VL + AVX512F + + Shift right and merge vectors ymm2 and ymm3/m256/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in ymm1, under writemask. + + + VALIGND + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst,imm8 + EVEX.NDS.512.66.0F3A.W0 03 /r ib + + AVX512F + + Shift right and merge vectors zmm2 and zmm3/m512/m32bcst with double-word granularity using imm8 as number of elements to shift, and store the final result in zmm1, under writemask. + + + VALIGNQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst,imm8 + EVEX.NDS.512.66.0F3A.W1 03 /r ib + + AVX512F + + Shift right and merge vectors zmm2 and zmm3/m512/m64bcst with quad-word granularity using imm8 as number of elements to shift, and store the final result in zmm1, under writemask. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VBLENDMPD/VBLENDMPS--Blend Float64/Float32 Vectors Using an OpMask Control. + + VBLENDMPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 65 /r + + AVX512VL + AVX512F + + Blend double-precision vector xmm2 and double-precision vector xmm3/m128/m64bcst and store the result in xmm1, under control mask. + + + VBLENDMPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 65 /r + + AVX512VL + AVX512F + + Blend double-precision vector ymm2 and double-precision vector ymm3/m256/m64bcst and store the result in ymm1, under control mask. + + + VBLENDMPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 65 /r + + AVX512F + + Blend double-precision vector zmm2 and double-precision vector zmm3/m512/m64bcst and store the result in zmm1, under control mask. + + + VBLENDMPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 65 /r + + AVX512VL + AVX512F + + Blend single-precision vector xmm2 and single-precision vector xmm3/m128/m32bcst and store the result in xmm1, under control mask. + + + VBLENDMPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 65 /r + + AVX512VL + AVX512F + + Blend single-precision vector ymm2 and single-precision vector ymm3/m256/m32bcst and store the result in ymm1, under control mask. + + + VBLENDMPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 65 /r + + AVX512F + + Blend single-precision vector zmm2 and single-precision vector zmm3/m512/m32bcst using k1 as select control and store the result in zmm1. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VPBLENDMB/VPBLENDMW--Blend Byte/Word Vectors Using an Opmask Control. + + VPBLENDMB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W0 66 /r + + AVX512VL + AVX512BW + + Blend byte integer vector xmm2 and byte vector xmm3/m128 and store the result in xmm1, under control mask. + + + VPBLENDMB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W0 66 /r + + AVX512VL + AVX512BW + + Blend byte integer vector ymm2 and byte vector ymm3/m256 and store the result in ymm1, under control mask. + + + VPBLENDMB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W0 66 /r + + AVX512BW + + Blend byte integer vector zmm2 and byte vector zmm3/m512 and store the result in zmm1, under control mask. + + + VPBLENDMW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W1 66 /r + + AVX512VL + AVX512BW + + Blend word integer vector xmm2 and word vector xmm3/m128 and store the result in xmm1, under control mask. + + + VPBLENDMW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W1 66 /r + + AVX512VL + AVX512BW + + Blend word integer vector ymm2 and word vector ymm3/m256 and store the result in ymm1, under control mask. + + + VPBLENDMW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W1 66 /r + + AVX512BW + + Blend word integer vector zmm2 and word vector zmm3/m512 and store the result in zmm1, under control mask. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VPBLENDMD/VPBLENDMQ--Blend Int32/Int64 Vectors Using an OpMask Control. + + VPBLENDMD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 64 /r + + AVX512VL + AVX512F + + Blend doubleword integer vector xmm2 and doubleword vector xmm3/m128/m32bcst and store the result in xmm1, under control mask. + + + VPBLENDMD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 64 /r + + AVX512VL + AVX512F + + Blend doubleword integer vector ymm2 and doubleword vector ymm3/m256/m32bcst and store the result in ymm1, under control mask. + + + VPBLENDMD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 64 /r + + AVX512F + + Blend doubleword integer vector zmm2 and doubleword vector zmm3/m512/m32bcst and store the result in zmm1, under control mask. + + + VPBLENDMQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 64 /r + + AVX512VL + AVX512F + + Blend quadword integer vector xmm2 and quadword vector xmm3/m128/m64bcst and store the result in xmm1, under control mask. + + + VPBLENDMQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 64 /r + + AVX512VL + AVX512F + + Blend quadword integer vector ymm2 and quadword vector ymm3/m256/m64bcst and store the result in ymm1, under control mask. + + + VPBLENDMQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 64 /r + + AVX512F + + Blend quadword integer vector zmm2 and quadword vector zmm3/m512/m64bcst and store the result in zmm1, under control mask. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + ANDPD--Bitwise Logical AND of Packed Double Precision Floating-Point Values. + + ANDPD + xmm1,xmm2/m128 + 66 0F 54 /r + + SSE2 + + Return the bitwise logical AND of packed double-precision floating-point values in xmm1 and xmm2/mem. + + + VANDPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F 54 /r + + AVX + + Return the bitwise logical AND of packed double-precision floating-point values in xmm2 and xmm3/mem. + + + VANDPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F 54 /r + + AVX + + Return the bitwise logical AND of packed double-precision floating-point values in ymm2 and ymm3/mem. + + + VANDPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 54 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical AND of packed double-precision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1. + + + VANDPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 54 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical AND of packed double-precision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1. + + + VANDPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 54 /r + + AVX512DQ + + Return the bitwise logical AND of packed double-precision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + ANDPS--Bitwise Logical AND of Packed Single Precision Floating-Point Values. + + ANDPS + xmm1,xmm2/m128 + 0F 54 /r + + SSE + + Return the bitwise logical AND of packed single-precision floating-point values in xmm1 and xmm2/mem. + + + VANDPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F 54 /r + + AVX + + Return the bitwise logical AND of packed single-precision floating-point values in xmm2 and xmm3/mem. + + + VANDPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F 54 /r + + AVX + + Return the bitwise logical AND of packed single-precision floating-point values in ymm2 and ymm3/mem. + + + VANDPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 54 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical AND of packed single-precision floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1. + + + VANDPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 54 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical AND of packed single-precision floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1. + + + VANDPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.0F.W0 54 /r + + AVX512DQ + + Return the bitwise logical AND of packed single-precision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + ANDNPD--Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values. + + ANDNPD + xmm1,xmm2/m128 + 66 0F 55 /r + + SSE2 + + Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm1 and xmm2/mem. + + + VANDNPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F 55 /r + + AVX + + Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm2 and xmm3/mem. + + + VANDNPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F 55/r + + AVX + + Return the bitwise logical AND NOT of packed doubleprecision floating-point values in ymm2 and ymm3/mem. + + + VANDNPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 55 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical AND NOT of packed doubleprecision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1. + + + VANDNPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 55 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical AND NOT of packed doubleprecision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1. + + + VANDNPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 55 /r + + AVX512DQ + + Return the bitwise logical AND NOT of packed doubleprecision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + ANDNPS--Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values. + + ANDNPS + xmm1,xmm2/m128 + 0F 55 /r + + SSE + + Return the bitwise logical AND NOT of packed single-precision floating-point values in xmm1 and xmm2/mem. + + + VANDNPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F 55 /r + + AVX + + Return the bitwise logical AND NOT of packed single-precision floating-point values in xmm2 and xmm3/mem. + + + VANDNPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F 55 /r + + AVX + + Return the bitwise logical AND NOT of packed single-precision floating-point values in ymm2 and ymm3/mem. + + + VANDNPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 55 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical AND of packed single-precision floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1. + + + VANDNPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 55 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical AND of packed single-precision floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1. + + + VANDNPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.0F.W0 55 /r + + AVX512DQ + + Return the bitwise logical AND of packed single-precision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VBROADCAST--Load with Broadcast Floating-Point Data. + + VBROADCASTSS + xmm1,m32 + VEX.128.66.0F38.W0 18 /r + + AVX + + Broadcast single-precision floating-point element in mem to four locations in xmm1. + + + VBROADCASTSS + ymm1,m32 + VEX.256.66.0F38.W0 18 /r + + AVX + + Broadcast single-precision floating-point element in mem to eight locations in ymm1. + + + VBROADCASTSD + ymm1,m64 + VEX.256.66.0F38.W0 19 /r + + AVX + + Broadcast double-precision floating-point element in mem to four locations in ymm1. + + + VBROADCASTF128 + ymm1,m128 + VEX.256.66.0F38.W0 1A /r + + AVX + + Broadcast 128 bits of floating-point data in mem to low and high 128-bits in ymm1. + + + VBROADCASTSD + ymm1 {k1}{z},xmm2/m64 + EVEX.256.66.0F38.W1 19 /r + + AVX512VL + AVX512F + + Broadcast low double-precision floating-point element in xmm2/m64 to four locations in ymm1 using writemask k1. + + + VBROADCASTSD + zmm1 {k1}{z},xmm2/m64 + EVEX.512.66.0F38.W1 19 /r + + AVX512F + + Broadcast low double-precision floating-point element in xmm2/m64 to eight locations in zmm1 using writemask k1. + + + VBROADCASTF32X2 + ymm1 {k1}{z},xmm2/m64 + EVEX.256.66.0F38.W0 19 /r + + AVX512VL + AVX512DQ + + Broadcast two single-precision floating-point elements in xmm2/m64 to locations in ymm1 using writemask k1. + + + VBROADCASTF32X2 + zmm1 {k1}{z},xmm2/m64 + EVEX.512.66.0F38.W0 19 /r + + AVX512DQ + + Broadcast two single-precision floating-point elements in xmm2/m64 to locations in zmm1 using writemask k1. + + + VBROADCASTSS + xmm1 {k1}{z},xmm2/m32 + EVEX.128.66.0F38.W0 18 /r + + AVX512VL + AVX512F + + Broadcast low single-precision floating-point element in xmm2/m32 to all locations in xmm1 using writemask k1. + + + VBROADCASTSS + ymm1 {k1}{z},xmm2/m32 + EVEX.256.66.0F38.W0 18 /r + + AVX512VL + AVX512F + + Broadcast low single-precision floating-point element in xmm2/m32 to all locations in ymm1 using writemask k1. + + + VBROADCASTSS + zmm1 {k1}{z},xmm2/m32 + EVEX.512.66.0F38.W0 18 /r + + AVX512F + + Broadcast low single-precision floating-point element in xmm2/m32 to all locations in zmm1 using writemask k1. + + + VBROADCASTF32X4 + ymm1 {k1}{z},m128 + EVEX.256.66.0F38.W0 1A /r + + AVX512VL + AVX512F + + Broadcast 128 bits of 4 single-precision floating-point data in mem to locations in ymm1 using writemask k1. + + + VBROADCASTF32X4 + zmm1 {k1}{z},m128 + EVEX.512.66.0F38.W0 1A /r + + AVX512F + + Broadcast 128 bits of 4 single-precision floating-point data in mem to locations in zmm1 using writemask k1. + + + VBROADCASTF64X2 + ymm1 {k1}{z},m128 + EVEX.256.66.0F38.W1 1A /r + + AVX512VL + AVX512DQ + + Broadcast 128 bits of 2 double-precision floating-point data in mem to locations in ymm1 using writemask k1. + + + VBROADCASTF64X2 + zmm1 {k1}{z},m128 + EVEX.512.66.0F38.W1 1A /r + + AVX512DQ + + Broadcast 128 bits of 2 double-precision floating-point data in mem to locations in zmm1 using writemask k1. + + + VBROADCASTF32X8 + zmm1 {k1}{z},m256 + EVEX.512.66.0F38.W0 1B /r + + AVX512DQ + + Broadcast 256 bits of 8 single-precision floating-point data in mem to locations in zmm1 using writemask k1. + + + VBROADCASTF64X4 + zmm1 {k1}{z},m256 + EVEX.512.66.0F38.W1 1B /r + + AVX512F + + Broadcast 256 bits of 4 double-precision floating-point data in mem to locations in zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + reg(w) :ModRM:r/m(r) + NA + NA + NA + + + reg(w) :ModRM:r/m(r) + NA + NA + NA + + + reg(w) :ModRM:r/m(r) + NA + NA + NA + + + reg(w) :ModRM:r/m(r) + NA + NA + NA + + + + VPBROADCASTB/W/D/Q--Load with Broadcast Integer Data from General Purpose Register. + + VPBROADCASTB + xmm1 {k1}{z},reg + EVEX.128.66.0F38.W0 7A /r + + AVX512VL + AVX512BW + + Broadcast an 8-bit value from a GPR to all bytes in the 128-bit destination subject to writemask k1. + + + VPBROADCASTB + ymm1 {k1}{z},reg + EVEX.256.66.0F38.W0 7A /r + + AVX512VL + AVX512BW + + Broadcast an 8-bit value from a GPR to all bytes in the 256-bit destination subject to writemask k1. + + + VPBROADCASTB + zmm1 {k1}{z},reg + EVEX.512.66.0F38.W0 7A /r + + AVX512BW + + Broadcast an 8-bit value from a GPR to all bytes in the 512-bit destination subject to writemask k1. + + + VPBROADCASTW + xmm1 {k1}{z},reg + EVEX.128.66.0F38.W0 7B /r + + AVX512VL + AVX512BW + + Broadcast a 16-bit value from a GPR to all words in the 128-bit destination subject to writemask k1. + + + VPBROADCASTW + ymm1 {k1}{z},reg + EVEX.256.66.0F38.W0 7B /r + + AVX512VL + AVX512BW + + Broadcast a 16-bit value from a GPR to all words in the 256-bit destination subject to writemask k1. + + + VPBROADCASTW + zmm1 {k1}{z},reg + EVEX.512.66.0F38.W0 7B /r + + AVX512BW + + Broadcast a 16-bit value from a GPR to all words in the 512-bit destination subject to writemask k1. + + + VPBROADCASTD + xmm1 {k1}{z},r32 + EVEX.128.66.0F38.W0 7C /r + + AVX512VL + AVX512F + + Broadcast a 32-bit value from a GPR to all double-words in the 128-bit destination subject to writemask k1. + + + VPBROADCASTD + ymm1 {k1}{z},r32 + EVEX.256.66.0F38.W0 7C /r + + AVX512VL + AVX512F + + Broadcast a 32-bit value from a GPR to all double-words in the 256-bit destination subject to writemask k1. + + + VPBROADCASTD + zmm1 {k1}{z},r32 + EVEX.512.66.0F38.W0 7C /r + + AVX512F + + Broadcast a 32-bit value from a GPR to all double-words in the 512-bit destination subject to writemask k1. + + + VPBROADCASTQ + xmm1 {k1}{z},r64 + EVEX.128.66.0F38.W1 7C /r + + AVX512VL + AVX512F + + Broadcast a 64-bit value from a GPR to all quad-words in the 128-bit destination subject to writemask k1. + + + VPBROADCASTQ + ymm1 {k1}{z},r64 + EVEX.256.66.0F38.W1 7C /r + + AVX512VL + AVX512F + + Broadcast a 64-bit value from a GPR to all quad-words in the 256-bit destination subject to writemask k1. + + + VPBROADCASTQ + zmm1 {k1}{z},r64 + EVEX.512.66.0F38.W1 7C /r + + AVX512F + + Broadcast a 64-bit value from a GPR to all quad-words in the 512-bit destination subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VPBROADCAST--Load Integer and Broadcast. + + VPBROADCASTB + xmm1,xmm2/m8 + VEX.128.66.0F38.W0 78 /r + + AVX2 + + Broadcast a byte integer in the source operand to sixteen locations in xmm1. + + + VPBROADCASTB + ymm1,xmm2/m8 + VEX.256.66.0F38.W0 78 /r + + AVX2 + + Broadcast a byte integer in the source operand to thirty-two locations in ymm1. + + + VPBROADCASTB + xmm1{k1}{z},xmm2/m8 + EVEX.128.66.0F38.W0 78 /r + + AVX512VL + AVX512BW + + Broadcast a byte integer in the source operand to locations in xmm1 subject to writemask k1. + + + VPBROADCASTB + ymm1{k1}{z},xmm2/m8 + EVEX.256.66.0F38.W0 78 /r + + AVX512VL + AVX512BW + + Broadcast a byte integer in the source operand to locations in ymm1 subject to writemask k1. + + + VPBROADCASTB + zmm1{k1}{z},xmm2/m8 + EVEX.512.66.0F38.W0 78 /r + + AVX512BW + + Broadcast a byte integer in the source operand to 64 locations in zmm1 subject to writemask k1. + + + VPBROADCASTW + xmm1,xmm2/m16 + VEX.128.66.0F38.W0 79 /r + + AVX2 + + Broadcast a word integer in the source operand to eight locations in xmm1. + + + VPBROADCASTW + ymm1,xmm2/m16 + VEX.256.66.0F38.W0 79 /r + + AVX2 + + Broadcast a word integer in the source operand to sixteen locations in ymm1. + + + VPBROADCASTW + xmm1{k1}{z},xmm2/m16 + EVEX.128.66.0F38.W0 79 /r + + AVX512VL + AVX512BW + + Broadcast a word integer in the source operand to locations in xmm1 subject to writemask k1. + + + VPBROADCASTW + ymm1{k1}{z},xmm2/m16 + EVEX.256.66.0F38.W0 79 /r + + AVX512VL + AVX512BW + + Broadcast a word integer in the source operand to locations in ymm1 subject to writemask k1. + + + VPBROADCASTW + zmm1{k1}{z},xmm2/m16 + EVEX.512.66.0F38.W0 79 /r + + AVX512BW + + Broadcast a word integer in the source operand to 32 locations in zmm1 subject to writemask k1. + + + VPBROADCASTD + xmm1,xmm2/m32 + VEX.128.66.0F38.W0 58 /r + + AVX2 + + Broadcast a dword integer in the source operand to four locations in xmm1. + + + VPBROADCASTD + ymm1,xmm2/m32 + VEX.256.66.0F38.W0 58 /r + + AVX2 + + Broadcast a dword integer in the source operand to eight locations in ymm1. + + + VPBROADCASTD + xmm1 {k1}{z},xmm2/m32 + EVEX.128.66.0F38.W0 58 /r + + AVX512VL + AVX512F + + Broadcast a dword integer in the source operand to locations in xmm1 subject to writemask k1. + + + VPBROADCASTD + ymm1 {k1}{z},xmm2/m32 + EVEX.256.66.0F38.W0 58 /r + + AVX512VL + AVX512F + + Broadcast a dword integer in the source operand to locations in ymm1 subject to writemask k1. + + + VPBROADCASTD + zmm1 {k1}{z},xmm2/m32 + EVEX.512.66.0F38.W0 58 /r + + AVX512F + + Broadcast a dword integer in the source operand to locations in zmm1 subject to writemask k1. + + + VPBROADCASTQ + xmm1,xmm2/m64 + VEX.128.66.0F38.W0 59 /r + + AVX2 + + Broadcast a qword element in source operand to two locations in xmm1. + + + VPBROADCASTQ + ymm1,xmm2/m64 + VEX.256.66.0F38.W0 59 /r + + AVX2 + + Broadcast a qword element in source operand to four locations in ymm1. + + + VPBROADCASTQ + xmm1 {k1}{z},xmm2/m64 + EVEX.128.66.0F38.W1 59 /r + + AVX512VL + AVX512F + + Broadcast a qword element in source operand to locations in xmm1 subject to writemask k1. + + + VPBROADCASTQ + ymm1 {k1}{z},xmm2/m64 + EVEX.256.66.0F38.W1 59 /r + + AVX512VL + AVX512F + + Broadcast a qword element in source operand to locations in ymm1 subject to writemask k1. + + + VPBROADCASTQ + zmm1 {k1}{z},xmm2/m64 + EVEX.512.66.0F38.W1 59 /r + + AVX512F + + Broadcast a qword element in source operand to locations in zmm1 subject to writemask k1. + + + VBROADCASTI32x2 + xmm1 {k 1}{z},xmm2/m64 + EVEX.128.66.0F38.W0 59 /r + + AVX512VL + AVX512DQ + + Broadcast two dword elements in source operand to locations in xmm1 subject to writemask k1. + + + VBROADCASTI32x2 + ymm1 {k 1}{z},xmm2/m64 + EVEX.256.66.0F38.W0 59 /r + + AVX512VL + AVX512DQ + + Broadcast two dword elements in source operand to locations in ymm1 subject to writemask k1. + + + VBROADCASTI32x2 + zmm1 {k1}{z},xmm2/m64 + EVEX.512.66.0F38.W0 59 /r + + AVX512DQ + + Broadcast two dword elements in source operand to locations in zmm1 subject to writemask k1. + + + VBROADCASTI128 + ymm1,m128 + VEX.256.66.0F38.W0 5A /r + + AVX2 + + Broadcast 128 bits of integer data in mem to low and high 128-bits in ymm1. + + + VBROADCASTI32X4 + ymm1 {k1}{z},m128 + EVEX.256.66.0F38.W0 5A /r + + AVX512VL + AVX512F + + Broadcast 128 bits of 4 doubleword integer data in mem to locations in ymm1 using writemask k1. + + + VBROADCASTI32X4 + zmm1 {k1}{z},m128 + EVEX.512.66.0F38.W0 5A /r + + AVX512F + + Broadcast 128 bits of 4 doubleword integer data in mem to locations in zmm1 using writemask k1. + + + VBROADCASTI64X2 + ymm1 {k1}{z},m128 + EVEX.256.66.0F38.W1 5A /r + + AVX512VL + AVX512DQ + + Broadcast 128 bits of 2 quadword integer data in mem to locations in ymm1 using writemask k1. + + + VBROADCASTI64X2 + zmm1 {k1}{z},m128 + EVEX.512.66.0F38.W1 5A /r + + AVX512DQ + + Broadcast 128 bits of 2 quadword integer data in mem to locations in zmm1 using writemask k1. + + + VBROADCASTI32X8 + zmm1 {k1}{z},m256 + EVEX.512.66.0F38.W0 5B /r + + AVX512DQ + + Broadcast 256 bits of 8 doubleword integer data in mem to locations in zmm1 using writemask k1. + + + VBROADCASTI64X4 + zmm1 {k1}{z},m256 + EVEX.512.66.0F38.W1 5B /r + + AVX512F + + Broadcast 256 bits of 4 quadword integer data in mem to locations in zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + reg(w) :ModRM:r/m(r) + NA + NA + NA + + + reg(w) :ModRM:r/m(r) + NA + NA + NA + + + reg(w) :ModRM:r/m(r) + NA + NA + NA + + + reg(w) :ModRM:r/m(r) + NA + NA + NA + + + + CMPPD--Compare Packed Double-Precision Floating-Point Values. + + CMPPD + xmm1,xmm2/m128,imm8 + 66 0F C2 /r ib + + SSE2 + + Compare packed double-precision floating-point values in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a comparison predicate. + + + VCMPPD + xmm1,xmm2,xmm3/m128,imm8 + VEX.NDS.128.66.0F.WIG C2 /r ib + + AVX + + Compare packed double-precision floating-point values in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a comparison predicate. + + + VCMPPD + ymm1,ymm2,ymm3/m256,imm8 + VEX.NDS.256.66.0F.WIG C2 /r ib + + AVX + + Compare packed double-precision floating-point values in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a comparison predicate. + + + VCMPPD + k1 {k2},xmm2,xmm3/m128/m64bcst,imm8 + EVEX.NDS.128.66.0F.W1 C2 /r ib + + AVX512VL + AVX512F + + Compare packed double-precision floating-point values in xmm3/m128/m64bcst and xmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VCMPPD + k1 {k2},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F.W1 C2 /r ib + + AVX512VL + AVX512F + + Compare packed double-precision floating-point values in ymm3/m256/m64bcst and ymm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VCMPPD + k1 {k2},zmm2,zmm3/m512/m64bcst{sae},imm8 + EVEX.NDS.512.66.0F.W1 C2 /r ib + + AVX512F + + Compare packed double-precision floating-point values in zmm3/m512/m64bcst and zmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + CMPPS--Compare Packed Single-Precision Floating-Point Values. + + CMPPS + xmm1,xmm2/m128,imm8 + 0F C2 /r ib + + SSE + + Compare packed single-precision floating-point values in xmm2/m128 and xmm1 using bits 2:0 of imm8 as a comparison predicate. + + + VCMPPS + xmm1,xmm2,xmm3/m128,imm8 + VEX.NDS.128.0F.WIG C2 /r ib + + AVX + + Compare packed single-precision floating-point values in xmm3/m128 and xmm2 using bits 4:0 of imm8 as a comparison predicate. + + + VCMPPS + ymm1,ymm2,ymm3/m256,imm8 + VEX.NDS.256.0F.WIG C2 /r ib + + AVX + + Compare packed single-precision floating-point values in ymm3/m256 and ymm2 using bits 4:0 of imm8 as a comparison predicate. + + + VCMPPS + k1 {k2},xmm2,xmm3/m128/m32bcst,imm8 + EVEX.NDS.128.0F.W0 C2 /r ib + + AVX512VL + AVX512F + + Compare packed single-precision floating-point values in xmm3/m128/m32bcst and xmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VCMPPS + k1 {k2},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.0F.W0 C2 /r ib + + AVX512VL + AVX512F + + Compare packed single-precision floating-point values in ymm3/m256/m32bcst and ymm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VCMPPS + k1 {k2},zmm2,zmm3/m512/m32bcst{sae},imm8 + EVEX.NDS.512.0F.W0 C2 /r ib + + AVX512F + + Compare packed single-precision floating-point values in zmm3/m512/m32bcst and zmm2 using bits 4:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + CMPSD--Compare Scalar Double-Precision Floating-Point Value. + + CMPSD + xmm1,xmm2/m64,imm8 + F2 0F C2 /r ib + + SSE2 + + Compare low double-precision floating-point value in xmm2/m64 and xmm1 using bits 2:0 of imm8 as comparison predicate. + + + VCMPSD + xmm1,xmm2,xmm3/m64,imm8 + VEX.NDS.128.F2.0F.WIG C2 /r ib + + AVX + + Compare low double-precision floating-point value in xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison predicate. + + + VCMPSD + k1 {k2},xmm2,xmm3/m64{sae},imm8 + EVEX.NDS.LIG.F2.0F.W1 C2 /r ib + + AVX512F + + Compare low double-precision floating-point value in xmm3/m64 and xmm2 using bits 4:0 of imm8 as comparison predicate with writemask k2 and leave the result in mask register k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + CMPSS--Compare Scalar Single-Precision Floating-Point Value. + + CMPSS + xmm1,xmm2/m32,imm8 + F3 0F C2 /r ib + + SSE + + Compare low single-precision floating-point value in xmm2/m32 and xmm1 using bits 2:0 of imm8 as comparison predicate. + + + VCMPSS + xmm1,xmm2,xmm3/m32,imm8 + VEX.NDS.128.F3.0F.WIG C2 /r ib + + AVX + + Compare low single-precision floating-point value in xmm3/m32 and xmm2 using bits 4:0 of imm8 as comparison predicate. + + + VCMPSS + k1 {k2},xmm2,xmm3/m32{sae},imm8 + EVEX.NDS.LIG.F3.0F.W0 C2 /r ib + + AVX512F + + Compare low single-precision floating-point value in xmm3/m32 and xmm2 using bits 4:0 of imm8 as comparison predicate with writemask k2 and leave the result in mask register k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + COMISD--Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS. + + COMISD + xmm1,xmm2/m64 + 66 0F 2F /r + + SSE2 + + Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly. + + + VCOMISD + xmm1,xmm2/m64 + VEX.128.66.0F.WIG 2F /r + + AVX + + Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly. + + + VCOMISD + xmm1,xmm2/m64{sae} + EVEX.LIG.66.0F.W1 2F /r + + AVX512F + + Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + COMISS--Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS. + + COMISS + xmm1,xmm2/m32 + 0F 2F /r + + SSE + + Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly. + + + VCOMISS + xmm1,xmm2/m32 + VEX.128.0F.WIG 2F /r + + AVX + + Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly. + + + VCOMISS + xmm1,xmm2/m32{sae} + EVEX.LIG.0F.W0 2F /r + + AVX512F + + Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + DIVPD--Divide Packed Double-Precision Floating-Point Values. + + DIVPD + xmm1,xmm2/m128 + 66 0F 5E /r + + SSE2 + + Divide packed double-precision floating-point values in xmm1 by packed double-precision floating-point values in xmm2/mem. + + + VDIVPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 5E /r + + AVX + + Divide packed double-precision floating-point values in xmm2 by packed double-precision floating-point values in xmm3/mem. + + + VDIVPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 5E /r + + AVX + + Divide packed double-precision floating-point values in ymm2 by packed double-precision floating-point values in ymm3/mem. + + + VDIVPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 5E /r + + AVX512VL + AVX512F + + Divide packed double-precision floating-point values in xmm2 by packed double-precision floating-point values in xmm3/m128/m64bcst and write results to xmm1 subject to writemask k1. + + + VDIVPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 5E /r + + AVX512VL + AVX512F + + Divide packed double-precision floating-point values in ymm2 by packed double-precision floating-point values in ymm3/m256/m64bcst and write results to ymm1 subject to writemask k1. + + + VDIVPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F.W1 5E /r + + AVX512F + + Divide packed double-precision floating-point values in zmm2 by packed double-precision FP values in zmm3/m512/m64bcst and write results to zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + DIVPS--Divide Packed Single-Precision Floating-Point Values. + + DIVPS + xmm1,xmm2/m128 + 0F 5E /r + + SSE + + Divide packed single-precision floating-point values in xmm1 by packed single-precision floating-point values in xmm2/mem. + + + VDIVPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 5E /r + + AVX + + Divide packed single-precision floating-point values in xmm2 by packed single-precision floating-point values in xmm3/mem. + + + VDIVPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F.WIG 5E /r + + AVX + + Divide packed single-precision floating-point values in ymm2 by packed single-precision floating-point values in ymm3/mem. + + + VDIVPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 5E /r + + AVX512VL + AVX512F + + Divide packed single-precision floating-point values in xmm2 by packed single-precision floating-point values in xmm3/m128/m32bcst and write results to xmm1 subject to writemask k1. + + + VDIVPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 5E /r + + AVX512VL + AVX512F + + Divide packed single-precision floating-point values in ymm2 by packed single-precision floating-point values in ymm3/m256/m32bcst and write results to ymm1 subject to writemask k1. + + + VDIVPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.0F.W0 5E /r + + AVX512F + + Divide packed single-precision floating-point values in zmm2 by packed single-precision floating-point values in zmm3/m512/m32bcst and write results to zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + DIVSD--Divide Scalar Double-Precision Floating-Point Value. + + DIVSD + xmm1,xmm2/m64 + F2 0F 5E /r + + SSE2 + + Divide low double-precision floating-point value in xmm1 by low double-precision floating-point value in xmm2/m64. + + + VDIVSD + xmm1,xmm2,xmm3/m64 + VEX.NDS.128.F2.0F.WIG 5E /r + + AVX + + Divide low double-precision floating-point value in xmm2 by low double-precision floating-point value in xmm3/m64. + + + VDIVSD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.NDS.LIG.F2.0F.W1 5E /r + + AVX512F + + Divide low double-precision floating-point value in xmm2 by low double-precision floating-point value in xmm3/m64. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + DIVSS--Divide Scalar Single-Precision Floating-Point Values. + + DIVSS + xmm1,xmm2/m32 + F3 0F 5E /r + + SSE + + Divide low single-precision floating-point value in xmm1 by low single-precision floating-point value in xmm2/m32. + + + VDIVSS + xmm1,xmm2,xmm3/m32 + VEX.NDS.128.F3.0F.WIG 5E /r + + AVX + + Divide low single-precision floating-point value in xmm2 by low single-precision floating-point value in xmm3/m32. + + + VDIVSS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.NDS.LIG.F3.0F.W0 5E /r + + AVX512F + + Divide low single-precision floating-point value in xmm2 by low single-precision floating-point value in xmm3/m32. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VCOMPRESSPD--Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory. + + VCOMPRESSPD + xmm1/m128 {k1}{z},xmm2 + EVEX.128.66.0F38.W1 8A /r + + AVX512VL + AVX512F + + Compress packed double-precision floating-point values from xmm2 to xmm1/m128 using writemask k1. + + + VCOMPRESSPD + ymm1/m256 {k1}{z},ymm2 + EVEX.256.66.0F38.W1 8A /r + + AVX512VL + AVX512F + + Compress packed double-precision floating-point values from ymm2 to ymm1/m256 using writemask k1. + + + VCOMPRESSPD + zmm1/m512 {k1}{z},zmm2 + EVEX.512.66.0F38.W1 8A /r + + AVX512F + + Compress packed double-precision floating-point values from zmm2 using control mask k1 to zmm1/m512. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + VCOMPRESSPS--Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory. + + VCOMPRESSPS + xmm1/m128 {k1}{z},xmm2 + EVEX.128.66.0F38.W0 8A /r + + AVX512VL + AVX512F + + Compress packed single-precision floating-point values from xmm2 to xmm1/m128 using writemask k1. + + + VCOMPRESSPS + ymm1/m256 {k1}{z},ymm2 + EVEX.256.66.0F38.W0 8A /r + + AVX512VL + AVX512F + + Compress packed single-precision floating-point values from ymm2 to ymm1/m256 using writemask k1. + + + VCOMPRESSPS + zmm1/m512 {k1}{z},zmm2 + EVEX.512.66.0F38.W0 8A /r + + AVX512F + + Compress packed single-precision floating-point values from zmm2 using control mask k1 to zmm1/m512. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + CVTDQ2PD--Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values. + + CVTDQ2PD + xmm1,xmm2/m64 + F3 0F E6 /r + + SSE2 + + Convert two packed signed doubleword integers from xmm2/mem to two packed double-precision floatingpoint values in xmm1. + + + VCVTDQ2PD + xmm1,xmm2/m64 + VEX.128.F3.0F.WIG E6 /r + + AVX + + Convert two packed signed doubleword integers from xmm2/mem to two packed double-precision floatingpoint values in xmm1. + + + VCVTDQ2PD + ymm1,xmm2/m128 + VEX.256.F3.0F.WIG E6 /r + + AVX + + Convert four packed signed doubleword integers from xmm2/mem to four packed double-precision floatingpoint values in ymm1. + + + VCVTDQ2PD + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.F3.0F.W0 E6 /r + + AVX512VL + AVX512F + + Convert 2 packed signed doubleword integers from xmm2/m128/m32bcst to eight packed double-precision floating-point values in xmm1 with writemask k1. + + + VCVTDQ2PD + ymm1 {k1}{z},xmm2/m128/m32bcst + EVEX.256.F3.0F.W0 E6 /r + + AVX512VL + AVX512F + + Convert 4 packed signed doubleword integers from xmm2/m128/m32bcst to 4 packed double-precision floating-point values in ymm1 with writemask k1. + + + VCVTDQ2PD + zmm1 {k1}{z},ymm2/m256/m32bcst + EVEX.512.F3.0F.W0 E6 /r + + AVX512F + + Convert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed double-precision floating-point values in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTDQ2PS--Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values. + + CVTDQ2PS + xmm1,xmm2/m128 + 0F 5B /r + + SSE2 + + Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision floatingpoint values in xmm1. + + + VCVTDQ2PS + xmm1,xmm2/m128 + VEX.128.0F.WIG 5B /r + + AVX + + Convert four packed signed doubleword integers from xmm2/mem to four packed single-precision floatingpoint values in xmm1. + + + VCVTDQ2PS + ymm1,ymm2/m256 + VEX.256.0F.WIG 5B /r + + AVX + + Convert eight packed signed doubleword integers from ymm2/mem to eight packed single-precision floatingpoint values in ymm1. + + + VCVTDQ2PS + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.0F.W0 5B /r + + AVX512VL + AVX512F + + Convert four packed signed doubleword integers from xmm2/m128/m32bcst to four packed single-precision floating-point values in xmm1with writemask k1. + + + VCVTDQ2PS + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.0F.W0 5B /r + + AVX512VL + AVX512F + + Convert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed single-precision floating-point values in ymm1with writemask k1. + + + VCVTDQ2PS + zmm1 {k1}{z},zmm2/m512/m32bcst{er} + EVEX.512.0F.W0 5B /r + + AVX512F + + Convert sixteen packed signed doubleword integers from zmm2/m512/m32bcst to sixteen packed singleprecision floating-point values in zmm1with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTPD2DQ--Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers. + + CVTPD2DQ + xmm1,xmm2/m128 + F2 0F E6 /r + + SSE2 + + Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1. + + + VCVTPD2DQ + xmm1,xmm2/m128 + VEX.128.F2.0F.WIG E6 /r + + AVX + + Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1. + + + VCVTPD2DQ + xmm1,ymm2/m256 + VEX.256.F2.0F.WIG E6 /r + + AVX + + Convert four packed double-precision floating-point values in ymm2/mem to four signed doubleword integers in xmm1. + + + VCVTPD2DQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.F2.0F.W1 E6 /r + + AVX512VL + AVX512F + + Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two signed doubleword integers in xmm1 subject to writemask k1. + + + VCVTPD2DQ + xmm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.F2.0F.W1 E6 /r + + AVX512VL + AVX512F + + Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 subject to writemask k1. + + + VCVTPD2DQ + ymm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.F2.0F.W1 E6 /r + + AVX512F + + Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTPD2PS--Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values. + + CVTPD2PS + xmm1,xmm2/m128 + 66 0F 5A /r + + SSE2 + + Convert two packed double-precision floating-point values in xmm2/mem to two single-precision floating-point values in xmm1. + + + VCVTPD2PS + xmm1,xmm2/m128 + VEX.128.66.0F.WIG 5A /r + + AVX + + Convert two packed double-precision floating-point values in xmm2/mem to two single-precision floating-point values in xmm1. + + + VCVTPD2PS + xmm1,ymm2/m256 + VEX.256.66.0F.WIG 5A /r + + AVX + + Convert four packed double-precision floating-point values in ymm2/mem to four single-precision floating-point values in xmm1. + + + VCVTPD2PS + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F.W1 5A /r + + AVX512VL + AVX512F + + Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two singleprecision floating-point values in xmm1with writemask k1. + + + VCVTPD2PS + xmm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F.W1 5A /r + + AVX512VL + AVX512F + + Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four singleprecision floating-point values in xmm1with writemask k1. + + + VCVTPD2PS + ymm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.66.0F.W1 5A /r + + AVX512F + + Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight singleprecision floating-point values in ymm1with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTPD2QQ--Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers. + + VCVTPD2QQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F.W1 7B /r + + AVX512VL + AVX512DQ + + Convert two packed double-precision floating-point values from xmm2/m128/m64bcst to two packed quadword integers in xmm1 with writemask k1. + + + VCVTPD2QQ + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F.W1 7B /r + + AVX512VL + AVX512DQ + + Convert four packed double-precision floating-point values from ymm2/m256/m64bcst to four packed quadword integers in ymm1 with writemask k1. + + + VCVTPD2QQ + zmm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.66.0F.W1 7B /r + + AVX512DQ + + Convert eight packed double-precision floating-point values from zmm2/m512/m64bcst to eight packed quadword integers in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTPD2UDQ--Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. + + VCVTPD2UDQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.0F.W1 79 /r + + AVX512VL + AVX512F + + Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two unsigned doubleword integers in xmm1 subject to writemask k1. + + + VCVTPD2UDQ + xmm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.0F.W1 79 /r + + AVX512VL + AVX512F + + Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four unsigned doubleword integers in xmm1 subject to writemask k1. + + + VCVTPD2UDQ + ymm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.0F.W1 79 /r + + AVX512F + + Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight unsigned doubleword integers in ymm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTPD2UQQ--Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers. + + VCVTPD2UQQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F.W1 79 /r + + AVX512VL + AVX512DQ + + Convert two packed double-precision floating-point values from xmm2/mem to two packed unsigned quadword integers in xmm1 with writemask k1. + + + VCVTPD2UQQ + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F.W1 79 /r + + AVX512VL + AVX512DQ + + Convert fourth packed double-precision floating-point values from ymm2/mem to four packed unsigned quadword integers in ymm1 with writemask k1. + + + VCVTPD2UQQ + zmm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.66.0F.W1 79 /r + + AVX512DQ + + Convert eight packed double-precision floating-point values from zmm2/mem to eight packed unsigned quadword integers in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTPH2PS--Convert 16-bit FP values to Single-Precision FP values. + + VCVTPH2PS + xmm1,xmm2/m64 + VEX.128.66.0F38.W0 1313 /r + + F16C + + Convert four packed half precision (16-bit) floatingpoint values in xmm2/m64 to packed single-precision floating-point value in xmm1. + + + VCVTPH2PS + ymm1,xmm2/m128 + VEX.256.66.0F38.W0 1313 /r + + F16C + + Convert eight packed half precision (16-bit) floatingpoint values in xmm2/m128 to packed singleprecision floating-point value in ymm1. + + + VCVTPH2PS + xmm1 {k1}{z},xmm2/m64 + EVEX.128.66.0F38.W0 1313 /r + + AVX512VL + AVX512F + + Convert four packed half precision (16-bit) floatingpoint values in xmm2/m64 to packed single-precision floating-point values in xmm1. + + + VCVTPH2PS + ymm1 {k1}{z},xmm2/m128 + EVEX.256.66.0F38.W0 1313 /r + + AVX512VL + AVX512F + + Convert eight packed half precision (16-bit) floatingpoint values in xmm2/m128 to packed singleprecision floating-point values in ymm1. + + + VCVTPH2PS + zmm1 {k1}{z},ymm2/m256 {sae} + EVEX.512.66.0F38.W0 1313 /r + + AVX512F + + Convert sixteen packed half precision (16-bit) floating-point values in ymm2/m256 to packed single-precision floating-point values in zmm1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTPS2PH--Convert Single-Precision FP value to 16-bit FP value. + + VCVTPS2PH + xmm1/m64,xmm2,imm8 + VEX.128.66.0F3A.W0 1D 1D/r ib + + F16C + + Convert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls. + + + VCVTPS2PH + xmm1/m128,ymm2,imm8 + VEX.256.66.0F3A.W0 1D1D /r ib + + F16C + + Convert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls. + + + VCVTPS2PH + xmm1/m64 {k1}{z},xmm2,imm8 + EVEX.128.66.0F3A.W0 1D1D /r ib + + AVX512VL + AVX512F + + Convert four packed single-precision floating-point values in xmm2 to packed half-precision (16-bit) floating-point values in xmm1/m64. Imm8 provides rounding controls. + + + VCVTPS2PH + xmm1/m128 {k1}{z},ymm2,imm8 + EVEX.256.66.0F3A.W0 1D1D /r ib + + AVX512VL + AVX512F + + Convert eight packed single-precision floating-point values in ymm2 to packed half-precision (16-bit) floating-point values in xmm1/m128. Imm8 provides rounding controls. + + + VCVTPS2PH + ymm1/m256 {k1}{z},zmm2{sae},imm8 + EVEX.512.66.0F3A.W0 1D1D /r ib + + AVX512F + + Convert sixteen packed single-precision floating-point values in zmm2 to packed half-precision (16-bit) floatingpoint values in ymm1/m256. Imm8 provides rounding controls. + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + + CVTPS2DQ--Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values. + + CVTPS2DQ + xmm1,xmm2/m128 + 66 0F 5B /r + + SSE2 + + Convert four packed single-precision floating-point values from xmm2/mem to four packed signed doubleword values in xmm1. + + + VCVTPS2DQ + xmm1,xmm2/m128 + VEX.128.66.0F.WIG 5B /r + + AVX + + Convert four packed single-precision floating-point values from xmm2/mem to four packed signed doubleword values in xmm1. + + + VCVTPS2DQ + ymm1,ymm2/m256 + VEX.256.66.0F.WIG 5B /r + + AVX + + Convert eight packed single-precision floating-point values from ymm2/mem to eight packed signed doubleword values in ymm1. + + + VCVTPS2DQ + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.66.0F.W0 5B /r + + AVX512VL + AVX512F + + Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed doubleword values in xmm1 subject to writemask k1. + + + VCVTPS2DQ + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.66.0F.W0 5B /r + + AVX512VL + AVX512F + + Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed doubleword values in ymm1 subject to writemask k1. + + + VCVTPS2DQ + zmm1 {k1}{z},zmm2/m512/m32bcst{er} + EVEX.512.66.0F.W0 5B /r + + AVX512F + + Convert sixteen packed single-precision floating-point values from zmm2/m512/m32bcst to sixteen packed signed doubleword values in zmm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTPS2UDQ--Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values. + + VCVTPS2UDQ + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.0F.W0 79 /r + + AVX512VL + AVX512F + + Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed unsigned doubleword values in xmm1 subject to writemask k1. + + + VCVTPS2UDQ + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.0F.W0 79 /r + + AVX512VL + AVX512F + + Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed unsigned doubleword values in ymm1 subject to writemask k1. + + + VCVTPS2UDQ + zmm1 {k1}{z},zmm2/m512/m32bcst{er} + EVEX.512.0F.W0 79 /r + + AVX512F + + Convert sixteen packed single-precision floating-point values from zmm2/m512/m32bcst to sixteen packed unsigned doubleword values in zmm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTPS2QQ--Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values. + + VCVTPS2QQ + xmm1 {k1}{z},xmm2/m64/m32bcst + EVEX.128.66.0F.W0 7B /r + + AVX512VL + AVX512DQ + + Convert two packed single precision floating-point values from xmm2/m64/m32bcst to two packed signed quadword values in xmm1 subject to writemask k1. + + + VCVTPS2QQ + ymm1 {k1}{z},xmm2/m128/m32bcst + EVEX.256.66.0F.W0 7B /r + + AVX512VL + AVX512DQ + + Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed quadword values in ymm1 subject to writemask k1. + + + VCVTPS2QQ + zmm1 {k1}{z},ymm2/m256/m32bcst{er} + EVEX.512.66.0F.W0 7B /r + + AVX512DQ + + Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTPS2UQQ--Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values. + + VCVTPS2UQQ + xmm1 {k1}{z},xmm2/m64/m32bcst + EVEX.128.66.0F.W0 79 /r + + AVX512VL + AVX512DQ + + Convert two packed single precision floating-point values from zmm2/m64/m32bcst to two packed unsigned quadword values in zmm1 subject to writemask k1. + + + VCVTPS2UQQ + ymm1 {k1}{z},xmm2/m128/m32bcst + EVEX.256.66.0F.W0 79 /r + + AVX512VL + AVX512DQ + + Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed unsigned quadword values in ymm1 subject to writemask k1. + + + VCVTPS2UQQ + zmm1 {k1}{z},ymm2/m256/m32bcst{er} + EVEX.512.66.0F.W0 79 /r + + AVX512DQ + + Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed unsigned quadword values in zmm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTPS2PD--Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values. + + CVTPS2PD + xmm1,xmm2/m64 + 0F 5A /r + + SSE2 + + Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1. + + + VCVTPS2PD + xmm1,xmm2/m64 + VEX.128.0F.WIG 5A /r + + AVX + + Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1. + + + VCVTPS2PD + ymm1,xmm2/m128 + VEX.256.0F.WIG 5A /r + + AVX + + Convert four packed single-precision floating-point values in xmm2/m128 to four packed double-precision floatingpoint values in ymm1. + + + VCVTPS2PD + xmm1 {k1}{z},xmm2/m64/m32bcst + EVEX.128.0F.W0 5A /r + + AVX512VL + AVX512F + + Convert two packed single-precision floating-point values in xmm2/m64/m32bcst to packed double-precision floatingpoint values in xmm1 with writemask k1. + + + VCVTPS2PD + ymm1 {k1}{z},xmm2/m128/m32bcst + EVEX.256.0F.W0 5A /r + + AVX512VL + + Convert four packed single-precision floating-point values in xmm2/m128/m32bcst to packed double-precision floating-point values in ymm1 with writemask k1. + + + VCVTPS2PD + zmm1 {k1}{z},ymm2/m256/m32bcst{sae} + EVEX.512.0F.W0 5A /r + + AVX512F + + Convert eight packed single-precision floating-point values in ymm2/m256/b32bcst to eight packed double-precision floating-point values in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTQQ2PD--Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values. + + VCVTQQ2PD + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.F3.0F.W1 E6 /r + + AVX512VL + AVX512DQ + + Convert two packed quadword integers from xmm2/m128/m64bcst to packed double-precision floatingpoint values in xmm1 with writemask k1. + + + VCVTQQ2PD + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.F3.0F.W1 E6 /r + + AVX512VL + AVX512DQ + + Convert four packed quadword integers from ymm2/m256/m64bcst to packed double-precision floatingpoint values in ymm1 with writemask k1. + + + VCVTQQ2PD + zmm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.F3.0F.W1 E6 /r + + AVX512DQ + + Convert eight packed quadword integers from zmm2/m512/m64bcst to eight packed double-precision floating-point values in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTQQ2PS--Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values. + + VCVTQQ2PS + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.0F.W1 5B /r + + AVX512VL + AVX512DQ + + Convert two packed quadword integers from xmm2/mem to packed single-precision floating-point values in xmm1 with writemask k1. + + + VCVTQQ2PS + xmm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.0F.W1 5B /r + + AVX512VL + AVX512DQ + + Convert four packed quadword integers from ymm2/mem to packed single-precision floating-point values in xmm1 with writemask k1. + + + VCVTQQ2PS + ymm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.0F.W1 5B /r + + AVX512DQ + + Convert eight packed quadword integers from zmm2/mem to eight packed single-precision floating-point values in ymm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTSD2SI--Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer. + + CVTSD2SI + r32,xmm1/m64 + F2 0F 2D /r + + SSE2 + + Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer r32. + + + CVTSD2SI + r64,xmm1/m64 + F2 REX.W 0F 2D /r + + SSE2 + + Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer signextended into r64. + + + VCVTSD2SI + r32,xmm1/m64 + VEX.128.F2.0F.W0 2D /r + + AVX + + Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer r32. + + + VCVTSD2SI + r64,xmm1/m64 + VEX.128.F2.0F.W1 2D /r + + AVX + + Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer signextended into r64. + + + VCVTSD2SI + r32,xmm1/m64{er} + EVEX.LIG.F2.0F.W0 2D /r + + AVX512F + + Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer r32. + + + VCVTSD2SI + r64,xmm1/m64{er} + EVEX.LIG.F2.0F.W1 2D /r + + AVX512F + + Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer signextended into r64. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTSD2USI--Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer. + + VCVTSD2USI + r32,xmm1/m64{er} + EVEX.LIG.F2.0F.W0 79 /r + + AVX512F + + Convert one double-precision floating-point value from xmm1/m64 to one unsigned doubleword integer r32. + + + VCVTSD2USI + r64,xmm1/m64{er} + EVEX.LIG.F2.0F.W1 79 /r + + AVX512F + + Convert one double-precision floating-point value from xmm1/m64 to one unsigned quadword integer zeroextended into r64. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTSD2SS--Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value. + + CVTSD2SS + xmm1,xmm2/m64 + F2 0F 5A /r + + SSE2 + + Convert one double-precision floating-point value in xmm2/m64 to one single-precision floating-point value in xmm1. + + + VCVTSD2SS + xmm1,xmm2,xmm3/m64 + VEX.NDS.128.F2.0F.WIG 5A /r + + AVX + + Convert one double-precision floating-point value in xmm3/m64 to one single-precision floating-point value and merge with high bits in xmm2. + + + VCVTSD2SS + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.NDS.LIG.F2.0F.W1 5A /r + + AVX512F + + Convert one double-precision floating-point value in xmm3/m64 to one single-precision floating-point value and merge with high bits in xmm2 under writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + CVTSI2SD--Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value. + + CVTSI2SD + xmm1,r32/m32 + F2 0F 2A /r + + SSE2 + + Convert one signed doubleword integer from r32/m32 to one double-precision floating-point value in xmm1. + + + CVTSI2SD + xmm1,r/m64 + F2 REX.W 0F 2A /r + + SSE2 + + Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm1. + + + VCVTSI2SD + xmm1,xmm2,r/m32 + VEX.NDS.128.F2.0F.W0 2A /r + + AVX + + Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm1. + + + VCVTSI2SD + xmm1,xmm2,r/m64 + VEX.NDS.128.F2.0F.W1 2A /r + + AVX + + Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm1. + + + VCVTSI2SD + xmm1,xmm2,r/m32 + EVEX.NDS.LIG.F2.0F.W0 2A /r + + AVX512F + + Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm1. + + + VCVTSI2SD + xmm1,xmm2,r/m64{er} + EVEX.NDS.LIG.F2.0F.W1 2A /r + + AVX512F + + Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + CVTSI2SS--Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value. + + CVTSI2SS + xmm1,r/m32 + F3 0F 2A /r + + SSE + + Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm1. + + + CVTSI2SS + xmm1,r/m64 + F3 REX.W 0F 2A /r + + SSE + + Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm1. + + + VCVTSI2SS + xmm1,xmm2,r/m32 + VEX.NDS.128.F3.0F.W0 2A /r + + AVX + + Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm1. + + + VCVTSI2SS + xmm1,xmm2,r/m64 + VEX.NDS.128.F3.0F.W1 2A /r + + AVX + + Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm1. + + + VCVTSI2SS + xmm1,xmm2,r/m32{er} + EVEX.NDS.LIG.F3.0F.W0 2A /r + + AVX512F + + Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm1. + + + VCVTSI2SS + xmm1,xmm2,r/m64{er} + EVEX.NDS.LIG.F3.0F.W1 2A /r + + AVX512F + + Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + CVTSS2SD--Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value. + + CVTSS2SD + xmm1,xmm2/m32 + F3 0F 5A /r + + SSE2 + + Convert one single-precision floating-point value in xmm2/m32 to one double-precision floating-point value in xmm1. + + + VCVTSS2SD + xmm1,xmm2,xmm3/m32 + VEX.NDS.128.F3.0F.WIG 5A /r + + AVX + + Convert one single-precision floating-point value in xmm3/m32 to one double-precision floating-point value and merge with high bits of xmm2. + + + VCVTSS2SD + xmm1 {k1}{z},xmm2,xmm3/m32{sae} + EVEX.NDS.LIG.F3.0F.W0 5A /r + + AVX512F + + Convert one single-precision floating-point value in xmm3/m32 to one double-precision floating-point value and merge with high bits of xmm2 under writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + CVTSS2SI--Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer. + + CVTSS2SI + r32,xmm1/m32 + F3 0F 2D /r + + SSE + + Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32. + + + CVTSS2SI + r64,xmm1/m32 + F3 REX.W 0F 2D /r + + SSE + + Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64. + + + VCVTSS2SI + r32,xmm1/m32 + VEX.128.F3.0F.W0 2D /r + + AVX + + Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32. + + + VCVTSS2SI + r64,xmm1/m32 + VEX.128.F3.0F.W1 2D /r + + AVX + + Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64. + + + VCVTSS2SI + r32,xmm1/m32{er} + EVEX.LIG.F3.0F.W0 2D /r + + AVX512F + + Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32. + + + VCVTSS2SI + r64,xmm1/m32{er} + EVEX.LIG.F3.0F.W1 2D /r + + AVX512F + + Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTSS2USI--Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer. + + VCVTSS2USI + r32,xmm1/m32{er} + EVEX.LIG.F3.0F.W0 79 /r + + AVX512F + + Convert one single-precision floating-point value from xmm1/m32 to one unsigned doubleword integer in r32. + + + VCVTSS2USI + r64,xmm1/m32{er} + EVEX.LIG.F3.0F.W1 79 /r + + AVX512F + + Convert one single-precision floating-point value from xmm1/m32 to one unsigned quadword integer in r64. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTTPD2DQ--Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers. + + CVTTPD2DQ + xmm1,xmm2/m128 + 66 0F E6 /r + + SSE2 + + Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1 using truncation. + + + VCVTTPD2DQ + xmm1,xmm2/m128 + VEX.128.66.0F.WIG E6 /r + + AVX + + Convert two packed double-precision floating-point values in xmm2/mem to two signed doubleword integers in xmm1 using truncation. + + + VCVTTPD2DQ + xmm1,ymm2/m256 + VEX.256.66.0F.WIG E6 /r + + AVX + + Convert four packed double-precision floating-point values in ymm2/mem to four signed doubleword integers in xmm1 using truncation. + + + VCVTTPD2DQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F.W1 E6 /r + + AVX512VL + AVX512F + + Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two signed doubleword integers in xmm1 using truncation subject to writemask k1. + + + VCVTTPD2DQ + xmm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F.W1 E6 /r + + AVX512VL + AVX512F + + Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four signed doubleword integers in xmm1 using truncation subject to writemask k1. + + + VCVTTPD2DQ + ymm1 {k1}{z},zmm2/m512/m64bcst{sae} + EVEX.512.66.0F.W1 E6 /r + + AVX512F + + Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight signed doubleword integers in ymm1 using truncation subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTTPD2QQ--Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers. + + VCVTTPD2QQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F.W1 7A /r + + AVX512VL + AVX512DQ + + Convert two packed double-precision floating-point values from zmm2/m128/m64bcst to two packed quadword integers in zmm1 using truncation with writemask k1. + + + VCVTTPD2QQ + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F.W1 7A /r + + AVX512VL + AVX512DQ + + Convert four packed double-precision floating-point values from ymm2/m256/m64bcst to four packed quadword integers in ymm1 using truncation with writemask k1. + + + VCVTTPD2QQ + zmm1 {k1}{z},zmm2/m512/m64bcst{sae} + EVEX.512.66.0F.W1 7A /r + + AVX512DQ + + Convert eight packed double-precision floating-point values from zmm2/m512 to eight packed quadword integers in zmm1 using truncation with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTTPD2UDQ--Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers. + + VCVTTPD2UDQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.0F.W1 78 /r + + AVX512VL + AVX512F + + Convert two packed double-precision floating-point values in xmm2/m128/m64bcst to two unsigned doubleword integers in xmm1 using truncation subject to writemask k1. + + + VCVTTPD2UDQ + xmm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.0F.W1 78 02 /r + + AVX512VL + AVX512F + + Convert four packed double-precision floating-point values in ymm2/m256/m64bcst to four unsigned doubleword integers in xmm1 using truncation subject to writemask k1. + + + VCVTTPD2UDQ + ymm1 {k1}{z},zmm2/m512/m64bcst{sae} + EVEX.512.0F.W1 78 /r + + AVX512F + + Convert eight packed double-precision floating-point values in zmm2/m512/m64bcst to eight unsigned doubleword integers in ymm1 using truncation subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTTPD2UQQ--Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers. + + VCVTTPD2UQQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F.W1 78 /r + + AVX512VL + AVX512DQ + + Convert two packed double-precision floating-point values from xmm2/m128/m64bcst to two packed unsigned quadword integers in xmm1 using truncation with writemask k1. + + + VCVTTPD2UQQ + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F.W1 78 /r + + AVX512VL + AVX512DQ + + Convert four packed double-precision floating-point values from ymm2/m256/m64bcst to four packed unsigned quadword integers in ymm1 using truncation with writemask k1. + + + VCVTTPD2UQQ + zmm1 {k1}{z},zmm2/m512/m64bcst{sae} + EVEX.512.66.0F.W1 78 /r + + AVX512DQ + + Convert eight packed double-precision floating-point values from zmm2/mem to eight packed unsigned quadword integers in zmm1 using truncation with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTTPS2DQ--Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values. + + CVTTPS2DQ + xmm1,xmm2/m128 + F3 0F 5B /r + + SSE2 + + Convert four packed single-precision floating-point values from xmm2/mem to four packed signed doubleword values in xmm1 using truncation. + + + VCVTTPS2DQ + xmm1,xmm2/m128 + VEX.128.F3.0F.WIG 5B /r + + AVX + + Convert four packed single-precision floating-point values from xmm2/mem to four packed signed doubleword values in xmm1 using truncation. + + + VCVTTPS2DQ + ymm1,ymm2/m256 + VEX.256.F3.0F.WIG 5B /r + + AVX + + Convert eight packed single-precision floating-point values from ymm2/mem to eight packed signed doubleword values in ymm1 using truncation. + + + VCVTTPS2DQ + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.F3.0F.W0 5B /r + + AVX512VL + AVX512F + + Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed doubleword values in xmm1 using truncation subject to writemask k1. + + + VCVTTPS2DQ + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.F3.0F.W0 5B /r + + AVX512VL + AVX512F + + Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed doubleword values in ymm1 using truncation subject to writemask k1. + + + VCVTTPS2DQ + zmm1 {k1}{z},zmm2/m512/m32bcst {sae} + EVEX.512.F3.0F.W0 5B /r + + AVX512F + + Convert sixteen packed single-precision floating-point values from zmm2/m512/m32bcst to sixteen packed signed doubleword values in zmm1 using truncation subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTTPS2UDQ--Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values. + + VCVTTPS2UDQ + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.0F.W0 78 /r + + AVX512VL + AVX512F + + Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed unsigned doubleword values in xmm1 using truncation subject to writemask k1. + + + VCVTTPS2UDQ + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.0F.W0 78 /r + + AVX512VL + AVX512F + + Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed unsigned doubleword values in ymm1 using truncation subject to writemask k1. + + + VCVTTPS2UDQ + zmm1 {k1}{z},zmm2/m512/m32bcst{sae} + EVEX.512.0F.W0 78 /r + + AVX512F + + Convert sixteen packed single-precision floatingpoint values from zmm2/m512/m32bcst to sixteen packed unsigned doubleword values in zmm1 using truncation subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTTPS2QQ--Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values. + + VCVTTPS2QQ + xmm1 {k1}{z},xmm2/m64/m32bcst + EVEX.128.66.0F.W0 7A /r + + AVX512VL + AVX512DQ + + Convert two packed single precision floating-point values from xmm2/m64/m32bcst to two packed signed quadword values in xmm1 using truncation subject to writemask k1. + + + VCVTTPS2QQ + ymm1 {k1}{z},xmm2/m128/m32bcst + EVEX.256.66.0F.W0 7A /r + + AVX512VL + AVX512DQ + + Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed signed quadword values in ymm1 using truncation subject to writemask k1. + + + VCVTTPS2QQ + zmm1 {k1}{z},ymm2/m256/m32bcst{sae} + EVEX.512.66.0F.W0 7A /r + + AVX512DQ + + Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed signed quadword values in zmm1 using truncation subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTTPS2UQQ--Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values. + + VCVTTPS2UQQ + xmm1 {k1}{z},xmm2/m64/m32bcst + EVEX.128.66.0F.W0 78 /r + + AVX512VL + AVX512DQ + + Convert two packed single precision floating-point values from zmm2/m64/m32bcst to two packed unsigned quadword values in zmm1 using truncation subject to writemask k1. + + + VCVTTPS2UQQ + ymm1 {k1}{z},xmm2/m128/m32bcst + EVEX.256.66.0F.W0 78 /r + + AVX512VL + AVX512DQ + + Convert four packed single precision floating-point values from xmm2/m128/m32bcst to four packed unsigned quadword values in ymm1 using truncation subject to writemask k1. + + + VCVTTPS2UQQ + zmm1 {k1}{z},ymm2/m256/m32bcst{sae} + EVEX.512.66.0F.W0 78 /r + + AVX512DQ + + Convert eight packed single precision floating-point values from ymm2/m256/m32bcst to eight packed unsigned quadword values in zmm1 using truncation subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTTSD2SI--Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer. + + CVTTSD2SI + r32,xmm1/m64 + F2 0F 2C /r + + SSE2 + + Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation. + + + CVTTSD2SI + r64,xmm1/m64 + F2 REX.W 0F 2C /r + + SSE2 + + Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation. + + + VCVTTSD2SI + r32,xmm1/m64 + VEX.128.F2.0F.W0 2C /r + + AVX + + Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation. + + + VCVTTSD2SI + r64,xmm1/m64 + VEX.128.F2.0F.W1 2C /r + + AVX + + Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation. + + + VCVTTSD2SI + r32,xmm1/m64{sae} + EVEX.LIG.F2.0F.W0 2C /r + + AVX512F + + Convert one double-precision floating-point value from xmm1/m64 to one signed doubleword integer in r32 using truncation. + + + VCVTTSD2SI + r64,xmm1/m64{sae} + EVEX.LIG.F2.0F.W1 2C /r + + AVX512F + + Convert one double-precision floating-point value from xmm1/m64 to one signed quadword integer in r64 using truncation. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTTSD2USI--Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer. + + VCVTTSD2USI + r32,xmm1/m64{sae} + EVEX.LIG.F2.0F.W0 78 /r + + AVX512F + + Convert one double-precision floating-point value from xmm1/m64 to one unsigned doubleword integer r32 using truncation. + + + VCVTTSD2USI + r64,xmm1/m64{sae} + EVEX.LIG.F2.0F.W1 78 /r + + AVX512F + + Convert one double-precision floating-point value from xmm1/m64 to one unsigned quadword integer zeroextended into r64 using truncation. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + CVTTSS2SI--Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer. + + CVTTSS2SI + r32,xmm1/m32 + F3 0F 2C /r + + SSE + + Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation. + + + CVTTSS2SI + r64,xmm1/m32 + F3 REX.W 0F 2C /r + + SSE + + Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation. + + + VCVTTSS2SI + r32,xmm1/m32 + VEX.128.F3.0F.W0 2C /r + + AVX + + Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation. + + + VCVTTSS2SI + r64,xmm1/m32 + VEX.128.F3.0F.W1 2C /r + + AVX + + Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation. + + + VCVTTSS2SI + r32,xmm1/m32{sae} + EVEX.LIG.F3.0F.W0 2C /r + + AVX512F + + Convert one single-precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation. + + + VCVTTSS2SI + r64,xmm1/m32{sae} + EVEX.LIG.F3.0F.W1 2C /r + + AVX512F + + Convert one single-precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTTSS2USI--Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer. + + VCVTTSS2USI + r32,xmm1/m32{sae} + EVEX.LIG.F3.0F.W0 78 /r + + AVX512F + + Convert one single-precision floating-point value from xmm1/m32 to one unsigned doubleword integer in r32 using truncation. + + + VCVTTSS2USI + r64,xmm1/m32{sae} + EVEX.LIG.F3.0F.W1 78 /r + + AVX512F + + Convert one single-precision floating-point value from xmm1/m32 to one unsigned quadword integer in r64 using truncation. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTUDQ2PD--Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values. + + VCVTUDQ2PD + xmm1 {k1}{z},xmm2/m64/m32bcst + EVEX.128.F3.0F.W0 7A /r + + AVX512VL + AVX512F + + Convert two packed unsigned doubleword integers from ymm2/m64/m32bcst to packed double-precision floating-point values in zmm1 with writemask k1. + + + VCVTUDQ2PD + ymm1 {k1}{z},xmm2/m128/m32bcst + EVEX.256.F3.0F.W0 7A /r + + AVX512VL + AVX512F + + Convert four packed unsigned doubleword integers from xmm2/m128/m32bcst to packed doubleprecision floating-point values in zmm1 with writemask k1. + + + VCVTUDQ2PD + zmm1 {k1}{z},ymm2/m256/m32bcst + EVEX.512.F3.0F.W0 7A /r + + AVX512F + + Convert eight packed unsigned doubleword integers from ymm2/m256/m32bcst to eight packed doubleprecision floating-point values in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTUDQ2PS--Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values. + + VCVTUDQ2PS + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.F2.0F.W0 7A /r + + AVX512VL + AVX512F + + Convert four packed unsigned doubleword integers from xmm2/m128/m32bcst to packed single-precision floating-point values in xmm1 with writemask k1. + + + VCVTUDQ2PS + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.F2.0F.W0 7A /r + + AVX512VL + AVX512F + + Convert eight packed unsigned doubleword integers from ymm2/m256/m32bcst to packed single-precision floating-point values in zmm1 with writemask k1. + + + VCVTUDQ2PS + zmm1 {k1}{z},zmm2/m512/m32bcst{er} + EVEX.512.F2.0F.W0 7A /r + + AVX512F + + Convert sixteen packed unsigned doubleword integers from zmm2/m512/m32bcst to sixteen packed singleprecision floating-point values in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTUQQ2PD--Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values. + + VCVTUQQ2PD + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.F3.0F.W1 7A /r + + AVX512VL + AVX512DQ + + Convert two packed unsigned quadword integers from xmm2/m128/m64bcst to two packed double-precision floating-point values in xmm1 with writemask k1. + + + VCVTUQQ2PD + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.F3.0F.W1 7A /r + + AVX512VL + AVX512DQ + + Convert four packed unsigned quadword integers from ymm2/m256/m64bcst to packed double-precision floatingpoint values in ymm1 with writemask k1. + + + VCVTUQQ2PD + zmm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.F3.0F.W1 7A /r + + AVX512DQ + + Convert eight packed unsigned quadword integers from zmm2/m512/m64bcst to eight packed double-precision floating-point values in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTUQQ2PS--Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values. + + VCVTUQQ2PS + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.F2.0F.W1 7A /r + + AVX512VL + AVX512DQ + + Convert two packed unsigned quadword integers from xmm2/m128/m64bcst to packed single-precision floatingpoint values in zmm1 with writemask k1. + + + VCVTUQQ2PS + xmm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.F2.0F.W1 7A /r + + AVX512VL + AVX512DQ + + Convert four packed unsigned quadword integers from ymm2/m256/m64bcst to packed single-precision floatingpoint values in xmm1 with writemask k1. + + + VCVTUQQ2PS + ymm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.F2.0F.W1 7A /r + + AVX512DQ + + Convert eight packed unsigned quadword integers from zmm2/m512/m64bcst to eight packed single-precision floating-point values in zmm1 with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VCVTUSI2SD--Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value. + + VCVTUSI2SD + xmm1,xmm2,r/m32 + EVEX.NDS.LIG.F2.0F.W0 7B /r + + AVX512F + + Convert one unsigned doubleword integer from r/m32 to one double-precision floating-point value in xmm1. + + + VCVTUSI2SD + xmm1,xmm2,r/m64{er} + EVEX.NDS.LIG.F2.0F.W1 7B /r + + AVX512F + + Convert one unsigned quadword integer from r/m64 to one double-precision floating-point value in xmm1. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VCVTUSI2SS--Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value. + + VCVTUSI2SS + xmm1,xmm2,r/m32{er} + EVEX.NDS.LIG.F3.0F.W0 7B /r + + AVX512F + + Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm1. + + + VCVTUSI2SS + xmm1,xmm2,r/m64{er} + EVEX.NDS.LIG.F3.0F.W1 7B /r + + AVX512F + + Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm1. + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + + VDBPSADBW--Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes. + + VDBPSADBW + xmm1 {k1}{z},xmm2,xmm3/m128,imm8 + EVEX.NDS.128.66.0F3A.W0 42 /r ib + + AVX512VL + AVX512BW + + Compute packed SAD word results of unsigned bytes in dword block from xmm2 with unsigned bytes of dword blocks transformed from xmm3/m128 using the shuffle controls in imm8. Results are written to xmm1 under the writemask k1. + + + VDBPSADBW + ymm1 {k1}{z},ymm2,ymm3/m256,imm8 + EVEX.NDS.256.66.0F3A.W0 42 /r ib + + AVX512VL + AVX512BW + + Compute packed SAD word results of unsigned bytes in dword block from ymm2 with unsigned bytes of dword blocks transformed from ymm3/m256 using the shuffle controls in imm8. Results are written to ymm1 under the writemask k1. + + + VDBPSADBW + zmm1 {k1}{z},zmm2,zmm3/m512,imm8 + EVEX.NDS.512.66.0F3A.W0 42 /r ib + + AVX512BW + + Compute packed SAD word results of unsigned bytes in dword block from zmm2 with unsigned bytes of dword blocks transformed from zmm3/m512 using the shuffle controls in imm8. Results are written to zmm1 under the writemask k1. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + VEXPANDPD--Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory. + + VEXPANDPD + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F38.W1 88 /r + + AVX512VL + AVX512F + + Expand packed double-precision floating-point values from xmm2/m128 to xmm1 using writemask k1. + + + VEXPANDPD + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F38.W1 88 /r + + AVX512VL + AVX512F + + Expand packed double-precision floating-point values from ymm2/m256 to ymm1 using writemask k1. + + + VEXPANDPD + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F38.W1 88 /r + + AVX512F + + Expand packed double-precision floating-point values from zmm2/m512 to zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VEXPANDPS--Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory. + + VEXPANDPS + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F38.W0 88 /r + + AVX512VL + AVX512F + + Expand packed single-precision floating-point values from xmm2/m128 to xmm1 using writemask k1. + + + VEXPANDPS + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F38.W0 88 /r + + AVX512VL + AVX512F + + Expand packed single-precision floating-point values from ymm2/m256 to ymm1 using writemask k1. + + + VEXPANDPS + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F38.W0 88 /r + + AVX512F + + Expand packed single-precision floating-point values from zmm2/m512 to zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4--Extr act Packed Floating-Point Values. + + VEXTRACTF128 + xmm1/m128,ymm2,imm8 + VEX.256.66.0F3A.W0 19 /r ib + + AVX + + Extract 128 bits of packed floating-point values from ymm2 and store results in xmm1/m128. + + + VEXTRACTF32X4 + xmm1/m128 {k1}{z},ymm2,imm8 + EVEX.256.66.0F3A.W0 19 /r ib + + AVX512VL + AVX512F + + Extract 128 bits of packed single-precision floatingpoint values from ymm2 and store results in xmm1/m128 subject to writemask k1. + + + VEXTRACTF32x4 + xmm1/m128 {k1}{z},zmm2,imm8 + EVEX.512.66.0F3A.W0 19 /r ib + + AVX512F + + Extract 128 bits of packed single-precision floatingpoint values from zmm2 and store results in xmm1/m128 subject to writemask k1. + + + VEXTRACTF64X2 + xmm1/m128 {k1}{z},ymm2,imm8 + EVEX.256.66.0F3A.W1 19 /r ib + + AVX512VL + AVX512DQ + + Extract 128 bits of packed double-precision floating-point values from ymm2 and store results in xmm1/m128 subject to writemask k1. + + + VEXTRACTF64X2 + xmm1/m128 {k1}{z},zmm2,imm8 + EVEX.512.66.0F3A.W1 19 /r ib + + AVX512DQ + + Extract 128 bits of packed double-precision floating-point values from zmm2 and store results in xmm1/m128 subject to writemask k1. + + + VEXTRACTF32X8 + ymm1/m256 {k1}{z},zmm2,imm8 + EVEX.512.66.0F3A.W0 1B /r ib + + AVX512DQ + + Extract 256 bits of packed single-precision floatingpoint values from zmm2 and store results in ymm1/m256 subject to writemask k1. + + + VEXTRACTF64x4 + ymm1/m256 {k1}{z},zmm2,imm8 + EVEX.512.66.0F3A.W1 1B /r ib + + AVX512F + + Extract 256 bits of packed double-precision floating-point values from zmm2 and store results in ymm1/m256 subject to writemask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + + VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4--Extract packed Integer Values. + + VEXTRACTI128 + xmm1/m128,ymm2,imm8 + VEX.256.66.0F3A.W0 39 /r ib + + AVX2 + + Extract 128 bits of integer data from ymm2 and store results in xmm1/m128. + + + VEXTRACTI32X4 + xmm1/m128 {k1}{z},ymm2,imm8 + EVEX.256.66.0F3A.W0 39 /r ib + + AVX512VL + AVX512F + + Extract 128 bits of double-word integer values from ymm2 and store results in xmm1/m128 subject to writemask k1. + + + VEXTRACTI32x4 + xmm1/m128 {k1}{z},zmm2,imm8 + EVEX.512.66.0F3A.W0 39 /r ib + + AVX512F + + Extract 128 bits of double-word integer values from zmm2 and store results in xmm1/m128 subject to writemask k1. + + + VEXTRACTI64X2 + xmm1/m128 {k1}{z},ymm2,imm8 + EVEX.256.66.0F3A.W1 39 /r ib + + AVX512VL + AVX512DQ + + Extract 128 bits of quad-word integer values from ymm2 and store results in xmm1/m128 subject to writemask k1. + + + VEXTRACTI64X2 + xmm1/m128 {k1}{z},zmm2,imm8 + EVEX.512.66.0F3A.W1 39 /r ib + + AVX512DQ + + Extract 128 bits of quad-word integer values from zmm2 and store results in xmm1/m128 subject to writemask k1. + + + VEXTRACTI32X8 + ymm1/m256 {k1}{z},zmm2,imm8 + EVEX.512.66.0F3A.W0 3B /r ib + + AVX512DQ + + Extract 256 bits of double-word integer values from zmm2 and store results in ymm1/m256 subject to writemask k1. + + + VEXTRACTI64x4 + ymm1/m256 {k1}{z},zmm2,imm8 + EVEX.512.66.0F3A.W1 3B /r ib + + AVX512F + + Extract 256 bits of quad-word integer values from zmm2 and store results in ymm1/m256 subject to writemask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + + EXTRACTPS--Extract Packed Floating-Point Values. + + EXTRACTPS + reg/m32,xmm1,imm8 + 66 0F 3A 17 /r ib + + SSE4_1 + + Extract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable. + + + VEXTRACTPS + reg/m32,xmm1,imm8 + VEX.128.66.0F3A.WIG 17 /r ib + + AVX + + Extract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable. + + + VEXTRACTPS + reg/m32,xmm1,imm8 + EVEX.128.66.0F3A.WIG 17 /r ib + + AVX512F + + Extract one single-precision floating-point value from xmm1 at the offset specified by imm8 and store the result in reg or m32. Zero extend the results in 64-bit register if applicable. + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + + VFIXUPIMMPD--Fix Up Special Packed Float64 Values. + + VFIXUPIMMPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst,imm8 + EVEX.NDS.128.66.0F3A.W1 54 /r ib + + AVX512VL + AVX512F + + Fix up special numbers in float64 vector xmm1, float64 vector xmm2 and int64 vector xmm3/m128/m64bcst and store the result in xmm1, under writemask. + + + VFIXUPIMMPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F3A.W1 54 /r ib + + AVX512VL + AVX512F + + Fix up special numbers in float64 vector ymm1, float64 vector ymm2 and int64 vector ymm3/m256/m64bcst and store the result in ymm1, under writemask. + + + VFIXUPIMMPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{sae},imm8 + EVEX.NDS.512.66.0F3A.W1 54 /r ib + + AVX512F + + Fix up elements of float64 vector in zmm2 using int64 vector table in zmm3/m512/m64bcst, combine with preserved elements from zmm1, and store the result in zmm1. + + + ModRM:reg(r,w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + VFIXUPIMMPS--Fix Up Special Packed Float32 Values. + + VFIXUPIMMPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst,imm8 + EVEX.NDS.128.66.0F3A.W0 54 /r + + AVX512VL + AVX512F + + Fix up special numbers in float32 vector xmm1, float32 vector xmm2 and int32 vector xmm3/m128/m32bcst and store the result in xmm1, under writemask. + + + VFIXUPIMMPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.66.0F3A.W0 54 /r + + AVX512VL + AVX512F + + Fix up special numbers in float32 vector ymm1, float32 vector ymm2 and int32 vector ymm3/m256/m32bcst and store the result in ymm1, under writemask. + + + VFIXUPIMMPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{sae},imm8 + EVEX.NDS.512.66.0F3A.W0 54 /r ib + + AVX512F + + Fix up elements of float32 vector in zmm2 using int32 vector table in zmm3/m512/m32bcst, combine with preserved elements from zmm1, and store the result in zmm1. + + + ModRM:reg(r,w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + VFIXUPIMMSD--Fix Up Special Scalar Float64 Value. + + VFIXUPIMMSD + xmm1 {k1}{z},xmm2,xmm3/m64{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W1 55 /r ib + + AVX512F + + Fix up a float64 number in the low quadword element of xmm2 using scalar int32 table in xmm3/m64 and store the result in xmm1. + + + ModRM:reg(r,w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + VFIXUPIMMSS--Fix Up Special Scalar Float32 Value. + + VFIXUPIMMSS + xmm1 {k1}{z},xmm2,xmm3/m32{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W0 55 /r ib + + AVX512F + + Fix up a float32 number in the low doubleword element in xmm2 using scalar int32 table in xmm3/m32 and store the result in xmm1. + + + ModRM:reg(r,w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + VFMADD132PD/VFMADD213PD/VFMADD231PD--Fused Multiply-Add of Packed Double-Precision Floating-Point Values. + + VFMADD132PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 98 /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, add to xmm2 and put result in xmm1. + + + VFMADD213PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 A8 /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm2, add to xmm3/mem and put result in xmm1. + + + VFMADD231PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 B8 /r + + FMA + + Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, add to xmm1 and put result in xmm1. + + + VFMADD132PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 98 /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, add to ymm2 and put result in ymm1. + + + VFMADD213PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 A8 /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm2, add to ymm3/mem and put result in ymm1. + + + VFMADD231PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 B8 /r + + FMA + + Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, add to ymm1 and put result in ymm1. + + + VFMADD132PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 98 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, add to xmm2 and put result in xmm1. + + + VFMADD213PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 A8 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm2, add to xmm3/m128/m64bcst and put result in xmm1. + + + VFMADD231PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 B8 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, add to xmm1 and put result in xmm1. + + + VFMADD132PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 98 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, add to ymm2 and put result in ymm1. + + + VFMADD213PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 A8 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm2, add to ymm3/m256/m64bcst and put result in ymm1. + + + VFMADD231PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 B8 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, add to ymm1 and put result in ymm1. + + + VFMADD132PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 98 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, add to zmm2 and put result in zmm1. + + + VFMADD213PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 A8 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm2, add to zmm3/m512/m64bcst and put result in zmm1. + + + VFMADD231PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 B8 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, add to zmm1 and put result in zmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMADD132PS/VFMADD213PS/VFMADD231PS--Fused Multiply-Add of Packed Single-Precision Floating-Point Values. + + VFMADD132PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 98 /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, add to xmm2 and put result in xmm1. + + + VFMADD213PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 A8 /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm2, add to xmm3/mem and put result in xmm1. + + + VFMADD231PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 B8 /r + + FMA + + Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, add to xmm1 and put result in xmm1. + + + VFMADD132PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 98 /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, add to ymm2 and put result in ymm1. + + + VFMADD213PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 A8 /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm2, add to ymm3/mem and put result in ymm1. + + + VFMADD231PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 B8 /r + + FMA + + Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, add to ymm1 and put result in ymm1. + + + VFMADD132PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 98 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, add to xmm2 and put result in xmm1. + + + VFMADD213PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 A8 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm2, add to xmm3/m128/m32bcst and put result in xmm1. + + + VFMADD231PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 B8 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, add to xmm1 and put result in xmm1. + + + VFMADD132PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 98 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, add to ymm2 and put result in ymm1. + + + VFMADD213PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 A8 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm2, add to ymm3/m256/m32bcst and put result in ymm1. + + + VFMADD231PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 B8 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, add to ymm1 and put result in ymm1. + + + VFMADD132PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 98 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, add to zmm2 and put result in zmm1. + + + VFMADD213PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 A8 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm2, add to zmm3/m512/m32bcst and put result in zmm1. + + + VFMADD231PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 B8 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, add to zmm1 and put result in zmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMADD132SD/VFMADD213SD/VFMADD231SD--Fused Multiply-Add of Scalar Double-Precision Floating-Point Values. + + VFMADD132SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 99 /r + + FMA + + Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, add to xmm2 and put result in xmm1. + + + VFMADD213SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 A9 /r + + FMA + + Multiply scalar double-precision floating-point value from xmm1 and xmm2, add to xmm3/m64 and put result in xmm1. + + + VFMADD231SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 B9 /r + + FMA + + Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, add to xmm1 and put result in xmm1. + + + VFMADD132SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 99 /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, add to xmm2 and put result in xmm1. + + + VFMADD213SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 A9 /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm1 and xmm2, add to xmm3/m64 and put result in xmm1. + + + VFMADD231SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 B9 /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, add to xmm1 and put result in xmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMADD132SS/VFMADD213SS/VFMADD231SS--Fused Multiply-Add of Scalar Single-Precision Floating-Point Values. + + VFMADD132SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 99 /r + + FMA + + Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, add to xmm2 and put result in xmm1. + + + VFMADD213SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 A9 /r + + FMA + + Multiply scalar single-precision floating-point value from xmm1 and xmm2, add to xmm3/m32 and put result in xmm1. + + + VFMADD231SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 B9 /r + + FMA + + Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, add to xmm1 and put result in xmm1. + + + VFMADD132SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 99 /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, add to xmm2 and put result in xmm1. + + + VFMADD213SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 A9 /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm1 and xmm2, add to xmm3/m32 and put result in xmm1. + + + VFMADD231SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 B9 /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, add to xmm1 and put result in xmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD--Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values. + + VFMADDSUB132PD + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W1 96 /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, add/subtract elements in xmm2 and put result in xmm1. + + + VFMADDSUB213PD + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W1 A6 /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/mem and put result in xmm1. + + + VFMADDSUB231PD + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W1 B6 /r + + FMA + + Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, add/subtract elements in xmm1 and put result in xmm1. + + + VFMADDSUB132PD + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W1 96 /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, add/subtract elements in ymm2 and put result in ymm1. + + + VFMADDSUB213PD + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W1 A6 /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/mem and put result in ymm1. + + + VFMADDSUB231PD + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W1 B6 /r + + FMA + + Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, add/subtract elements in ymm1 and put result in ymm1. + + + VFMADDSUB213PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 A6 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1. + + + VFMADDSUB231PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 B6 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, add/subtract elements in xmm1 and put result in xmm1 subject to writemask k1. + + + VFMADDSUB132PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 96 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, add/subtract elements in xmm2 and put result in xmm1 subject to writemask k1. + + + VFMADDSUB213PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 A6 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1. + + + VFMADDSUB231PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 B6 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, add/subtract elements in ymm1 and put result in ymm1 subject to writemask k1. + + + VFMADDSUB132PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 96 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, add/subtract elements in ymm2 and put result in ymm1 subject to writemask k1. + + + VFMADDSUB213PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.DDS.512.66.0F38.W1 A6 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1and zmm2, add/subtract elements in zmm3/m512/m64bcst and put result in zmm1 subject to writemask k1. + + + VFMADDSUB231PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.DDS.512.66.0F38.W1 B6 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, add/subtract elements in zmm1 and put result in zmm1 subject to writemask k1. + + + VFMADDSUB132PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.DDS.512.66.0F38.W1 96 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, add/subtract elements in zmm2 and put result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS--Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values. + + VFMADDSUB132PS + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W0 96 /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, add/subtract elements in xmm2 and put result in xmm1. + + + VFMADDSUB213PS + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W0 A6 /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/mem and put result in xmm1. + + + VFMADDSUB231PS + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W0 B6 /r + + FMA + + Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, add/subtract elements in xmm1 and put result in xmm1. + + + VFMADDSUB132PS + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W0 96 /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, add/subtract elements in ymm2 and put result in ymm1. + + + VFMADDSUB213PS + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W0 A6 /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/mem and put result in ymm1. + + + VFMADDSUB231PS + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W0 B6 /r + + FMA + + Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, add/subtract elements in ymm1 and put result in ymm1. + + + VFMADDSUB213PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 A6 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm2, add/subtract elements in xmm3/m128/m32bcst and put result in xmm1 subject to writemask k1. + + + VFMADDSUB231PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 B6 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, add/subtract elements in xmm1 and put result in xmm1 subject to writemask k1. + + + VFMADDSUB132PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 96 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, add/subtract elements in zmm2 and put result in xmm1 subject to writemask k1. + + + VFMADDSUB213PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 A6 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm2, add/subtract elements in ymm3/m256/m32bcst and put result in ymm1 subject to writemask k1. + + + VFMADDSUB231PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 B6 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, add/subtract elements in ymm1 and put result in ymm1 subject to writemask k1. + + + VFMADDSUB132PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 96 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, add/subtract elements in ymm2 and put result in ymm1 subject to writemask k1. + + + VFMADDSUB213PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.DDS.512.66.0F38.W0 A6 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm2, add/subtract elements in zmm3/m512/m32bcst and put result in zmm1 subject to writemask k1. + + + VFMADDSUB231PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.DDS.512.66.0F38.W0 B6 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, add/subtract elements in zmm1 and put result in zmm1 subject to writemask k1. + + + VFMADDSUB132PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.DDS.512.66.0F38.W0 96 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, add/subtract elements in zmm2 and put result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD--Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values. + + VFMSUBADD132PD + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W1 97 /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, subtract/add elements in xmm2 and put result in xmm1. + + + VFMSUBADD213PD + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W1 A7 /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm2, subtract/add elements in xmm3/mem and put result in xmm1. + + + VFMSUBADD231PD + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W1 B7 /r + + FMA + + Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, subtract/add elements in xmm1 and put result in xmm1. + + + VFMSUBADD132PD + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W1 97 /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, subtract/add elements in ymm2 and put result in ymm1. + + + VFMSUBADD213PD + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W1 A7 /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm2, subtract/add elements in ymm3/mem and put result in ymm1. + + + VFMSUBADD231PD + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W1 B7 /r + + FMA + + Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, subtract/add elements in ymm1 and put result in ymm1. + + + VFMSUBADD132PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 97 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, subtract/add elements in xmm2 and put result in xmm1 subject to writemask k1. + + + VFMSUBADD213PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 A7 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm2, subtract/add elements in xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1. + + + VFMSUBADD231PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 B7 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, subtract/add elements in xmm1 and put result in xmm1 subject to writemask k1. + + + VFMSUBADD132PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 97 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, subtract/add elements in ymm2 and put result in ymm1 subject to writemask k1. + + + VFMSUBADD213PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 A7 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm2, subtract/add elements in ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1. + + + VFMSUBADD231PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 B7 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, subtract/add elements in ymm1 and put result in ymm1 subject to writemask k1. + + + VFMSUBADD132PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.DDS.512.66.0F38.W1 97 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, subtract/add elements in zmm2 and put result in zmm1 subject to writemask k1. + + + VFMSUBADD213PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.DDS.512.66.0F38.W1 A7 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm2, subtract/add elements in zmm3/m512/m64bcst and put result in zmm1 subject to writemask k1. + + + VFMSUBADD231PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.DDS.512.66.0F38.W1 B7 /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, subtract/add elements in zmm1 and put result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS--Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values. + + VFMSUBADD132PS + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W0 97 /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, subtract/add elements in xmm2 and put result in xmm1. + + + VFMSUBADD213PS + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W0 A7 /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm2, subtract/add elements in xmm3/mem and put result in xmm1. + + + VFMSUBADD231PS + xmm1,xmm2,xmm3/m128 + VEX.DDS.128.66.0F38.W0 B7 /r + + FMA + + Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, subtract/add elements in xmm1 and put result in xmm1. + + + VFMSUBADD132PS + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W0 97 /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, subtract/add elements in ymm2 and put result in ymm1. + + + VFMSUBADD213PS + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W0 A7 /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm2, subtract/add elements in ymm3/mem and put result in ymm1. + + + VFMSUBADD231PS + ymm1,ymm2,ymm3/m256 + VEX.DDS.256.66.0F38.W0 B7 /r + + FMA + + Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, subtract/add elements in ymm1 and put result in ymm1. + + + VFMSUBADD132PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 97 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, subtract/add elements in xmm2 and put result in xmm1 subject to writemask k1. + + + VFMSUBADD213PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 A7 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm2, subtract/add elements in xmm3/m128/m32bcst and put result in xmm1 subject to writemask k1. + + + VFMSUBADD231PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 B7 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, subtract/add elements in xmm1 and put result in xmm1 subject to writemask k1. + + + VFMSUBADD132PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 97 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, subtract/add elements in ymm2 and put result in ymm1 subject to writemask k1. + + + VFMSUBADD213PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 A7 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm2, subtract/add elements in ymm3/m256/m32bcst and put result in ymm1 subject to writemask k1. + + + VFMSUBADD231PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 B7 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, subtract/add elements in ymm1 and put result in ymm1 subject to writemask k1. + + + VFMSUBADD132PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.DDS.512.66.0F38.W0 97 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, subtract/add elements in zmm2 and put result in zmm1 subject to writemask k1. + + + VFMSUBADD213PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.DDS.512.66.0F38.W0 A7 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm2, subtract/add elements in zmm3/m512/m32bcst and put result in zmm1 subject to writemask k1. + + + VFMSUBADD231PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.DDS.512.66.0F38.W0 B7 /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, subtract/add elements in zmm1 and put result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMSUB132PD/VFMSUB213PD/VFMSUB231PD--Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values. + + VFMSUB132PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 9A /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, subtract xmm2 and put result in xmm1. + + + VFMSUB213PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 AA /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm2, subtract xmm3/mem and put result in xmm1. + + + VFMSUB231PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 BA /r + + FMA + + Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, subtract xmm1 and put result in xmm1. + + + VFMSUB132PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 9A /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, subtract ymm2 and put result in ymm1. + + + VFMSUB213PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 AA /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm2, subtract ymm3/mem and put result in ymm1. + + + VFMSUB231PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 BA /r + + FMA + + Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, subtract ymm1 and put result in ymm1.S. + + + VFMSUB132PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 9A /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, subtract xmm2 and put result in xmm1 subject to writemask k1. + + + VFMSUB213PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 AA /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm2, subtract xmm3/m128/m64bcst and put result in xmm1 subject to writemask k1. + + + VFMSUB231PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 BA /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, subtract xmm1 and put result in xmm1 subject to writemask k1. + + + VFMSUB132PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 9A /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, subtract ymm2 and put result in ymm1 subject to writemask k1. + + + VFMSUB213PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 AA /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm2, subtract ymm3/m256/m64bcst and put result in ymm1 subject to writemask k1. + + + VFMSUB231PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 BA /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, subtract ymm1 and put result in ymm1 subject to writemask k1. + + + VFMSUB132PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 9A /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, subtract zmm2 and put result in zmm1 subject to writemask k1. + + + VFMSUB213PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 AA /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm2, subtract zmm3/m512/m64bcst and put result in zmm1 subject to writemask k1. + + + VFMSUB231PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 BA /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, subtract zmm1 and put result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMSUB132PS/VFMSUB213PS/VFMSUB231PS--Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values. + + VFMSUB132PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 9A /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, subtract xmm2 and put result in xmm1. + + + VFMSUB213PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 AA /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm2, subtract xmm3/mem and put result in xmm1. + + + VFMSUB231PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 BA /r + + FMA + + Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, subtract xmm1 and put result in xmm1. + + + VFMSUB132PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 9A /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, subtract ymm2 and put result in ymm1. + + + VFMSUB213PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 AA /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm2, subtract ymm3/mem and put result in ymm1. + + + VFMSUB231PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 BA /r + + FMA + + Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, subtract ymm1 and put result in ymm1. + + + VFMSUB132PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 9A /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, subtract xmm2 and put result in xmm1. + + + VFMSUB213PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 AA /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm2, subtract xmm3/m128/m32bcst and put result in xmm1. + + + VFMSUB231PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 BA /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, subtract xmm1 and put result in xmm1. + + + VFMSUB132PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 9A /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, subtract ymm2 and put result in ymm1. + + + VFMSUB213PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 AA /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm2, subtract ymm3/m256/m32bcst and put result in ymm1. + + + VFMSUB231PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 BA /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, subtract ymm1 and put result in ymm1. + + + VFMSUB132PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 9A /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, subtract zmm2 and put result in zmm1. + + + VFMSUB213PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 AA /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm2, subtract zmm3/m512/m32bcst and put result in zmm1. + + + VFMSUB231PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 BA /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, subtract zmm1 and put result in zmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMSUB132SD/VFMSUB213SD/VFMSUB231SD--Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values. + + VFMSUB132SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 9B /r + + FMA + + Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, subtract xmm2 and put result in xmm1. + + + VFMSUB213SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 AB /r + + FMA + + Multiply scalar double-precision floating-point value from xmm1 and xmm2, subtract xmm3/m64 and put result in xmm1. + + + VFMSUB231SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 BB /r + + FMA + + Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, subtract xmm1 and put result in xmm1. + + + VFMSUB132SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 9B /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, subtract xmm2 and put result in xmm1. + + + VFMSUB213SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 AB /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm1 and xmm2, subtract xmm3/m64 and put result in xmm1. + + + VFMSUB231SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 BB /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, subtract xmm1 and put result in xmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFMSUB132SS/VFMSUB213SS/VFMSUB231SS--Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values. + + VFMSUB132SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 9B /r + + FMA + + Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, subtract xmm2 and put result in xmm1. + + + VFMSUB213SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 AB /r + + FMA + + Multiply scalar single-precision floating-point value from xmm1 and xmm2, subtract xmm3/m32 and put result in xmm1. + + + VFMSUB231SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 BB /r + + FMA + + Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, subtract xmm1 and put result in xmm1. + + + VFMSUB132SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 9B /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, subtract xmm2 and put result in xmm1. + + + VFMSUB213SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 AB /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm1 and xmm2, subtract xmm3/m32 and put result in xmm1. + + + VFMSUB231SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 BB /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, subtract xmm1 and put result in xmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFNMADD132PD/VFNMADD213PD/VFNMADD231PD--Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values. + + VFNMADD132PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 9C /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and add to xmm2 and put result in xmm1. + + + VFNMADD213PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 AC /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/mem and put result in xmm1. + + + VFNMADD231PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 BC /r + + FMA + + Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and add to xmm1 and put result in xmm1. + + + VFNMADD132PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 9C /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and add to ymm2 and put result in ymm1. + + + VFNMADD213PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 AC /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/mem and put result in ymm1. + + + VFNMADD231PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 BC /r + + FMA + + Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and add to ymm1 and put result in ymm1. + + + VFNMADD132PD + xmm0 {k1}{z},xmm1,xmm2/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 9C /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, negate the multiplication result and add to xmm2 and put result in xmm1. + + + VFNMADD213PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 AC /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/m128/m64bcst and put result in xmm1. + + + VFNMADD231PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 BC /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, negate the multiplication result and add to xmm1 and put result in xmm1. + + + VFNMADD132PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 9C /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, negate the multiplication result and add to ymm2 and put result in ymm1. + + + VFNMADD213PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 AC /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/m256/m64bcst and put result in ymm1. + + + VFNMADD231PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 BC /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, negate the multiplication result and add to ymm1 and put result in ymm1. + + + VFNMADD132PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 9C /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, negate the multiplication result and add to zmm2 and put result in zmm1. + + + VFNMADD213PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 AC /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm2, negate the multiplication result and add to zmm3/m512/m64bcst and put result in zmm1. + + + VFNMADD231PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 BC /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, negate the multiplication result and add to zmm1 and put result in zmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFNMADD132PS/VFNMADD213PS/VFNMADD231PS--Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values. + + VFNMADD132PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 9C /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and add to xmm2 and put result in xmm1. + + + VFNMADD213PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 AC /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/mem and put result in xmm1. + + + VFNMADD231PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 BC /r + + FMA + + Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and add to xmm1 and put result in xmm1. + + + VFNMADD132PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 9C /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and add to ymm2 and put result in ymm1. + + + VFNMADD213PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 AC /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/mem and put result in ymm1. + + + VFNMADD231PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 BC /r + + FMA + + Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and add to ymm1 and put result in ymm1. + + + VFNMADD132PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 9C /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, negate the multiplication result and add to xmm2 and put result in xmm1. + + + VFNMADD213PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 AC /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and add to xmm3/m128/m32bcst and put result in xmm1. + + + VFNMADD231PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 BC /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, negate the multiplication result and add to xmm1 and put result in xmm1. + + + VFNMADD132PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 9C /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, negate the multiplication result and add to ymm2 and put result in ymm1. + + + VFNMADD213PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 AC /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and add to ymm3/m256/m32bcst and put result in ymm1. + + + VFNMADD231PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 BC /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, negate the multiplication result and add to ymm1 and put result in ymm1. + + + VFNMADD132PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 9C /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, negate the multiplication result and add to zmm2 and put result in zmm1. + + + VFNMADD213PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 AC /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm2, negate the multiplication result and add to zmm3/m512/m32bcst and put result in zmm1. + + + VFNMADD231PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 BC /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, negate the multiplication result and add to zmm1 and put result in zmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFNMADD132SD/VFNMADD213SD/VFNMADD231SD--Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values. + + VFNMADD132SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 9D /r + + FMA + + Multiply scalar double-precision floating-point value from xmm1 and xmm3/mem, negate the multiplication result and add to xmm2 and put result in xmm1. + + + VFNMADD213SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 AD /r + + FMA + + Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/mem and put result in xmm1. + + + VFNMADD231SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 BD /r + + FMA + + Multiply scalar double-precision floating-point value from xmm2 and xmm3/mem, negate the multiplication result and add to xmm1 and put result in xmm1. + + + VFNMADD132SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 9D /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, negate the multiplication result and add to xmm2 and put result in xmm1. + + + VFNMADD213SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 AD /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/m64 and put result in xmm1. + + + VFNMADD231SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 BD /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, negate the multiplication result and add to xmm1 and put result in xmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFNMADD132SS/VFNMADD213SS/VFNMADD231SS--Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values. + + VFNMADD132SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 9D /r + + FMA + + Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and add to xmm2 and put result in xmm1. + + + VFNMADD213SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 AD /r + + FMA + + Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/m32 and put result in xmm1. + + + VFNMADD231SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 BD /r + + FMA + + Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and add to xmm1 and put result in xmm1. + + + VFNMADD132SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 9D /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and add to xmm2 and put result in xmm1. + + + VFNMADD213SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 AD /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and add to xmm3/m32 and put result in xmm1. + + + VFNMADD231SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 BD /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and add to xmm1 and put result in xmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD--Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values. + + VFNMSUB132PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 9E /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and subtract xmm2 and put result in xmm1. + + + VFNMSUB213PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 AE /r + + FMA + + Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/mem and put result in xmm1. + + + VFNMSUB231PD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 BE /r + + FMA + + Multiply packed double-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and subtract xmm1 and put result in xmm1. + + + VFNMSUB132PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 9E /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and subtract ymm2 and put result in ymm1. + + + VFNMSUB213PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 AE /r + + FMA + + Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/mem and put result in ymm1. + + + VFNMSUB231PD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 BE /r + + FMA + + Multiply packed double-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and subtract ymm1 and put result in ymm1. + + + VFNMSUB132PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 9E /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm3/m128/m64bcst, negate the multiplication result and subtract xmm2 and put result in xmm1. + + + VFNMSUB213PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 AE /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m128/m64bcst and put result in xmm1. + + + VFNMSUB231PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 BE /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm2 and xmm3/m128/m64bcst, negate the multiplication result and subtract xmm1 and put result in xmm1. + + + VFNMSUB132PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 9E /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm3/m256/m64bcst, negate the multiplication result and subtract ymm2 and put result in ymm1. + + + VFNMSUB213PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 AE /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/m256/m64bcst and put result in ymm1. + + + VFNMSUB231PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 BE /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm2 and ymm3/m256/m64bcst, negate the multiplication result and subtract ymm1 and put result in ymm1. + + + VFNMSUB132PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 9E /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm3/m512/m64bcst, negate the multiplication result and subtract zmm2 and put result in zmm1. + + + VFNMSUB213PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 AE /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm1 and zmm2, negate the multiplication result and subtract zmm3/m512/m64bcst and put result in zmm1. + + + VFNMSUB231PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 BE /r + + AVX512F + + Multiply packed double-precision floating-point values from zmm2 and zmm3/m512/m64bcst, negate the multiplication result and subtract zmm1 and put result in zmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS--Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values. + + VFNMSUB132PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 9E /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm3/mem, negate the multiplication result and subtract xmm2 and put result in xmm1. + + + VFNMSUB213PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 AE /r + + FMA + + Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/mem and put result in xmm1. + + + VFNMSUB231PS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 BE /r + + FMA + + Multiply packed single-precision floating-point values from xmm2 and xmm3/mem, negate the multiplication result and subtract xmm1 and put result in xmm1. + + + VFNMSUB132PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 9E /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm3/mem, negate the multiplication result and subtract ymm2 and put result in ymm1. + + + VFNMSUB213PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 AE /r + + FMA + + Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/mem and put result in ymm1. + + + VFNMSUB231PS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 BE /r + + FMA + + Multiply packed single-precision floating-point values from ymm2 and ymm3/mem, negate the multiplication result and subtract ymm1 and put result in ymm1. + + + VFNMSUB132PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 9E /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm3/m128/m32bcst, negate the multiplication result and subtract xmm2 and put result in xmm1. + + + VFNMSUB213PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 AE /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m128/m32bcst and put result in xmm1. + + + VFNMSUB231PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 BE /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm2 and xmm3/m128/m32bcst, negate the multiplication result subtract add to xmm1 and put result in xmm1. + + + VFNMSUB132PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 9E /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm3/m256/m32bcst, negate the multiplication result and subtract ymm2 and put result in ymm1. + + + VFNMSUB213PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 AE /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm1 and ymm2, negate the multiplication result and subtract ymm3/m256/m32bcst and put result in ymm1. + + + VFNMSUB231PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 BE /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm2 and ymm3/m256/m32bcst, negate the multiplication result subtract add to ymm1 and put result in ymm1. + + + VFNMSUB132PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 9E /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm3/m512/m32bcst, negate the multiplication result and subtract zmm2 and put result in zmm1. + + + VFNMSUB213PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 AE /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm1 and zmm2, negate the multiplication result and subtract zmm3/m512/m32bcst and put result in zmm1. + + + VFNMSUB231PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 BE /r + + AVX512F + + Multiply packed single-precision floating-point values from zmm2 and zmm3/m512/m32bcst, negate the multiplication result subtract add to zmm1 and put result in zmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD--Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values. + + VFNMSUB132SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 9F /r + + FMA + + Multiply scalar double-precision floating-point value from xmm1 and xmm3/mem, negate the multiplication result and subtract xmm2 and put result in xmm1. + + + VFNMSUB213SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 AF /r + + FMA + + Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/mem and put result in xmm1. + + + VFNMSUB231SD + xmm1,xmm2,xmm3/m64 + VEX.DDS.LIG.66.0F38.W1 BF /r + + FMA + + Multiply scalar double-precision floating-point value from xmm2 and xmm3/mem, negate the multiplication result and subtract xmm1 and put result in xmm1. + + + VFNMSUB132SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 9F /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm1 and xmm3/m64, negate the multiplication result and subtract xmm2 and put result in xmm1. + + + VFNMSUB213SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 AF /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m64 and put result in xmm1. + + + VFNMSUB231SD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.DDS.LIG.66.0F38.W1 BF /r + + AVX512F + + Multiply scalar double-precision floating-point value from xmm2 and xmm3/m64, negate the multiplication result and subtract xmm1 and put result in xmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS--Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values. + + VFNMSUB132SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 9F /r + + FMA + + Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and subtract xmm2 and put result in xmm1. + + + VFNMSUB213SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 AF /r + + FMA + + Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m32 and put result in xmm1. + + + VFNMSUB231SS + xmm1,xmm2,xmm3/m32 + VEX.DDS.LIG.66.0F38.W0 BF /r + + FMA + + Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and subtract xmm1 and put result in xmm1. + + + VFNMSUB132SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 9F /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm1 and xmm3/m32, negate the multiplication result and subtract xmm2 and put result in xmm1. + + + VFNMSUB213SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 AF /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm1 and xmm2, negate the multiplication result and subtract xmm3/m32 and put result in xmm1. + + + VFNMSUB231SS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.DDS.LIG.66.0F38.W0 BF /r + + AVX512F + + Multiply scalar single-precision floating-point value from xmm2 and xmm3/m32, negate the multiplication result and subtract xmm1 and put result in xmm1. + + + ModRM:reg(r,w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VFPCLASSPD--Tests Types Of a Packed Float64 Values. + + VFPCLASSPD + k2 {k1},xmm2/m128/m64bcst,imm8 + EVEX.128.66.0F3A.W1 66 /r ib + + AVX512VL + AVX512DQ + + Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. + + + VFPCLASSPD + k2 {k1},ymm2/m256/m64bcst,imm8 + EVEX.256.66.0F3A.W1 66 /r ib + + AVX512VL + AVX512DQ + + Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. + + + VFPCLASSPD + k2 {k1},zmm2/m512/m64bcst,imm8 + EVEX.512.66.0F3A.W1 66 /r ib + + AVX512DQ + + Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VFPCLASSPS--Tests Types Of a Packed Float32 Values. + + VFPCLASSPS + k2 {k1},xmm2/m128/m32bcst,imm8 + EVEX.128.66.0F3A.W0 66 /r ib + + AVX512VL + AVX512DQ + + Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. + + + VFPCLASSPS + k2 {k1},ymm2/m256/m32bcst,imm8 + EVEX.256.66.0F3A.W0 66 /r ib + + AVX512VL + AVX512DQ + + Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. + + + VFPCLASSPS + k2 {k1},zmm2/m512/m32bcst,imm8 + EVEX.512.66.0F3A.W0 66 /r ib + + AVX512DQ + + Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VFPCLASSSD--Tests Types Of a Scalar Float64 Values. + + VFPCLASSSD + k2 {k1},xmm2/m64,imm8 + EVEX.LIG.66.0F3A.W1 67 /r ib + + AVX512DQ + + Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VFPCLASSSS--Tests Types Of a Scalar Float32 Values. + + VFPCLASSSS + k2 {k1},xmm2/m32,imm8 + EVEX.LIG.66.0F3A.W0 67 /r + + AVX512DQ + + Tests the input for the following categories: NaN, +0, -0, +Infinity, -Infinity, denormal, finite negative. The immediate field provides a mask bit for each of these category tests. The masked test results are OR-ed together to form a mask result. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VPGATHERDD/VPGATHERDQ--Gather Packed Dword, Packed Qword with Signed Dword Indices. + + VPGATHERDD + xmm1 {k1},vm32x + EVEX.128.66.0F38.W0 90 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, gather dword values from memory using writemask k1 for merging-masking. + + + VPGATHERDD + ymm1 {k1},vm32y + EVEX.256.66.0F38.W0 90 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, gather dword values from memory using writemask k1 for merging-masking. + + + VPGATHERDD + zmm1 {k1},vm32z + EVEX.512.66.0F38.W0 90 /vsib + + AVX512F + + Using signed dword indices, gather dword values from memory using writemask k1 for merging-masking. + + + VPGATHERDQ + xmm1 {k1},vm32x + EVEX.128.66.0F38.W1 90 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, gather quadword values from memory using writemask k1 for merging-masking. + + + VPGATHERDQ + ymm1 {k1},vm32x + EVEX.256.66.0F38.W1 90 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, gather quadword values from memory using writemask k1 for merging-masking. + + + VPGATHERDQ + zmm1 {k1},vm32y + EVEX.512.66.0F38.W1 90 /vsib + + AVX512F + + Using signed dword indices, gather quadword values from memory using writemask k1 for merging-masking. + + + ModRM:reg(w) + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + NA + NA + + + + VPGATHERQD/VPGATHERQQ--Gather Packed Dword, Packed Qword with Signed Qword Indices. + + VPGATHERQD + xmm1 {k1},vm64x + EVEX.128.66.0F38.W0 91 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, gather dword values from memory using writemask k1 for merging-masking. + + + VPGATHERQD + xmm1 {k1},vm64y + EVEX.256.66.0F38.W0 91 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, gather dword values from memory using writemask k1 for merging-masking. + + + VPGATHERQD + ymm1 {k1},vm64z + EVEX.512.66.0F38.W0 91 /vsib + + AVX512F + + Using signed qword indices, gather dword values from memory using writemask k1 for merging-masking. + + + VPGATHERQQ + xmm1 {k1},vm64x + EVEX.128.66.0F38.W1 91 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, gather quadword values from memory using writemask k1 for merging-masking. + + + VPGATHERQQ + ymm1 {k1},vm64y + EVEX.256.66.0F38.W1 91 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, gather quadword values from memory using writemask k1 for merging-masking. + + + VPGATHERQQ + zmm1 {k1},vm64z + EVEX.512.66.0F38.W1 91 /vsib + + AVX512F + + Using signed qword indices, gather quadword values from memory using writemask k1 for merging-masking. + + + ModRM:reg(w) + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + NA + NA + + + + VGATHERDPS/VGATHERDPD--Gather Packed Single, Packed Double with Signed Dword. + + VGATHERDPS + xmm1 {k1},vm32x + EVEX.128.66.0F38.W0 92 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, gather single-precision floatingpoint values from memory using k1 as completion mask. + + + VGATHERDPS + ymm1 {k1},vm32y + EVEX.256.66.0F38.W0 92 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, gather single-precision floatingpoint values from memory using k1 as completion mask. + + + VGATHERDPS + zmm1 {k1},vm32z + EVEX.512.66.0F38.W0 92 /vsib + + AVX512F + + Using signed dword indices, gather single-precision floatingpoint values from memory using k1 as completion mask. + + + VGATHERDPD + xmm1 {k1},vm32x + EVEX.128.66.0F38.W1 92 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, gather float64 vector into float64 vector xmm1 using k1 as completion mask. + + + VGATHERDPD + ymm1 {k1},vm32x + EVEX.256.66.0F38.W1 92 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, gather float64 vector into float64 vector ymm1 using k1 as completion mask. + + + VGATHERDPD + zmm1 {k1},vm32y + EVEX.512.66.0F38.W1 92 /vsib + + AVX512F + + Using signed dword indices, gather float64 vector into float64 vector zmm1 using k1 as completion mask. + + + ModRM:reg(w) + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + NA + NA + + + + VGATHERQPS/VGATHERQPD--Gather Packed Single, Packed Double with Signed Qword Indices. + + VGATHERQPS + xmm1 {k1},vm64x + EVEX.128.66.0F38.W0 93 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, gather single-precision floating-point values from memory using k1 as completion mask. + + + VGATHERQPS + xmm1 {k1},vm64y + EVEX.256.66.0F38.W0 93 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, gather single-precision floating-point values from memory using k1 as completion mask. + + + VGATHERQPS + ymm1 {k1},vm64z + EVEX.512.66.0F38.W0 93 /vsib + + AVX512F + + Using signed qword indices, gather single-precision floating-point values from memory using k1 as completion mask. + + + VGATHERQPD + xmm1 {k1},vm64x + EVEX.128.66.0F38.W1 93 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, gather float64 vector into float64 vector xmm1 using k1 as completion mask. + + + VGATHERQPD + ymm1 {k1},vm64y + EVEX.256.66.0F38.W1 93 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, gather float64 vector into float64 vector ymm1 using k1 as completion mask. + + + VGATHERQPD + zmm1 {k1},vm64z + EVEX.512.66.0F38.W1 93 /vsib + + AVX512F + + Using signed qword indices, gather float64 vector into float64 vector zmm1 using k1 as completion mask. + + + ModRM:reg(w) + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + NA + NA + + + + VGETEXPPD--Convert Exponents of Packed DP FP Values to DP FP Values. + + VGETEXPPD + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F38.W1 42 /r + + AVX512VL + AVX512F + + Convert the exponent of packed double-precision floating-point values in the source operand to DP FP results representing unbiased integer exponents and stores the results in the destination register. + + + VGETEXPPD + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F38.W1 42 /r + + AVX512VL + AVX512F + + Convert the exponent of packed double-precision floating-point values in the source operand to DP FP results representing unbiased integer exponents and stores the results in the destination register. + + + VGETEXPPD + zmm1 {k1}{z},zmm2/m512/m64bcst{sae} + EVEX.512.66.0F38.W1 42 /r + + AVX512F + + Convert the exponent of packed double-precision floating-point values in the source operand to DP FP results representing unbiased integer exponents and stores the results in the destination under writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VGETEXPPS--Convert Exponents of Packed SP FP Values to SP FP Values. + + VGETEXPPS + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.66.0F38.W0 42 /r + + AVX512VL + AVX512F + + Convert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register. + + + VGETEXPPS + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.66.0F38.W0 42 /r + + AVX512VL + AVX512F + + Convert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register. + + + VGETEXPPS + zmm1 {k1}{z},zmm2/m512/m32bcst{sae} + EVEX.512.66.0F38.W0 42 /r + + AVX512F + + Convert the exponent of packed single-precision floating-point values in the source operand to SP FP results representing unbiased integer exponents and stores the results in the destination register. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VGETEXPSD--Convert Exponents of Scalar DP FP Values to DP FP Value. + + VGETEXPSD + xmm1 {k1}{z},xmm2,xmm3/m64{sae} + EVEX.NDS.LIG.66.0F38.W1 43 /r + + AVX512F + + Convert the biased exponent (bits 62:52) of the low doubleprecision floating-point value in xmm3/m64 to a DP FP value representing unbiased integer exponent. Stores the result to the low 64-bit of xmm1 under the writemask k1 and merge with the other elements of xmm2. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VGETEXPSS--Convert Exponents of Scalar SP FP Values to SP FP Value. + + VGETEXPSS + xmm1 {k1}{z},xmm2,xmm3/m32{sae} + EVEX.NDS.LIG.66.0F38.W0 43 /r + + AVX512F + + Convert the biased exponent (bits 30:23) of the low singleprecision floating-point value in xmm3/m32 to a SP FP value representing unbiased integer exponent. Stores the result to xmm1 under the writemask k1 and merge with the other elements of xmm2. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VGETMANTPD--Extract Float64 Vector of Normalized Mantissas from Float64 Vector. + + VGETMANTPD + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.128.66.0F3A.W1 26 /r ib + + AVX512VL + AVX512F + + Get Normalized Mantissa from float64 vector xmm2/m128/m64bcst and store the result in xmm1, using imm8 for sign control and mantissa interval normalization, under writemask. + + + VGETMANTPD + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.256.66.0F3A.W1 26 /r ib + + AVX512VL + AVX512F + + Get Normalized Mantissa from float64 vector ymm2/m256/m64bcst and store the result in ymm1, using imm8 for sign control and mantissa interval normalization, under writemask. + + + VGETMANTPD + zmm1 {k1}{z},zmm2/m512/m64bcst{sae},imm8 + EVEX.512.66.0F3A.W1 26 /r ib + + AVX512F + + Get Normalized Mantissa from float64 vector zmm2/m512/m64bcst and store the result in zmm1, using imm8 for sign control and mantissa interval normalization, under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + VGETMANTPS--Extract Float32 Vector of Normalized Mantissas from Float32 Vector. + + VGETMANTPS + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.128.66.0F3A.W0 26 /r ib + + AVX512VL + AVX512F + + Get normalized mantissa from float32 vector xmm2/m128/m32bcst and store the result in xmm1, using imm8 for sign control and mantissa interval normalization, under writemask. + + + VGETMANTPS + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.256.66.0F3A.W0 26 /r ib + + AVX512VL + AVX512F + + Get normalized mantissa from float32 vector ymm2/m256/m32bcst and store the result in ymm1, using imm8 for sign control and mantissa interval normalization, under writemask. + + + VGETMANTPS + zmm1 {k1}{z},zmm2/m512/m32bcst{sae},imm8 + EVEX.512.66.0F3A.W0 26 /r ib + + AVX512F + + Get normalized mantissa from float32 vector zmm2/m512/m32bcst and store the result in zmm1, using imm8 for sign control and mantissa interval normalization, under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + VGETMANTSD--Extract Float64 of Normalized Mantissas from Float64 Scalar. + + VGETMANTSD + xmm1 {k1}{z},xmm2,xmm3/m64{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W1 27 /r ib + + AVX512F + + Extract the normalized mantissa of the low float64 element in xmm3/m64 using imm8 for sign control and mantissa interval normalization. Store the mantissa to xmm1 under the writemask k1 and merge with the other elements of xmm2. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VGETMANTSS--Extract Float32 Vector of Normalized Mantissa from Float32 Vector. + + VGETMANTSS + xmm1 {k1}{z},xmm2,xmm3/m32{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W0 27 /r ib + + AVX512F + + Extract the normalized mantissa from the low float32 element of xmm3/m32 using imm8 for sign control and mantissa interval normalization, store the mantissa to xmm1 under the writemask k1 and merge with the other elements of xmm2. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4--Insert Packed Floating-Point Values. + + VINSERTF128 + ymm1,ymm2,xmm3/m128,imm8 + VEX.NDS.256.66.0F3A.W0 18 /r ib + + AVX + + Insert 128 bits of packed floating-point values from xmm3/m128 and the remaining values from ymm2 into ymm1. + + + VINSERTF32X4 + ymm1 {k1}{z},ymm2,xmm3/m128,imm8 + EVEX.NDS.256.66.0F3A.W0 18 /r ib + + AVX512VL + AVX512F + + Insert 128 bits of packed single-precision floatingpoint values from xmm3/m128 and the remaining values from ymm2 into ymm1 under writemask k1. + + + VINSERTF32X4 + zmm1 {k1}{z},zmm2,xmm3/m128,imm8 + EVEX.NDS.512.66.0F3A.W0 18 /r ib + + AVX512F + + Insert 128 bits of packed single-precision floatingpoint values from xmm3/m128 and the remaining values from zmm2 into zmm1 under writemask k1. + + + VINSERTF64X2 + ymm1 {k1}{z},ymm2,xmm3/m128,imm8 + EVEX.NDS.256.66.0F3A.W1 18 /r ib + + AVX512VL + AVX512DQ + + Insert 128 bits of packed double-precision floatingpoint values from xmm3/m128 and the remaining values from ymm2 into ymm1 under writemask k1. + + + VINSERTF64X2 + zmm1 {k1}{z},zmm2,xmm3/m128,imm8 + EVEX.NDS.512.66.0F3A.W1 18 /r ib + + AVX512DQ + + Insert 128 bits of packed double-precision floatingpoint values from xmm3/m128 and the remaining values from zmm2 into zmm1 under writemask k1. + + + VINSERTF32X8 + zmm1 {k1}{z},zmm2,ymm3/m256,imm8 + EVEX.NDS.512.66.0F3A.W0 1A /r ib + + AVX512DQ + + Insert 256 bits of packed single-precision floatingpoint values from ymm3/m256 and the remaining values from zmm2 into zmm1 under writemask k1. + + + VINSERTF64X4 + zmm1 {k1}{z},zmm2,ymm3/m256,imm8 + EVEX.NDS.512.66.0F3A.W1 1A /r ib + + AVX512F + + Insert 256 bits of packed double-precision floatingpoint values from ymm3/m256 and the remaining values from zmm2 into zmm1 under writemask k1. + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4--Insert Packed Integer Values. + + VINSERTI128 + ymm1,ymm2,xmm3/m128,imm8 + VEX.NDS.256.66.0F3A.W0 38 /r ib + + AVX2 + + Insert 128 bits of integer data from xmm3/m128 and the remaining values from ymm2 into ymm1. + + + VINSERTI32X4 + ymm1 {k1}{z},ymm2,xmm3/m128,imm8 + EVEX.NDS.256.66.0F3A.W0 38 /r ib + + AVX512VL + AVX512F + + Insert 128 bits of packed doubleword integer values from xmm3/m128 and the remaining values from ymm2 into ymm1 under writemask k1. + + + VINSERTI32X4 + zmm1 {k1}{z},zmm2,xmm3/m128,imm8 + EVEX.NDS.512.66.0F3A.W0 38 /r ib + + AVX512F + + Insert 128 bits of packed doubleword integer values from xmm3/m128 and the remaining values from zmm2 into zmm1 under writemask k1. + + + VINSERTI64X2 + ymm1 {k1}{z},ymm2,xmm3/m128,imm8 + EVEX.NDS.256.66.0F3A.W1 38 /r ib + + AVX512VL + AVX512DQ + + Insert 128 bits of packed quadword integer values from xmm3/m128 and the remaining values from ymm2 into ymm1 under writemask k1. + + + VINSERTI64X2 + zmm1 {k1}{z},zmm2,xmm3/m128,imm8 + EVEX.NDS.512.66.0F3A.W1 38 /r ib + + AVX512DQ + + Insert 128 bits of packed quadword integer values from xmm3/m128 and the remaining values from zmm2 into zmm1 under writemask k1. + + + VINSERTI32X8 + zmm1 {k1}{z},zmm2,ymm3/m256,imm8 + EVEX.NDS.512.66.0F3A.W0 3A /r ib + + AVX512DQ + + Insert 256 bits of packed doubleword integer values from ymm3/m256 and the remaining values from zmm2 into zmm1 under writemask k1. + + + VINSERTI64X4 + zmm1 {k1}{z},zmm2,ymm3/m256,imm8 + EVEX.NDS.512.66.0F3A.W1 3A /r ib + + AVX512F + + Insert 256 bits of packed quadword integer values from ymm3/m256 and the remaining values from zmm2 into zmm1 under writemask k1. + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + INSERTPS--Insert Scalar Single-Precision Floating-Point Value. + + INSERTPS + xmm1,xmm2/m32,imm8 + 66 0F 3A 21 /r ib + + SSE4_1 + + Insert a single-precision floating-point value selected by imm8 from xmm2/m32 into xmm1 at the specified destination element specified by imm8 and zero out destination elements in xmm1 as indicated in imm8. + + + VINSERTPS + xmm1,xmm2,xmm3/m32,imm8 + VEX.NDS.128.66.0F3A.WIG 21 /r ib + + AVX + + Insert a single-precision floating-point value selected by imm8 from xmm3/m32 and merge with values in xmm2 at the specified destination element specified by imm8 and write out the result and zero out destination elements in xmm1 as indicated in imm8. + + + VINSERTPS + xmm1,xmm2,xmm3/m32,imm8 + EVEX.NDS.128.66.0F3A.W0 21 /r ib + + AVX512F + + Insert a single-precision floating-point value selected by imm8 from xmm3/m32 and merge with values in xmm2 at the specified destination element specified by imm8 and write out the result and zero out destination elements in xmm1 as indicated in imm8. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + Imm8 + + + + MAXPD--Maximum of Packed Double-Precision Floating-Point Values. + + MAXPD + xmm1,xmm2/m128 + 66 0F 5F /r + + SSE2 + + Return the maximum double-precision floating-point values between xmm1 and xmm2/m128. + + + VMAXPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 5F /r + + AVX + + Return the maximum double-precision floating-point values between xmm2 and xmm3/m128. + + + VMAXPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 5F /r + + AVX + + Return the maximum packed double-precision floating-point values between ymm2 and ymm3/m256. + + + VMAXPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 5F /r + + AVX512VL + AVX512F + + Return the maximum packed double-precision floating-point values between xmm2 and xmm3/m128/m64bcst and store result in xmm1 subject to writemask k1. + + + VMAXPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 5F /r + + AVX512VL + AVX512F + + Return the maximum packed double-precision floating-point values between ymm2 and ymm3/m256/m64bcst and store result in ymm1 subject to writemask k1. + + + VMAXPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{sae} + EVEX.NDS.512.66.0F.W1 5F /r + + AVX512F + + Return the maximum packed double-precision floating-point values between zmm2 and zmm3/m512/m64bcst and store result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MAXPS--Maximum of Packed Single-Precision Floating-Point Values. + + MAXPS + xmm1,xmm2/m128 + 0F 5F /r + + SSE + + Return the maximum single-precision floating-point values between xmm1 and xmm2/mem. + + + VMAXPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 5F /r + + AVX + + Return the maximum single-precision floating-point values between xmm2 and xmm3/mem. + + + VMAXPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F.WIG 5F /r + + AVX + + Return the maximum single-precision floating-point values between ymm2 and ymm3/mem. + + + VMAXPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 5F /r + + AVX512VL + AVX512F + + Return the maximum packed single-precision floating-point values between xmm2 and xmm3/m128/m32bcst and store result in xmm1 subject to writemask k1. + + + VMAXPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 5F /r + + AVX512VL + AVX512F + + Return the maximum packed single-precision floating-point values between ymm2 and ymm3/m256/m32bcst and store result in ymm1 subject to writemask k1. + + + VMAXPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{sae} + EVEX.NDS.512.0F.W0 5F /r + + AVX512F + + Return the maximum packed single-precision floating-point values between zmm2 and zmm3/m512/m32bcst and store result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MAXSD--Return Maximum Scalar Double-Precision Floating-Point Value. + + MAXSD + xmm1,xmm2/m64 + F2 0F 5F /r + + SSE2 + + Return the maximum scalar double-precision floating-point value between xmm2/m64 and xmm1. + + + VMAXSD + xmm1,xmm2,xmm3/m64 + VEX.NDS.128.F2.0F.WIG 5F /r + + AVX + + Return the maximum scalar double-precision floating-point value between xmm3/m64 and xmm2. + + + VMAXSD + xmm1 {k1}{z},xmm2,xmm3/m64{sae} + EVEX.NDS.LIG.F2.0F.W1 5F /r + + AVX512F + + Return the maximum scalar double-precision floating-point value between xmm3/m64 and xmm2. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MAXSS--Return Maximum Scalar Single-Precision Floating-Point Value. + + MAXSS + xmm1,xmm2/m32 + F3 0F 5F /r + + SSE + + Return the maximum scalar single-precision floating-point value between xmm2/m32 and xmm1. + + + VMAXSS + xmm1,xmm2,xmm3/m32 + VEX.NDS.128.F3.0F.WIG 5F /r + + AVX + + Return the maximum scalar single-precision floating-point value between xmm3/m32 and xmm2. + + + VMAXSS + xmm1 {k1}{z},xmm2,xmm3/m32{sae} + EVEX.NDS.LIG.F3.0F.W0 5F /r + + AVX512F + + Return the maximum scalar single-precision floating-point value between xmm3/m32 and xmm2. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MINPD--Minimum of Packed Double-Precision Floating-Point Values. + + MINPD + xmm1,xmm2/m128 + 66 0F 5D /r + + SSE2 + + Return the minimum double-precision floating-point values between xmm1 and xmm2/mem. + + + VMINPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 5D /r + + AVX + + Return the minimum double-precision floating-point values between xmm2 and xmm3/mem. + + + VMINPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 5D /r + + AVX + + Return the minimum packed double-precision floating-point values between ymm2 and ymm3/mem. + + + VMINPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 5D /r + + AVX512VL + AVX512F + + Return the minimum packed double-precision floating-point values between xmm2 and xmm3/m128/m64bcst and store result in xmm1 subject to writemask k1. + + + VMINPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 5D /r + + AVX512VL + AVX512F + + Return the minimum packed double-precision floating-point values between ymm2 and ymm3/m256/m64bcst and store result in ymm1 subject to writemask k1. + + + VMINPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{sae} + EVEX.NDS.512.66.0F.W1 5D /r + + AVX512F + + Return the minimum packed double-precision floating-point values between zmm2 and zmm3/m512/m64bcst and store result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MINPS--Minimum of Packed Single-Precision Floating-Point Values. + + MINPS + xmm1,xmm2/m128 + 0F 5D /r + + SSE + + Return the minimum single-precision floating-point values between xmm1 and xmm2/mem. + + + VMINPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 5D /r + + AVX + + Return the minimum single-precision floating-point values between xmm2 and xmm3/mem. + + + VMINPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F.WIG 5D /r + + AVX + + Return the minimum single double-precision floating-point values between ymm2 and ymm3/mem. + + + VMINPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 5D /r + + AVX512VL + AVX512F + + Return the minimum packed single-precision floating-point values between xmm2 and xmm3/m128/m32bcst and store result in xmm1 subject to writemask k1. + + + VMINPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 5D /r + + AVX512VL + AVX512F + + Return the minimum packed single-precision floating-point values between ymm2 and ymm3/m256/m32bcst and store result in ymm1 subject to writemask k1. + + + VMINPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{sae} + EVEX.NDS.512.0F.W0 5D /r + + AVX512F + + Return the minimum packed single-precision floating-point values between zmm2 and zmm3/m512/m32bcst and store result in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MINSD--Return Minimum Scalar Double-Precision Floating-Point Value. + + MINSD + xmm1,xmm2/m64 + F2 0F 5D /r + + SSE2 + + Return the minimum scalar double-precision floatingpoint value between xmm2/m64 and xmm1. + + + VMINSD + xmm1,xmm2,xmm3/m64 + VEX.NDS.128.F2.0F.WIG 5D /r + + AVX + + Return the minimum scalar double-precision floatingpoint value between xmm3/m64 and xmm2. + + + VMINSD + xmm1 {k1}{z},xmm2,xmm3/m64{sae} + EVEX.NDS.LIG.F2.0F.W1 5D /r + + AVX512F + + Return the minimum scalar double-precision floatingpoint value between xmm3/m64 and xmm2. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MINSS--Return Minimum Scalar Single-Precision Floating-Point Value. + + MINSS + xmm1,xmm2/m32 + F3 0F 5D /r + + SSE + + Return the minimum scalar single-precision floatingpoint value between xmm2/m32 and xmm1. + + + VMINSS + xmm1,xmm2,xmm3/m32 + VEX.NDS.128.F3.0F.WIG 5D /r + + AVX + + Return the minimum scalar single-precision floatingpoint value between xmm3/m32 and xmm2. + + + VMINSS + xmm1 {k1}{z},xmm2,xmm3/m32{sae} + EVEX.NDS.LIG.F3.0F.W0 5D /r + + AVX512F + + Return the minimum scalar single-precision floatingpoint value between xmm3/m32 and xmm2. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MOVAPD--Move Aligned Packed Double-Precision Floating-Point Values. + + MOVAPD + xmm1,xmm2/m128 + 66 0F 28 /r + + SSE2 + + Move aligned packed double-precision floatingpoint values from xmm2/mem to xmm1. + + + MOVAPD + xmm2/m128,xmm1 + 66 0F 29 /r + + SSE2 + + Move aligned packed double-precision floatingpoint values from xmm1 to xmm2/mem. + + + VMOVAPD + xmm1,xmm2/m128 + VEX.128.66.0F.WIG 28 /r + + AVX + + Move aligned packed double-precision floatingpoint values from xmm2/mem to xmm1. + + + VMOVAPD + xmm2/m128,xmm1 + VEX.128.66.0F.WIG 29 /r + + AVX + + Move aligned packed double-precision floatingpoint values from xmm1 to xmm2/mem. + + + VMOVAPD + ymm1,ymm2/m256 + VEX.256.66.0F.WIG 28 /r + + AVX + + Move aligned packed double-precision floatingpoint values from ymm2/mem to ymm1. + + + VMOVAPD + ymm2/m256,ymm1 + VEX.256.66.0F.WIG 29 /r + + AVX + + Move aligned packed double-precision floatingpoint values from ymm1 to ymm2/mem. + + + VMOVAPD + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F.W1 28 /r + + AVX512VL + AVX512F + + Move aligned packed double-precision floatingpoint values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVAPD + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F.W1 28 /r + + AVX512VL + AVX512F + + Move aligned packed double-precision floatingpoint values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVAPD + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F.W1 28 /r + + AVX512F + + Move aligned packed double-precision floatingpoint values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVAPD + xmm2/m128 {k1}{z},xmm1 + EVEX.128.66.0F.W1 29 /r + + AVX512VL + AVX512F + + Move aligned packed double-precision floatingpoint values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVAPD + ymm2/m256 {k1}{z},ymm1 + EVEX.256.66.0F.W1 29 /r + + AVX512VL + AVX512F + + Move aligned packed double-precision floatingpoint values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVAPD + zmm2/m512 {k1}{z},zmm1 + EVEX.512.66.0F.W1 29 /r + + AVX512F + + Move aligned packed double-precision floatingpoint values from zmm1 to zmm2/m512 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVAPS--Move Aligned Packed Single-Precision Floating-Point Values. + + MOVAPS + xmm1,xmm2/m128 + 0F 28 /r + + SSE + + Move aligned packed single-precision floating-point values from xmm2/mem to xmm1. + + + MOVAPS + xmm2/m128,xmm1 + 0F 29 /r + + SSE + + Move aligned packed single-precision floating-point values from xmm1 to xmm2/mem. + + + VMOVAPS + xmm1,xmm2/m128 + VEX.128.0F.WIG 28 /r + + AVX + + Move aligned packed single-precision floating-point values from xmm2/mem to xmm1. + + + VMOVAPS + xmm2/m128,xmm1 + VEX.128.0F.WIG 29 /r + + AVX + + Move aligned packed single-precision floating-point values from xmm1 to xmm2/mem. + + + VMOVAPS + ymm1,ymm2/m256 + VEX.256.0F.WIG 28 /r + + AVX + + Move aligned packed single-precision floating-point values from ymm2/mem to ymm1. + + + VMOVAPS + ymm2/m256,ymm1 + VEX.256.0F.WIG 29 /r + + AVX + + Move aligned packed single-precision floating-point values from ymm1 to ymm2/mem. + + + VMOVAPS + xmm1 {k1}{z},xmm2/m128 + EVEX.128.0F.W0 28 /r + + AVX512VL + AVX512F + + Move aligned packed single-precision floating-point values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVAPS + ymm1 {k1}{z},ymm2/m256 + EVEX.256.0F.W0 28 /r + + AVX512VL + AVX512F + + Move aligned packed single-precision floating-point values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVAPS + zmm1 {k1}{z},zmm2/m512 + EVEX.512.0F.W0 28 /r + + AVX512F + + Move aligned packed single-precision floating-point values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVAPS + xmm2/m128 {k1}{z},xmm1 + EVEX.128.0F.W0 29 /r + + AVX512VL + AVX512F + + Move aligned packed single-precision floating-point values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVAPS + ymm2/m256 {k 1}{z},ymm1 + EVEX.256.0F.W0 29 /r + + AVX512VL + AVX512F + + Move aligned packed single-precision floating-point values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVAPS + zmm2/m512 {k1}{z},zmm1 + EVEX.512.0F.W0 29 /r + + AVX512F + + Move aligned packed single-precision floating-point values from zmm1 to zmm2/m512 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVD/MOVQ--Move Doubleword and Quadword. + + MOVD + xmm1,r32/m32 + 66 0F 6E /r + + SSE2 + + Move doubleword from r/m32 to xmm1. + + + MOVQ + xmm1,r64/m64 + 66 REX.W 0F 6E /r + + SSE2 + + Move quadword from r/m64 to xmm1. + + + VMOVD + xmm1,r32/m32 + VEX.128.66.0F.W0 6E /r + + AVX + + Move doubleword from r/m32 to xmm1. + + + VMOVQ + xmm1,r64/m64 + VEX.128.66.0F.W1 6E /r + + AVX + + Move quadword from r/m64 to xmm1. + + + VMOVD + xmm1,r32/m32 + EVEX.128.66.0F.W0 6E /r + + AVX512F + + Move doubleword from r/m32 to xmm1. + + + VMOVQ + xmm1,r64/m64 + EVEX.128.66.0F.W1 6E /r + + AVX512F + + Move quadword from r/m64 to xmm1. + + + MOVD + r32/m32,xmm1 + 66 0F 7E /r + + SSE2 + + Move doubleword from xmm1 register to r/m32. + + + MOVQ + r64/m64,xmm1 + 66 REX.W 0F 7E /r + + SSE2 + + Move quadword from xmm1 register to r/m64. + + + VMOVD + r32/m32,xmm1 + VEX.128.66.0F.W0 7E /r + + AVX + + Move doubleword from xmm1 register to r/m32. + + + VMOVQ + r64/m64,xmm1 + VEX.128.66.0F.W1 7E /r + + AVX + + Move quadword from xmm1 register to r/m64. + + + VMOVD + r32/m32,xmm1 + EVEX.128.66.0F.W0 7E /r + + AVX512F + + Move doubleword from xmm1 register to r/m32. + + + VMOVQ + r64/m64,xmm1 + EVEX.128.66.0F.W1 7E /r + + AVX512F + + Move quadword from xmm1 register to r/m64. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVQ--Move Quadword. + + MOVQ + xmm1,xmm2/m64 + F3 0F 7E /r + + SSE2 + + Move quadword from xmm2/m64 to xmm1. + + + VMOVQ + xmm1,xmm2/m64 + VEX.128.F3.0F.WIG 7E /r + + AVX + + Move quadword from xmm2/m64 to xmm1. + + + VMOVQ + xmm1,xmm2/m64 + EVEX.128.F3.0F.W1 7E /r + + AVX512F + + Move quadword from xmm2/m64 to xmm1. + + + MOVQ + xmm1/m64,xmm2 + 66 0F D6 /r + + SSE2 + + Move quadword from xmm2 register to xmm1/m64. + + + VMOVQ + xmm1/m64,xmm2 + VEX.128.66.0F.WIG D6 /r + + AVX + + Move quadword from xmm2 register to xmm1/m64. + + + VMOVQ + xmm1/m64,xmm2 + EVEX.128.66.0F.W1 D6 /r + + AVX512F + + Move quadword from xmm2 register to xmm1/m64. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVDDUP--Replicate Double FP Values. + + MOVDDUP + xmm1,xmm2/m64 + F2 0F 12 /r + + SSE3 + + Move double-precision floating-point value from xmm2/m64 and duplicate into xmm1. + + + VMOVDDUP + xmm1,xmm2/m64 + VEX.128.F2.0F.WIG 12 /r + + AVX + + Move double-precision floating-point value from xmm2/m64 and duplicate into xmm1. + + + VMOVDDUP + ymm1,ymm2/m256 + VEX.256.F2.0F.WIG 12 /r + + AVX + + Move even index double-precision floating-point values from ymm2/mem and duplicate each element into ymm1. + + + VMOVDDUP + xmm1 {k1}{z},xmm2/m64 + EVEX.128.F2.0F.W1 12 /r + + AVX512VL + AVX512F + + Move double-precision floating-point value from xmm2/m64 and duplicate each element into xmm1 subject to writemask k1. + + + VMOVDDUP + ymm1 {k1}{z},ymm2/m256 + EVEX.256.F2.0F.W1 12 /r + + AVX512VL + AVX512F + + Move even index double-precision floating-point values from ymm2/m256 and duplicate each element into ymm1 subject to writemask k1. + + + VMOVDDUP + zmm1 {k1}{z},zmm2/m512 + EVEX.512.F2.0F.W1 12 /r + + AVX512F + + Move even index double-precision floating-point values from zmm2/m512 and duplicate each element into zmm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + MOVDQA,VMOVDQA32/64--Move Aligned Packed Integer Values. + + MOVDQA + xmm1,xmm2/m128 + 66 0F 6F /r + + SSE2 + + Move aligned packed integer values from xmm2/mem to xmm1. + + + MOVDQA + xmm2/m128,xmm1 + 66 0F 7F /r + + SSE2 + + Move aligned packed integer values from xmm1 to xmm2/mem. + + + VMOVDQA + xmm1,xmm2/m128 + VEX.128.66.0F.WIG 6F /r + + AVX + + Move aligned packed integer values from xmm2/mem to xmm1. + + + VMOVDQA + xmm2/m128,xmm1 + VEX.128.66.0F.WIG 7F /r + + AVX + + Move aligned packed integer values from xmm1 to xmm2/mem. + + + VMOVDQA + ymm1,ymm2/m256 + VEX.256.66.0F.WIG 6F /r + + AVX + + Move aligned packed integer values from ymm2/mem to ymm1. + + + VMOVDQA + ymm2/m256,ymm1 + VEX.256.66.0F.WIG 7F /r + + AVX + + Move aligned packed integer values from ymm1 to ymm2/mem. + + + VMOVDQA32 + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F.W0 6F /r + + AVX512VL + AVX512F + + Move aligned packed doubleword integer values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVDQA32 + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F.W0 6F /r + + AVX512VL + AVX512F + + Move aligned packed doubleword integer values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVDQA32 + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F.W0 6F /r + + AVX512F + + Move aligned packed doubleword integer values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVDQA32 + xmm2/m128 {k1}{z},xmm1 + EVEX.128.66.0F.W0 7F /r + + AVX512VL + AVX512F + + Move aligned packed doubleword integer values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVDQA32 + ymm2/m256 {k1}{z},ymm1 + EVEX.256.66.0F.W0 7F /r + + AVX512VL + AVX512F + + Move aligned packed doubleword integer values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVDQA32 + zmm2/m512 {k1}{z},zmm1 + EVEX.512.66.0F.W0 7F /r + + AVX512F + + Move aligned packed doubleword integer values from zmm1 to zmm2/m512 using writemask k1. + + + VMOVDQA64 + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F.W1 6F /r + + AVX512VL + AVX512F + + Move aligned quadword integer values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVDQA64 + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F.W1 6F /r + + AVX512VL + AVX512F + + Move aligned quadword integer values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVDQA64 + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F.W1 6F /r + + AVX512F + + Move aligned packed quadword integer values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVDQA64 + xmm2/m128 {k1}{z},xmm1 + EVEX.128.66.0F.W1 7F /r + + AVX512VL + AVX512F + + Move aligned packed quadword integer values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVDQA64 + ymm2/m256 {k1}{z},ymm1 + EVEX.256.66.0F.W1 7F /r + + AVX512VL + AVX512F + + Move aligned packed quadword integer values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVDQA64 + zmm2/m512 {k1}{z},zmm1 + EVEX.512.66.0F.W1 7F /r + + AVX512F + + Move aligned packed quadword integer values from zmm1 to zmm2/m512 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVDQU,VMOVDQU8/16/32/64--Move Unaligned Packed Integer Values. + + MOVDQU + xmm1,xmm2/m128 + F3 0F 6F /r + + SSE2 + + Move unaligned packed integer values from xmm2/m128 to xmm1. + + + MOVDQU + xmm2/m128,xmm1 + F3 0F 7F /r + + SSE2 + + Move unaligned packed integer values from xmm1 to xmm2/m128. + + + VMOVDQU + xmm1,xmm2/m128 + VEX.128.F3.0F.WIG 6F /r + + AVX + + Move unaligned packed integer values from xmm2/m128 to xmm1. + + + VMOVDQU + xmm2/m128,xmm1 + VEX.128.F3.0F.WIG 7F /r + + AVX + + Move unaligned packed integer values from xmm1 to xmm2/m128. + + + VMOVDQU + ymm1,ymm2/m256 + VEX.256.F3.0F.WIG 6F /r + + AVX + + Move unaligned packed integer values from ymm2/m256 to ymm1. + + + VMOVDQU + ymm2/m256,ymm1 + VEX.256.F3.0F.WIG 7F /r + + AVX + + Move unaligned packed integer values from ymm1 to ymm2/m256. + + + VMOVDQU8 + xmm1 {k1}{z},xmm2/m128 + EVEX.128.F2.0F.W0 6F /r + + AVX512VL + AVX512BW + + Move unaligned packed byte integer values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVDQU8 + ymm1 {k1}{z},ymm2/m256 + EVEX.256.F2.0F.W0 6F /r + + AVX512VL + AVX512BW + + Move unaligned packed byte integer values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVDQU8 + zmm1 {k1}{z},zmm2/m512 + EVEX.512.F2.0F.W0 6F /r + + AVX512BW + + Move unaligned packed byte integer values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVDQU8 + xmm2/m128 {k1}{z},xmm1 + EVEX.128.F2.0F.W0 7F /r + + AVX512VL + AVX512BW + + Move unaligned packed byte integer values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVDQU8 + ymm2/m256 {k 1}{z},ymm1 + EVEX.256.F2.0F.W0 7F /r + + AVX512VL + AVX512BW + + Move unaligned packed byte integer values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVDQU8 + zmm2/m512 {k1}{z},zmm1 + EVEX.512.F2.0F.W0 7F /r + + AVX512BW + + Move unaligned packed byte integer values from zmm1 to zmm2/m512 using writemask k1. + + + VMOVDQU16 + xmm1 {k1}{z},xmm2/m128 + EVEX.128.F2.0F.W1 6F /r + + AVX512VL + AVX512BW + + Move unaligned packed word integer values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVDQU16 + ymm1 {k1}{z},ymm2/m256 + EVEX.256.F2.0F.W1 6F /r + + AVX512VL + AVX512BW + + Move unaligned packed word integer values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVDQU16 + zmm1 {k1}{z},zmm2/m512 + EVEX.512.F2.0F.W1 6F /r + + AVX512BW + + Move unaligned packed word integer values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVDQU16 + xmm2/m128 {k1}{z},xmm1 + EVEX.128.F2.0F.W1 7F /r + + AVX512VL + AVX512BW + + Move unaligned packed word integer values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVDQU16 + ymm2/m256 {k1}{z},ymm1 + EVEX.256.F2.0F.W1 7F /r + + AVX512VL + AVX512BW + + Move unaligned packed word integer values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVDQU16 + zmm2/m512 {k1}{z},zmm1 + EVEX.512.F2.0F.W1 7F /r + + AVX512BW + + Move unaligned packed word integer values from zmm1 to zmm2/m512 using writemask k1. + + + VMOVDQU32 + xmm1 {k1}{z},xmm2/mm128 + EVEX.128.F3.0F.W0 6F /r + + AVX512VL + AVX512F + + Move unaligned packed doubleword integer values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVDQU32 + ymm1 {k1}{z},ymm2/m256 + EVEX.256.F3.0F.W0 6F /r + + AVX512VL + AVX512F + + Move unaligned packed doubleword integer values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVDQU32 + zmm1 {k 1}{z},zmm2/m512 + EVEX.512.F3.0F.W0 6F /r + + AVX512F + + Move unaligned packed doubleword integer values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVDQU32 + xmm2/m128 {k1}{z},xmm1 + EVEX.128.F3.0F.W0 7F /r + + AVX512VL + AVX512F + + Move unaligned packed doubleword integer values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVDQU32 + ymm2/m256 {k1}{z},ymm1 + EVEX.256.F3.0F.W0 7F /r + + AVX512VL + AVX512F + + Move unaligned packed doubleword integer values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVDQU32 + zmm2/m512 {k1}{z},zmm1 + EVEX.512.F3.0F.W0 7F /r + + AVX512F + + Move unaligned packed doubleword integer values from zmm1 to zmm2/m512 using writemask k1. + + + VMOVDQU64 + xmm1 {k1}{z},xmm2/m128 + EVEX.128.F3.0F.W1 6F /r + + AVX512VL + AVX512F + + Move unaligned packed quadword integer values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVDQU64 + ymm1 {k1}{z},ymm2/m256 + EVEX.256.F3.0F.W1 6F /r + + AVX512VL + AVX512F + + Move unaligned packed quadword integer values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVDQU64 + zmm1 {k1}{z},zmm2/m512 + EVEX.512.F3.0F.W1 6F /r + + AVX512F + + Move unaligned packed quadword integer values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVDQU64 + xmm2/m128 {k1}{z},xmm1 + EVEX.128.F3.0F.W1 7F /r + + AVX512VL + AVX512F + + Move unaligned packed quadword integer values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVDQU64 + ymm2/m256 {k1}{z},ymm1 + EVEX.256.F3.0F.W1 7F /r + + AVX512VL + AVX512F + + Move unaligned packed quadword integer values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVDQU64 + zmm2/m512 {k1}{z},zmm1 + EVEX.512.F3.0F.W1 7F /r + + AVX512F + + Move unaligned packed quadword integer values from zmm1 to zmm2/m512 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVHLPS--Move Packed Single-Precision Floating-Point Values High to Low. + + MOVHLPS + xmm1,xmm2 + 0F 12 /r + + SSE + + Move two packed single-precision floating-point values from high quadword of xmm2 to low quadword of xmm1. + + + VMOVHLPS + xmm1,xmm2,xmm3 + VEX.NDS.128.0F.WIG 12 /r + + AVX + + Merge two packed single-precision floating-point values from high quadword of xmm3 and low quadword of xmm2. + + + VMOVHLPS + xmm1,xmm2,xmm3 + EVEX.NDS.128.0F.W0 12 /r + + AVX512F + + Merge two packed single-precision floating-point values from high quadword of xmm3 and low quadword of xmm2. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + vvvv(r) + ModRM:r/m(r) + NA + + + + MOVHPD--Move High Packed Double-Precision Floating-Point Value. + + MOVHPD + xmm1,m64 + 66 0F 16 /r + + SSE2 + + Move double-precision floating-point value from m64 to high quadword of xmm1. + + + VMOVHPD + xmm2,xmm1,m64 + VEX.NDS.128.66.0F.WIG 16 /r + + AVX + + Merge double-precision floating-point value from m64 and the low quadword of xmm1. + + + VMOVHPD + xmm2,xmm1,m64 + EVEX.NDS.128.66.0F.W1 16 /r + + AVX512F + + Merge double-precision floating-point value from m64 and the low quadword of xmm1. + + + MOVHPD + m64,xmm1 + 66 0F 17 /r + + SSE2 + + Move double-precision floating-point value from high quadword of xmm1 to m64. + + + VMOVHPD + m64,xmm1 + VEX.128.66.0F.WIG 17 /r + + AVX + + Move double-precision floating-point value from high quadword of xmm1 to m64. + + + VMOVHPD + m64,xmm1 + EVEX.128.66.0F.W1 17 /r + + AVX512F + + Move double-precision floating-point value from high quadword of xmm1 to m64. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVHPS--Move High Packed Single-Precision Floating-Point Values. + + MOVHPS + xmm1,m64 + 0F 16 /r + + SSE + + Move two packed single-precision floating-point values from m64 to high quadword of xmm1. + + + VMOVHPS + xmm2,xmm1,m64 + VEX.NDS.128.0F.WIG 16 /r + + AVX + + Merge two packed single-precision floating-point values from m64 and the low quadword of xmm1. + + + VMOVHPS + xmm2,xmm1,m64 + EVEX.NDS.128.0F.W0 16 /r + + AVX512F + + Merge two packed single-precision floating-point values from m64 and the low quadword of xmm1. + + + MOVHPS + m64,xmm1 + 0F 17 /r + + SSE + + Move two packed single-precision floating-point values from high quadword of xmm1 to m64. + + + VMOVHPS + m64,xmm1 + VEX.128.0F.WIG 17 /r + + AVX + + Move two packed single-precision floating-point values from high quadword of xmm1 to m64. + + + VMOVHPS + m64,xmm1 + EVEX.128.0F.W0 17 /r + + AVX512F + + Move two packed single-precision floating-point values from high quadword of xmm1 to m64. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVLHPS--Move Packed Single-Precision Floating-Point Values Low to High. + + MOVLHPS + xmm1,xmm2 + 0F 16 /r + + SSE + + Move two packed single-precision floating-point values from low quadword of xmm2 to high quadword of xmm1. + + + VMOVLHPS + xmm1,xmm2,xmm3 + VEX.NDS.128.0F.WIG 16 /r + + AVX + + Merge two packed single-precision floating-point values from low quadword of xmm3 and low quadword of xmm2. + + + VMOVLHPS + xmm1,xmm2,xmm3 + EVEX.NDS.128.0F.W0 16 /r + + AVX512F + + Merge two packed single-precision floating-point values from low quadword of xmm3 and low quadword of xmm2. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + vvvv(r) + ModRM:r/m(r) + NA + + + + MOVLPD--Move Low Packed Double-Precision Floating-Point Value. + + MOVLPD + xmm1,m64 + 66 0F 12 /r + + SSE2 + + Move double-precision floating-point value from m64 to low quadword of xmm1. + + + VMOVLPD + xmm2,xmm1,m64 + VEX.NDS.128.66.0F.WIG 12 /r + + AVX + + Merge double-precision floating-point value from m64 and the high quadword of xmm1. + + + VMOVLPD + xmm2,xmm1,m64 + EVEX.NDS.128.66.0F.W1 12 /r + + AVX512F + + Merge double-precision floating-point value from m64 and the high quadword of xmm1. + + + MOVLPD + m64,xmm1 + 66 0F 13/r + + SSE2 + + Move double-precision floating-point value from low quadword of xmm1 to m64. + + + VMOVLPD + m64,xmm1 + VEX.128.66.0F.WIG 13/r + + AVX + + Move double-precision floating-point value from low quadword of xmm1 to m64. + + + VMOVLPD + m64,xmm1 + EVEX.128.66.0F.W1 13/r + + AVX512F + + Move double-precision floating-point value from low quadword of xmm1 to m64. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(r) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVLPS--Move Low Packed Single-Precision Floating-Point Values. + + MOVLPS + xmm1,m64 + 0F 12 /r + + SSE + + Move two packed single-precision floating-point values from m64 to low quadword of xmm1. + + + VMOVLPS + xmm2,xmm1,m64 + VEX.NDS.128.0F.WIG 12 /r + + AVX + + Merge two packed single-precision floating-point values from m64 and the high quadword of xmm1. + + + VMOVLPS + xmm2,xmm1,m64 + EVEX.NDS.128.0F.W0 12 /r + + AVX512F + + Merge two packed single-precision floating-point values from m64 and the high quadword of xmm1. + + + MOVLPS + m64,xmm1 + 0F 13/r + + SSE + + Move two packed single-precision floating-point values from low quadword of xmm1 to m64. + + + VMOVLPS + m64,xmm1 + VEX.128.0F.WIG 13/r + + AVX + + Move two packed single-precision floating-point values from low quadword of xmm1 to m64. + + + VMOVLPS + m64,xmm1 + EVEX.128.0F.W0 13/r + + AVX512F + + Move two packed single-precision floating-point values from low quadword of xmm1 to m64. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVNTDQA--Load Double Quadword Non-Temporal Aligned Hint. + + MOVNTDQA + xmm1,m128 + 66 0F 38 2A /r + + SSE4_1 + + Move double quadword from m128 to xmm1 using nontemporal hint if WC memory type. + + + VMOVNTDQA + xmm1,m128 + VEX.128.66.0F38.WIG 2A /r + + AVX + + Move double quadword from m128 to xmm using nontemporal hint if WC memory type. + + + VMOVNTDQA + ymm1,m256 + VEX.256.66.0F38.WIG 2A /r + + AVX2 + + Move 256-bit data from m256 to ymm using non-temporal hint if WC memory type. + + + VMOVNTDQA + xmm1,m128 + EVEX.128.66.0F38.W0 2A /r + + AVX512VL + AVX512F + + Move 128-bit data from m128 to xmm using non-temporal hint if WC memory type. + + + VMOVNTDQA + ymm1,m256 + EVEX.256.66.0F38.W0 2A /r + + AVX512VL + AVX512F + + Move 256-bit data from m256 to ymm using non-temporal hint if WC memory type. + + + VMOVNTDQA + zmm1,m512 + EVEX.512.66.0F38.W0 2A /r + + AVX512F + + Move 512-bit data from m512 to zmm using non-temporal hint if WC memory type. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + MOVNTDQ--Store Packed Integers Using Non-Temporal Hint. + + MOVNTDQ + m128,xmm1 + 66 0F E7 /r + + SSE2 + + Move packed integer values in xmm1 to m128 using nontemporal hint. + + + VMOVNTDQ + m128,xmm1 + VEX.128.66.0F.WIG E7 /r + + AVX + + Move packed integer values in xmm1 to m128 using nontemporal hint. + + + VMOVNTDQ + m256,ymm1 + VEX.256.66.0F.WIG E7 /r + + AVX + + Move packed integer values in ymm1 to m256 using nontemporal hint. + + + VMOVNTDQ + m128,xmm1 + EVEX.128.66.0F.W0 E7 /r + + AVX512VL + AVX512F + + Move packed integer values in xmm1 to m128 using nontemporal hint. + + + VMOVNTDQ + m256,ymm1 + EVEX.256.66.0F.W0 E7 /r + + AVX512VL + AVX512F + + Move packed integer values in zmm1 to m256 using nontemporal hint. + + + VMOVNTDQ + m512,zmm1 + EVEX.512.66.0F.W0 E7 /r + + AVX512F + + Move packed integer values in zmm1 to m512 using nontemporal hint. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVNTPD--Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint. + + MOVNTPD + m128,xmm1 + 66 0F 2B /r + + SSE2 + + Move packed double-precision values in xmm1 to m128 using non-temporal hint. + + + VMOVNTPD + m128,xmm1 + VEX.128.66.0F.WIG 2B /r + + AVX + + Move packed double-precision values in xmm1 to m128 using non-temporal hint. + + + VMOVNTPD + m256,ymm1 + VEX.256.66.0F.WIG 2B /r + + AVX + + Move packed double-precision values in ymm1 to m256 using non-temporal hint. + + + VMOVNTPD + m128,xmm1 + EVEX.128.66.0F.W1 2B /r + + AVX512VL + AVX512F + + Move packed double-precision values in xmm1 to m128 using non-temporal hint. + + + VMOVNTPD + m256,ymm1 + EVEX.256.66.0F.W1 2B /r + + AVX512VL + AVX512F + + Move packed double-precision values in ymm1 to m256 using non-temporal hint. + + + VMOVNTPD + m512,zmm1 + EVEX.512.66.0F.W1 2B /r + + AVX512F + + Move packed double-precision values in zmm1 to m512 using non-temporal hint. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVNTPS--Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint. + + MOVNTPS + m128,xmm1 + 0F 2B /r + + SSE + + Move packed single-precision values xmm1 to mem using non-temporal hint. + + + VMOVNTPS + m128,xmm1 + VEX.128.0F.WIG 2B /r + + AVX + + Move packed single-precision values xmm1 to mem using non-temporal hint. + + + VMOVNTPS + m256,ymm1 + VEX.256.0F.WIG 2B /r + + AVX + + Move packed single-precision values ymm1 to mem using non-temporal hint. + + + VMOVNTPS + m128,xmm1 + EVEX.128.0F.W0 2B /r + + AVX512VL + AVX512F + + Move packed single-precision values in xmm1 to m128 using non-temporal hint. + + + VMOVNTPS + m256,ymm1 + EVEX.256.0F.W0 2B /r + + AVX512VL + AVX512F + + Move packed single-precision values in ymm1 to m256 using non-temporal hint. + + + VMOVNTPS + m512,zmm1 + EVEX.512.0F.W0 2B /r + + AVX512F + + Move packed single-precision values in zmm1 to m512 using non-temporal hint. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVSD--Move or Merge Scalar Double-Precision Floating-Point Value. + + MOVSD + xmm1,xmm2 + F2 0F 10 /r + + SSE2 + + Move scalar double-precision floating-point value from xmm2 to xmm1 register. + + + MOVSD + xmm1,m64 + F2 0F 10 /r + + SSE2 + + Load scalar double-precision floating-point value from m64 to xmm1 register. + + + MOVSD + xmm1/m64,xmm2 + F2 0F 11 /r + + SSE2 + + Move scalar double-precision floating-point value from xmm2 register to xmm1/m64. + + + VMOVSD + xmm1,xmm2,xmm3 + VEX.NDS.LIG.F2.0F.WIG 10 /r + + AVX + + Merge scalar double-precision floating-point value from xmm2 and xmm3 to xmm1 register. + + + VMOVSD + xmm1,m64 + VEX.LIG.F2.0F.WIG 10 /r + + AVX + + Load scalar double-precision floating-point value from m64 to xmm1 register. + + + VMOVSD + xmm1,xmm2,xmm3 + VEX.NDS.LIG.F2.0F.WIG 11 /r + + AVX + + Merge scalar double-precision floating-point value from xmm2 and xmm3 registers to xmm1. + + + VMOVSD + m64,xmm1 + VEX.LIG.F2.0F.WIG 11 /r + + AVX + + Store scalar double-precision floating-point value from xmm1 register to m64. + + + VMOVSD + xmm1 {k1}{z},xmm2,xmm3 + EVEX.NDS.LIG.F2.0F.W1 10 /r + + AVX512F + + Merge scalar double-precision floating-point value from xmm2 and xmm3 registers to xmm1 under writemask k1. + + + VMOVSD + xmm1 {k1}{z},m64 + EVEX.LIG.F2.0F.W1 10 /r + + AVX512F + + Load scalar double-precision floating-point value from m64 to xmm1 register under writemask k1. + + + VMOVSD + xmm1 {k1}{z},xmm2,xmm3 + EVEX.NDS.LIG.F2.0F.W1 11 /r + + AVX512F + + Merge scalar double-precision floating-point value from xmm2 and xmm3 registers to xmm1 under writemask k1. + + + VMOVSD + m64 {k1},xmm1 + EVEX.LIG.F2.0F.W1 11 /r + + AVX512F + + Store scalar double-precision floating-point value from xmm1 register to m64 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + vvvv(r) + ModRM:reg(r) + NA + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVSHDUP--Replicate Single FP Values. + + MOVSHDUP + xmm1,xmm2/m128 + F3 0F 16 /r + + SSE3 + + Move odd index single-precision floating-point values from xmm2/mem and duplicate each element into xmm1. + + + VMOVSHDUP + xmm1,xmm2/m128 + VEX.128.F3.0F.WIG 16 /r + + AVX + + Move odd index single-precision floating-point values from xmm2/mem and duplicate each element into xmm1. + + + VMOVSHDUP + ymm1,ymm2/m256 + VEX.256.F3.0F.WIG 16 /r + + AVX + + Move odd index single-precision floating-point values from ymm2/mem and duplicate each element into ymm1. + + + VMOVSHDUP + xmm1 {k1}{z},xmm2/m128 + EVEX.128.F3.0F.W0 16 /r + + AVX512VL + AVX512F + + Move odd index single-precision floating-point values from xmm2/m128 and duplicate each element into xmm1 under writemask. + + + VMOVSHDUP + ymm1 {k1}{z},ymm2/m256 + EVEX.256.F3.0F.W0 16 /r + + AVX512VL + AVX512F + + Move odd index single-precision floating-point values from ymm2/m256 and duplicate each element into ymm1 under writemask. + + + VMOVSHDUP + zmm1 {k1}{z},zmm2/m512 + EVEX.512.F3.0F.W0 16 /r + + AVX512F + + Move odd index single-precision floating-point values from zmm2/m512 and duplicate each element into zmm1 under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + MOVSLDUP--Replicate Single FP Values. + + MOVSLDUP + xmm1,xmm2/m128 + F3 0F 12 /r + + SSE3 + + Move even index single-precision floating-point values from xmm2/mem and duplicate each element into xmm1. + + + VMOVSLDUP + xmm1,xmm2/m128 + VEX.128.F3.0F.WIG 12 /r + + AVX + + Move even index single-precision floating-point values from xmm2/mem and duplicate each element into xmm1. + + + VMOVSLDUP + ymm1,ymm2/m256 + VEX.256.F3.0F.WIG 12 /r + + AVX + + Move even index single-precision floating-point values from ymm2/mem and duplicate each element into ymm1. + + + VMOVSLDUP + xmm1 {k1}{z},xmm2/m128 + EVEX.128.F3.0F.W0 12 /r + + AVX512VL + AVX512F + + Move even index single-precision floating-point values from xmm2/m128 and duplicate each element into xmm1 under writemask. + + + VMOVSLDUP + ymm1 {k1}{z},ymm2/m256 + EVEX.256.F3.0F.W0 12 /r + + AVX512VL + AVX512F + + Move even index single-precision floating-point values from ymm2/m256 and duplicate each element into ymm1 under writemask. + + + VMOVSLDUP + zmm1 {k1}{z},zmm2/m512 + EVEX.512.F3.0F.W0 12 /r + + AVX512F + + Move even index single-precision floating-point values from zmm2/m512 and duplicate each element into zmm1 under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + MOVSS--Move or Merge Scalar Single-Precision Floating-Point Value. + + MOVSS + xmm1,xmm2 + F3 0F 10 /r + + SSE + + Merge scalar single-precision floating-point value from xmm2 to xmm1 register. + + + MOVSS + xmm1,m32 + F3 0F 10 /r + + SSE + + Load scalar single-precision floating-point value from m32 to xmm1 register. + + + VMOVSS + xmm1,xmm2,xmm3 + VEX.NDS.LIG.F3.0F.WIG 10 /r + + AVX + + Merge scalar single-precision floating-point value from xmm2 and xmm3 to xmm1 register. + + + VMOVSS + xmm1,m32 + VEX.LIG.F3.0F.WIG 10 /r + + AVX + + Load scalar single-precision floating-point value from m32 to xmm1 register. + + + MOVSS + xmm2/m32,xmm1 + F3 0F 11 /r + + SSE + + Move scalar single-precision floating-point value from xmm1 register to xmm2/m32. + + + VMOVSS + xmm1,xmm2,xmm3 + VEX.NDS.LIG.F3.0F.WIG 11 /r + + AVX + + Move scalar single-precision floating-point value from xmm2 and xmm3 to xmm1 register. + + + VMOVSS + m32,xmm1 + VEX.LIG.F3.0F.WIG 11 /r + + AVX + + Move scalar single-precision floating-point value from xmm1 register to m32. + + + VMOVSS + xmm1 {k1}{z},xmm2,xmm3 + EVEX.NDS.LIG.F3.0F.W0 10 /r + + AVX512F + + Move scalar single-precision floating-point value from xmm2 and xmm3 to xmm1 register under writemask k1. + + + VMOVSS + xmm1 {k1}{z},m32 + EVEX.LIG.F3.0F.W0 10 /r + + AVX512F + + Move scalar single-precision floating-point values from m32 to xmm1 under writemask k1. + + + VMOVSS + xmm1 {k1}{z},xmm2,xmm3 + EVEX.NDS.LIG.F3.0F.W0 11 /r + + AVX512F + + Move scalar single-precision floating-point value from xmm2 and xmm3 to xmm1 register under writemask k1. + + + VMOVSS + m32 {k1},xmm1 + EVEX.LIG.F3.0F.W0 11 /r + + AVX512F + + Move scalar single-precision floating-point values from xmm1 to m32 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + vvvv(r) + ModRM:reg(r) + NA + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVUPD--Move Unaligned Packed Double-Precision Floating-Point Values. + + MOVUPD + xmm1,xmm2/m128 + 66 0F 10 /r + + SSE2 + + Move unaligned packed double-precision floatingpoint from xmm2/mem to xmm1. + + + MOVUPD + xmm2/m128,xmm1 + 66 0F 11 /r + + SSE2 + + Move unaligned packed double-precision floatingpoint from xmm1 to xmm2/mem. + + + VMOVUPD + xmm1,xmm2/m128 + VEX.128.66.0F.WIG 10 /r + + AVX + + Move unaligned packed double-precision floatingpoint from xmm2/mem to xmm1. + + + VMOVUPD + xmm2/m128,xmm1 + VEX.128.66.0F.WIG 11 /r + + AVX + + Move unaligned packed double-precision floatingpoint from xmm1 to xmm2/mem. + + + VMOVUPD + ymm1,ymm2/m256 + VEX.256.66.0F.WIG 10 /r + + AVX + + Move unaligned packed double-precision floatingpoint from ymm2/mem to ymm1. + + + VMOVUPD + ymm2/m256,ymm1 + VEX.256.66.0F.WIG 11 /r + + AVX + + Move unaligned packed double-precision floatingpoint from ymm1 to ymm2/mem. + + + VMOVUPD + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F.W1 10 /r + + AVX512VL + AVX512F + + Move unaligned packed double-precision floatingpoint from xmm2/m128 to xmm1 using writemask k1. + + + VMOVUPD + xmm2/m128 {k1}{z},xmm1 + EVEX.128.66.0F.W1 11 /r + + AVX512VL + AVX512F + + Move unaligned packed double-precision floatingpoint from xmm1 to xmm2/m128 using writemask k1. + + + VMOVUPD + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F.W1 10 /r + + AVX512VL + AVX512F + + Move unaligned packed double-precision floatingpoint from ymm2/m256 to ymm1 using writemask k1. + + + VMOVUPD + ymm2/m256 {k1}{z},ymm1 + EVEX.256.66.0F.W1 11 /r + + AVX512VL + AVX512F + + Move unaligned packed double-precision floatingpoint from ymm1 to ymm2/m256 using writemask k1. + + + VMOVUPD + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F.W1 10 /r + + AVX512F + + Move unaligned packed double-precision floatingpoint values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVUPD + zmm2/m512 {k1}{z},zmm1 + EVEX.512.66.0F.W1 11 /r + + AVX512F + + Move unaligned packed double-precision floatingpoint values from zmm1 to zmm2/m512 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + MOVUPS--Move Unaligned Packed Single-Precision Floating-Point Values. + + MOVUPS + xmm1,xmm2/m128 + 0F 10 /r + + SSE + + Move unaligned packed single-precision floating-point from xmm2/mem to xmm1. + + + MOVUPS + xmm2/m128,xmm1 + 0F 11 /r + + SSE + + Move unaligned packed single-precision floating-point from xmm1 to xmm2/mem. + + + VMOVUPS + xmm1,xmm2/m128 + VEX.128.0F.WIG 10 /r + + AVX + + Move unaligned packed single-precision floating-point from xmm2/mem to xmm1. + + + VMOVUPS + xmm2/m128,xmm1 + VEX.128.0F 11.WIG /r + + AVX + + Move unaligned packed single-precision floating-point from xmm1 to xmm2/mem. + + + VMOVUPS + ymm1,ymm2/m256 + VEX.256.0F 10.WIG /r + + AVX + + Move unaligned packed single-precision floating-point from ymm2/mem to ymm1. + + + VMOVUPS + ymm2/m256,ymm1 + VEX.256.0F 11.WIG /r + + AVX + + Move unaligned packed single-precision floating-point from ymm1 to ymm2/mem. + + + VMOVUPS + xmm1 {k1}{z},xmm2/m128 + EVEX.128.0F.W0 10 /r + + AVX512VL + AVX512F + + Move unaligned packed single-precision floating-point values from xmm2/m128 to xmm1 using writemask k1. + + + VMOVUPS + ymm1 {k1}{z},ymm2/m256 + EVEX.256.0F.W0 10 /r + + AVX512VL + AVX512F + + Move unaligned packed single-precision floating-point values from ymm2/m256 to ymm1 using writemask k1. + + + VMOVUPS + zmm1 {k1}{z},zmm2/m512 + EVEX.512.0F.W0 10 /r + + AVX512F + + Move unaligned packed single-precision floating-point values from zmm2/m512 to zmm1 using writemask k1. + + + VMOVUPS + xmm2/m128 {k 1}{z},xmm1 + EVEX.128.0F.W0 11 /r + + AVX512VL + AVX512F + + Move unaligned packed single-precision floating-point values from xmm1 to xmm2/m128 using writemask k1. + + + VMOVUPS + ymm2/m256 {k1}{z},ymm1 + EVEX.256.0F.W0 11 /r + + AVX512VL + AVX512F + + Move unaligned packed single-precision floating-point values from ymm1 to ymm2/m256 using writemask k1. + + + VMOVUPS + zmm2/m512 {k1}{z},zmm1 + EVEX.512.0F.W0 11 /r + + AVX512F + + Move unaligned packed single-precision floating-point values from zmm1 to zmm2/m512 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + PSADBW--Compute Sum of Absolute Differences. + + PSADBW + xmm1,xmm2/m128 + 66 0F F6 /r + + SSE2 + + Computes the absolute differences of the packed unsigned byte integers from xmm2 /m128 and xmm1; the 8 low differences and 8 high differences are then summed separately to produce two unsigned word integer results. + + + VPSADBW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F F6 /r + + AVX + + Computes the absolute differences of the packed unsigned byte integers from xmm3 /m128 and xmm2; the 8 low differences and 8 high differences are then summed separately to produce two unsigned word integer results. + + + VPSADBW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F F6 /r + + AVX2 + + Computes the absolute differences of the packed unsigned byte integers from ymm3 /m256 and ymm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results. + + + VPSADBW + xmm1,xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG F6 /r + + AVX512VL + AVX512BW + + Computes the absolute differences of the packed unsigned byte integers from xmm3 /m128 and xmm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results. + + + VPSADBW + ymm1,ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG F6 /r + + AVX512VL + AVX512BW + + Computes the absolute differences of the packed unsigned byte integers from ymm3 /m256 and ymm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results. + + + VPSADBW + zmm1,zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG F6 /r + + AVX512BW + + Computes the absolute differences of the packed unsigned byte integers from zmm3 /m512 and zmm2; then each consecutive 8 differences are summed separately to produce four unsigned word integer results. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + MULPD--Multiply Packed Double-Precision Floating-Point Values. + + MULPD + xmm1,xmm2/m128 + 66 0F 59 /r + + SSE2 + + Multiply packed double-precision floating-point values in xmm2/m128 with xmm1 and store result in xmm1. + + + VMULPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 59 /r + + AVX + + Multiply packed double-precision floating-point values in xmm3/m128 with xmm2 and store result in xmm1. + + + VMULPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 59 /r + + AVX + + Multiply packed double-precision floating-point values in ymm3/m256 with ymm2 and store result in ymm1. + + + VMULPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 59 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from xmm3/m128/m64bcst to xmm2 and store result in xmm1. + + + VMULPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 59 /r + + AVX512VL + AVX512F + + Multiply packed double-precision floating-point values from ymm3/m256/m64bcst to ymm2 and store result in ymm1. + + + VMULPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F.W1 59 /r + + AVX512F + + Multiply packed double-precision floating-point values in zmm3/m512/m64bcst with zmm2 and store result in zmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + MULPS--Multiply Packed Single-Precision Floating-Point Values. + + MULPS + xmm1,xmm2/m128 + 0F 59 /r + + SSE + + Multiply packed single-precision floating-point values in xmm2/m128 with xmm1 and store result in xmm1. + + + VMULPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 59 /r + + AVX + + Multiply packed single-precision floating-point values in xmm3/m128 with xmm2 and store result in xmm1. + + + VMULPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F.WIG 59 /r + + AVX + + Multiply packed single-precision floating-point values in ymm3/m256 with ymm2 and store result in ymm1. + + + VMULPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 59 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from xmm3/m128/m32bcst to xmm2 and store result in xmm1. + + + VMULPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 59 /r + + AVX512VL + AVX512F + + Multiply packed single-precision floating-point values from ymm3/m256/m32bcst to ymm2 and store result in ymm1. + + + VMULPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst {er} + EVEX.NDS.512.0F.W0 59 /r + + AVX512F + + Multiply packed single-precision floating-point values in zmm3/m512/m32bcst with zmm2 and store result in zmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + MULSD--Multiply Scalar Double-Precision Floating-Point Value. + + MULSD + xmm1,xmm2/m64 + F2 0F 59 /r + + SSE2 + + Multiply the low double-precision floating-point value in xmm2/m64 by low double-precision floating-point value in xmm1. + + + VMULSD + xmm1,xmm2,xmm3/m64 + VEX.NDS.128.F2.0F.WIG 59 /r + + AVX + + Multiply the low double-precision floating-point value in xmm3/m64 by low double-precision floating-point value in xmm2. + + + VMULSD + xmm1 {k1}{z},xmm2,xmm3/m64 {er} + EVEX.NDS.LIG.F2.0F.W1 59 /r + + AVX512F + + Multiply the low double-precision floating-point value in xmm3/m64 by low double-precision floating-point value in xmm2. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + MULSS--Multiply Scalar Single-Precision Floating-Point Values. + + MULSS + xmm1,xmm2/m32 + F3 0F 59 /r + + SSE + + Multiply the low single-precision floating-point value in xmm2/m32 by the low single-precision floating-point value in xmm1. + + + VMULSS + xmm1,xmm2,xmm3/m32 + VEX.NDS.128.F3.0F.WIG 59 /r + + AVX + + Multiply the low single-precision floating-point value in xmm3/m32 by the low single-precision floating-point value in xmm2. + + + VMULSS + xmm1 {k1}{z},xmm2,xmm3/m32 {er} + EVEX.NDS.LIG.F3.0F.W0 59 /r + + AVX512F + + Multiply the low single-precision floating-point value in xmm3/m32 by the low single-precision floating-point value in xmm2. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + ORPD--Bitwise Logical OR of Packed Double Precision Floating-Point Values. + + ORPD + xmm1,xmm2/m128 + 66 0F 56/r + + SSE2 + + Return the bitwise logical OR of packed double-precision floating-point values in xmm1 and xmm2/mem. + + + VORPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F 56 /r + + AVX + + Return the bitwise logical OR of packed double-precision floating-point values in xmm2 and xmm3/mem. + + + VORPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F 56 /r + + AVX + + Return the bitwise logical OR of packed double-precision floating-point values in ymm2 and ymm3/mem. + + + VORPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 56 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical OR of packed double-precision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1. + + + VORPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 56 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical OR of packed double-precision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1. + + + VORPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 56 /r + + AVX512DQ + + Return the bitwise logical OR of packed double-precision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + ORPS--Bitwise Logical OR of Packed Single Precision Floating-Point Values. + + ORPS + xmm1,xmm2/m128 + 0F 56 /r + + SSE + + Return the bitwise logical OR of packed single-precision floating-point values in xmm1 and xmm2/mem. + + + VORPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F 56 /r + + AVX + + Return the bitwise logical OR of packed single-precision floating-point values in xmm2 and xmm3/mem. + + + VORPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F 56 /r + + AVX + + Return the bitwise logical OR of packed single-precision floating-point values in ymm2 and ymm3/mem. + + + VORPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 56 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical OR of packed single-precision floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1. + + + VORPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 56 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical OR of packed single-precision floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1. + + + VORPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.0F.W0 56 /r + + AVX512DQ + + Return the bitwise logical OR of packed single-precision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PABSB/PABSW/PABSD/PABSQ--Packed Absolute Value. + + PABSB + xmm1,xmm2/m128 + 66 0F 38 1C /r + + SSSE3 + + Compute the absolute value of bytes in xmm2/m128 and store UNSIGNED result in xmm1. + + + PABSW + xmm1,xmm2/m128 + 66 0F 38 1D /r + + SSSE3 + + Compute the absolute value of 16-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. + + + PABSD + xmm1,xmm2/m128 + 66 0F 38 1E /r + + SSSE3 + + Compute the absolute value of 32-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. + + + VPABSB + xmm1,xmm2/m128 + VEX.128.66.0F38.WIG 1C /r + + AVX + + Compute the absolute value of bytes in xmm2/m128 and store UNSIGNED result in xmm1. + + + VPABSW + xmm1,xmm2/m128 + VEX.128.66.0F38.WIG 1D /r + + AVX + + Compute the absolute value of 16-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. + + + VPABSD + xmm1,xmm2/m128 + VEX.128.66.0F38.WIG 1E /r + + AVX + + Compute the absolute value of 32-bit integers in xmm2/m128 and store UNSIGNED result in xmm1. + + + VPABSB + ymm1,ymm2/m256 + VEX.256.66.0F38.WIG 1C /r + + AVX2 + + Compute the absolute value of bytes in ymm2/m256 and store UNSIGNED result in ymm1. + + + VPABSW + ymm1,ymm2/m256 + VEX.256.66.0F38.WIG 1D /r + + AVX2 + + Compute the absolute value of 16-bit integers in ymm2/m256 and store UNSIGNED result in ymm1. + + + VPABSD + ymm1,ymm2/m256 + VEX.256.66.0F38.WIG 1E /r + + AVX2 + + Compute the absolute value of 32-bit integers in ymm2/m256 and store UNSIGNED result in ymm1. + + + VPABSB + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F38.WIG 1C /r + + AVX512VL + AVX512BW + + Compute the absolute value of bytes in xmm2/m128 and store UNSIGNED result in xmm1 using writemask k1. + + + VPABSB + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F38.WIG 1C /r + + AVX512VL + AVX512BW + + Compute the absolute value of bytes in ymm2/m256 and store UNSIGNED result in ymm1 using writemask k1. + + + VPABSB + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F38.WIG 1C /r + + AVX512BW + + Compute the absolute value of bytes in zmm2/m512 and store UNSIGNED result in zmm1 using writemask k1. + + + VPABSW + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F38.WIG 1D /r + + AVX512VL + AVX512BW + + Compute the absolute value of 16-bit integers in xmm2/m128 and store UNSIGNED result in xmm1 using writemask k1. + + + VPABSW + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F38.WIG 1D /r + + AVX512VL + AVX512BW + + Compute the absolute value of 16-bit integers in ymm2/m256 and store UNSIGNED result in ymm1 using writemask k1. + + + VPABSW + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F38.WIG 1D /r + + AVX512BW + + Compute the absolute value of 16-bit integers in zmm2/m512 and store UNSIGNED result in zmm1 using writemask k1. + + + VPABSD + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.66.0F38.W0 1E /r + + AVX512VL + AVX512F + + Compute the absolute value of 32-bit integers in xmm2/m128/m32bcst and store UNSIGNED result in xmm1 using writemask k1. + + + VPABSD + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.66.0F38.W0 1E /r + + AVX512VL + AVX512F + + Compute the absolute value of 32-bit integers in ymm2/m256/m32bcst and store UNSIGNED result in ymm1 using writemask k1. + + + VPABSD + zmm1 {k1}{z},zmm2/m512/m32bcst + EVEX.512.66.0F38.W0 1E /r + + AVX512F + + Compute the absolute value of 32-bit integers in zmm2/m512/m32bcst and store UNSIGNED result in zmm1 using writemask k1. + + + VPABSQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F38.W1 1F /r + + AVX512VL + AVX512F + + Compute the absolute value of 64-bit integers in xmm2/m128/m64bcst and store UNSIGNED result in xmm1 using writemask k1. + + + VPABSQ + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F38.W1 1F /r + + AVX512VL + AVX512F + + Compute the absolute value of 64-bit integers in ymm2/m256/m64bcst and store UNSIGNED result in ymm1 using writemask k1. + + + VPABSQ + zmm1 {k1}{z},zmm2/m512/m64bcst + EVEX.512.66.0F38.W1 1F /r + + AVX512F + + Compute the absolute value of 64-bit integers in zmm2/m512/m64bcst and store UNSIGNED result in zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + PACKSSWB/PACKSSDW--Pack with Signed Saturation. + + PACKSSWB + xmm1,xmm2/m128 + 66 0F 63 /r + + SSE2 + + Converts 8 packed signed word integers from xmm1 and from xxm2/m128 into 16 packed signed byte integers in xmm1 using signed saturation. + + + PACKSSDW + xmm1,xmm2/m128 + 66 0F 6B /r + + SSE2 + + Converts 4 packed signed doubleword integers from xmm1 and from xmm2/m128 into 8 packed signed word integers in xmm1 using signed saturation. + + + VPACKSSWB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F 63 /r + + AVX + + Converts 8 packed signed word integers from xmm2 and from xmm3/m128 into 16 packed signed byte integers in xmm1 using signed saturation. + + + VPACKSSDW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F 6B /r + + AVX + + Converts 4 packed signed doubleword integers from xmm2 and from xmm3/m128 into 8 packed signed word integers in xmm1 using signed saturation. + + + VPACKSSWB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F 63 /r + + AVX2 + + Converts 16 packed signed word integers from ymm2 and from ymm3/m256 into 32 packed signed byte integers in ymm1 using signed saturation. + + + VPACKSSDW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F 6B /r + + AVX2 + + Converts 8 packed signed doubleword integers from ymm2 and from ymm3/m256 into 16 packed signed word integers in ymm1 using signed saturation. + + + VPACKSSWB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG 63 /r + + AVX512VL + AVX512BW + + Converts packed signed word integers from xmm2 and from xmm3/m128 into packed signed byte integers in xmm1 using signed saturation under writemask k1. + + + VPACKSSWB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG 63 /r + + AVX512VL + AVX512BW + + Converts packed signed word integers from ymm2 and from ymm3/m256 into packed signed byte integers in ymm1 using signed saturation under writemask k1. + + + VPACKSSWB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG 63 /r + + AVX512BW + + Converts packed signed word integers from zmm2 and from zmm3/m512 into packed signed byte integers in zmm1 using signed saturation under writemask k1. + + + VPACKSSDW + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 6B /r + + AVX512VL + AVX512BW + + Converts packed signed doubleword integers from xmm2 and from xmm3/m128/m32bcst into packed signed word integers in xmm1 using signed saturation under writemask k1. + + + VPACKSSDW + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 6B /r + + AVX512VL + AVX512BW + + Converts packed signed doubleword integers from ymm2 and from ymm3/m256/m32bcst into packed signed word integers in ymm1 using signed saturation under writemask k1. + + + VPACKSSDW + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 6B /r + + AVX512BW + + Converts packed signed doubleword integers from zmm2 and from zmm3/m512/m32bcst into packed signed word integers in zmm1 using signed saturation under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PACKUSDW--Pack with Unsigned Saturation. + + PACKUSDW + xmm1,xmm2/m128 + 66 0F 38 2B /r + + SSE4_1 + + Convert 4 packed signed doubleword integers from xmm1 and 4 packed signed doubleword integers from xmm2/m128 into 8 packed unsigned word integers in xmm1 using unsigned saturation. + + + VPACKUSDW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38 2B /r + + AVX + + Convert 4 packed signed doubleword integers from xmm2 and 4 packed signed doubleword integers from xmm3/m128 into 8 packed unsigned word integers in xmm1 using unsigned saturation. + + + VPACKUSDW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38 2B /r + + AVX2 + + Convert 8 packed signed doubleword integers from ymm2 and 8 packed signed doubleword integers from ymm3/m256 into 16 packed unsigned word integers in ymm1 using unsigned saturation. + + + VPACKUSDW + xmm1{k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 2B /r + + AVX512VL + AVX512BW + + Convert packed signed doubleword integers from xmm2 and packed signed doubleword integers from xmm3/m128/m32bcst into packed unsigned word integers in xmm1 using unsigned saturation under writemask k1. + + + VPACKUSDW + ymm1{k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 2B /r + + AVX512VL + AVX512BW + + Convert packed signed doubleword integers from ymm2 and packed signed doubleword integers from ymm3/m256/m32bcst into packed unsigned word integers in ymm1 using unsigned saturation under writemask k1. + + + VPACKUSDW + zmm1{k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 2B /r + + AVX512BW + + Convert packed signed doubleword integers from zmm2 and packed signed doubleword integers from zmm3/m512/m32bcst into packed unsigned word integers in zmm1 using unsigned saturation under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PACKUSWB--Pack with Unsigned Saturation. + + PACKUSWB + xmm1,xmm2/m128 + 66 0F 67 /r + + SSE2 + + Converts 8 signed word integers from xmm1 and 8 signed word integers from xmm2/m128 into 16 unsigned byte integers in xmm1 using unsigned saturation. + + + VPACKUSWB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F 67 /r + + AVX + + Converts 8 signed word integers from xmm2 and 8 signed word integers from xmm3/m128 into 16 unsigned byte integers in xmm1 using unsigned saturation. + + + VPACKUSWB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F 67 /r + + AVX2 + + Converts 16 signed word integers from ymm2 and 16 signed word integers from ymm3/m256 into 32 unsigned byte integers in ymm1 using unsigned saturation. + + + VPACKUSWB + xmm1{k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG 67 /r + + AVX512VL + AVX512BW + + Converts signed word integers from xmm2 and signed word integers from xmm3/m128 into unsigned byte integers in xmm1 using unsigned saturation under writemask k1. + + + VPACKUSWB + ymm1{k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG 67 /r + + AVX512VL + AVX512BW + + Converts signed word integers from ymm2 and signed word integers from ymm3/m256 into unsigned byte integers in ymm1 using unsigned saturation under writemask k1. + + + VPACKUSWB + zmm1{k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG 67 /r + + AVX512BW + + Converts signed word integers from zmm2 and signed word integers from zmm3/m512 into unsigned byte integers in zmm1 using unsigned saturation under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PADDB/PADDW/PADDD/PADDQ--Add Packed Integers. + + PADDB + xmm1,xmm2/m128 + 66 0F FC /r + + SSE2 + + Add packed byte integers from xmm2/m128 and xmm1. + + + PADDW + xmm1,xmm2/m128 + 66 0F FD /r + + SSE2 + + Add packed word integers from xmm2/m128 and xmm1. + + + PADDD + xmm1,xmm2/m128 + 66 0F FE /r + + SSE2 + + Add packed doubleword integers from xmm2/m128 and xmm1. + + + PADDQ + xmm1,xmm2/m128 + 66 0F D4 /r + + SSE2 + + Add packed quadword integers from xmm2/m128 and xmm1. + + + VPADDB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG FC /r + + AVX + + Add packed byte integers from xmm2, and xmm3/m128 and store in xmm1. + + + VPADDW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG FD /r + + AVX + + Add packed word integers from xmm2, xmm3/m128 and store in xmm1. + + + VPADDD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG FE /r + + AVX + + Add packed doubleword integers from xmm2, xmm3/m128 and store in xmm1. + + + VPADDQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG D4 /r + + AVX + + Add packed quadword integers from xmm2, xmm3/m128 and store in xmm1. + + + VPADDB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG FC /r + + AVX2 + + Add packed byte integers from ymm2, and ymm3/m256 and store in ymm1. + + + VPADDW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG FD /r + + AVX2 + + Add packed word integers from ymm2, ymm3/m256 and store in ymm1. + + + VPADDD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG FE /r + + AVX2 + + Add packed doubleword integers from ymm2, ymm3/m256 and store in ymm1. + + + VPADDQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG D4 /r + + AVX2 + + Add packed quadword integers from ymm2, ymm3/m256 and store in ymm1. + + + VPADDB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG FC /r + + AVX512VL + AVX512BW + + Add packed byte integers from xmm2, and xmm3/m128 and store in xmm1 using writemask k1. + + + VPADDW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG FD /r + + AVX512VL + AVX512BW + + Add packed word integers from xmm2, and xmm3/m128 and store in xmm1 using writemask k1. + + + VPADDD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 FE /r + + AVX512VL + AVX512F + + Add packed doubleword integers from xmm2, and xmm3/m128/m32bcst and store in xmm1 using writemask k1. + + + VPADDQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 D4 /r + + AVX512VL + AVX512F + + Add packed quadword integers from xmm2, and xmm3/m128/m64bcst and store in xmm1 using writemask k1. + + + VPADDB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG FC /r + + AVX512VL + AVX512BW + + Add packed byte integers from ymm2, and ymm3/m256 and store in ymm1 using writemask k1. + + + VPADDW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG FD /r + + AVX512VL + AVX512BW + + Add packed word integers from ymm2, and ymm3/m256 and store in ymm1 using writemask k1. + + + VPADDD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 FE /r + + AVX512VL + AVX512F + + Add packed doubleword integers from ymm2, ymm3/m256/m32bcst and store in ymm1 using writemask k1. + + + VPADDQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 D4 /r + + AVX512VL + AVX512F + + Add packed quadword integers from ymm2, ymm3/m256/m64bcst and store in ymm1 using writemask k1. + + + VPADDB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG FC /r + + AVX512BW + + Add packed byte integers from zmm2, and zmm3/m512 and store in zmm1 using writemask k1. + + + VPADDW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG FD /r + + AVX512BW + + Add packed word integers from zmm2, and zmm3/m512 and store in zmm1 using writemask k1. + + + VPADDD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 FE /r + + AVX512F + + Add packed doubleword integers from zmm2, zmm3/m512/m32bcst and store in zmm1 using writemask k1. + + + VPADDQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 D4 /r + + AVX512F + + Add packed quadword integers from zmm2, zmm3/m512/m64bcst and store in zmm1 using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PADDSB/PADDSW--Add Packed Signed Integers with Signed Saturation. + + PADDSB + xmm1,xmm2/m128 + 66 0F EC /r + + SSE2 + + Add packed signed byte integers from xmm2/m128 and xmm1 and saturate the results. + + + PADDSW + xmm1,xmm2/m128 + 66 0F ED /r + + SSE2 + + Add packed signed word integers from xmm2/m128 and xmm1 and saturate the results. + + + VPADDSB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F EC + + AVX + + Add packed signed byte integers from xmm2, and xmm3/m128 and store the saturated results in xmm1. + + + VPADDSW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F ED + + AVX + + Add packed signed word integers from xmm2, and xmm3/m128 and store the saturated results in xmm1. + + + VPADDSB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F EC + + AVX2 + + Add packed signed byte integers from ymm2, and ymm3/m256 and store the saturated results in ymm1. + + + VPADDSW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F ED + + AVX2 + + Add packed signed word integers from ymm2, and ymm3/m256 and store the saturated results in ymm1. + + + VPADDSB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG EC /r + + AVX512VL + AVX512BW + + Add packed signed byte integers from xmm2, and xmm3/m128 and store the saturated results in xmm1 under writemask k1. + + + VPADDSB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG EC /r + + AVX512VL + AVX512BW + + Add packed signed byte integers from ymm2, and ymm3/m256 and store the saturated results in ymm1 under writemask k1. + + + VPADDSB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG EC /r + + AVX512BW + + Add packed signed byte integers from zmm2, and zmm3/m512 and store the saturated results in zmm1 under writemask k1. + + + VPADDSW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG ED /r + + AVX512VL + AVX512BW + + Add packed signed word integers from xmm2, and xmm3/m128 and store the saturated results in xmm1 under writemask k1. + + + VPADDSW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG ED /r + + AVX512VL + AVX512BW + + Add packed signed word integers from ymm2, and ymm3/m256 and store the saturated results in ymm1 under writemask k1. + + + VPADDSW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG ED /r + + AVX512BW + + Add packed signed word integers from zmm2, and zmm3/m512 and store the saturated results in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PADDUSB/PADDUSW--Add Packed Unsigned Integers with Unsigned Saturation. + + PADDUSB + xmm1,xmm2/m128 + 66 0F DC /r + + SSE2 + + Add packed unsigned byte integers from xmm2/m128 and xmm1 and saturate the results. + + + PADDUSW + xmm1,xmm2/m128 + 66 0F DD /r + + SSE2 + + Add packed unsigned word integers from xmm2/m128 and xmm1 and saturate the results. + + + VPADDUSB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F DC + + AVX + + Add packed unsigned byte integers from xmm2, and xmm3/m128 and store the saturated results in xmm1. + + + VPADDUSW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F DD + + AVX + + Add packed unsigned word integers from xmm2, and xmm3/m128 and store the saturated results in xmm1. + + + VPADDUSB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F DC + + AVX2 + + Add packed unsigned byte integers from ymm2, and ymm3/m256 and store the saturated results in ymm1. + + + VPADDUSW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F DD + + AVX2 + + Add packed unsigned word integers from ymm2, and ymm3/m256 and store the saturated results in ymm1. + + + VPADDUSB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG DC /r + + AVX512VL + AVX512BW + + Add packed unsigned byte integers from xmm2, and xmm3/m128 and store the saturated results in xmm1 under writemask k1. + + + VPADDUSB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG DC /r + + AVX512VL + AVX512BW + + Add packed unsigned byte integers from ymm2, and ymm3/m256 and store the saturated results in ymm1 under writemask k1. + + + VPADDUSB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG DC /r + + AVX512BW + + Add packed unsigned byte integers from zmm2, and zmm3/m512 and store the saturated results in zmm1 under writemask k1. + + + VPADDUSW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG DD /r + + AVX512VL + AVX512BW + + Add packed unsigned word integers from xmm2, and xmm3/m128 and store the saturated results in xmm1 under writemask k1. + + + VPADDUSW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG DD /r + + AVX512VL + AVX512BW + + Add packed unsigned word integers from ymm2, and ymm3/m256 and store the saturated results in ymm1 under writemask k1. + + + VPADDUSW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG DD /r + + AVX512BW + + Add packed unsigned word integers from zmm2, and zmm3/m512 and store the saturated results in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PALIGNR--Byte Align. + + PALIGNR + xmm1,xmm2/m128,imm8 + 66 0F 3A 0F /r ib + + SSSE3 + + Concatenate destination and source operands, extract byte aligned result shifted to the right by constant value in imm8 and result is stored in xmm1. + + + VPALIGNR + xmm1,xmm2,xmm3/m128,imm8 + VEX.NDS.128.66.0F3A 0F /r ib + + AVX + + Concatenate xmm2 and xmm3/m128 into a 32-byte intermediate result, extract byte aligned result shifted to the right by constant value in imm8 and result is stored in xmm1. + + + VPALIGNR + ymm1,ymm2,ymm3/m256,imm8 + VEX.NDS.256.66.0F3A 0F /r ib + + AVX2 + + Concatenate pairs of 16 bytes in ymm2 and ymm3/m256 into 32-byte intermediate result, extract byte-aligned, 16-byte result shifted to the right by constant values in imm8 from each intermediate result, and two 16-byte results are stored in ymm1. + + + VPALIGNR + xmm1 {k1}{z},xmm2,xmm3/m128,imm8 + EVEX.NDS.128.66.0F3A.WIG 0F /r ib + + AVX512VL + AVX512BW + + Concatenate xmm2 and xmm3/m128 into a 32-byte intermediate result, extract byte aligned result shifted to the right by constant value in imm8 and result is stored in xmm1. + + + VPALIGNR + ymm1 {k1}{z},ymm2,ymm3/m256,imm8 + EVEX.NDS.256.66.0F3A.WIG 0F /r ib + + AVX512VL + AVX512BW + + Concatenate pairs of 16 bytes in ymm2 and ymm3/m256 into 32-byte intermediate result, extract byte-aligned, 16-byte result shifted to the right by constant values in imm8 from each intermediate result, and two 16-byte results are stored in ymm1. + + + VPALIGNR + zmm1 {k1}{z},zmm2,zmm3/m512,imm8 + EVEX.NDS.512.66.0F3A.WIG 0F /r ib + + AVX512BW + + Concatenate pairs of 16 bytes in zmm2 and zmm3/m512 into 32-byte intermediate result, extract byte-aligned, 16-byte result shifted to the right by constant values in imm8 from each intermediate result, and four 16-byte results are stored in zmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PAND--Logical AND. + + PAND + xmm1,xmm2/m128 + 66 0F DB /r + + SSE2 + + Bitwise AND of xmm2/m128 and xmm1. + + + VPAND + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG DB /r + + AVX + + Bitwise AND of xmm2, and xmm3/m128 and store result in xmm1. + + + VPAND + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG DB /r + + AVX2 + + Bitwise AND of ymm2, and ymm3/m256 and store result in ymm1. + + + VPANDD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 DB /r + + AVX512VL + AVX512F + + Bitwise AND of packed doubleword integers in xmm2 and xmm3/m128/m32bcst and store result in xmm1 using writemask k1. + + + VPANDD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 DB /r + + AVX512VL + AVX512F + + Bitwise AND of packed doubleword integers in ymm2 and ymm3/m256/m32bcst and store result in ymm1 using writemask k1. + + + VPANDD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 DB /r + + AVX512F + + Bitwise AND of packed doubleword integers in zmm2 and zmm3/m512/m32bcst and store result in zmm1 using writemask k1. + + + VPANDQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 DB /r + + AVX512VL + AVX512F + + Bitwise AND of packed quadword integers in xmm2 and xmm3/m128/m64bcst and store result in xmm1 using writemask k1. + + + VPANDQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 DB /r + + AVX512VL + AVX512F + + Bitwise AND of packed quadword integers in ymm2 and ymm3/m256/m64bcst and store result in ymm1 using writemask k1. + + + VPANDQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 DB /r + + AVX512F + + Bitwise AND of packed quadword integers in zmm2 and zmm3/m512/m64bcst and store result in zmm1 using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PANDN--Logical AND NOT. + + PANDN + xmm1,xmm2/m128 + 66 0F DF /r + + SSE2 + + Bitwise AND NOT of xmm2/m128 and xmm1. + + + VPANDN + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG DF /r + + AVX + + Bitwise AND NOT of xmm2, and xmm3/m128 and store result in xmm1. + + + VPANDN + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG DF /r + + AVX2 + + Bitwise AND NOT of ymm2, and ymm3/m256 and store result in ymm1. + + + VPANDND + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 DF /r + + AVX512VL + AVX512F + + Bitwise AND NOT of packed doubleword integers in xmm2 and xmm3/m128/m32bcst and store result in xmm1 using writemask k1. + + + VPANDND + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 DF /r + + AVX512VL + AVX512F + + Bitwise AND NOT of packed doubleword integers in ymm2 and ymm3/m256/m32bcst and store result in ymm1 using writemask k1. + + + VPANDND + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 DF /r + + AVX512F + + Bitwise AND NOT of packed doubleword integers in zmm2 and zmm3/m512/m32bcst and store result in zmm1 using writemask k1. + + + VPANDNQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 DF /r + + AVX512VL + AVX512F + + Bitwise AND NOT of packed quadword integers in xmm2 and xmm3/m128/m64bcst and store result in xmm1 using writemask k1. + + + VPANDNQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 DF /r + + AVX512VL + AVX512F + + Bitwise AND NOT of packed quadword integers in ymm2 and ymm3/m256/m64bcst and store result in ymm1 using writemask k1. + + + VPANDNQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 DF /r + + AVX512F + + Bitwise AND NOT of packed quadword integers in zmm2 and zmm3/m512/m64bcst and store result in zmm1 using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PAVGB/PAVGW--Average Packed Integers. + + PAVGB + xmm1,xmm2/m128 + 66 0F E0,/r + + SSE2 + + Average packed unsigned byte integers from xmm2/m128 and xmm1 with rounding. + + + PAVGW + xmm1,xmm2/m128 + 66 0F E3,/r + + SSE2 + + Average packed unsigned word integers from xmm2/m128 and xmm1 with rounding. + + + VPAVGB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F E0 + + AVX + + Average packed unsigned byte integers from xmm2, and xmm3/m128 with rounding and store to xmm1. + + + VPAVGW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F E3 + + AVX + + Average packed unsigned word integers from xmm2, xmm3/m128 with rounding to xmm1. + + + VPAVGB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F E0 + + AVX2 + + Average packed unsigned byte integers from ymm2, and ymm3/m256 with rounding and store to ymm1. + + + VPAVGW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F E3 + + AVX2 + + Average packed unsigned word integers from ymm2, ymm3/m256 with rounding to ymm1. + + + VPAVGB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG E0 /r + + AVX512VL + AVX512BW + + Average packed unsigned byte integers from xmm2, and xmm3/m128 with rounding and store to xmm1 under writemask k1. + + + VPAVGB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG E0 /r + + AVX512VL + AVX512BW + + Average packed unsigned byte integers from ymm2, and ymm3/m256 with rounding and store to ymm1 under writemask k1. + + + VPAVGB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG E0 /r + + AVX512BW + + Average packed unsigned byte integers from zmm2, and zmm3/m512 with rounding and store to zmm1 under writemask k1. + + + VPAVGW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG E3 /r + + AVX512VL + AVX512BW + + Average packed unsigned word integers from xmm2, xmm3/m128 with rounding to xmm1 under writemask k1. + + + VPAVGW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG E3 /r + + AVX512VL + AVX512BW + + Average packed unsigned word integers from ymm2, ymm3/m256 with rounding to ymm1 under writemask k1. + + + VPAVGW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG E3 /r + + AVX512BW + + Average packed unsigned word integers from zmm2, zmm3/m512 with rounding to zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPBROADCASTM--Broadcast Mask to Vector Register. + + VPBROADCASTMB2Q + xmm1,k1 + EVEX.128.F3.0F38.W1 2A /r + + AVX512VL + AVX512CD + + Broadcast low byte value in k1 to two locations in xmm1. + + + VPBROADCASTMB2Q + ymm1,k1 + EVEX.256.F3.0F38.W1 2A /r + + AVX512VL + AVX512CD + + Broadcast low byte value in k1 to four locations in ymm1. + + + VPBROADCASTMB2Q + zmm1,k1 + EVEX.512.F3.0F38.W1 2A /r + + AVX512CD + + Broadcast low byte value in k1 to eight locations in zmm1. + + + VPBROADCASTMW2D + xmm1,k1 + EVEX.128.F3.0F38.W0 3A /r + + AVX512VL + AVX512CD + + Broadcast low word value in k1 to four locations in xmm1. + + + VPBROADCASTMW2D + ymm1,k1 + EVEX.256.F3.0F38.W0 3A /r + + AVX512VL + AVX512CD + + Broadcast low word value in k1 to eight locations in ymm1. + + + VPBROADCASTMW2D + zmm1,k1 + EVEX.512.F3.0F38.W0 3A /r + + AVX512CD + + Broadcast low word value in k1 to sixteen locations in zmm1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + PCMPEQB/PCMPEQW/PCMPEQD/PCMPEQQ--Compare Packed Integers for Equality. + + PCMPEQB + xmm1,xmm2/m128 + 66 0F 74 /r + + SSE2 + + Compare packed bytes in xmm2/m128 and xmm1 for equality. + + + PCMPEQW + xmm1,xmm2/m128 + 66 0F 75 /r + + SSE2 + + Compare packed words in xmm2/m128 and xmm1 for equality. + + + PCMPEQD + xmm1,xmm2/m128 + 66 0F 76 /r + + SSE2 + + Compare packed doublewords in xmm2/m128 and xmm1 for equality. + + + PCMPEQQ + xmm1,xmm2/m128 + 66 0F 38 29 /r + + SSE4_1 + + Compare packed quadwords in xmm2/m128 and xmm1 for equality. + + + VPCMPEQB + xmm1,xmm2,xmm3 /m128 + VEX.NDS.128.66.0F.WIG 74 /r + + AVX + + Compare packed bytes in xmm3/m128 and xmm2 for equality. + + + VPCMPEQW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 75 /r + + AVX + + Compare packed words in xmm3/m128 and xmm2 for equality. + + + VPCMPEQD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 76 /r + + AVX + + Compare packed doublewords in xmm3/m128 and xmm2 for equality. + + + VPCMPEQQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 29 /r + + AVX + + Compare packed quadwords in xmm3/m128 and xmm2 for equality. + + + VPCMPEQB + ymm1,ymm2,ymm3 /m256 + VEX.NDS.256.66.0F.WIG 74 /r + + AVX2 + + Compare packed bytes in ymm3/m256 and ymm2 for equality. + + + VPCMPEQW + ymm1,ymm2,ymm3 /m256 + VEX.NDS.256.66.0F.WIG 75 /r + + AVX2 + + Compare packed words in ymm3/m256 and ymm2 for equality. + + + VPCMPEQD + ymm1,ymm2,ymm3 /m256 + VEX.NDS.256.66.0F.WIG 76 /r + + AVX2 + + Compare packed doublewords in ymm3/m256 and ymm2 for equality. + + + VPCMPEQQ + ymm1,ymm2,ymm3 /m256 + VEX.NDS.256.66.0F38.WIG 29 /r + + AVX2 + + Compare packed quadwords in ymm3/m256 and ymm2 for equality. + + + VPCMPEQD + k1 {k2},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 76 /r + + AVX512VL + AVX512F + + Compare Equal between int32 vector xmm2 and int32 vector xmm3/m128/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQD + k1 {k2},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 76 /r + + AVX512VL + AVX512F + + Compare Equal between int32 vector ymm2 and int32 vector ymm3/m256/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQD + k1 {k2},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 76 /r + + AVX512F + + Compare Equal between int32 vectors in zmm2 and zmm3/m512/m32bcst, and set destination k1 according to the comparison results under writemask k2,. + + + VPCMPEQQ + k1 {k2},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 29 /r + + AVX512VL + AVX512F + + Compare Equal between int64 vector xmm2 and int64 vector xmm3/m128/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQQ + k1 {k2},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 29 /r + + AVX512VL + AVX512F + + Compare Equal between int64 vector ymm2 and int64 vector ymm3/m256/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQQ + k1 {k2},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 29 /r + + AVX512F + + Compare Equal between int64 vector zmm2 and int64 vector zmm3/m512/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQB + k1 {k2},xmm2,xmm3 /m128 + EVEX.NDS.128.66.0F.WIG 74 /r + + AVX512VL + AVX512BW + + Compare packed bytes in xmm3/m128 and xmm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQB + k1 {k2},ymm2,ymm3 /m256 + EVEX.NDS.256.66.0F.WIG 74 /r + + AVX512VL + AVX512BW + + Compare packed bytes in ymm3/m256 and ymm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQB + k1 {k2},zmm2,zmm3 /m512 + EVEX.NDS.512.66.0F.WIG 74 /r + + AVX512BW + + Compare packed bytes in zmm3/m512 and zmm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQW + k1 {k2},xmm2,xmm3 /m128 + EVEX.NDS.128.66.0F.WIG 75 /r + + AVX512VL + AVX512BW + + Compare packed words in xmm3/m128 and xmm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQW + k1 {k2},ymm2,ymm3 /m256 + EVEX.NDS.256.66.0F.WIG 75 /r + + AVX512VL + AVX512BW + + Compare packed words in ymm3/m256 and ymm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPEQW + k1 {k2},zmm2,zmm3 /m512 + EVEX.NDS.512.66.0F.WIG 75 /r + + AVX512BW + + Compare packed words in zmm3/m512 and zmm2 for equality and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PCMPGTB/PCMPGTW/PCMPGTD/PCMPGTQ--Compare Packed Integers for Greater Than. + + PCMPGTB + xmm1,xmm2/m128 + 66 0F 64 /r + + SSE2 + + Compare packed signed byte integers in xmm1 and xmm2/m128 for greater than. + + + PCMPGTW + xmm1,xmm2/m128 + 66 0F 65 /r + + SSE2 + + Compare packed signed word integers in xmm1 and xmm2/m128 for greater than. + + + PCMPGTD + xmm1,xmm2/m128 + 66 0F 66 /r + + SSE2 + + Compare packed signed doubleword integers in xmm1 and xmm2/m128 for greater than. + + + PCMPGTQ + xmm1,xmm2/m128 + 66 0F 38 37 /r + + SSE4_2 + + Compare packed qwords in xmm2/m128 and xmm1 for greater than. + + + VPCMPGTB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 64 /r + + AVX + + Compare packed signed byte integers in xmm2 and xmm3/m128 for greater than. + + + VPCMPGTW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 65 /r + + AVX + + Compare packed signed word integers in xmm2 and xmm3/m128 for greater than. + + + VPCMPGTD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 66 /r + + AVX + + Compare packed signed doubleword integers in xmm2 and xmm3/m128 for greater than. + + + VPCMPGTQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 37 /r + + AVX + + Compare packed signed qwords in xmm2 and xmm3/m128 for greater than. + + + VPCMPGTB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 64 /r + + AVX2 + + Compare packed signed byte integers in ymm2 and ymm3/m256 for greater than. + + + VPCMPGTW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 65 /r + + AVX2 + + Compare packed signed word integers in ymm2 and ymm3/m256 for greater than. + + + VPCMPGTD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 66 /r + + AVX2 + + Compare packed signed doubleword integers in ymm2 and ymm3/m256 for greater than. + + + VPCMPGTQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.WIG 37 /r + + AVX2 + + Compare packed signed qwords in ymm2 and ymm3/m256 for greater than. + + + VPCMPGTD + k1 {k2},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 66 /r + + AVX512VL + AVX512F + + Compare Greater between int32 vector xmm2 and int32 vector xmm3/m128/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTD + k1 {k2},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 66 /r + + AVX512VL + AVX512F + + Compare Greater between int32 vector ymm2 and int32 vector ymm3/m256/m32bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTD + k1 {k2},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 66 /r + + AVX512F + + Compare Greater between int32 elements in zmm2 and zmm3/m512/m32bcst, and set destination k1 according to the comparison results under writemask. k2. + + + VPCMPGTQ + k1 {k2},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 37 /r + + AVX512VL + AVX512F + + Compare Greater between int64 vector xmm2 and int64 vector xmm3/m128/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTQ + k1 {k2},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 37 /r + + AVX512VL + AVX512F + + Compare Greater between int64 vector ymm2 and int64 vector ymm3/m256/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTQ + k1 {k2},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 37 /r + + AVX512F + + Compare Greater between int64 vector zmm2 and int64 vector zmm3/m512/m64bcst, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTB + k1 {k2},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG 64 /r + + AVX512VL + AVX512BW + + Compare packed signed byte integers in xmm2 and xmm3/m128 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTB + k1 {k2},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG 64 /r + + AVX512VL + AVX512BW + + Compare packed signed byte integers in ymm2 and ymm3/m256 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTB + k1 {k2},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG 64 /r + + AVX512BW + + Compare packed signed byte integers in zmm2 and zmm3/m512 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTW + k1 {k2},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG 65 /r + + AVX512VL + AVX512BW + + Compare packed signed word integers in xmm2 and xmm3/m128 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTW + k1 {k2},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG 65 /r + + AVX512VL + AVX512BW + + Compare packed signed word integers in ymm2 and ymm3/m256 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + VPCMPGTW + k1 {k2},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG 65 /r + + AVX512BW + + Compare packed signed word integers in zmm2 and zmm3/m512 for greater than, and set vector mask k1 to reflect the zero/nonzero status of each element of the result, under writemask. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPCMPB/VPCMPUB--Compare Packed Byte Values Into Mask. + + VPCMPB + k1 {k2},xmm2,xmm3/m128,imm8 + EVEX.NDS.128.66.0F3A.W0 3F /r ib + + AVX512VL + AVX512BW + + Compare packed signed byte values in xmm3/m128 and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPB + k1 {k2},ymm2,ymm3/m256,imm8 + EVEX.NDS.256.66.0F3A.W0 3F /r ib + + AVX512VL + AVX512BW + + Compare packed signed byte values in ymm3/m256 and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPB + k1 {k2},zmm2,zmm3/m512,imm8 + EVEX.NDS.512.66.0F3A.W0 3F /r ib + + AVX512BW + + Compare packed signed byte values in zmm3/m512 and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUB + k1 {k2},xmm2,xmm3/m128,imm8 + EVEX.NDS.128.66.0F3A.W0 3E /r ib + + AVX512VL + AVX512BW + + Compare packed unsigned byte values in xmm3/m128 and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUB + k1 {k2},ymm2,ymm3/m256,imm8 + EVEX.NDS.256.66.0F3A.W0 3E /r ib + + AVX512VL + AVX512BW + + Compare packed unsigned byte values in ymm3/m256 and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUB + k1 {k2},zmm2,zmm3/m512,imm8 + EVEX.NDS.512.66.0F3A.W0 3E /r ib + + AVX512BW + + Compare packed unsigned byte values in zmm3/m512 and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + ModRM:reg(w) + vvvv(r) + ModRM:r/m(r) + NA + + + + VPCMPD/VPCMPUD--Compare Packed Integer Values into Mask. + + VPCMPD + k1 {k2},xmm2,xmm3/m128/m32bcst,imm8 + EVEX.NDS.128.66.0F3A.W0 1F /r ib + + AVX512VL + AVX512F + + Compare packed signed doubleword integer values in xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPD + k1 {k2},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.66.0F3A.W0 1F /r ib + + AVX512VL + AVX512F + + Compare packed signed doubleword integer values in ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPD + k1 {k2},zmm2,zmm3/m512/m32bcst,imm8 + EVEX.NDS.512.66.0F3A.W0 1F /r ib + + AVX512F + + Compare packed signed doubleword integer values in zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8 as a comparison predicate. The comparison results are written to the destination k1 under writemask k2. + + + VPCMPUD + k1 {k2},xmm2,xmm3/m128/m32bcst,imm8 + EVEX.NDS.128.66.0F3A.W0 1E /r ib + + AVX512VL + AVX512F + + Compare packed unsigned doubleword integer values in xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUD + k1 {k2},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.66.0F3A.W0 1E /r ib + + AVX512VL + AVX512F + + Compare packed unsigned doubleword integer values in ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUD + k1 {k2},zmm2,zmm3/m512/m32bcst,imm8 + EVEX.NDS.512.66.0F3A.W0 1E /r ib + + AVX512F + + Compare packed unsigned doubleword integer values in zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8 as a comparison predicate. The comparison results are written to the destination k1 under writemask k2. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + VPCMPQ/VPCMPUQ--Compare Packed Integer Values into Mask. + + VPCMPQ + k1 {k2},xmm2,xmm3/m128/m64bcst,imm8 + EVEX.NDS.128.66.0F3A.W1 1F /r ib + + AVX512VL + AVX512F + + Compare packed signed quadword integer values in xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPQ + k1 {k2},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F3A.W1 1F /r ib + + AVX512VL + AVX512F + + Compare packed signed quadword integer values in ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPQ + k1 {k2},zmm2,zmm3/m512/m64bcst,imm8 + EVEX.NDS.512.66.0F3A.W1 1F /r ib + + AVX512F + + Compare packed signed quadword integer values in zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUQ + k1 {k2},xmm2,xmm3/m128/m64bcst,imm8 + EVEX.NDS.128.66.0F3A.W1 1E /r ib + + AVX512VL + AVX512F + + Compare packed unsigned quadword integer values in xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUQ + k1 {k2},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F3A.W1 1E /r ib + + AVX512VL + AVX512F + + Compare packed unsigned quadword integer values in ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUQ + k1 {k2},zmm2,zmm3/m512/m64bcst,imm8 + EVEX.NDS.512.66.0F3A.W1 1E /r ib + + AVX512F + + Compare packed unsigned quadword integer values in zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + VPCMPW/VPCMPUW--Compare Packed Word Values Into Mask. + + VPCMPW + k1 {k2},xmm2,xmm3/m128,imm8 + EVEX.NDS.128.66.0F3A.W1 3F /r ib + + AVX512VL + AVX512BW + + Compare packed signed word integers in xmm3/m128 and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPW + k1 {k2},ymm2,ymm3/m256,imm8 + EVEX.NDS.256.66.0F3A.W1 3F /r ib + + AVX512VL + AVX512BW + + Compare packed signed word integers in ymm3/m256 and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPW + k1 {k2},zmm2,zmm3/m512,imm8 + EVEX.NDS.512.66.0F3A.W1 3F /r ib + + AVX512BW + + Compare packed signed word integers in zmm3/m512 and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUW + k1 {k2},xmm2,xmm3/m128,imm8 + EVEX.NDS.128.66.0F3A.W1 3E /r ib + + AVX512VL + AVX512BW + + Compare packed unsigned word integers in xmm3/m128 and xmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUW + k1 {k2},ymm2,ymm3/m256,imm8 + EVEX.NDS.256.66.0F3A.W1 3E /r ib + + AVX512VL + AVX512BW + + Compare packed unsigned word integers in ymm3/m256 and ymm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + VPCMPUW + k1 {k2},zmm2,zmm3/m512,imm8 + EVEX.NDS.512.66.0F3A.W1 3E /r ib + + AVX512BW + + Compare packed unsigned word integers in zmm3/m512 and zmm2 using bits 2:0 of imm8 as a comparison predicate with writemask k2 and leave the result in mask register k1. + + + ModRM:reg(w) + vvvv(r) + ModRM:r/m(r) + NA + + + + VPCOMPRESSD--Store Sparse Packed Doubleword Integer Values into Dense Memory/Register. + + VPCOMPRESSD + xmm1/m128 {k1}{z},xmm2 + EVEX.128.66.0F38.W0 8B /r + + AVX512VL + AVX512F + + Compress packed doubleword integer values from xmm2 to xmm1/m128 using controlmask k1. + + + VPCOMPRESSD + ymm1/m256 {k1}{z},ymm2 + EVEX.256.66.0F38.W0 8B /r + + AVX512VL + AVX512F + + Compress packed doubleword integer values from ymm2 to ymm1/m256 using controlmask k1. + + + VPCOMPRESSD + zmm1/m512 {k1}{z},zmm2 + EVEX.512.66.0F38.W0 8B /r + + AVX512F + + Compress packed doubleword integer values from zmm2 to zmm1/m512 using controlmask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + VPCOMPRESSQ--Store Sparse Packed Quadword Integer Values into Dense Memory/Register. + + VPCOMPRESSQ + xmm1/m128 {k1}{z},xmm2 + EVEX.128.66.0F38.W1 8B /r + + AVX512VL + AVX512F + + Compress packed quadword integer values from xmm2 to xmm1/m128 using controlmask k1. + + + VPCOMPRESSQ + ymm1/m256 {k1}{z},ymm2 + EVEX.256.66.0F38.W1 8B /r + + AVX512VL + AVX512F + + Compress packed quadword integer values from ymm2 to ymm1/m256 using controlmask k1. + + + VPCOMPRESSQ + zmm1/m512 {k1}{z},zmm2 + EVEX.512.66.0F38.W1 8B /r + + AVX512F + + Compress packed quadword integer values from zmm2 to zmm1/m512 using controlmask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + VPCONFLICTD/Q--Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register. + + VPCONFLICTD + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.66.0F38.W0 C4 /r + + AVX512VL + AVX512CD + + Detect duplicate double-word values in xmm2/m128/m32bcst using writemask k1. + + + VPCONFLICTD + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.66.0F38.W0 C4 /r + + AVX512VL + AVX512CD + + Detect duplicate double-word values in ymm2/m256/m32bcst using writemask k1. + + + VPCONFLICTD + zmm1 {k1}{z},zmm2/m512/m32bcst + EVEX.512.66.0F38.W0 C4 /r + + AVX512CD + + Detect duplicate double-word values in zmm2/m512/m32bcst using writemask k1. + + + VPCONFLICTQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F38.W1 C4 /r + + AVX512VL + AVX512CD + + Detect duplicate quad-word values in xmm2/m128/m64bcst using writemask k1. + + + VPCONFLICTQ + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F38.W1 C4 /r + + AVX512VL + AVX512CD + + Detect duplicate quad-word values in ymm2/m256/m64bcst using writemask k1. + + + VPCONFLICTQ + zmm1 {k1}{z},zmm2/m512/m64bcst + EVEX.512.66.0F38.W1 C4 /r + + AVX512CD + + Detect duplicate quad-word values in zmm2/m512/m64bcst using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VPERMB--Permute Packed Bytes Elements. + + VPERMB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W0 8D /r + + AVX512VL + AVX512VBMI + + Permute bytes in xmm3/m128 using byte indexes in xmm2 and store the result in xmm1 using writemask k1. + + + VPERMB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W0 8D /r + + AVX512VL + AVX512VBMI + + Permute bytes in ymm3/m256 using byte indexes in ymm2 and store the result in ymm1 using writemask k1. + + + VPERMB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W0 8D /r + + AVX512VBMI + + Permute bytes in zmm3/m512 using byte indexes in zmm2 and store the result in zmm1 using writemask k1. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VPERMD/VPERMW--Permute Packed Doublewords/Words Elements. + + VPERMD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 36 /r + + AVX2 + + Permute doublewords in ymm3/m256 using indices in ymm2 and store the result in ymm1. + + + VPERMD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 36 /r + + AVX512VL + AVX512F + + Permute doublewords in ymm3/m256/m32bcst using indexes in ymm2 and store the result in ymm1 using writemask k1. + + + VPERMD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 36 /r + + AVX512F + + Permute doublewords in zmm3/m512/m32bcst using indices in zmm2 and store the result in zmm1 using writemask k1. + + + VPERMW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W1 8D /r + + AVX512VL + AVX512BW + + Permute word integers in xmm3/m128 using indexes in xmm2 and store the result in xmm1 using writemask k1. + + + VPERMW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W1 8D /r + + AVX512VL + AVX512BW + + Permute word integers in ymm3/m256 using indexes in ymm2 and store the result in ymm1 using writemask k1. + + + VPERMW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W1 8D /r + + AVX512BW + + Permute word integers in zmm3/m512 using indexes in zmm2 and store the result in zmm1 using writemask k1. + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + + VPERMI2B--Full Permute of Bytes From Two Tables Overwriting the Index. + + VPERMI2B + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.DDS.128.66.0F38.W0 75 /r + + AVX512VL + AVX512VBMI + + Permute bytes in xmm3/m128 and xmm2 using byte indexes in xmm1 and store the byte results in xmm1 using writemask k1. + + + VPERMI2B + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.DDS.256.66.0F38.W0 75 /r + + AVX512VL + AVX512VBMI + + Permute bytes in ymm3/m256 and ymm2 using byte indexes in ymm1 and store the byte results in ymm1 using writemask k1. + + + VPERMI2B + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.DDS.512.66.0F38.W0 75 /r + + AVX512VBMI + + Permute bytes in zmm3/m512 and zmm2 using byte indexes in zmm1 and store the byte results in zmm1 using writemask k1. + + + ModRM:reg(r,w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VPERMI2W/D/Q/PS/PD--Full Permute From Two Tables Overwriting the Index. + + VPERMI2W + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.DDS.128.66.0F38.W1 75 /r + + AVX512VL + AVX512BW + + Permute word integers from two tables in xmm3/m128 and xmm2 using indexes in xmm1 and store the result in xmm1 using writemask k1. + + + VPERMI2W + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.DDS.256.66.0F38.W1 75 /r + + AVX512VL + AVX512BW + + Permute word integers from two tables in ymm3/m256 and ymm2 using indexes in ymm1 and store the result in ymm1 using writemask k1. + + + VPERMI2W + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.DDS.512.66.0F38.W1 75 /r + + AVX512BW + + Permute word integers from two tables in zmm3/m512 and zmm2 using indexes in zmm1 and store the result in zmm1 using writemask k1. + + + VPERMI2D + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 76 /r + + AVX512VL + AVX512F + + Permute double-words from two tables in xmm3/m128/m32bcst and xmm2 using indexes in xmm1 and store the result in xmm1 using writemask k1. + + + VPERMI2D + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 76 /r + + AVX512VL + AVX512F + + Permute double-words from two tables in ymm3/m256/m32bcst and ymm2 using indexes in ymm1 and store the result in ymm1 using writemask k1. + + + VPERMI2D + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.DDS.512.66.0F38.W0 76 /r + + AVX512F + + Permute double-words from two tables in zmm3/m512/m32bcst and zmm2 using indices in zmm1 and store the result in zmm1 using writemask k1. + + + VPERMI2Q + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 76 /r + + AVX512VL + AVX512F + + Permute quad-words from two tables in xmm3/m128/m64bcst and xmm2 using indexes in xmm1 and store the result in xmm1 using writemask k1. + + + VPERMI2Q + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 76 /r + + AVX512VL + AVX512F + + Permute quad-words from two tables in ymm3/m256/m64bcst and ymm2 using indexes in ymm1 and store the result in ymm1 using writemask k1. + + + VPERMI2Q + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.DDS.512.66.0F38.W1 76 /r + + AVX512F + + Permute quad-words from two tables in zmm3/m512/m64bcst and zmm2 using indices in zmm1 and store the result in zmm1 using writemask k1. + + + VPERMI2PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 77 /r + + AVX512VL + AVX512F + + Permute single-precision FP values from two tables in xmm3/m128/m32bcst and xmm2 using indexes in xmm1 and store the result in xmm1 using writemask k1. + + + VPERMI2PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 77 /r + + AVX512VL + AVX512F + + Permute single-precision FP values from two tables in ymm3/m256/m32bcst and ymm2 using indexes in ymm1 and store the result in ymm1 using writemask k1. + + + VPERMI2PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.DDS.512.66.0F38.W0 77 /r + + AVX512F + + Permute single-precision FP values from two tables in zmm3/m512/m32bcst and zmm2 using indices in zmm1 and store the result in zmm1 using writemask k1. + + + VPERMI2PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 77 /r + + AVX512VL + AVX512F + + Permute double-precision FP values from two tables in xmm3/m128/m64bcst and xmm2 using indexes in xmm1 and store the result in xmm1 using writemask k1. + + + VPERMI2PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 77 /r + + AVX512VL + AVX512F + + Permute double-precision FP values from two tables in ymm3/m256/m64bcst and ymm2 using indexes in ymm1 and store the result in ymm1 using writemask k1. + + + VPERMI2PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.DDS.512.66.0F38.W1 77 /r + + AVX512F + + Permute double-precision FP values from two tables in zmm3/m512/m64bcst and zmm2 using indices in zmm1 and store the result in zmm1 using writemask k1. + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPERMT2B--Full Permute of Bytes From Two Tables Overwriting a Table. + + VPERMT2B + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.DDS.128.66.0F38.W0 7D /r + + AVX512VL + AVX512VBMI + + Permute bytes in xmm3/m128 and xmm1 using byte indexes in xmm2 and store the byte results in xmm1 using writemask k1. + + + VPERMT2B + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W0 7D /r + + AVX512VL + AVX512VBMI + + Permute bytes in ymm3/m256 and ymm1 using byte indexes in ymm2 and store the byte results in ymm1 using writemask k1. + + + VPERMT2B + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W0 7D /r + + AVX512VBMI + + Permute bytes in zmm3/m512 and zmm1 using byte indexes in zmm2 and store the byte results in zmm1 using writemask k1. + + + ModRM:reg(r,w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VPERMT2W/D/Q/PS/PD--Full Permute from Two Tables Overwriting one Table. + + VPERMT2W + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.DDS.128.66.0F38.W1 7D /r + + AVX512VL + AVX512BW + + Permute word integers from two tables in xmm3/m128 and xmm1 using indexes in xmm2 and store the result in xmm1 using writemask k1. + + + VPERMT2W + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.DDS.256.66.0F38.W1 7D /r + + AVX512VL + AVX512BW + + Permute word integers from two tables in ymm3/m256 and ymm1 using indexes in ymm2 and store the result in ymm1 using writemask k1. + + + VPERMT2W + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.DDS.512.66.0F38.W1 7D /r + + AVX512BW + + Permute word integers from two tables in zmm3/m512 and zmm1 using indexes in zmm2 and store the result in zmm1 using writemask k1. + + + VPERMT2D + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 7E /r + + AVX512VL + AVX512F + + Permute double-words from two tables in xmm3/m128/m32bcst and xmm1 using indexes in xmm2 and store the result in xmm1 using writemask k1. + + + VPERMT2D + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 7E /r + + AVX512VL + AVX512F + + Permute double-words from two tables in ymm3/m256/m32bcst and ymm1 using indexes in ymm2 and store the result in ymm1 using writemask k1. + + + VPERMT2D + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.DDS.512.66.0F38.W0 7E /r + + AVX512F + + Permute double-words from two tables in zmm3/m512/m32bcst and zmm1 using indices in zmm2 and store the result in zmm1 using writemask k1. + + + VPERMT2Q + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 7E /r + + AVX512VL + AVX512F + + Permute quad-words from two tables in xmm3/m128/m64bcst and xmm1 using indexes in xmm2 and store the result in xmm1 using writemask k1. + + + VPERMT2Q + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 7E /r + + AVX512VL + AVX512F + + Permute quad-words from two tables in ymm3/m256/m64bcst and ymm1 using indexes in ymm2 and store the result in ymm1 using writemask k1. + + + VPERMT2Q + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.DDS.512.66.0F38.W1 7E /r + + AVX512F + + Permute quad-words from two tables in zmm3/m512/m64bcst and zmm1 using indices in zmm2 and store the result in zmm1 using writemask k1. + + + VPERMT2PS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.DDS.128.66.0F38.W0 7F /r + + AVX512VL + AVX512F + + Permute single-precision FP values from two tables in xmm3/m128/m32bcst and xmm1 using indexes in xmm2 and store the result in xmm1 using writemask k1. + + + VPERMT2PS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.DDS.256.66.0F38.W0 7F /r + + AVX512VL + AVX512F + + Permute single-precision FP values from two tables in ymm3/m256/m32bcst and ymm1 using indexes in ymm2 and store the result in ymm1 using writemask k1. + + + VPERMT2PS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.DDS.512.66.0F38.W0 7F /r + + AVX512F + + Permute single-precision FP values from two tables in zmm3/m512/m32bcst and zmm1 using indices in zmm2 and store the result in zmm1 using writemask k1. + + + VPERMT2PD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 7F /r + + AVX512VL + AVX512F + + Permute double-precision FP values from two tables in xmm3/m128/m64bcst and xmm1 using indexes in xmm2 and store the result in xmm1 using writemask k1. + + + VPERMT2PD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 7F /r + + AVX512VL + AVX512F + + Permute double-precision FP values from two tables in ymm3/m256/m64bcst and ymm1 using indexes in ymm2 and store the result in ymm1 using writemask k1. + + + VPERMT2PD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.DDS.512.66.0F38.W1 7F /r + + AVX512F + + Permute double-precision FP values from two tables in zmm3/m512/m64bcst and zmm1 using indices in zmm2 and store the result in zmm1 using writemask k1. + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPERMILPD--Permute In-Lane of Pairs of Double-Precision Floating-Point Values. + + VPERMILPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 0D /r + + AVX + + Permute double-precision floating-point values in xmm2 using controls from xmm3/m128 and store result in xmm1. + + + VPERMILPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 0D /r + + AVX + + Permute double-precision floating-point values in ymm2 using controls from ymm3/m256 and store result in ymm1. + + + VPERMILPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 0D /r + + AVX512VL + AVX512F + + Permute double-precision floating-point values in xmm2 using control from xmm3/m128/m64bcst and store the result in xmm1 using writemask k1. + + + VPERMILPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 0D /r + + AVX512VL + AVX512F + + Permute double-precision floating-point values in ymm2 using control from ymm3/m256/m64bcst and store the result in ymm1 using writemask k1. + + + VPERMILPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 0D /r + + AVX512F + + Permute double-precision floating-point values in zmm2 using control from zmm3/m512/m64bcst and store the result in zmm1 using writemask k1. + + + VPERMILPD + xmm1,xmm2/m128,imm8 + VEX.128.66.0F3A.W0 05 /r ib + + AVX + + Permute double-precision floating-point values in xmm2/m128 using controls from imm8. + + + VPERMILPD + ymm1,ymm2/m256,imm8 + VEX.256.66.0F3A.W0 05 /r ib + + AVX + + Permute double-precision floating-point values in ymm2/m256 using controls from imm8. + + + VPERMILPD + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.128.66.0F3A.W1 05 /r ib + + AVX512VL + AVX512F + + Permute double-precision floating-point values in xmm2/m128/m64bcst using controls from imm8 and store the result in xmm1 using writemask k1. + + + VPERMILPD + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.256.66.0F3A.W1 05 /r ib + + AVX512VL + AVX512F + + Permute double-precision floating-point values in ymm2/m256/m64bcst using controls from imm8 and store the result in ymm1 using writemask k1. + + + VPERMILPD + zmm1 {k1}{z},zmm2/m512/m64bcst,imm8 + EVEX.512.66.0F3A.W1 05 /r ib + + AVX512F + + Permute double-precision floating-point values in zmm2/m512/m64bcst using controls from imm8 and store the result in zmm1 using writemask k1. + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VPERMILPS--Permute In-Lane of Quadruples of Single-Precision Floating-Point Values. + + VPERMILPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 0C /r + + AVX + + Permute single-precision floating-point values in xmm2 using controls from xmm3/m128 and store result in xmm1. + + + VPERMILPS + xmm1,xmm2/m128,imm8 + VEX.128.66.0F3A.W0 04 /r ib + + AVX + + Permute single-precision floating-point values in xmm2/m128 using controls from imm8 and store result in xmm1. + + + VPERMILPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 0C /r + + AVX + + Permute single-precision floating-point values in ymm2 using controls from ymm3/m256 and store result in ymm1. + + + VPERMILPS + ymm1,ymm2/m256,imm8 + VEX.256.66.0F3A.W0 04 /r ib + + AVX + + Permute single-precision floating-point values in ymm2/m256 using controls from imm8 and store result in ymm1. + + + VPERMILPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 0C /r + + AVX512VL + AVX512F + + Permute single-precision floating-point values xmm2 using control from xmm3/m128/m32bcst and store the result in xmm1 using writemask k1. + + + VPERMILPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 0C /r + + AVX512VL + AVX512F + + Permute single-precision floating-point values ymm2 using control from ymm3/m256/m32bcst and store the result in ymm1 using writemask k1. + + + VPERMILPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 0C /r + + AVX512F + + Permute single-precision floating-point values zmm2 using control from zmm3/m512/m32bcst and store the result in zmm1 using writemask k1. + + + VPERMILPS + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.128.66.0F3A.W0 04 /r ib + + AVX512VL + AVX512F + + Permute single-precision floating-point values xmm2/m128/m32bcst using controls from imm8 and store the result in xmm1 using writemask k1. + + + VPERMILPS + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.256.66.0F3A.W0 04 /r ib + + AVX512VL + AVX512F + + Permute single-precision floating-point values ymm2/m256/m32bcst using controls from imm8 and store the result in ymm1 using writemask k1. + + + VPERMILPS + zmm1 {k1}{z},zmm2/m512/m32bcst,imm8 + EVEX.512.66.0F3A.W0 04 /r ib + + AVX512F + + Permute single-precision floating-point values zmm2/m512/m32bcst using controls from imm8 and store the result in zmm1 using writemask k1. + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VPERMPD--Permute Double-Precision Floating-Point Elements. + + VPERMPD + ymm1,ymm2/m256,imm8 + VEX.256.66.0F3A.W1 01 /r ib + + AVX2 + + Permute double-precision floating-point elements in ymm2/m256 using indices in imm8 and store the result in ymm1. + + + VPERMPD + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.256.66.0F3A.W1 01 /r ib + + AVX512VL + AVX512F + + Permute double-precision floating-point elements in ymm2/m256/m64bcst using indexes in imm8 and store the result in ymm1 subject to writemask k1. + + + VPERMPD + zmm1 {k1}{z},zmm2/m512/m64bcst,imm8 + EVEX.512.66.0F3A.W1 01 /r ib + + AVX512F + + Permute double-precision floating-point elements in zmm2/m512/m64bcst using indices in imm8 and store the result in zmm1 subject to writemask k1. + + + VPERMPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 16 /r + + AVX512VL + AVX512F + + Permute double-precision floating-point elements in ymm3/m256/m64bcst using indexes in ymm2 and store the result in ymm1 subject to writemask k1. + + + VPERMPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 16 /r + + AVX512F + + Permute double-precision floating-point elements in zmm3/m512/m64bcst using indices in zmm2 and store the result in zmm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPERMPS--Permute Single-Precision Floating-Point Elements. + + VPERMPS + ymm1,ymm2,ymm3/m256 + VEX.256.66.0F38.W0 16 /r + + AVX2 + + Permute single-precision floating-point elements in ymm3/m256 using indices in ymm2 and store the result in ymm1. + + + VPERMPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 16 /r + + AVX512VL + AVX512F + + Permute single-precision floating-point elements in ymm3/m256/m32bcst using indexes in ymm2 and store the result in ymm1 subject to write mask k1. + + + VPERMPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 16 /r + + AVX512F + + Permute single-precision floating-point values in zmm3/m512/m32bcst using indices in zmm2 and store the result in zmm1 subject to write mask k1. + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPERMQ--Qwords Element Permutation. + + VPERMQ + ymm1,ymm2/m256,imm8 + VEX.256.66.0F3A.W1 00 /r ib + + AVX2 + + Permute qwords in ymm2/m256 using indices in imm8 and store the result in ymm1. + + + VPERMQ + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.256.66.0F3A.W1 00 /r ib + + AVX512VL + AVX512F + + Permute qwords in ymm2/m256/m64bcst using indexes in imm8 and store the result in ymm1. + + + VPERMQ + zmm1 {k1}{z},zmm2/m512/m64bcst,imm8 + EVEX.512.66.0F3A.W1 00 /r ib + + AVX512F + + Permute qwords in zmm2/m512/m64bcst using indices in imm8 and store the result in zmm1. + + + VPERMQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 36 /r + + AVX512VL + AVX512F + + Permute qwords in ymm3/m256/m64bcst using indexes in ymm2 and store the result in ymm1. + + + VPERMQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 36 /r + + AVX512F + + Permute qwords in zmm3/m512/m64bcst using indices in zmm2 and store the result in zmm1. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPEXPANDD--Load Sparse Packed Doubleword Integer Values from Dense Memory / Register. + + VPEXPANDD + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F38.W0 89 /r + + AVX512VL + AVX512F + + Expand packed double-word integer values from xmm2/m128 to xmm1 using writemask k1. + + + VPEXPANDD + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F38.W0 89 /r + + AVX512VL + AVX512F + + Expand packed double-word integer values from ymm2/m256 to ymm1 using writemask k1. + + + VPEXPANDD + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F38.W0 89 /r + + AVX512F + + Expand packed double-word integer values from zmm2/m512 to zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VPEXPANDQ--Load Sparse Packed Quadword Integer Values from Dense Memory / Register. + + VPEXPANDQ + xmm1 {k1}{z},xmm2/m128 + EVEX.128.66.0F38.W1 89 /r + + AVX512VL + AVX512F + + Expand packed quad-word integer values from xmm2/m128 to xmm1 using writemask k1. + + + VPEXPANDQ + ymm1 {k1}{z},ymm2/m256 + EVEX.256.66.0F38.W1 89 /r + + AVX512VL + AVX512F + + Expand packed quad-word integer values from ymm2/m256 to ymm1 using writemask k1. + + + VPEXPANDQ + zmm1 {k1}{z},zmm2/m512 + EVEX.512.66.0F38.W1 89 /r + + AVX512F + + Expand packed quad-word integer values from zmm2/m512 to zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + PEXTRB/PEXTRW/PEXTRD/PEXTRQ--Extract Integer. + + PEXTRB + reg/m8,xmm2,imm8 + 66 0F 3A 14 /r ib + + SSE4_1 + + Extract a byte integer value from xmm2 at the source byte offset specified by imm8 into reg or m8. The upper bits of r64/r32 is filled with zeros. + + + PEXTRW + reg,xmm1,imm8 + 66 0F C5 /r ib + + SSE2 + + Extract the word specified by imm8 from xmm1 and move it to reg, bits 15:0. The upper bits of r64/r32 is filled with zeros. + + + PEXTRW + reg/m16,xmm2,imm8 + 66 0F 3A 15 /r ib + + SSE4_1 + + Extract a word integer value from xmm2 at the source word offset specified by imm8 into reg or m16. The upper bits of r64/r32 is filled with zeros. + + + PEXTRD + r32/m32,xmm2,imm8 + 66 0F 3A 16 /r ib + + SSE4_1 + + Extract a dword integer value from xmm2 at the source dword offset specified by imm8 into r32/m32. + + + PEXTRQ + r64/m64,xmm2,imm8 + 66 REX.W 0F 3A 16 /r ib + + SSE4_1 + + Extract a qword integer value from xmm2 at the source dword offset specified by imm8 into r64/m64. + + + VPEXTRB + reg/m8,xmm2,imm8 + VEX.128.66.0F3A 14 /r ib + + AVX + + Extract a byte integer value from xmm2 at the source byte offset specified by imm8 into reg or m8. The upper bits of r64/r32 is filled with zeros. + + + VPEXTRW + reg,xmm1,imm8 + VEX.128.66.0F C5 /r ib + + AVX + + Extract the word specified by imm8 from xmm1 and move it to reg, bits 15:0. Zero-extend the result. The upper bits of r64/r32 is filled with zeros. + + + VPEXTRW + reg/m16,xmm2,imm8 + VEX.128.66.0F3A 15 /r ib + + AVX + + Extract a word integer value from xmm2 at the source word offset specified by imm8 into reg or m16. The upper bits of r64/r32 is filled with zeros. + + + VPEXTRD + r32/m32,xmm2,imm8 + VEX.128.66.0F3A.W0 16 /r ib + + AVX + + Extract a dword integer value from xmm2 at the source dword offset specified by imm8 into r32/m32. + + + VPEXTRQ + r64/m64,xmm2,imm8 + VEX.128.66.0F3A.W1 16 /r ib + + AVX + + Extract a qword integer value from xmm2 at the source dword offset specified by imm8 into r64/m64. + + + VPEXTRB + reg/m8,xmm2,imm8 + EVEX.128.66.0F3A.WIG 14 /r ib + + AVX512BW + + Extract a byte integer value from xmm2 at the source byte offset specified by imm8 into reg or m8. The upper bits of r64/r32 is filled with zeros. + + + VPEXTRW + reg,xmm1,imm8 + EVEX.128.66.0F.WIG C5 /r ib + + AVX512BW + + Extract the word specified by imm8 from xmm1 and move it to reg, bits 15:0. Zero-extend the result. The upper bits of r64/r32 is filled with zeros. + + + VPEXTRW + reg/m16,xmm2,imm8 + EVEX.128.66.0F3A.WIG 15 /r ib + + AVX512BW + + Extract a word integer value from xmm2 at the source word offset specified by imm8 into reg or m16. The upper bits of r64/r32 is filled with zeros. + + + VPEXTRD + r32/m32,xmm2,imm8 + EVEX.128.66.0F3A.W0 16 /r ib + + AVX512DQ + + Extract a dword integer value from xmm2 at the source dword offset specified by imm8 into r32/m32. + + + VPEXTRQ + r64/m64,xmm2,imm8 + EVEX.128.66.0F3A.W1 16 /r ib + + AVX512DQ + + Extract a qword integer value from xmm2 at the source dword offset specified by imm8 into r64/m64. + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:r/m(w) + ModRM:reg(r) + Imm8 + NA + + + + VPLZCNTD/Q--Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values. + + VPLZCNTD + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.66.0F38.W0 44 /r + + AVX512VL + AVX512CD + + Count the number of leading zero bits in each dword element of xmm2/m128/m32bcst using writemask k1. + + + VPLZCNTD + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.66.0F38.W0 44 /r + + AVX512VL + AVX512CD + + Count the number of leading zero bits in each dword element of ymm2/m256/m32bcst using writemask k1. + + + VPLZCNTD + zmm1 {k1}{z},zmm2/m512/m32bcst + EVEX.512.66.0F38.W0 44 /r + + AVX512CD + + Count the number of leading zero bits in each dword element of zmm2/m512/m32bcst using writemask k1. + + + VPLZCNTQ + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F38.W1 44 /r + + AVX512VL + AVX512CD + + Count the number of leading zero bits in each qword element of xmm2/m128/m64bcst using writemask k1. + + + VPLZCNTQ + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F38.W1 44 /r + + AVX512VL + AVX512CD + + Count the number of leading zero bits in each qword element of ymm2/m256/m64bcst using writemask k1. + + + VPLZCNTQ + zmm1 {k1}{z},zmm2/m512/m64bcst + EVEX.512.66.0F38.W1 44 /r + + AVX512CD + + Count the number of leading zero bits in each qword element of zmm2/m512/m64bcst using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + PMADDUBSW--Multiply and Add Packed Integers. + + PMADDUBSW + xmm1,xmm2/m128 + 66 0F 38 04 /r + + SSSE3 + + Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1. + + + VPMADDUBSW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38 04 /r + + AVX + + Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1. + + + VPMADDUBSW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38 04 /r + + AVX2 + + Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1. + + + VPMADDUBSW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.WIG 04 /r + + AVX512VL + AVX512BW + + Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to xmm1 under writemask k1. + + + VPMADDUBSW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.WIG 04 /r + + AVX512VL + AVX512BW + + Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to ymm1 under writemask k1. + + + VPMADDUBSW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.WIG 04 /r + + AVX512BW + + Multiply signed and unsigned bytes, add horizontal pair of signed words, pack saturated signed-words to zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMADDWD--Multiply and Add Packed Integers. + + PMADDWD + xmm1,xmm2/m128 + 66 0F F5 /r + + SSE2 + + Multiply the packed word integers in xmm1 by the packed word integers in xmm2/m128, add adjacent doubleword results, and store in xmm1. + + + VPMADDWD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F F5 /r + + AVX + + Multiply the packed word integers in xmm2 by the packed word integers in xmm3/m128, add adjacent doubleword results, and store in xmm1. + + + VPMADDWD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F F5 /r + + AVX2 + + Multiply the packed word integers in ymm2 by the packed word integers in ymm3/m256, add adjacent doubleword results, and store in ymm1. + + + VPMADDWD + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG F5 /r + + AVX512VL + AVX512BW + + Multiply the packed word integers in xmm2 by the packed word integers in xmm3/m128, add adjacent doubleword results, and store in xmm1 under writemask k1. + + + VPMADDWD + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG F5 /r + + AVX512VL + AVX512BW + + Multiply the packed word integers in ymm2 by the packed word integers in ymm3/m256, add adjacent doubleword results, and store in ymm1 under writemask k1. + + + VPMADDWD + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG F5 /r + + AVX512BW + + Multiply the packed word integers in zmm2 by the packed word integers in zmm3/m512, add adjacent doubleword results, and store in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PINSRB/PINSRW/PINSRD/PINSRQ--Insert Integer. + + PINSRB + xmm1,r32/m8,imm8 + 66 0F 3A 20 /r ib + + SSE4_1 + + Insert a byte integer value from r32/m8 into xmm1 at the byte offset in imm8. + + + PINSRW + xmm1,r32/m16,imm8 + 66 0F C4 /r ib + + SSE2 + + Insert a word integer value from r32/m16 into xmm1 at the word offset in imm8. + + + PINSRD + xmm1,r32/m32,imm8 + 66 0F 3A 22 /r ib + + SSE4_1 + + Insert a dword integer value from r32/m32 into xmm1 at the dword offset in imm8. + + + PINSRQ + xmm1,r64/m64,imm8 + 66 REX.W 0F 3A 22 /r ib + + SSE4_1 + + Insert a qword integer value from r64/m64 into xmm1 at the qword offset in imm8. + + + VPINSRB + xmm1,xmm2,r32/m8,imm8 + VEX.NDS.128.66.0F3A 20 /r ib + + AVX + + Merge a byte integer value from r32/m8 and rest from xmm2 into xmm1 at the byte offset in imm8. + + + VPINSRW + xmm1,xmm2,r32/m16,imm8 + VEX.NDS.128.66.0F C4 /r ib + + AVX + + Insert a word integer value from r32/m16 and rest from xmm2 into xmm1 at the word offset in imm8. + + + VPINSRD + xmm1,xmm2,r32/m32,imm8 + VEX.NDS.128.66.0F3A.W0 22 /r ib + + AVX + + Insert a dword integer value from r32/m32 and rest from xmm2 into xmm1 at the dword offset in imm8. + + + VPINSRQ + xmm1,xmm2,r64/m64,imm8 + VEX.NDS.128.66.0F3A.W1 22 /r ib + + AVX + + Insert a qword integer value from r64/m64 and rest from xmm2 into xmm1 at the qword offset in imm8. + + + VPINSRB + xmm1,xmm2,r32/m8,imm8 + EVEX.NDS.128.66.0F3A.WIG 20 /r ib + + AVX512BW + + Merge a byte integer value from r32/m8 and rest from xmm2 into xmm1 at the byte offset in imm8. + + + VPINSRW + xmm1,xmm2,r32/m16,imm8 + EVEX.NDS.128.66.0F.WIG C4 /r ib + + AVX512BW + + Insert a word integer value from r32/m16 and rest from xmm2 into xmm1 at the word offset in imm8. + + + VPINSRD + xmm1,xmm2,r32/m32,imm8 + EVEX.NDS.128.66.0F3A.W0 22 /r ib + + AVX512DQ + + Insert a dword integer value from r32/m32 and rest from xmm2 into xmm1 at the dword offset in imm8. + + + VPINSRQ + xmm1,xmm2,r64/m64,imm8 + EVEX.NDS.128.66.0F3A.W1 22 /r ib + + AVX512DQ + + Insert a qword integer value from r64/m64 and rest from xmm2 into xmm1 at the qword offset in imm8. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + VPMADD52LUQ--Packed Multiply of Unsigned 52-bit Integers and Add the Low 52-bit Products to Qword Accumulators. + + VPMADD52LUQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 B4 /r + + AVX512IFMA + AVX512VL + + Multiply unsigned 52-bit integers in xmm2 and xmm3/m128 and add the low 52 bits of the 104-bit product to the qword unsigned integers in xmm1 using writemask k1. + + + VPMADD52LUQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 B4 /r + + AVX512IFMA + AVX512VL + + Multiply unsigned 52-bit integers in ymm2 and ymm3/m128 and add the low 52 bits of the 104-bit product to the qword unsigned integers in ymm1 using writemask k1. + + + VPMADD52LUQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.DDS.512.66.0F38.W1 B4 /r + + AVX512IFMA + + Multiply unsigned 52-bit integers in zmm2 and zmm3/m128 and add the low 52 bits of the 104-bit product to the qword unsigned integers in zmm1 using writemask k1. + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPMADD52HUQ--Packed Multiply of Unsigned 52-bit Unsigned Integers and Add High 52-bit Products to 64-bit Accumulators'. + + VPMADD52HUQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.DDS.128.66.0F38.W1 B5 /r + + AVX512IFMA + AVX512VL + + Multiply unsigned 52-bit integers in xmm2 and xmm3/m128 and add the high 52 bits of the 104bit product to the qword unsigned integers in xmm1 using writemask k1. + + + VPMADD52HUQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.DDS.256.66.0F38.W1 B5 /r + + AVX512IFMA + AVX512VL + + Multiply unsigned 52-bit integers in ymm2 and ymm3/m128 and add the high 52 bits of the 104bit product to the qword unsigned integers in ymm1 using writemask k1. + + + VPMADD52HUQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.DDS.512.66.0F38.W1 B5 /r + + AVX512IFMA + + Multiply unsigned 52-bit integers in zmm2 and zmm3/m128 and add the high 52 bits of the 104bit product to the qword unsigned integers in zmm1 using writemask k1. + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMAXSB/PMAXSW/PMAXSD/PMAXSQ--Maximum of Packed Signed Integers. + + PMAXSB + xmm1,xmm2/m128 + 66 0F 38 3C /r + + SSE4_1 + + Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed maximum values in xmm1. + + + PMAXSW + xmm1,xmm2/m128 + 66 0F EE /r + + SSE2 + + Compare packed signed word integers in xmm2/m128 and xmm1 and stores maximum packed values in xmm1. + + + PMAXSD + xmm1,xmm2/m128 + 66 0F 38 3D /r + + SSE4_1 + + Compare packed signed dword integers in xmm1 and xmm2/m128 and store packed maximum values in xmm1. + + + VPMAXSB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 3C /r + + AVX + + Compare packed signed byte integers in xmm2 and xmm3/m128 and store packed maximum values in xmm1. + + + VPMAXSW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG EE /r + + AVX + + Compare packed signed word integers in xmm3/m128 and xmm2 and store packed maximum values in xmm1. + + + VPMAXSD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 3D /r + + AVX + + Compare packed signed dword integers in xmm2 and xmm3/m128 and store packed maximum values in xmm1. + + + VPMAXSB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.WIG 3C /r + + AVX2 + + Compare packed signed byte integers in ymm2 and ymm3/m256 and store packed maximum values in ymm1. + + + VPMAXSW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG EE /r + + AVX2 + + Compare packed signed word integers in ymm3/m256 and ymm2 and store packed maximum values in ymm1. + + + VPMAXSD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.WIG 3D /r + + AVX2 + + Compare packed signed dword integers in ymm2 and ymm3/m256 and store packed maximum values in ymm1. + + + VPMAXSB + xmm1{k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.WIG 3C /r + + AVX512VL + AVX512BW + + Compare packed signed byte integers in xmm2 and xmm3/m128 and store packed maximum values in xmm1 under writemask k1. + + + VPMAXSB + ymm1{k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.WIG 3C /r + + AVX512VL + AVX512BW + + Compare packed signed byte integers in ymm2 and ymm3/m256 and store packed maximum values in ymm1 under writemask k1. + + + VPMAXSB + zmm1{k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.WIG 3C /r + + AVX512BW + + Compare packed signed byte integers in zmm2 and zmm3/m512 and store packed maximum values in zmm1 under writemask k1. + + + VPMAXSW + xmm1{k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG EE /r + + AVX512VL + AVX512BW + + Compare packed signed word integers in xmm2 and xmm3/m128 and store packed maximum values in xmm1 under writemask k1. + + + VPMAXSW + ymm1{k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG EE /r + + AVX512VL + AVX512BW + + Compare packed signed word integers in ymm2 and ymm3/m256 and store packed maximum values in ymm1 under writemask k1. + + + VPMAXSW + zmm1{k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG EE /r + + AVX512BW + + Compare packed signed word integers in zmm2 and zmm3/m512 and store packed maximum values in zmm1 under writemask k1. + + + VPMAXSD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 3D /r + + AVX512VL + AVX512F + + Compare packed signed dword integers in xmm2 and xmm3/m128/m32bcst and store packed maximum values in xmm1 using writemask k1. + + + VPMAXSD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 3D /r + + AVX512VL + AVX512F + + Compare packed signed dword integers in ymm2 and ymm3/m256/m32bcst and store packed maximum values in ymm1 using writemask k1. + + + VPMAXSD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 3D /r + + AVX512F + + Compare packed signed dword integers in zmm2 and zmm3/m512/m32bcst and store packed maximum values in zmm1 using writemask k1. + + + VPMAXSQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 3D /r + + AVX512VL + AVX512F + + Compare packed signed qword integers in xmm2 and xmm3/m128/m64bcst and store packed maximum values in xmm1 using writemask k1. + + + VPMAXSQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 3D /r + + AVX512VL + AVX512F + + Compare packed signed qword integers in ymm2 and ymm3/m256/m64bcst and store packed maximum values in ymm1 using writemask k1. + + + VPMAXSQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 3D /r + + AVX512F + + Compare packed signed qword integers in zmm2 and zmm3/m512/m64bcst and store packed maximum values in zmm1 using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMAXUB/PMAXUW--Maximum of Packed Unsigned Integers. + + PMAXUB + xmm1,xmm2/m128 + 66 0F DE /r + + SSE2 + + Compare packed unsigned byte integers in xmm1 and xmm2/m128 and store packed maximum values in xmm1. + + + PMAXUW + xmm1,xmm2/m128 + 66 0F 38 3E/r + + SSE4_1 + + Compare packed unsigned word integers in xmm2/m128 and xmm1 and stores maximum packed values in xmm1. + + + VPMAXUB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F DE /r + + AVX + + Compare packed unsigned byte integers in xmm2 and xmm3/m128 and store packed maximum values in xmm1. + + + VPMAXUW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38 3E/r + + AVX + + Compare packed unsigned word integers in xmm3/m128 and xmm2 and store maximum packed values in xmm1. + + + VPMAXUB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F DE /r + + AVX2 + + Compare packed unsigned byte integers in ymm2 and ymm3/m256 and store packed maximum values in ymm1. + + + VPMAXUW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38 3E/r + + AVX2 + + Compare packed unsigned word integers in ymm3/m256 and ymm2 and store maximum packed values in ymm1. + + + VPMAXUB + xmm1{k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG DE /r + + AVX512VL + AVX512BW + + Compare packed unsigned byte integers in xmm2 and xmm3/m128 and store packed maximum values in xmm1 under writemask k1. + + + VPMAXUB + ymm1{k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG DE /r + + AVX512VL + AVX512BW + + Compare packed unsigned byte integers in ymm2 and ymm3/m256 and store packed maximum values in ymm1 under writemask k1. + + + VPMAXUB + zmm1{k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG DE /r + + AVX512BW + + Compare packed unsigned byte integers in zmm2 and zmm3/m512 and store packed maximum values in zmm1 under writemask k1. + + + VPMAXUW + xmm1{k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.WIG 3E /r + + AVX512VL + AVX512BW + + Compare packed unsigned word integers in xmm2 and xmm3/m128 and store packed maximum values in xmm1 under writemask k1. + + + VPMAXUW + ymm1{k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.WIG 3E /r + + AVX512VL + AVX512BW + + Compare packed unsigned word integers in ymm2 and ymm3/m256 and store packed maximum values in ymm1 under writemask k1. + + + VPMAXUW + zmm1{k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.WIG 3E /r + + AVX512BW + + Compare packed unsigned word integers in zmm2 and zmm3/m512 and store packed maximum values in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMAXUD/PMAXUQ--Maximum of Packed Unsigned Integers. + + PMAXUD + xmm1,xmm2/m128 + 66 0F 38 3F /r + + SSE4_1 + + Compare packed unsigned dword integers in xmm1 and xmm2/m128 and store packed maximum values in xmm1. + + + VPMAXUD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 3F /r + + AVX + + Compare packed unsigned dword integers in xmm2 and xmm3/m128 and store packed maximum values in xmm1. + + + VPMAXUD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.WIG 3F /r + + AVX2 + + Compare packed unsigned dword integers in ymm2 and ymm3/m256 and store packed maximum values in ymm1. + + + VPMAXUD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 3F /r + + AVX512VL + AVX512F + + Compare packed unsigned dword integers in xmm2 and xmm3/m128/m32bcst and store packed maximum values in xmm1 under writemask k1. + + + VPMAXUD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 3F /r + + AVX512VL + AVX512F + + Compare packed unsigned dword integers in ymm2 and ymm3/m256/m32bcst and store packed maximum values in ymm1 under writemask k1. + + + VPMAXUD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 3F /r + + AVX512F + + Compare packed unsigned dword integers in zmm2 and zmm3/m512/m32bcst and store packed maximum values in zmm1 under writemask k1. + + + VPMAXUQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 3F /r + + AVX512VL + AVX512F + + Compare packed unsigned qword integers in xmm2 and xmm3/m128/m64bcst and store packed maximum values in xmm1 under writemask k1. + + + VPMAXUQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 3F /r + + AVX512VL + AVX512F + + Compare packed unsigned qword integers in ymm2 and ymm3/m256/m64bcst and store packed maximum values in ymm1 under writemask k1. + + + VPMAXUQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 3F /r + + AVX512F + + Compare packed unsigned qword integers in zmm2 and zmm3/m512/m64bcst and store packed maximum values in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + PMINSB/PMINSW--Minimum of Packed Signed Integers. + + PMINSB + xmm1,xmm2/m128 + 66 0F 38 38 /r + + SSE4_1 + + Compare packed signed byte integers in xmm1 and xmm2/m128 and store packed minimum values in xmm1. + + + PMINSW + xmm1,xmm2/m128 + 66 0F EA /r + + SSE2 + + Compare packed signed word integers in xmm2/m128 and xmm1 and store packed minimum values in xmm1. + + + VPMINSB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38 38 /r + + AVX + + Compare packed signed byte integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1. + + + VPMINSW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F EA /r + + AVX + + Compare packed signed word integers in xmm3/m128 and xmm2 and return packed minimum values in xmm1. + + + VPMINSB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38 38 /r + + AVX2 + + Compare packed signed byte integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1. + + + VPMINSW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F EA /r + + AVX2 + + Compare packed signed word integers in ymm3/m256 and ymm2 and return packed minimum values in ymm1. + + + VPMINSB + xmm1{k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.WIG 38 /r + + AVX512VL + AVX512BW + + Compare packed signed byte integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1 under writemask k1. + + + VPMINSB + ymm1{k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.WIG 38 /r + + AVX512VL + AVX512BW + + Compare packed signed byte integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1 under writemask k1. + + + VPMINSB + zmm1{k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.WIG 38 /r + + AVX512BW + + Compare packed signed byte integers in zmm2 and zmm3/m512 and store packed minimum values in zmm1 under writemask k1. + + + VPMINSW + xmm1{k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG EA /r + + AVX512VL + AVX512BW + + Compare packed signed word integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1 under writemask k1. + + + VPMINSW + ymm1{k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG EA /r + + AVX512VL + AVX512BW + + Compare packed signed word integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1 under writemask k1. + + + VPMINSW + zmm1{k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG EA /r + + AVX512BW + + Compare packed signed word integers in zmm2 and zmm3/m512 and store packed minimum values in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMINSD/PMINSQ--Minimum of Packed Signed Integers. + + PMINSD + xmm1,xmm2/m128 + 66 0F 38 39 /r + + SSE4_1 + + Compare packed signed dword integers in xmm1 and xmm2/m128 and store packed minimum values in xmm1. + + + VPMINSD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 39 /r + + AVX + + Compare packed signed dword integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1. + + + VPMINSD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.WIG 39 /r + + AVX2 + + Compare packed signed dword integers in ymm2 and ymm3/m128 and store packed minimum values in ymm1. + + + VPMINSD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 39 /r + + AVX512VL + AVX512F + + Compare packed signed dword integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1 under writemask k1. + + + VPMINSD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 39 /r + + AVX512VL + AVX512F + + Compare packed signed dword integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1 under writemask k1. + + + VPMINSD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 39 /r + + AVX512F + + Compare packed signed dword integers in zmm2 and zmm3/m512/m32bcst and store packed minimum values in zmm1 under writemask k1. + + + VPMINSQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 39 /r + + AVX512VL + AVX512F + + Compare packed signed qword integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1 under writemask k1. + + + VPMINSQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 39 /r + + AVX512VL + AVX512F + + Compare packed signed qword integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1 under writemask k1. + + + VPMINSQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 39 /r + + AVX512F + + Compare packed signed qword integers in zmm2 and zmm3/m512/m64bcst and store packed minimum values in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMINUB/PMINUW--Minimum of Packed Unsigned Integers. + + PMINUB + xmm1,xmm2/m128 + 66 0F DA /r + + SSE2 + + Compare packed unsigned byte integers in xmm1 and xmm2/m128 and store packed minimum values in xmm1. + + + PMINUW + xmm1,xmm2/m128 + 66 0F 38 3A/r + + SSE4_1 + + Compare packed unsigned word integers in xmm2/m128 and xmm1 and store packed minimum values in xmm1. + + + VPMINUB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F DA /r + + AVX + + Compare packed unsigned byte integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1. + + + VPMINUW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38 3A/r + + AVX + + Compare packed unsigned word integers in xmm3/m128 and xmm2 and return packed minimum values in xmm1. + + + VPMINUB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F DA /r + + AVX2 + + Compare packed unsigned byte integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1. + + + VPMINUW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38 3A/r + + AVX2 + + Compare packed unsigned word integers in ymm3/m256 and ymm2 and return packed minimum values in ymm1. + + + VPMINUB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F DA /r + + AVX512VL + AVX512BW + + Compare packed unsigned byte integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1 under writemask k1. + + + VPMINUB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F DA /r + + AVX512VL + AVX512BW + + Compare packed unsigned byte integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1 under writemask k1. + + + VPMINUB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F DA /r + + AVX512BW + + Compare packed unsigned byte integers in zmm2 and zmm3/m512 and store packed minimum values in zmm1 under writemask k1. + + + VPMINUW + xmm1{k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38 3A/r + + AVX512VL + AVX512BW + + Compare packed unsigned word integers in xmm3/m128 and xmm2 and return packed minimum values in xmm1 under writemask k1. + + + VPMINUW + ymm1{k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38 3A/r + + AVX512VL + AVX512BW + + Compare packed unsigned word integers in ymm3/m256 and ymm2 and return packed minimum values in ymm1 under writemask k1. + + + VPMINUW + zmm1{k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38 3A/r + + AVX512BW + + Compare packed unsigned word integers in zmm3/m512 and zmm2 and return packed minimum values in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMINUD/PMINUQ--Minimum of Packed Unsigned Integers. + + PMINUD + xmm1,xmm2/m128 + 66 0F 38 3B /r + + SSE4_1 + + Compare packed unsigned dword integers in xmm1 and xmm2/m128 and store packed minimum values in xmm1. + + + VPMINUD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 3B /r + + AVX + + Compare packed unsigned dword integers in xmm2 and xmm3/m128 and store packed minimum values in xmm1. + + + VPMINUD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.WIG 3B /r + + AVX2 + + Compare packed unsigned dword integers in ymm2 and ymm3/m256 and store packed minimum values in ymm1. + + + VPMINUD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 3B /r + + AVX512VL + AVX512F + + Compare packed unsigned dword integers in xmm2 and xmm3/m128/m32bcst and store packed minimum values in xmm1 under writemask k1. + + + VPMINUD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 3B /r + + AVX512VL + AVX512F + + Compare packed unsigned dword integers in ymm2 and ymm3/m256/m32bcst and store packed minimum values in ymm1 under writemask k1. + + + VPMINUD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 3B /r + + AVX512F + + Compare packed unsigned dword integers in zmm2 and zmm3/m512/m32bcst and store packed minimum values in zmm1 under writemask k1. + + + VPMINUQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 3B /r + + AVX512VL + AVX512F + + Compare packed unsigned qword integers in xmm2 and xmm3/m128/m64bcst and store packed minimum values in xmm1 under writemask k1. + + + VPMINUQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 3B /r + + AVX512VL + AVX512F + + Compare packed unsigned qword integers in ymm2 and ymm3/m256/m64bcst and store packed minimum values in ymm1 under writemask k1. + + + VPMINUQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 3B /r + + AVX512F + + Compare packed unsigned qword integers in zmm2 and zmm3/m512/m64bcst and store packed minimum values in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q--Convert a Mask Register to a Vector Register. + + VPMOVM2B + xmm1,k1 + EVEX.128.F3.0F38.W0 28 /r + + AVX512VL + AVX512BW + + Sets each byte in XMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2B + ymm1,k1 + EVEX.256.F3.0F38.W0 28 /r + + AVX512VL + AVX512BW + + Sets each byte in YMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2B + zmm1,k1 + EVEX.512.F3.0F38.W0 28 /r + + AVX512BW + + Sets each byte in ZMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2W + xmm1,k1 + EVEX.128.F3.0F38.W1 28 /r + + AVX512VL + AVX512BW + + Sets each word in XMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2W + ymm1,k1 + EVEX.256.F3.0F38.W1 28 /r + + AVX512VL + AVX512BW + + Sets each word in YMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2W + zmm1,k1 + EVEX.512.F3.0F38.W1 28 /r + + AVX512BW + + Sets each word in ZMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2D + xmm1,k1 + EVEX.128.F3.0F38.W0 38 /r + + AVX512VL + AVX512DQ + + Sets each doubleword in XMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2D + ymm1,k1 + EVEX.256.F3.0F38.W0 38 /r + + AVX512VL + AVX512DQ + + Sets each doubleword in YMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2D + zmm1,k1 + EVEX.512.F3.0F38.W0 38 /r + + AVX512DQ + + Sets each doubleword in ZMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2Q + xmm1,k1 + EVEX.128.F3.0F38.W1 38 /r + + AVX512VL + AVX512DQ + + Sets each quadword in XMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2Q + ymm1,k1 + EVEX.256.F3.0F38.W1 38 /r + + AVX512VL + AVX512DQ + + Sets each quadword in YMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + VPMOVM2Q + zmm1,k1 + EVEX.512.F3.0F38.W1 38 /r + + AVX512DQ + + Sets each quadword in ZMM1 to all 1's or all 0's based on the value of the corresponding bit in k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M--Convert a Vector Register to a Mask. + + VPMOVB2M + k1,xmm1 + EVEX.128.F3.0F38.W0 29 /r + + AVX512VL + AVX512BW + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in XMM1. + + + VPMOVB2M + k1,ymm1 + EVEX.256.F3.0F38.W0 29 /r + + AVX512VL + AVX512BW + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in YMM1. + + + VPMOVB2M + k1,zmm1 + EVEX.512.F3.0F38.W0 29 /r + + AVX512BW + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding byte in ZMM1. + + + VPMOVW2M + k1,xmm1 + EVEX.128.F3.0F38.W1 29 /r + + AVX512VL + AVX512BW + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in XMM1. + + + VPMOVW2M + k1,ymm1 + EVEX.256.F3.0F38.W1 29 /r + + AVX512VL + AVX512BW + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in YMM1. + + + VPMOVW2M + k1,zmm1 + EVEX.512.F3.0F38.W1 29 /r + + AVX512BW + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding word in ZMM1. + + + VPMOVD2M + k1,xmm1 + EVEX.128.F3.0F38.W0 39 /r + + AVX512VL + AVX512DQ + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in XMM1. + + + VPMOVD2M + k1,ymm1 + EVEX.256.F3.0F38.W0 39 /r + + AVX512VL + AVX512DQ + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in YMM1. + + + VPMOVD2M + k1,zmm1 + EVEX.512.F3.0F38.W0 39 /r + + AVX512DQ + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding doubleword in ZMM1. + + + VPMOVQ2M + k1,xmm1 + EVEX.128.F3.0F38.W1 39 /r + + AVX512VL + AVX512DQ + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in XMM1. + + + VPMOVQ2M + k1,ymm1 + EVEX.256.F3.0F38.W1 39 /r + + AVX512VL + AVX512DQ + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in YMM1. + + + VPMOVQ2M + k1,zmm1 + EVEX.512.F3.0F38.W1 39 /r + + AVX512DQ + + Sets each bit in k1 to 1 or 0 based on the value of the most significant bit of the corresponding quadword in ZMM1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VPMOVQB/VPMOVSQB/VPMOVUSQB--Down Convert QWord to Byte. + + VPMOVQB + xmm1/m16 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 32 /r + + AVX512VL + AVX512F + + Converts 2 packed quad-word integers from xmm2 into 2 packed byte integers in xmm1/m16 with truncation under writemask k1. + + + VPMOVSQB + xmm1/m16 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 22 /r + + AVX512VL + AVX512F + + Converts 2 packed signed quad-word integers from xmm2 into 2 packed signed byte integers in xmm1/m16 using signed saturation under writemask k1. + + + VPMOVUSQB + xmm1/m16 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 12 /r + + AVX512VL + AVX512F + + Converts 2 packed unsigned quad-word integers from xmm2 into 2 packed unsigned byte integers in xmm1/m16 using unsigned saturation under writemask k1. + + + VPMOVQB + xmm1/m32 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 32 /r + + AVX512VL + AVX512F + + Converts 4 packed quad-word integers from ymm2 into 4 packed byte integers in xmm1/m32 with truncation under writemask k1. + + + VPMOVSQB + xmm1/m32 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 22 /r + + AVX512VL + AVX512F + + Converts 4 packed signed quad-word integers from ymm2 into 4 packed signed byte integers in xmm1/m32 using signed saturation under writemask k1. + + + VPMOVUSQB + xmm1/m32 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 12 /r + + AVX512VL + AVX512F + + Converts 4 packed unsigned quad-word integers from ymm2 into 4 packed unsigned byte integers in xmm1/m32 using unsigned saturation under writemask k1. + + + VPMOVQB + xmm1/m64 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 32 /r + + AVX512F + + Converts 8 packed quad-word integers from zmm2 into 8 packed byte integers in xmm1/m64 with truncation under writemask k1. + + + VPMOVSQB + xmm1/m64 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 22 /r + + AVX512F + + Converts 8 packed signed quad-word integers from zmm2 into 8 packed signed byte integers in xmm1/m64 using signed saturation under writemask k1. + + + VPMOVUSQB + xmm1/m64 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 12 /r + + AVX512F + + Converts 8 packed unsigned quad-word integers from zmm2 into 8 packed unsigned byte integers in xmm1/m64 using unsigned saturation under writemask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + VPMOVQW/VPMOVSQW/VPMOVUSQW--Down Convert QWord to Word. + + VPMOVQW + xmm1/m32 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 34 /r + + AVX512VL + AVX512F + + Converts 2 packed quad-word integers from xmm2 into 2 packed word integers in xmm1/m32 with truncation under writemask k1. + + + VPMOVSQW + xmm1/m32 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 24 /r + + AVX512VL + AVX512F + + Converts 8 packed signed quad-word integers from zmm2 into 8 packed signed word integers in xmm1/m32 using signed saturation under writemask k1. + + + VPMOVUSQW + xmm1/m32 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 14 /r + + AVX512VL + AVX512F + + Converts 2 packed unsigned quad-word integers from xmm2 into 2 packed unsigned word integers in xmm1/m32 using unsigned saturation under writemask k1. + + + VPMOVQW + xmm1/m64 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 34 /r + + AVX512VL + AVX512F + + Converts 4 packed quad-word integers from ymm2 into 4 packed word integers in xmm1/m64 with truncation under writemask k1. + + + VPMOVSQW + xmm1/m64 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 24 /r + + AVX512VL + AVX512F + + Converts 4 packed signed quad-word integers from ymm2 into 4 packed signed word integers in xmm1/m64 using signed saturation under writemask k1. + + + VPMOVUSQW + xmm1/m64 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 14 /r + + AVX512VL + AVX512F + + Converts 4 packed unsigned quad-word integers from ymm2 into 4 packed unsigned word integers in xmm1/m64 using unsigned saturation under writemask k1. + + + VPMOVQW + xmm1/m128 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 34 /r + + AVX512F + + Converts 8 packed quad-word integers from zmm2 into 8 packed word integers in xmm1/m128 with truncation under writemask k1. + + + VPMOVSQW + xmm1/m128 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 24 /r + + AVX512F + + Converts 8 packed signed quad-word integers from zmm2 into 8 packed signed word integers in xmm1/m128 using signed saturation under writemask k1. + + + VPMOVUSQW + xmm1/m128 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 14 /r + + AVX512F + + Converts 8 packed unsigned quad-word integers from zmm2 into 8 packed unsigned word integers in xmm1/m128 using unsigned saturation under writemask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + VPMOVQD/VPMOVSQD/VPMOVUSQD--Down Convert QWord to DWord. + + VPMOVQD + xmm1/m128 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 35 /r + + AVX512VL + AVX512F + + Converts 2 packed quad-word integers from xmm2 into 2 packed double-word integers in xmm1/m128 with truncation subject to writemask k1. + + + VPMOVSQD + xmm1/m64 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 25 /r + + AVX512VL + AVX512F + + Converts 2 packed signed quad-word integers from xmm2 into 2 packed signed double-word integers in xmm1/m64 using signed saturation subject to writemask k1. + + + VPMOVUSQD + xmm1/m64 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 15 /r + + AVX512VL + AVX512F + + Converts 2 packed unsigned quad-word integers from xmm2 into 2 packed unsigned double-word integers in xmm1/m64 using unsigned saturation subject to writemask k1. + + + VPMOVQD + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 35 /r + + AVX512VL + AVX512F + + Converts 4 packed quad-word integers from ymm2 into 4 packed double-word integers in xmm1/m128 with truncation subject to writemask k1. + + + VPMOVSQD + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 25 /r + + AVX512VL + AVX512F + + Converts 4 packed signed quad-word integers from ymm2 into 4 packed signed double-word integers in xmm1/m128 using signed saturation subject to writemask k1. + + + VPMOVUSQD + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 15 /r + + AVX512VL + AVX512F + + Converts 4 packed unsigned quad-word integers from ymm2 into 4 packed unsigned double-word integers in xmm1/m128 using unsigned saturation subject to writemask k1. + + + VPMOVQD + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 35 /r + + AVX512F + + Converts 8 packed quad-word integers from zmm2 into 8 packed double-word integers in ymm1/m256 with truncation subject to writemask k1. + + + VPMOVSQD + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 25 /r + + AVX512F + + Converts 8 packed signed quad-word integers from zmm2 into 8 packed signed double-word integers in ymm1/m256 using signed saturation subject to writemask k1. + + + VPMOVUSQD + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 15 /r + + AVX512F + + Converts 8 packed unsigned quad-word integers from zmm2 into 8 packed unsigned double-word integers in ymm1/m256 using unsigned saturation subject to writemask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + VPMOVDB/VPMOVSDB/VPMOVUSDB--Down Convert DWord to Byte. + + VPMOVDB + xmm1/m32 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 31 /r + + AVX512VL + AVX512F + + Converts 4 packed double-word integers from xmm2 into 4 packed byte integers in xmm1/m32 with truncation under writemask k1. + + + VPMOVSDB + xmm1/m32 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 21 /r + + AVX512VL + AVX512F + + Converts 4 packed signed double-word integers from xmm2 into 4 packed signed byte integers in xmm1/m32 using signed saturation under writemask k1. + + + VPMOVUSDB + xmm1/m32 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 11 /r + + AVX512VL + AVX512F + + Converts 4 packed unsigned double-word integers from xmm2 into 4 packed unsigned byte integers in xmm1/m32 using unsigned saturation under writemask k1. + + + VPMOVDB + xmm1/m64 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 31 /r + + AVX512VL + AVX512F + + Converts 8 packed double-word integers from ymm2 into 8 packed byte integers in xmm1/m64 with truncation under writemask k1. + + + VPMOVSDB + xmm1/m64 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 21 /r + + AVX512VL + AVX512F + + Converts 8 packed signed double-word integers from ymm2 into 8 packed signed byte integers in xmm1/m64 using signed saturation under writemask k1. + + + VPMOVUSDB + xmm1/m64 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 11 /r + + AVX512VL + AVX512F + + Converts 8 packed unsigned double-word integers from ymm2 into 8 packed unsigned byte integers in xmm1/m64 using unsigned saturation under writemask k1. + + + VPMOVDB + xmm1/m128 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 31 /r + + AVX512F + + Converts 16 packed double-word integers from zmm2 into 16 packed byte integers in xmm1/m128 with truncation under writemask k1. + + + VPMOVSDB + xmm1/m128 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 21 /r + + AVX512F + + Converts 16 packed signed double-word integers from zmm2 into 16 packed signed byte integers in xmm1/m128 using signed saturation under writemask k1. + + + VPMOVUSDB + xmm1/m128 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 11 /r + + AVX512F + + Converts 16 packed unsigned double-word integers from zmm2 into 16 packed unsigned byte integers in xmm1/m128 using unsigned saturation under writemask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + VPMOVDW/VPMOVSDW/VPMOVUSDW--Down Convert DWord to Word. + + VPMOVDW + xmm1/m64 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 33 /r + + AVX512VL + AVX512F + + Converts 4 packed double-word integers from xmm2 into 4 packed word integers in xmm1/m64 with truncation under writemask k1. + + + VPMOVSDW + xmm1/m64 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 23 /r + + AVX512VL + AVX512F + + Converts 4 packed signed double-word integers from xmm2 into 4 packed signed word integers in ymm1/m64 using signed saturation under writemask k1. + + + VPMOVUSDW + xmm1/m64 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 13 /r + + AVX512VL + AVX512F + + Converts 4 packed unsigned double-word integers from xmm2 into 4 packed unsigned word integers in xmm1/m64 using unsigned saturation under writemask k1. + + + VPMOVDW + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 33 /r + + AVX512VL + AVX512F + + Converts 8 packed double-word integers from ymm2 into 8 packed word integers in xmm1/m128 with truncation under writemask k1. + + + VPMOVSDW + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 23 /r + + AVX512VL + AVX512F + + Converts 8 packed signed double-word integers from ymm2 into 8 packed signed word integers in xmm1/m128 using signed saturation under writemask k1. + + + VPMOVUSDW + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 13 /r + + AVX512VL + AVX512F + + Converts 8 packed unsigned double-word integers from ymm2 into 8 packed unsigned word integers in xmm1/m128 using unsigned saturation under writemask k1. + + + VPMOVDW + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 33 /r + + AVX512F + + Converts 16 packed double-word integers from zmm2 into 16 packed word integers in ymm1/m256 with truncation under writemask k1. + + + VPMOVSDW + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 23 /r + + AVX512F + + Converts 16 packed signed double-word integers from zmm2 into 16 packed signed word integers in ymm1/m256 using signed saturation under writemask k1. + + + VPMOVUSDW + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 13 /r + + AVX512F + + Converts 16 packed unsigned double-word integers from zmm2 into 16 packed unsigned word integers in ymm1/m256 using unsigned saturation under writemask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + VPMOVWB/VPMOVSWB/VPMOVUSWB--Down Convert Word to Byte. + + VPMOVWB + xmm1/m64 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 30 /r + + AVX512VL + AVX512BW + + Converts 8 packed word integers from xmm2 into 8 packed bytes in xmm1/m64 with truncation under writemask k1. + + + VPMOVSWB + xmm1/m64 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 20 /r + + AVX512VL + AVX512BW + + Converts 8 packed signed word integers from xmm2 into 8 packed signed bytes in xmm1/m64 using signed saturation under writemask k1. + + + VPMOVUSWB + xmm1/m64 {k1}{z},xmm2 + EVEX.128.F3.0F38.W0 10 /r + + AVX512VL + AVX512BW + + Converts 8 packed unsigned word integers from xmm2 into 8 packed unsigned bytes in 8mm1/m64 using unsigned saturation under writemask k1. + + + VPMOVWB + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 30 /r + + AVX512VL + AVX512BW + + Converts 16 packed word integers from ymm2 into 16 packed bytes in xmm1/m128 with truncation under writemask k1. + + + VPMOVSWB + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 20 /r + + AVX512VL + AVX512BW + + Converts 16 packed signed word integers from ymm2 into 16 packed signed bytes in xmm1/m128 using signed saturation under writemask k1. + + + VPMOVUSWB + xmm1/m128 {k1}{z},ymm2 + EVEX.256.F3.0F38.W0 10 /r + + AVX512VL + AVX512BW + + Converts 16 packed unsigned word integers from ymm2 into 16 packed unsigned bytes in xmm1/m128 using unsigned saturation under writemask k1. + + + VPMOVWB + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 30 /r + + AVX512BW + + Converts 32 packed word integers from zmm2 into 32 packed bytes in ymm1/m256 with truncation under writemask k1. + + + VPMOVSWB + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 20 /r + + AVX512BW + + Converts 32 packed signed word integers from zmm2 into 32 packed signed bytes in ymm1/m256 using signed saturation under writemask k1. + + + VPMOVUSWB + ymm1/m256 {k1}{z},zmm2 + EVEX.512.F3.0F38.W0 10 /r + + AVX512BW + + Converts 32 packed unsigned word integers from zmm2 into 32 packed unsigned bytes in ymm1/m256 using unsigned saturation under writemask k1. + + + ModRM:r/m(w) + ModRM:reg(r) + NA + NA + + + + PMOVSX--Packed Move with Sign Extend. + + PMOVSXBW + xmm1,xmm2/m64 + 66 0f 38 20 /r + + SSE4_1 + + Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit integers in xmm1. + + + PMOVSXBD + xmm1,xmm2/m32 + 66 0f 38 21 /r + + SSE4_1 + + Sign extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 32-bit integers in xmm1. + + + PMOVSXBQ + xmm1,xmm2/m16 + 66 0f 38 22 /r + + SSE4_1 + + Sign extend 2 packed 8-bit integers in the low 2 bytes of xmm2/m16 to 2 packed 64-bit integers in xmm1. + + + PMOVSXWD + xmm1,xmm2/m64 + 66 0f 38 23/r + + SSE4_1 + + Sign extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit integers in xmm1. + + + PMOVSXWQ + xmm1,xmm2/m32 + 66 0f 38 24 /r + + SSE4_1 + + Sign extend 2 packed 16-bit integers in the low 4 bytes of xmm2/m32 to 2 packed 64-bit integers in xmm1. + + + PMOVSXDQ + xmm1,xmm2/m64 + 66 0f 38 25 /r + + SSE4_1 + + Sign extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit integers in xmm1. + + + VPMOVSXBW + xmm1,xmm2/m64 + VEX.128.66.0F38.WIG 20 /r + + AVX + + Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit integers in xmm1. + + + VPMOVSXBD + xmm1,xmm2/m32 + VEX.128.66.0F38.WIG 21 /r + + AVX + + Sign extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 32-bit integers in xmm1. + + + VPMOVSXBQ + xmm1,xmm2/m16 + VEX.128.66.0F38.WIG 22 /r + + AVX + + Sign extend 2 packed 8-bit integers in the low 2 bytes of xmm2/m16 to 2 packed 64-bit integers in xmm1. + + + VPMOVSXWD + xmm1,xmm2/m64 + VEX.128.66.0F38.WIG 23 /r + + AVX + + Sign extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit integers in xmm1. + + + VPMOVSXWQ + xmm1,xmm2/m32 + VEX.128.66.0F38.WIG 24 /r + + AVX + + Sign extend 2 packed 16-bit integers in the low 4 bytes of xmm2/m32 to 2 packed 64-bit integers in xmm1. + + + VPMOVSXDQ + xmm1,xmm2/m64 + VEX.128.66.0F38.WIG 25 /r + + AVX + + Sign extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit integers in xmm1. + + + VPMOVSXBW + ymm1,xmm2/m128 + VEX.256.66.0F38.WIG 20 /r + + AVX2 + + Sign extend 16 packed 8-bit integers in xmm2/m128 to 16 packed 16-bit integers in ymm1. + + + VPMOVSXBD + ymm1,xmm2/m64 + VEX.256.66.0F38.WIG 21 /r + + AVX2 + + Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 32-bit integers in ymm1. + + + VPMOVSXBQ + ymm1,xmm2/m32 + VEX.256.66.0F38.WIG 22 /r + + AVX2 + + Sign extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 64-bit integers in ymm1. + + + VPMOVSXWD + ymm1,xmm2/m128 + VEX.256.66.0F38.WIG 23 /r + + AVX2 + + Sign extend 8 packed 16-bit integers in the low 16 bytes of xmm2/m128 to 8 packed 32-bit integers in ymm1. + + + VPMOVSXWQ + ymm1,xmm2/m64 + VEX.256.66.0F38.WIG 24 /r + + AVX2 + + Sign extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 64-bit integers in ymm1. + + + VPMOVSXDQ + ymm1,xmm2/m128 + VEX.256.66.0F38.WIG 25 /r + + AVX2 + + Sign extend 4 packed 32-bit integers in the low 16 bytes of xmm2/m128 to 4 packed 64-bit integers in ymm1. + + + VPMOVSXBW + xmm1 {k1}{z},xmm2/m64 + EVEX.128.66.0F38.WIG 20 /r + + AVX512VL + AVX512BW + + Sign extend 8 packed 8-bit integers in xmm2/m64 to 8 packed 16-bit integers in zmm1. + + + VPMOVSXBW + ymm1 {k1}{z},xmm2/m128 + EVEX.256.66.0F38.WIG 20 /r + + AVX512VL + AVX512BW + + Sign extend 16 packed 8-bit integers in xmm2/m128 to 16 packed 16-bit integers in ymm1. + + + VPMOVSXBW + zmm1 {k1}{z},ymm2/m256 + EVEX.512.66.0F38.WIG 20 /r + + AVX512BW + + Sign extend 32 packed 8-bit integers in ymm2/m256 to 32 packed 16-bit integers in zmm1. + + + VPMOVSXBD + xmm1 {k1}{z},xmm2/m32 + EVEX.128.66.0F38.WIG 21 /r + + AVX512VL + AVX512F + + Sign extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 32-bit integers in xmm1 subject to writemask k1. + + + VPMOVSXBD + ymm1 {k1}{z},xmm2/m64 + EVEX.256.66.0F38.WIG 21 /r + + AVX512VL + AVX512F + + Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 32-bit integers in ymm1 subject to writemask k1. + + + VPMOVSXBD + zmm1 {k1}{z},xmm2/m128 + EVEX.512.66.0F38.WIG 21 /r + + AVX512F + + Sign extend 16 packed 8-bit integers in the low 16 bytes of xmm2/m128 to 16 packed 32-bit integers in zmm1 subject to writemask k1. + + + VPMOVSXBQ + xmm1 {k1}{z},xmm2/m16 + EVEX.128.66.0F38.WIG 22 /r + + AVX512VL + AVX512F + + Sign extend 2 packed 8-bit integers in the low 2 bytes of xmm2/m16 to 2 packed 64-bit integers in xmm1 subject to writemask k1. + + + VPMOVSXBQ + ymm1 {k1}{z},xmm2/m32 + EVEX.256.66.0F38.WIG 22 /r + + AVX512VL + AVX512F + + Sign extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 64-bit integers in ymm1 subject to writemask k1. + + + VPMOVSXBQ + zmm1 {k1}{z},xmm2/m64 + EVEX.512.66.0F38.WIG 22 /r + + AVX512F + + Sign extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 64-bit integers in zmm1 subject to writemask k1. + + + VPMOVSXWD + xmm1 {k1}{z},xmm2/m64 + EVEX.128.66.0F38.WIG 23 /r + + AVX512VL + AVX512F + + Sign extend 4 packed 16-bit integers in the low 8 bytes of ymm2/mem to 4 packed 32-bit integers in xmm1 subject to writemask k1. + + + VPMOVSXWD + ymm1 {k1}{z},xmm2/m128 + EVEX.256.66.0F38.WIG 23 /r + + AVX512VL + AVX512F + + Sign extend 8 packed 16-bit integers in the low 16 bytes of ymm2/m128 to 8 packed 32-bit integers in ymm1 subject to writemask k1. + + + VPMOVSXWD + zmm1 {k1}{z},ymm2/m256 + EVEX.512.66.0F38.WIG 23 /r + + AVX512F + + Sign extend 16 packed 16-bit integers in the low 32 bytes of ymm2/m256 to 16 packed 32-bit integers in zmm1 subject to writemask k1. + + + VPMOVSXWQ + xmm1 {k1}{z},xmm2/m32 + EVEX.128.66.0F38.WIG 24 /r + + AVX512VL + AVX512F + + Sign extend 2 packed 16-bit integers in the low 4 bytes of xmm2/m32 to 2 packed 64-bit integers in xmm1 subject to writemask k1. + + + VPMOVSXWQ + ymm1 {k1}{z},xmm2/m64 + EVEX.256.66.0F38.WIG 24 /r + + AVX512VL + AVX512F + + Sign extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 64-bit integers in ymm1 subject to writemask k1. + + + VPMOVSXWQ + zmm1 {k1}{z},xmm2/m128 + EVEX.512.66.0F38.WIG 24 /r + + AVX512F + + Sign extend 8 packed 16-bit integers in the low 16 bytes of xmm2/m128 to 8 packed 64-bit integers in zmm1 subject to writemask k1. + + + VPMOVSXDQ + xmm1 {k1}{z},xmm2/m64 + EVEX.128.66.0F38.W0 25 /r + + AVX512VL + AVX512F + + Sign extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit integers in zmm1 using writemask k1. + + + VPMOVSXDQ + ymm1 {k1}{z},xmm2/m128 + EVEX.256.66.0F38.W0 25 /r + + AVX512VL + AVX512F + + Sign extend 4 packed 32-bit integers in the low 16 bytes of xmm2/m128 to 4 packed 64-bit integers in zmm1 using writemask k1. + + + VPMOVSXDQ + zmm1 {k1}{z},ymm2/m256 + EVEX.512.66.0F38.W0 25 /r + + AVX512F + + Sign extend 8 packed 32-bit integers in the low 32 bytes of ymm2/m256 to 8 packed 64-bit integers in zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + PMOVZX--Packed Move with Zero Extend. + + PMOVZXBW + xmm1,xmm2/m64 + 66 0f 38 30 /r + + SSE4_1 + + Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit integers in xmm1. + + + PMOVZXBD + xmm1,xmm2/m32 + 66 0f 38 31 /r + + SSE4_1 + + Zero extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 32-bit integers in xmm1. + + + PMOVZXBQ + xmm1,xmm2/m16 + 66 0f 38 32 /r + + SSE4_1 + + Zero extend 2 packed 8-bit integers in the low 2 bytes of xmm2/m16 to 2 packed 64-bit integers in xmm1. + + + PMOVZXWD + xmm1,xmm2/m64 + 66 0f 38 33 /r + + SSE4_1 + + Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit integers in xmm1. + + + PMOVZXWQ + xmm1,xmm2/m32 + 66 0f 38 34 /r + + SSE4_1 + + Zero extend 2 packed 16-bit integers in the low 4 bytes of xmm2/m32 to 2 packed 64-bit integers in xmm1. + + + PMOVZXDQ + xmm1,xmm2/m64 + 66 0f 38 35 /r + + SSE4_1 + + Zero extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit integers in xmm1. + + + VPMOVZXBW + xmm1,xmm2/m64 + VEX.128.66.0F38.WIG 30 /r + + AVX + + Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit integers in xmm1. + + + VPMOVZXBD + xmm1,xmm2/m32 + VEX.128.66.0F38.WIG 31 /r + + AVX + + Zero extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 32-bit integers in xmm1. + + + VPMOVZXBQ + xmm1,xmm2/m16 + VEX.128.66.0F38.WIG 32 /r + + AVX + + Zero extend 2 packed 8-bit integers in the low 2 bytes of xmm2/m16 to 2 packed 64-bit integers in xmm1. + + + VPMOVZXWD + xmm1,xmm2/m64 + VEX.128.66.0F38.WIG 33 /r + + AVX + + Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit integers in xmm1. + + + VPMOVZXWQ + xmm1,xmm2/m32 + VEX.128.66.0F38.WIG 34 /r + + AVX + + Zero extend 2 packed 16-bit integers in the low 4 bytes of xmm2/m32 to 2 packed 64-bit integers in xmm1. + + + VPMOVZXDQ + xmm1,xmm2/m64 + VEX.128.66.0F 38.WIG 35 /r + + AVX + + Zero extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit integers in xmm1. + + + VPMOVZXBW + ymm1,xmm2/m128 + VEX.256.66.0F38.WIG 30 /r + + AVX2 + + Zero extend 16 packed 8-bit integers in xmm2/m128 to 16 packed 16-bit integers in ymm1. + + + VPMOVZXBD + ymm1,xmm2/m64 + VEX.256.66.0F38.WIG 31 /r + + AVX2 + + Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 32-bit integers in ymm1. + + + VPMOVZXBQ + ymm1,xmm2/m32 + VEX.256.66.0F38.WIG 32 /r + + AVX2 + + Zero extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 64-bit integers in ymm1. + + + VPMOVZXWD + ymm1,xmm2/m128 + VEX.256.66.0F38.WIG 33 /r + + AVX2 + + Zero extend 8 packed 16-bit integers xmm2/m128 to 8 packed 32-bit integers in ymm1. + + + VPMOVZXWQ + ymm1,xmm2/m64 + VEX.256.66.0F38.WIG 34 /r + + AVX2 + + Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 64-bit integers in xmm1. + + + VPMOVZXDQ + ymm1,xmm2/m128 + VEX.256.66.0F38.WIG 35 /r + + AVX2 + + Zero extend 4 packed 32-bit integers in xmm2/m128 to 4 packed 64-bit integers in ymm1. + + + VPMOVZXBW + xmm1 {k1}{z},xmm2/m64 + EVEX.128.66.0F38 30.WIG /r + + AVX512VL + AVX512BW + + Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 16-bit integers in xmm1. + + + VPMOVZXBW + ymm1 {k1}{z},xmm2/m128 + EVEX.256.66.0F38.WIG 30 /r + + AVX512VL + AVX512BW + + Zero extend 16 packed 8-bit integers in xmm2/m128 to 16 packed 16-bit integers in ymm1. + + + VPMOVZXBW + zmm1 {k1}{z},ymm2/m256 + EVEX.512.66.0F38.WIG 30 /r + + AVX512BW + + Zero extend 32 packed 8-bit integers in ymm2/m256 to 32 packed 16-bit integers in zmm1. + + + VPMOVZXBD + xmm1 {k1}{z},xmm2/m32 + EVEX.128.66.0F38.WIG 31 /r + + AVX512VL + AVX512F + + Zero extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 32-bit integers in xmm1 subject to writemask k1. + + + VPMOVZXBD + ymm1 {k1}{z},xmm2/m64 + EVEX.256.66.0F38.WIG 31 /r + + AVX512VL + AVX512F + + Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 32-bit integers in ymm1 subject to writemask k1. + + + VPMOVZXBD + zmm1 {k1}{z},xmm2/m128 + EVEX.512.66.0F38.WIG 31 /r + + AVX512F + + Zero extend 16 packed 8-bit integers in xmm2/m128 to 16 packed 32-bit integers in zmm1 subject to writemask k1. + + + VPMOVZXBQ + xmm1 {k1}{z},xmm2/m16 + EVEX.128.66.0F38.WIG 32 /r + + AVX512VL + AVX512F + + Zero extend 2 packed 8-bit integers in the low 2 bytes of xmm2/m16 to 2 packed 64-bit integers in xmm1 subject to writemask k1. + + + VPMOVZXBQ + ymm1 {k1}{z},xmm2/m32 + EVEX.256.66.0F38.WIG 32 /r + + AVX512VL + AVX512F + + Zero extend 4 packed 8-bit integers in the low 4 bytes of xmm2/m32 to 4 packed 64-bit integers in ymm1 subject to writemask k1. + + + VPMOVZXBQ + zmm1 {k1}{z},xmm2/m64 + EVEX.512.66.0F38.WIG 32 /r + + AVX512F + + Zero extend 8 packed 8-bit integers in the low 8 bytes of xmm2/m64 to 8 packed 64-bit integers in zmm1 subject to writemask k1. + + + VPMOVZXWD + xmm1 {k1}{z},xmm2/m64 + EVEX.128.66.0F38.WIG 33 /r + + AVX512VL + AVX512F + + Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 32-bit integers in xmm1 subject to writemask k1. + + + VPMOVZXWD + ymm1 {k1}{z},xmm2/m128 + EVEX.256.66.0F38.WIG 33 /r + + AVX512VL + AVX512F + + Zero extend 8 packed 16-bit integers in xmm2/m128 to 8 packed 32-bit integers in zmm1 subject to writemask k1. + + + VPMOVZXWD + zmm1 {k1}{z},ymm2/m256 + EVEX.512.66.0F38.WIG 33 /r + + AVX512F + + Zero extend 16 packed 16-bit integers in ymm2/m256 to 16 packed 32-bit integers in zmm1 subject to writemask k1. + + + VPMOVZXWQ + xmm1 {k1}{z},xmm2/m32 + EVEX.128.66.0F38.WIG 34 /r + + AVX512VL + AVX512F + + Zero extend 2 packed 16-bit integers in the low 4 bytes of xmm2/m32 to 2 packed 64-bit integers in xmm1 subject to writemask k1. + + + VPMOVZXWQ + ymm1 {k1}{z},xmm2/m64 + EVEX.256.66.0F38.WIG 34 /r + + AVX512VL + AVX512F + + Zero extend 4 packed 16-bit integers in the low 8 bytes of xmm2/m64 to 4 packed 64-bit integers in ymm1 subject to writemask k1. + + + VPMOVZXWQ + zmm1 {k1}{z},xmm2/m128 + EVEX.512.66.0F38.WIG 34 /r + + AVX512F + + Zero extend 8 packed 16-bit integers in xmm2/m128 to 8 packed 64-bit integers in zmm1 subject to writemask k1. + + + VPMOVZXDQ + xmm1 {k1}{z},xmm2/m64 + EVEX.128.66.0F38.W0 35 /r + + AVX512VL + AVX512F + + Zero extend 2 packed 32-bit integers in the low 8 bytes of xmm2/m64 to 2 packed 64-bit integers in zmm1 using writemask k1. + + + VPMOVZXDQ + ymm1 {k1}{z},xmm2/m128 + EVEX.256.66.0F38.W0 35 /r + + AVX512VL + AVX512F + + Zero extend 4 packed 32-bit integers in xmm2/m128 to 4 packed 64-bit integers in zmm1 using writemask k1. + + + VPMOVZXDQ + zmm1 {k1}{z},ymm2/m256 + EVEX.512.66.0F38.W0 35 /r + + AVX512F + + Zero extend 8 packed 32-bit integers in ymm2/m256 to 8 packed 64-bit integers in zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + PMULDQ--Multiply Packed Doubleword Integers. + + PMULDQ + xmm1,xmm2/m128 + 66 0F 38 28 /r + + SSE4_1 + + Multiply packed signed doubleword integers in xmm1 by packed signed doubleword integers in xmm2/m128, and store the quadword results in xmm1. + + + VPMULDQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 28 /r + + AVX + + Multiply packed signed doubleword integers in xmm2 by packed signed doubleword integers in xmm3/m128, and store the quadword results in xmm1. + + + VPMULDQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.WIG 28 /r + + AVX2 + + Multiply packed signed doubleword integers in ymm2 by packed signed doubleword integers in ymm3/m256, and store the quadword results in ymm1. + + + VPMULDQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 28 /r + + AVX512VL + AVX512F + + Multiply packed signed doubleword integers in xmm2 by packed signed doubleword integers in xmm3/m128/m64bcst, and store the quadword results in xmm1 using writemask k1. + + + VPMULDQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 28 /r + + AVX512VL + AVX512F + + Multiply packed signed doubleword integers in ymm2 by packed signed doubleword integers in ymm3/m256/m64bcst, and store the quadword results in ymm1 using writemask k1. + + + VPMULDQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 28 /r + + AVX512F + + Multiply packed signed doubleword integers in zmm2 by packed signed doubleword integers in zmm3/m512/m64bcst, and store the quadword results in zmm1 using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMULHRSW--Multiply Packed Unsigned Integers with Round and Scale. + + PMULHRSW + xmm1,xmm2/m128 + 66 0F 38 0B /r + + SSSE3 + + Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1. + + + VPMULHRSW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38 0B /r + + AVX + + Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1. + + + VPMULHRSW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38 0B /r + + AVX2 + + Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to ymm1. + + + VPMULHRSW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.WIG 0B /r + + AVX512VL + AVX512BW + + Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to xmm1 under writemask k1. + + + VPMULHRSW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.WIG 0B /r + + AVX512VL + AVX512BW + + Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to ymm1 under writemask k1. + + + VPMULHRSW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.WIG 0B /r + + AVX512BW + + Multiply 16-bit signed words, scale and round signed doublewords, pack high 16 bits to zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMULHUW--Multiply Packed Unsigned Integers and Store High Result. + + PMULHUW + xmm1,xmm2/m128 + 66 0F E4 /r + + SSE2 + + Multiply the packed unsigned word integers in xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1. + + + VPMULHUW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F E4 /r + + AVX + + Multiply the packed unsigned word integers in xmm2 and xmm3/m128, and store the high 16 bits of the results in xmm1. + + + VPMULHUW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F E4 /r + + AVX2 + + Multiply the packed unsigned word integers in ymm2 and ymm3/m256, and store the high 16 bits of the results in ymm1. + + + VPMULHUW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG E4 /r + + AVX512VL + AVX512BW + + Multiply the packed unsigned word integers in xmm2 and xmm3/m128, and store the high 16 bits of the results in xmm1 under writemask k1. + + + VPMULHUW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG E4 /r + + AVX512VL + AVX512BW + + Multiply the packed unsigned word integers in ymm2 and ymm3/m256, and store the high 16 bits of the results in ymm1 under writemask k1. + + + VPMULHUW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG E4 /r + + AVX512BW + + Multiply the packed unsigned word integers in zmm2 and zmm3/m512, and store the high 16 bits of the results in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMULHW--Multiply Packed Integers and Store High Result. + + PMULHW + xmm1,xmm2/m128 + 66 0F E5 /r + + SSE2 + + Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the high 16 bits of the results in xmm1. + + + VPMULHW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F E5 /r + + AVX + + Multiply the packed signed word integers in xmm2 and xmm3/m128, and store the high 16 bits of the results in xmm1. + + + VPMULHW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F E5 /r + + AVX2 + + Multiply the packed signed word integers in ymm2 and ymm3/m256, and store the high 16 bits of the results in ymm1. + + + VPMULHW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG E5 /r + + AVX512VL + AVX512BW + + Multiply the packed signed word integers in xmm2 and xmm3/m128, and store the high 16 bits of the results in xmm1 under writemask k1. + + + VPMULHW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG E5 /r + + AVX512VL + AVX512BW + + Multiply the packed signed word integers in ymm2 and ymm3/m256, and store the high 16 bits of the results in ymm1 under writemask k1. + + + VPMULHW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG E5 /r + + AVX512BW + + Multiply the packed signed word integers in zmm2 and zmm3/m512, and store the high 16 bits of the results in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMULLD/PMULLQ--Multiply Packed Integers and Store Low Result. + + PMULLD + xmm1,xmm2/m128 + 66 0F 38 40 /r + + SSE4_1 + + Multiply the packed dword signed integers in xmm1 and xmm2/m128 and store the low 32 bits of each product in xmm1. + + + VPMULLD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.WIG 40 /r + + AVX + + Multiply the packed dword signed integers in xmm2 and xmm3/m128 and store the low 32 bits of each product in xmm1. + + + VPMULLD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.WIG 40 /r + + AVX2 + + Multiply the packed dword signed integers in ymm2 and ymm3/m256 and store the low 32 bits of each product in ymm1. + + + VPMULLD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 40 /r + + AVX512VL + AVX512F + + Multiply the packed dword signed integers in xmm2 and xmm3/m128/m32bcst and store the low 32 bits of each product in xmm1 under writemask k1. + + + VPMULLD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 40 /r + + AVX512VL + AVX512F + + Multiply the packed dword signed integers in ymm2 and ymm3/m256/m32bcst and store the low 32 bits of each product in ymm1 under writemask k1. + + + VPMULLD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 40 /r + + AVX512F + + Multiply the packed dword signed integers in zmm2 and zmm3/m512/m32bcst and store the low 32 bits of each product in zmm1 under writemask k1. + + + VPMULLQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 40 /r + + AVX512VL + AVX512DQ + + Multiply the packed qword signed integers in xmm2 and xmm3/m128/m64bcst and store the low 64 bits of each product in xmm1 under writemask k1. + + + VPMULLQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 40 /r + + AVX512VL + AVX512DQ + + Multiply the packed qword signed integers in ymm2 and ymm3/m256/m64bcst and store the low 64 bits of each product in ymm1 under writemask k1. + + + VPMULLQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 40 /r + + AVX512DQ + + Multiply the packed qword signed integers in zmm2 and zmm3/m512/m64bcst and store the low 64 bits of each product in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMULLW--Multiply Packed Integers and Store Low Result. + + PMULLW + xmm1,xmm2/m128 + 66 0F D5 /r + + SSE2 + + Multiply the packed signed word integers in xmm1 and xmm2/m128, and store the low 16 bits of the results in xmm1. + + + VPMULLW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F D5 /r + + AVX + + Multiply the packed signed word integers in xmm2 and xmm3/m128, and store the low 16 bits of the results in xmm1. + + + VPMULLW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F D5 /r + + AVX2 + + Multiply the packed signed word integers in ymm2 and ymm3/m256, and store the low 16 bits of the results in ymm1. + + + VPMULLW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG D5 /r + + AVX512VL + AVX512BW + + Multiply the packed signed word integers in xmm2 and xmm3/m128, and store the low 16 bits of the results in xmm1 under writemask k1. + + + VPMULLW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG D5 /r + + AVX512VL + AVX512BW + + Multiply the packed signed word integers in ymm2 and ymm3/m256, and store the low 16 bits of the results in ymm1 under writemask k1. + + + VPMULLW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG D5 /r + + AVX512BW + + Multiply the packed signed word integers in zmm2 and zmm3/m512, and store the low 16 bits of the results in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPMULTISHIFTQB--Select Packed Unaligned Bytes from Quadword Sources. + + VPMULTISHIFTQB + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 83 /r + + AVX512VBMI + AVX512VL + + Select unaligned bytes from qwords in xmm3/m128/m64bcst using control bytes in xmm2, write byte results to xmm1 under k1. + + + VPMULTISHIFTQB + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 83 /r + + AVX512VBMI + AVX512VL + + Select unaligned bytes from qwords in ymm3/m256/m64bcst using control bytes in ymm2, write byte results to ymm1 under k1. + + + VPMULTISHIFTQB + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 83 /r + + AVX512VBMI + + Select unaligned bytes from qwords in zmm3/m512/m64bcst using control bytes in zmm2, write byte results to zmm1 under k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PMULUDQ--Multiply Packed Unsigned Doubleword Integers. + + PMULUDQ + xmm1,xmm2/m128 + 66 0F F4 /r + + SSE4_1 + + Multiply packed unsigned doubleword integers in xmm1 by packed unsigned doubleword integers in xmm2/m128, and store the quadword results in xmm1. + + + VPMULUDQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG F4 /r + + AVX + + Multiply packed unsigned doubleword integers in xmm2 by packed unsigned doubleword integers in xmm3/m128, and store the quadword results in xmm1. + + + VPMULUDQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG F4 /r + + AVX2 + + Multiply packed unsigned doubleword integers in ymm2 by packed unsigned doubleword integers in ymm3/m256, and store the quadword results in ymm1. + + + VPMULUDQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 F4 /r + + AVX512VL + AVX512F + + Multiply packed unsigned doubleword integers in xmm2 by packed unsigned doubleword integers in xmm3/m128/m64bcst, and store the quadword results in xmm1 under writemask k1. + + + VPMULUDQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 F4 /r + + AVX512VL + AVX512F + + Multiply packed unsigned doubleword integers in ymm2 by packed unsigned doubleword integers in ymm3/m256/m64bcst, and store the quadword results in ymm1 under writemask k1. + + + VPMULUDQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 F4 /r + + AVX512F + + Multiply packed unsigned doubleword integers in zmm2 by packed unsigned doubleword integers in zmm3/m512/m64bcst, and store the quadword results in zmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + POR--Bitwise Logical Or. + + POR + xmm1,xmm2/m128 + 66 0F EB /r + + SSE2 + + Bitwise OR of xmm2/m128 and xmm1. + + + VPOR + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG EB /r + + AVX + + Bitwise OR of xmm2/m128 and xmm3. + + + VPOR + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG EB /r + + AVX2 + + Bitwise OR of ymm2/m256 and ymm3. + + + VPORD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 EB /r + + AVX512VL + AVX512F + + Bitwise OR of packed doubleword integers in xmm2 and xmm3/m128/m32bcst using writemask k1. + + + VPORD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 EB /r + + AVX512VL + AVX512F + + Bitwise OR of packed doubleword integers in ymm2 and ymm3/m256/m32bcst using writemask k1. + + + VPORD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 EB /r + + AVX512F + + Bitwise OR of packed doubleword integers in zmm2 and zmm3/m512/m32bcst using writemask k1. + + + VPORQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 EB /r + + AVX512VL + AVX512F + + Bitwise OR of packed quadword integers in xmm2 and xmm3/m128/m64bcst using writemask k1. + + + VPORQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 EB /r + + AVX512VL + AVX512F + + Bitwise OR of packed quadword integers in ymm2 and ymm3/m256/m64bcst using writemask k1. + + + VPORQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 EB /r + + AVX512F + + Bitwise OR of packed quadword integers in zmm2 and zmm3/m512/m64bcst using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PROLD/PROLVD/PROLQ/PROLVQ--Bit Rotate Left. + + VPROLVD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 15 /r + + AVX512VL + AVX512F + + Rotate doublewords in xmm2 left by count in the corresponding element of xmm3/m128/m32bcst. Result written to xmm1 under writemask k1. + + + VPROLD + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.NDD.128.66.0F.W0 72 /1 ib + + AVX512VL + AVX512F + + Rotate doublewords in xmm2/m128/m32bcst left by imm8. Result written to xmm1 using writemask k1. + + + VPROLVQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 15 /r + + AVX512VL + AVX512F + + Rotate quadwords in xmm2 left by count in the corresponding element of xmm3/m128/m64bcst. Result written to xmm1 under writemask k1. + + + VPROLQ + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.NDD.128.66.0F.W1 72 /1 ib + + AVX512VL + AVX512F + + Rotate quadwords in xmm2/m128/m64bcst left by imm8. Result written to xmm1 using writemask k1. + + + VPROLVD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 15 /r + + AVX512VL + AVX512F + + Rotate doublewords in ymm2 left by count in the corresponding element of ymm3/m256/m32bcst. Result written to ymm1 under writemask k1. + + + VPROLD + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.NDD.256.66.0F.W0 72 /1 ib + + AVX512VL + AVX512F + + Rotate doublewords in ymm2/m256/m32bcst left by imm8. Result written to ymm1 using writemask k1. + + + VPROLVQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 15 /r + + AVX512VL + AVX512F + + Rotate quadwords in ymm2 left by count in the corresponding element of ymm3/m256/m64bcst. Result written to ymm1 under writemask k1. + + + VPROLQ + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.NDD.256.66.0F.W1 72 /1 ib + + AVX512VL + AVX512F + + Rotate quadwords in ymm2/m256/m64bcst left by imm8. Result written to ymm1 using writemask k1. + + + VPROLVD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 15 /r + + AVX512F + + Rotate left of doublewords in zmm2 by count in the corresponding element of zmm3/m512/m32bcst. Result written to zmm1 using writemask k1. + + + VPROLD + zmm1 {k1}{z},zmm2/m512/m32bcst,imm8 + EVEX.NDD.512.66.0F.W0 72 /1 ib + + AVX512F + + Rotate left of doublewords in zmm3/m512/m32bcst by imm8. Result written to zmm1 using writemask k1. + + + VPROLVQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 15 /r + + AVX512F + + Rotate quadwords in zmm2 left by count in the corresponding element of zmm3/m512/m64bcst. Result written to zmm1under writemask k1. + + + VPROLQ + zmm1 {k1}{z},zmm2/m512/m64bcst,imm8 + EVEX.NDD.512.66.0F.W1 72 /1 ib + + AVX512F + + Rotate quadwords in zmm2/m512/m64bcst left by imm8. Result written to zmm1 using writemask k1. + + + VEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PRORD/PRORVD/PRORQ/PRORVQ--Bit Rotate Right. + + VPRORVD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 14 /r + + AVX512VL + AVX512F + + Rotate doublewords in xmm2 right by count in the corresponding element of xmm3/m128/m32bcst, store result using writemask k1. + + + VPRORD + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.NDD.128.66.0F.W0 72 /0 ib + + AVX512VL + AVX512F + + Rotate doublewords in xmm2/m128/m32bcst right by imm8, store result using writemask k1. + + + VPRORVQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 14 /r + + AVX512VL + AVX512F + + Rotate quadwords in xmm2 right by count in the corresponding element of xmm3/m128/m64bcst, store result using writemask k1. + + + VPRORQ + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.NDD.128.66.0F.W1 72 /0 ib + + AVX512VL + AVX512F + + Rotate quadwords in xmm2/m128/m64bcst right by imm8, store result using writemask k1. + + + VPRORVD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 14 /r + + AVX512VL + AVX512F + + Rotate doublewords in ymm2 right by count in the corresponding element of ymm3/m256/m32bcst, store using result writemask k1. + + + VPRORD + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.NDD.256.66.0F.W0 72 /0 ib + + AVX512VL + AVX512F + + Rotate doublewords in ymm2/m256/m32bcst right by imm8, store result using writemask k1. + + + VPRORVQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 14 /r + + AVX512VL + AVX512F + + Rotate quadwords in ymm2 right by count in the corresponding element of ymm3/m256/m64bcst, store result using writemask k1. + + + VPRORQ + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.NDD.256.66.0F.W1 72 /0 ib + + AVX512VL + AVX512F + + Rotate quadwords in ymm2/m256/m64bcst right by imm8, store result using writemask k1. + + + VPRORVD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 14 /r + + AVX512F + + Rotate doublewords in zmm2 right by count in the corresponding element of zmm3/m512/m32bcst, store result using writemask k1. + + + VPRORD + zmm1 {k1}{z},zmm2/m512/m32bcst,imm8 + EVEX.NDD.512.66.0F.W0 72 /0 ib + + AVX512F + + Rotate doublewords in zmm2/m512/m32bcst right by imm8, store result using writemask k1. + + + VPRORVQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 14 /r + + AVX512F + + Rotate quadwords in zmm2 right by count in the corresponding element of zmm3/m512/m64bcst, store result using writemask k1. + + + VPRORQ + zmm1 {k1}{z},zmm2/m512/m64bcst,imm8 + EVEX.NDD.512.66.0F.W1 72 /0 ib + + AVX512F + + Rotate quadwords in zmm2/m512/m64bcst right by imm8, store result using writemask k1. + + + VEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ--Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices. + + VPSCATTERDD + vm32x {k1},xmm1 + EVEX.128.66.0F38.W0 A0 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, scatter dword values to memory using writemask k1. + + + VPSCATTERDD + vm32y {k1},ymm1 + EVEX.256.66.0F38.W0 A0 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, scatter dword values to memory using writemask k1. + + + VPSCATTERDD + vm32z {k1},zmm1 + EVEX.512.66.0F38.W0 A0 /vsib + + AVX512F + + Using signed dword indices, scatter dword values to memory using writemask k1. + + + VPSCATTERDQ + vm32x {k1},xmm1 + EVEX.128.66.0F38.W1 A0 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, scatter qword values to memory using writemask k1. + + + VPSCATTERDQ + vm32x {k1},ymm1 + EVEX.256.66.0F38.W1 A0 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, scatter qword values to memory using writemask k1. + + + VPSCATTERDQ + vm32y {k1},zmm1 + EVEX.512.66.0F38.W1 A0 /vsib + + AVX512F + + Using signed dword indices, scatter qword values to memory using writemask k1. + + + VPSCATTERQD + vm64x {k1},xmm1 + EVEX.128.66.0F38.W0 A1 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, scatter dword values to memory using writemask k1. + + + VPSCATTERQD + vm64y {k1},xmm1 + EVEX.256.66.0F38.W0 A1 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, scatter dword values to memory using writemask k1. + + + VPSCATTERQD + vm64z {k1},ymm1 + EVEX.512.66.0F38.W0 A1 /vsib + + AVX512F + + Using signed qword indices, scatter dword values to memory using writemask k1. + + + VPSCATTERQQ + vm64x {k1},xmm1 + EVEX.128.66.0F38.W1 A1 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, scatter qword values to memory using writemask k1. + + + VPSCATTERQQ + vm64y {k1},ymm1 + EVEX.256.66.0F38.W1 A1 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, scatter qword values to memory using writemask k1. + + + VPSCATTERQQ + vm64z {k1},zmm1 + EVEX.512.66.0F38.W1 A1 /vsib + + AVX512F + + Using signed qword indices, scatter qword values to memory using writemask k1. + + + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + ModRM:reg(r) + NA + NA + + + + PSHUFB--Packed Shuffle Bytes. + + PSHUFB + xmm1,xmm2/m128 + 66 0F 38 00 /r + + SSSE3 + + Shuffle bytes in xmm1 according to contents of xmm2/m128. + + + VPSHUFB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38 00 /r + + AVX + + Shuffle bytes in xmm2 according to contents of xmm3/m128. + + + VPSHUFB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38 00 /r + + AVX2 + + Shuffle bytes in ymm2 according to contents of ymm3/m256. + + + VPSHUFB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.WIG 00 /r + + AVX512VL + AVX512BW + + Shuffle bytes in xmm2 according to contents of xmm3/m128 under write mask k1. + + + VPSHUFB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.WIG 00 /r + + AVX512VL + AVX512BW + + Shuffle bytes in ymm2 according to contents of ymm3/m256 under write mask k1. + + + VPSHUFB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.WIG 00 /r + + AVX512BW + + Shuffle bytes in zmm2 according to contents of zmm3/m512 under write mask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PSHUFHW--Shuffle Packed High Words. + + PSHUFHW + xmm1,xmm2/m128,imm8 + F3 0F 70 /r ib + + SSE2 + + Shuffle the high words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1. + + + VPSHUFHW + xmm1,xmm2/m128,imm8 + VEX.128.F3.0F 70 /r ib + + AVX + + Shuffle the high words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1. + + + VPSHUFHW + ymm1,ymm2/m256,imm8 + VEX.256.F3.0F 70 /r ib + + AVX2 + + Shuffle the high words in ymm2/m256 based on the encoding in imm8 and store the result in ymm1. + + + VPSHUFHW + xmm1 {k1}{z},xmm2/m128,imm8 + EVEX.128.F3.0F.WIG 70 /r ib + + AVX512VL + AVX512BW + + Shuffle the high words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1 under write mask k1. + + + VPSHUFHW + ymm1 {k1}{z},ymm2/m256,imm8 + EVEX.256.F3.0F.WIG 70 /r ib + + AVX512VL + AVX512BW + + Shuffle the high words in ymm2/m256 based on the encoding in imm8 and store the result in ymm1 under write mask k1. + + + VPSHUFHW + zmm1 {k1}{z},zmm2/m512,imm8 + EVEX.512.F3.0F.WIG 70 /r ib + + AVX512BW + + Shuffle the high words in zmm2/m512 based on the encoding in imm8 and store the result in zmm1 under write mask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + PSHUFLW--Shuffle Packed Low Words. + + PSHUFLW + xmm1,xmm2/m128,imm8 + F2 0F 70 /r ib + + SSE2 + + Shuffle the low words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1. + + + VPSHUFLW + xmm1,xmm2/m128,imm8 + VEX.128.F2.0F 70 /r ib + + AVX + + Shuffle the low words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1. + + + VPSHUFLW + ymm1,ymm2/m256,imm8 + VEX.256.F2.0F 70 /r ib + + AVX2 + + Shuffle the low words in ymm2/m256 based on the encoding in imm8 and store the result in ymm1. + + + VPSHUFLW + xmm1 {k1}{z},xmm2/m128,imm8 + EVEX.128.F2.0F.WIG 70 /r ib + + AVX512VL + AVX512BW + + Shuffle the low words in xmm2/m128 based on the encoding in imm8 and store the result in xmm1 under write mask k1. + + + VPSHUFLW + ymm1 {k1}{z},ymm2/m256,imm8 + EVEX.256.F2.0F.WIG 70 /r ib + + AVX512VL + AVX512BW + + Shuffle the low words in ymm2/m256 based on the encoding in imm8 and store the result in ymm1 under write mask k1. + + + VPSHUFLW + zmm1 {k1}{z},zmm2/m512,imm8 + EVEX.512.F2.0F.WIG 70 /r ib + + AVX512BW + + Shuffle the low words in zmm2/m512 based on the encoding in imm8 and store the result in zmm1 under write mask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + PSHUFD--Shuffle Packed Doublewords. + + PSHUFD + xmm1,xmm2/m128,imm8 + 66 0F 70 /r ib + + SSE2 + + Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and store the result in xmm1. + + + VPSHUFD + xmm1,xmm2/m128,imm8 + VEX.128.66.0F.WIG 70 /r ib + + AVX + + Shuffle the doublewords in xmm2/m128 based on the encoding in imm8 and store the result in xmm1. + + + VPSHUFD + ymm1,ymm2/m256,imm8 + VEX.256.66.0F.WIG 70 /r ib + + AVX2 + + Shuffle the doublewords in ymm2/m256 based on the encoding in imm8 and store the result in ymm1. + + + VPSHUFD + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.128.66.0F.W0 70 /r ib + + AVX512VL + AVX512F + + Shuffle the doublewords in xmm2/m128/m32bcst based on the encoding in imm8 and store the result in xmm1 using writemask k1. + + + VPSHUFD + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.256.66.0F.W0 70 /r ib + + AVX512VL + AVX512F + + Shuffle the doublewords in ymm2/m256/m32bcst based on the encoding in imm8 and store the result in ymm1 using writemask k1. + + + VPSHUFD + zmm1 {k1}{z},zmm2/m512/m32bcst,imm8 + EVEX.512.66.0F.W0 70 /r ib + + AVX512F + + Shuffle the doublewords in zmm2/m512/m32bcst based on the encoding in imm8 and store the result in zmm1 using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + PSLLDQ--Byte Shift Left. + + PSLLDQ + xmm1,imm8 + 66 0F 73 /7 ib + + SSE2 + + Shift xmm1 left by imm8 bytes while shifting in 0s and store result in xmm1. + + + VPSLLDQ + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 73 /7 ib + + AVX + + Shift xmm2 left by imm8 bytes while shifting in 0s and store result in xmm1. + + + VPSLLDQ + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 73 /7 ib + + AVX2 + + Shift ymm2 left by imm8 bytes while shifting in 0s and store result in ymm1. + + + VPSLLDQ + xmm1,xmm2/ m128,imm8 + EVEX.NDD.128.66.0F.WIG 73 /7 ib + + AVX512VL + AVX512BW + + Shift xmm2/m128 left by imm8 bytes while shifting in 0s and store result in xmm1. + + + VPSLLDQ + ymm1,ymm2/m256,imm8 + EVEX.NDD.256.66.0F.WIG 73 /7 ib + + AVX512VL + AVX512BW + + Shift ymm2/m256 left by imm8 bytes while shifting in 0s and store result in ymm1. + + + VPSLLDQ + zmm1,zmm2/m512,imm8 + EVEX.NDD.512.66.0F.WIG 73 /7 ib + + AVX512BW + + Shift zmm2/m512 left by imm8 bytes while shifting in 0s and store result in zmm1. + + + ModRM:r/m(r,w) + Imm8 + NA + NA + + + VEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + EVEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + + PSLLW/PSLLD/PSLLQ--Bit Shift Left. + + PSLLW + xmm1,xmm2/m128 + 66 0F F1/r + + SSE2 + + Shift words in xmm1 left by amount specified in xmm2/m128 while shifting in 0s. + + + PSLLW + xmm1,imm8 + 66 0F 71 /6 ib + + SSE2 + + Shift words in xmm1 left by imm8 while shifting in 0s. + + + PSLLD + xmm1,imm8 + 66 0F 72 /6 ib + + SSE2 + + Shift doublewords in xmm1 left by imm8 while shifting in 0s. + + + PSLLQ + xmm1,imm8 + 66 0F 73 /6 ib + + SSE2 + + Shift quadwords in xmm1 left by imm8 while shifting in 0s. + + + VPSLLW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG F1 /r + + AVX + + Shift words in xmm2 left by amount specified in xmm3/m128 while shifting in 0s. + + + VPSLLW + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 71 /6 ib + + AVX + + Shift words in xmm2 left by imm8 while shifting in 0s. + + + VPSLLD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG F2 /r + + AVX + + Shift doublewords in xmm2 left by amount specified in xmm3/m128 while shifting in 0s. + + + VPSLLD + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 72 /6 ib + + AVX + + Shift doublewords in xmm2 left by imm8 while shifting in 0s. + + + VPSLLQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG F3 /r + + AVX + + Shift quadwords in xmm2 left by amount specified in xmm3/m128 while shifting in 0s. + + + VPSLLQ + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 73 /6 ib + + AVX + + Shift quadwords in xmm2 left by imm8 while shifting in 0s. + + + VPSLLW + ymm1,ymm2,xmm3/m128 + VEX.NDS.256.66.0F.WIG F1 /r + + AVX2 + + Shift words in ymm2 left by amount specified in xmm3/m128 while shifting in 0s. + + + VPSLLW + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 71 /6 ib + + AVX2 + + Shift words in ymm2 left by imm8 while shifting in 0s. + + + VPSLLD + ymm1,ymm2,xmm3/m128 + VEX.NDS.256.66.0F.WIG F2 /r + + AVX2 + + Shift doublewords in ymm2 left by amount specified in xmm3/m128 while shifting in 0s. + + + VPSLLD + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 72 /6 ib + + AVX2 + + Shift doublewords in ymm2 left by imm8 while shifting in 0s. + + + VPSLLQ + ymm1,ymm2,xmm3/m128 + VEX.NDS.256.66.0F.WIG F3 /r + + AVX2 + + Shift quadwords in ymm2 left by amount specified in xmm3/m128 while shifting in 0s. + + + VPSLLQ + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 73 /6 ib + + AVX2 + + Shift quadwords in ymm2 left by imm8 while shifting in 0s. + + + VPSLLW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG F1 /r + + AVX512VL + AVX512BW + + Shift words in xmm2 left by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSLLW + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.WIG F1 /r + + AVX512VL + AVX512BW + + Shift words in ymm2 left by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSLLW + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.WIG F1 /r + + AVX512BW + + Shift words in zmm2 left by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSLLW + xmm1 {k1}{z},xmm2/m128,imm8 + EVEX.NDD.128.66.0F.WIG 71 /6 ib + + AVX512VL + AVX512BW + + Shift words in xmm2/m128 left by imm8 while shifting in 0s using writemask k1. + + + VPSLLW + ymm1 {k1}{z},ymm2/m256,imm8 + EVEX.NDD.256.66.0F.WIG 71 /6 ib + + AVX512VL + AVX512BW + + Shift words in ymm2/m256 left by imm8 while shifting in 0s using writemask k1. + + + VPSLLW + zmm1 {k1}{z},zmm2/m512,imm8 + EVEX.NDD.512.66.0F.WIG 71 /6 ib + + AVX512BW + + Shift words in zmm2/m512 left by imm8 while shifting in 0 using writemask k1. + + + VPSLLD + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.W0 F2 /r + + AVX512VL + AVX512F + + Shift doublewords in xmm2 left by amount specified in xmm3/m128 while shifting in 0s under writemask k1. + + + VPSLLD + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.W0 F2 /r + + AVX512VL + AVX512F + + Shift doublewords in ymm2 left by amount specified in xmm3/m128 while shifting in 0s under writemask k1. + + + VPSLLD + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.W0 F2 /r + + AVX512F + + Shift doublewords in zmm2 left by amount specified in xmm3/m128 while shifting in 0s under writemask k1. + + + VPSLLD + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.NDD.128.66.0F.W0 72 /6 ib + + AVX512VL + AVX512F + + Shift doublewords in xmm2/m128/m32bcst left by imm8 while shifting in 0s using writemask k1. + + + VPSLLD + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.NDD.256.66.0F.W0 72 /6 ib + + AVX512VL + AVX512F + + Shift doublewords in ymm2/m256/m32bcst left by imm8 while shifting in 0s using writemask k1. + + + VPSLLD + zmm1 {k1}{z},zmm2/m512/m32bcst,imm8 + EVEX.NDD.512.66.0F.W0 72 /6 ib + + AVX512F + + Shift doublewords in zmm2/m512/m32bcst left by imm8 while shifting in 0s using writemask k1. + + + VPSLLQ + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.W1 F3 /r + + AVX512VL + AVX512F + + Shift quadwords in xmm2 left by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSLLQ + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.W1 F3 /r + + AVX512VL + AVX512F + + Shift quadwords in ymm2 left by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSLLQ + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.W1 F3 /r + + AVX512F + + Shift quadwords in zmm2 left by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSLLQ + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.NDD.128.66.0F.W1 73 /6 ib + + AVX512VL + AVX512F + + Shift quadwords in xmm2/m128/m64bcst left by imm8 while shifting in 0s using writemask k1. + + + VPSLLQ + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.NDD.256.66.0F.W1 73 /6 ib + + AVX512VL + AVX512F + + Shift quadwords in ymm2/m256/m64bcst left by imm8 while shifting in 0s using writemask k1. + + + VPSLLQ + zmm1 {k1}{z},zmm2/m512/m64bcst,imm8 + EVEX.NDD.512.66.0F.W1 73 /6 ib + + AVX512F + + Shift quadwords in zmm2/m512/m64bcst left by imm8 while shifting in 0s using writemask k1. + + + ModRM:r/m(r,w) + Imm8 + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + VEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + EVEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + EVEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PSRAW/PSRAD/PSRAQ--Bit Shift Arithmetic Right. + + PSRAW + xmm1,xmm2/m128 + 66 0F E1/r + + SSE2 + + Shift words in xmm1 right by amount specified in xmm2/m128 while shifting in sign bits. + + + PSRAW + xmm1,imm8 + 66 0F 71 /4 ib + + SSE2 + + Shift words in xmm1 right by imm8 while shifting in sign bits. + + + PSRAD + xmm1,xmm2/m128 + 66 0F E2 /r + + SSE2 + + Shift doublewords in xmm1 right by amount specified in xmm2/m128 while shifting in sign bits. + + + PSRAD + xmm1,imm8 + 66 0F 72 /4 ib + + SSE2 + + Shift doublewords in xmm1 right by imm8 while shifting in sign bits. + + + VPSRAW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG E1 /r + + AVX + + Shift words in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits. + + + VPSRAW + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 71 /4 ib + + AVX + + Shift words in xmm2 right by imm8 while shifting in sign bits. + + + VPSRAD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG E2 /r + + AVX + + Shift doublewords in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits. + + + VPSRAD + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 72 /4 ib + + AVX + + Shift doublewords in xmm2 right by imm8 while shifting in sign bits. + + + VPSRAW + ymm1,ymm2,ymm3/m128 + VEX.NDS.256.66.0F.WIG E1 /r + + AVX2 + + Shift words in ymm2 right by amount specified in ymm3/m128 while shifting in sign bits. + + + VPSRAW + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 71 /4 ib + + AVX2 + + Shift words in ymm2 right by imm8 while shifting in sign bits. + + + VPSRAD + ymm1,ymm2,xmm3/m128 + VEX.NDS.256.66.0F.WIG E2 /r + + AVX2 + + Shift doublewords in ymm2 right by amount specified in ymm3/m128 while shifting in sign bits. + + + VPSRAD + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 72 /4 ib + + AVX2 + + Shift doublewords in ymm2 right by imm8 while shifting in sign bits. + + + VPSRAW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG E1 /r + + AVX512VL + AVX512BW + + Shift words in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAW + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.WIG E1 /r + + AVX512VL + AVX512BW + + Shift words in ymm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAW + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.WIG E1 /r + + AVX512BW + + Shift words in zmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAW + xmm1 {k1}{z},xmm2/m128,imm8 + EVEX.NDD.128.66.0F.WIG 71 /4 ib + + AVX512VL + AVX512BW + + Shift words in xmm2/m128 right by imm8 while shifting in sign bits using writemask k1. + + + VPSRAW + ymm1 {k1}{z},ymm2/m256,imm8 + EVEX.NDD.256.66.0F.WIG 71 /4 ib + + AVX512VL + AVX512BW + + Shift words in ymm2/m256 right by imm8 while shifting in sign bits using writemask k1. + + + VPSRAW + zmm1 {k1}{z},zmm2/m512,imm8 + EVEX.NDD.512.66.0F.WIG 71 /4 ib + + AVX512BW + + Shift words in zmm2/m512 right by imm8 while shifting in sign bits using writemask k1. + + + VPSRAD + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.W0 E2 /r + + AVX512VL + AVX512F + + Shift doublewords in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAD + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.W0 E2 /r + + AVX512VL + AVX512F + + Shift doublewords in ymm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAD + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.W0 E2 /r + + AVX512F + + Shift doublewords in zmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAD + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.NDD.128.66.0F.W0 72 /4 ib + + AVX512VL + AVX512F + + Shift doublewords in xmm2/m128/m32bcst right by imm8 while shifting in sign bits using writemask k1. + + + VPSRAD + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.NDD.256.66.0F.W0 72 /4 ib + + AVX512VL + AVX512F + + Shift doublewords in ymm2/m256/m32bcst right by imm8 while shifting in sign bits using writemask k1. + + + VPSRAD + zmm1 {k1}{z},zmm2/m512/m32bcst,imm8 + EVEX.NDD.512.66.0F.W0 72 /4 ib + + AVX512F + + Shift doublewords in zmm2/m512/m32bcst right by imm8 while shifting in sign bits using writemask k1. + + + VPSRAQ + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.W1 E2 /r + + AVX512VL + AVX512F + + Shift quadwords in xmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAQ + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.W1 E2 /r + + AVX512VL + AVX512F + + Shift quadwords in ymm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAQ + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.W1 E2 /r + + AVX512F + + Shift quadwords in zmm2 right by amount specified in xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAQ + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.NDD.128.66.0F.W1 72 /4 ib + + AVX512VL + AVX512F + + Shift quadwords in xmm2/m128/m64bcst right by imm8 while shifting in sign bits using writemask k1. + + + VPSRAQ + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.NDD.256.66.0F.W1 72 /4 ib + + AVX512VL + AVX512F + + Shift quadwords in ymm2/m256/m64bcst right by imm8 while shifting in sign bits using writemask k1. + + + VPSRAQ + zmm1 {k1}{z},zmm2/m512/m64bcst,imm8 + EVEX.NDD.512.66.0F.W1 72 /4 ib + + AVX512F + + Shift quadwords in zmm2/m512/m64bcst right by imm8 while shifting in sign bits using writemask k1. + + + ModRM:r/m(r,w) + Imm8 + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + VEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + EVEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + EVEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PSRLDQ--Byte Shift Right. + + PSRLDQ + xmm1,imm8 + 66 0F 73 /3 ib + + SSE2 + + Shift xmm1 right by imm8 bytes while shifting in 0s and store result in xmm1. + + + VPSRLDQ + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F 73 /3 ib + + AVX + + Shift xmm2 right by imm8 bytes while shifting in 0s and store result in xmm1. + + + VPSRLDQ + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F 73 /3 ib + + AVX2 + + Shift ymm2 right by imm8 bytes while shifting in 0s and store result in ymm1. + + + VPSRLDQ + xmm1,xmm2/m128,imm8 + EVEX.NDD.128.66.0F.WIG 73 /3 ib + + AVX512VL + AVX512BW + + Shift xmm2/m128 right by imm8 bytes while shifting in 0s and store result in xmm1. + + + VPSRLDQ + ymm1,ymm2/m256,imm8 + EVEX.NDD.256.66.0F.WIG 73 /3 ib + + AVX512VL + AVX512BW + + Shift ymm2/m256 right by imm8 bytes while shifting in 0s and store result in ymm1. + + + VPSRLDQ + zmm1,zmm2/m512,imm8 + EVEX.NDD.512.66.0F.WIG 73 /3 ib + + AVX512BW + + Shift zmm2/m512 right by imm8 bytes while shifting in 0s and store result in zmm1. + + + ModRM:r/m(r,w) + Imm8 + NA + NA + + + VEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + EVEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + + PSRLW/PSRLD/PSRLQ--Shift Packed Data Right Logical. + + PSRLW + xmm1,xmm2/m128 + 66 0F D1 /r + + SSE2 + + Shift words in xmm1 right by amount specified in xmm2/m128 while shifting in 0s. + + + PSRLW + xmm1,imm8 + 66 0F 71 /2 ib + + SSE2 + + Shift words in xmm1 right by imm8 while shifting in 0s. + + + PSRLD + xmm1,xmm2/m128 + 66 0F D2 /r + + SSE2 + + Shift doublewords in xmm1 right by amount specified in xmm2/m128 while shifting in 0s. + + + PSRLD + xmm1,imm8 + 66 0F 72 /2 ib + + SSE2 + + Shift doublewords in xmm1 right by imm8 while shifting in 0s. + + + PSRLQ + xmm1,xmm2/m128 + 66 0F D3 /r + + SSE2 + + Shift quadwords in xmm1 right by amount specified in xmm2/m128 while shifting in 0s. + + + PSRLQ + xmm1,imm8 + 66 0F 73 /2 ib + + SSE2 + + Shift quadwords in xmm1 right by imm8 while shifting in 0s. + + + VPSRLW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG D1 /r + + AVX + + Shift words in xmm2 right by amount specified in xmm3/m128 while shifting in 0s. + + + VPSRLW + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 71 /2 ib + + AVX + + Shift words in xmm2 right by imm8 while shifting in 0s. + + + VPSRLD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG D2 /r + + AVX + + Shift doublewords in xmm2 right by amount specified in xmm3/m128 while shifting in 0s. + + + VPSRLD + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 72 /2 ib + + AVX + + Shift doublewords in xmm2 right by imm8 while shifting in 0s. + + + VPSRLQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG D3 /r + + AVX + + Shift quadwords in xmm2 right by amount specified in xmm3/m128 while shifting in 0s. + + + VPSRLQ + xmm1,xmm2,imm8 + VEX.NDD.128.66.0F.WIG 73 /2 ib + + AVX + + Shift quadwords in xmm2 right by imm8 while shifting in 0s. + + + VPSRLW + ymm1,ymm2,xmm3/m128 + VEX.NDS.256.66.0F.WIG D1 /r + + AVX2 + + Shift words in ymm2 right by amount specified in xmm3/m128 while shifting in 0s. + + + VPSRLW + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 71 /2 ib + + AVX2 + + Shift words in ymm2 right by imm8 while shifting in 0s. + + + VPSRLD + ymm1,ymm2,xmm3/m128 + VEX.NDS.256.66.0F.WIG D2 /r + + AVX2 + + Shift doublewords in ymm2 right by amount specified in xmm3/m128 while shifting in 0s. + + + VPSRLD + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 72 /2 ib + + AVX2 + + Shift doublewords in ymm2 right by imm8 while shifting in 0s. + + + VPSRLQ + ymm1,ymm2,xmm3/m128 + VEX.NDS.256.66.0F.WIG D3 /r + + AVX2 + + Shift quadwords in ymm2 right by amount specified in xmm3/m128 while shifting in 0s. + + + VPSRLQ + ymm1,ymm2,imm8 + VEX.NDD.256.66.0F.WIG 73 /2 ib + + AVX2 + + Shift quadwords in ymm2 right by imm8 while shifting in 0s. + + + VPSRLW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG D1 /r + + AVX512VL + AVX512BW + + Shift words in xmm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLW + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.WIG D1 /r + + AVX512VL + AVX512BW + + Shift words in ymm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLW + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.WIG D1 /r + + AVX512BW + + Shift words in zmm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLW + xmm1 {k1}{z},xmm2/m128,imm8 + EVEX.NDD.128.66.0F.WIG 71 /2 ib + + AVX512VL + AVX512BW + + Shift words in xmm2/m128 right by imm8 while shifting in 0s using writemask k1. + + + VPSRLW + ymm1 {k1}{z},ymm2/m256,imm8 + EVEX.NDD.256.66.0F.WIG 71 /2 ib + + AVX512VL + AVX512BW + + Shift words in ymm2/m256 right by imm8 while shifting in 0s using writemask k1. + + + VPSRLW + zmm1 {k1}{z},zmm2/m512,imm8 + EVEX.NDD.512.66.0F.WIG 71 /2 ib + + AVX512BW + + Shift words in zmm2/m512 right by imm8 while shifting in 0s using writemask k1. + + + VPSRLD + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.W0 D2 /r + + AVX512VL + AVX512F + + Shift doublewords in xmm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLD + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.W0 D2 /r + + AVX512VL + AVX512F + + Shift doublewords in ymm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLD + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.W0 D2 /r + + AVX512F + + Shift doublewords in zmm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLD + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.NDD.128.66.0F.W0 72 /2 ib + + AVX512VL + AVX512F + + Shift doublewords in xmm2/m128/m32bcst right by imm8 while shifting in 0s using writemask k1. + + + VPSRLD + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.NDD.256.66.0F.W0 72 /2 ib + + AVX512VL + AVX512F + + Shift doublewords in ymm2/m256/m32bcst right by imm8 while shifting in 0s using writemask k1. + + + VPSRLD + zmm1 {k1}{z},zmm2/m512/m32bcst,imm8 + EVEX.NDD.512.66.0F.W0 72 /2 ib + + AVX512F + + Shift doublewords in zmm2/m512/m32bcst right by imm8 while shifting in 0s using writemask k1. + + + VPSRLQ + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.W1 D3 /r + + AVX512VL + AVX512F + + Shift quadwords in xmm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLQ + ymm1 {k1}{z},ymm2,xmm3/m128 + EVEX.NDS.256.66.0F.W1 D3 /r + + AVX512VL + AVX512F + + Shift quadwords in ymm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLQ + zmm1 {k1}{z},zmm2,xmm3/m128 + EVEX.NDS.512.66.0F.W1 D3 /r + + AVX512F + + Shift quadwords in zmm2 right by amount specified in xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLQ + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.NDD.128.66.0F.W1 73 /2 ib + + AVX512VL + AVX512F + + Shift quadwords in xmm2/m128/m64bcst right by imm8 while shifting in 0s using writemask k1. + + + VPSRLQ + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.NDD.256.66.0F.W1 73 /2 ib + + AVX512VL + AVX512F + + Shift quadwords in ymm2/m256/m64bcst right by imm8 while shifting in 0s using writemask k1. + + + VPSRLQ + zmm1 {k1}{z},zmm2/m512/m64bcst,imm8 + EVEX.NDD.512.66.0F.W1 73 /2 ib + + AVX512F + + Shift quadwords in zmm2/m512/m64bcst right by imm8 while shifting in 0s using writemask k1. + + + ModRM:r/m(r,w) + Imm8 + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + VEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + EVEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + EVEX.vvvv(w) + ModRM:r/m(R) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPSLLVW/VPSLLVD/VPSLLVQ--Variable Bit Shift Left Logical. + + VPSLLVD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 47 /r + + AVX2 + + Shift doublewords in xmm2 left by amount specified in the corresponding element of xmm3/m128 while shifting in 0s. + + + VPSLLVQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 47 /r + + AVX2 + + Shift quadwords in xmm2 left by amount specified in the corresponding element of xmm3/m128 while shifting in 0s. + + + VPSLLVD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 47 /r + + AVX2 + + Shift doublewords in ymm2 left by amount specified in the corresponding element of ymm3/m256 while shifting in 0s. + + + VPSLLVQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 47 /r + + AVX2 + + Shift quadwords in ymm2 left by amount specified in the corresponding element of ymm3/m256 while shifting in 0s. + + + VPSLLVW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W1 12 /r + + AVX512VL + AVX512BW + + Shift words in xmm2 left by amount specified in the corresponding element of xmm3/m128 while shifting in 0s using writemask k1. + + + VPSLLVW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W1 12 /r + + AVX512VL + AVX512BW + + Shift words in ymm2 left by amount specified in the corresponding element of ymm3/m256 while shifting in 0s using writemask k1. + + + VPSLLVW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W1 12 /r + + AVX512BW + + Shift words in zmm2 left by amount specified in the corresponding element of zmm3/m512 while shifting in 0s using writemask k1. + + + VPSLLVD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 47 /r + + AVX512VL + AVX512F + + Shift doublewords in xmm2 left by amount specified in the corresponding element of xmm3/m128/m32bcst while shifting in 0s using writemask k1. + + + VPSLLVD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 47 /r + + AVX512VL + AVX512F + + Shift doublewords in ymm2 left by amount specified in the corresponding element of ymm3/m256/m32bcst while shifting in 0s using writemask k1. + + + VPSLLVD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 47 /r + + AVX512F + + Shift doublewords in zmm2 left by amount specified in the corresponding element of zmm3/m512/m32bcst while shifting in 0s using writemask k1. + + + VPSLLVQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 47 /r + + AVX512VL + AVX512F + + Shift quadwords in xmm2 left by amount specified in the corresponding element of xmm3/m128/m64bcst while shifting in 0s using writemask k1. + + + VPSLLVQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 47 /r + + AVX512VL + AVX512F + + Shift quadwords in ymm2 left by amount specified in the corresponding element of ymm3/m256/m64bcst while shifting in 0s using writemask k1. + + + VPSLLVQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 47 /r + + AVX512F + + Shift quadwords in zmm2 left by amount specified in the corresponding element of zmm3/m512/m64bcst while shifting in 0s using writemask k1. + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPSRLVW/VPSRLVD/VPSRLVQ--Variable Bit Shift Right Logical. + + VPSRLVD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 45 /r + + AVX2 + + Shift doublewords in xmm2 right by amount specified in the corresponding element of xmm3/m128 while shifting in 0s. + + + VPSRLVQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W1 45 /r + + AVX2 + + Shift quadwords in xmm2 right by amount specified in the corresponding element of xmm3/m128 while shifting in 0s. + + + VPSRLVD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 45 /r + + AVX2 + + Shift doublewords in ymm2 right by amount specified in the corresponding element of ymm3/m256 while shifting in 0s. + + + VPSRLVQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W1 45 /r + + AVX2 + + Shift quadwords in ymm2 right by amount specified in the corresponding element of ymm3/m256 while shifting in 0s. + + + VPSRLVW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W1 10 /r + + AVX512VL + AVX512BW + + Shift words in xmm2 right by amount specified in the corresponding element of xmm3/m128 while shifting in 0s using writemask k1. + + + VPSRLVW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W1 10 /r + + AVX512VL + AVX512BW + + Shift words in ymm2 right by amount specified in the corresponding element of ymm3/m256 while shifting in 0s using writemask k1. + + + VPSRLVW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W1 10 /r + + AVX512BW + + Shift words in zmm2 right by amount specified in the corresponding element of zmm3/m512 while shifting in 0s using writemask k1. + + + VPSRLVD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 45 /r + + AVX512VL + AVX512F + + Shift doublewords in xmm2 right by amount specified in the corresponding element of xmm3/m128/m32bcst while shifting in 0s using writemask k1. + + + VPSRLVD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 45 /r + + AVX512VL + AVX512F + + Shift doublewords in ymm2 right by amount specified in the corresponding element of ymm3/m256/m32bcst while shifting in 0s using writemask k1. + + + VPSRLVD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 45 /r + + AVX512F + + Shift doublewords in zmm2 right by amount specified in the corresponding element of zmm3/m512/m32bcst while shifting in 0s using writemask k1. + + + VPSRLVQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 45 /r + + AVX512VL + AVX512F + + Shift quadwords in xmm2 right by amount specified in the corresponding element of xmm3/m128/m64bcst while shifting in 0s using writemask k1. + + + VPSRLVQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 45 /r + + AVX512VL + AVX512F + + Shift quadwords in ymm2 right by amount specified in the corresponding element of ymm3/m256/m64bcst while shifting in 0s using writemask k1. + + + VPSRLVQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 45 /r + + AVX512F + + Shift quadwords in zmm2 right by amount specified in the corresponding element of zmm3/m512/m64bcst while shifting in 0s using writemask k1. + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PSUBB/PSUBW/PSUBD/PSUBQ--Packed Integer Subtract. + + PSUBB + xmm1,xmm2/m128 + 66 0F F8 /r + + SSE2 + + Subtract packed byte integers in xmm2/m128 from xmm1. + + + PSUBW + xmm1,xmm2/m128 + 66 0F F9 /r + + SSE2 + + Subtract packed word integers in xmm2/m128 from xmm1. + + + PSUBD + xmm1,xmm2/m128 + 66 0F FA /r + + SSE2 + + Subtract packed doubleword integers in xmm2/m128 from xmm1. + + + PSUBQ + xmm1,xmm2/m128 + 66 0F FB/r + + SSE2 + + Subtract packed quadword integers in xmm2/m128 from xmm1. + + + VPSUBB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG F8 /r + + AVX + + Subtract packed byte integers in xmm3/m128 from xmm2. + + + VPSUBW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG F9 /r + + AVX + + Subtract packed word integers in xmm3/m128 from xmm2. + + + VPSUBD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG FA /r + + AVX + + Subtract packed doubleword integers in xmm3/m128 from xmm2. + + + VPSUBQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG FB/r + + AVX + + Subtract packed quadword integers in xmm3/m128 from xmm2. + + + VPSUBB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG F8 /r + + AVX2 + + Subtract packed byte integers in ymm3/m256 from ymm2. + + + VPSUBW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG F9 /r + + AVX2 + + Subtract packed word integers in ymm3/m256 from ymm2. + + + VPSUBD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG FA /r + + AVX2 + + Subtract packed doubleword integers in ymm3/m256 from ymm2. + + + VPSUBQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG FB/r + + AVX2 + + Subtract packed quadword integers in ymm3/m256 from ymm2. + + + VPSUBB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG F8 /r + + AVX512VL + AVX512BW + + Subtract packed byte integers in xmm3/m128 from xmm2 and store in xmm1 using writemask k1. + + + VPSUBB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG F8 /r + + AVX512VL + AVX512BW + + Subtract packed byte integers in ymm3/m256 from ymm2 and store in ymm1 using writemask k1. + + + VPSUBB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG F8 /r + + AVX512BW + + Subtract packed byte integers in zmm3/m512 from zmm2 and store in zmm1 using writemask k1. + + + VPSUBW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG F9 /r + + AVX512VL + AVX512BW + + Subtract packed word integers in xmm3/m128 from xmm2 and store in xmm1 using writemask k1. + + + VPSUBW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG F9 /r + + AVX512VL + AVX512BW + + Subtract packed word integers in ymm3/m256 from ymm2 and store in ymm1 using writemask k1. + + + VPSUBW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG F9 /r + + AVX512BW + + Subtract packed word integers in zmm3/m512 from zmm2 and store in zmm1 using writemask k1. + + + VPSUBD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 FA /r + + AVX512VL + AVX512F + + Subtract packed doubleword integers in xmm3/m128/m32bcst from xmm2 and store in xmm1 using writemask k1. + + + VPSUBD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 FA /r + + AVX512VL + AVX512F + + Subtract packed doubleword integers in ymm3/m256/m32bcst from ymm2 and store in ymm1 using writemask k1. + + + VPSUBD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 FA /r + + AVX512F + + Subtract packed doubleword integers in zmm3/m512/m32bcst from zmm2 and store in zmm1 using writemask k1. + + + VPSUBQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 FB /r + + AVX512VL + AVX512F + + Subtract packed quadword integers in xmm3/m128/m64bcst from xmm2 and store in xmm1 using writemask k1. + + + VPSUBQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 FB /r + + AVX512VL + AVX512F + + Subtract packed quadword integers in ymm3/m256/m64bcst from ymm2 and store in ymm1 using writemask k1. + + + VPSUBQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 FB/r + + AVX512F + + Subtract packed quadword integers in zmm3/m512/m64bcst from zmm2 and store in zmm1 using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PSUBSB/PSUBSW--Subtract Packed Signed Integers with Signed Saturation. + + PSUBSB + xmm1,xmm2/m128 + 66 0F E8 /r + + SSE2 + + Subtract packed signed byte integers in xmm2/m128 from packed signed byte integers in xmm1 and saturate results. + + + PSUBSW + xmm1,xmm2/m128 + 66 0F E9 /r + + SSE2 + + Subtract packed signed word integers in xmm2/m128 from packed signed word integers in xmm1 and saturate results. + + + VPSUBSB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F E8 /r + + AVX + + Subtract packed signed byte integers in xmm3/m128 from packed signed byte integers in xmm2 and saturate results. + + + VPSUBSW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F E9 /r + + AVX + + Subtract packed signed word integers in xmm3/m128 from packed signed word integers in xmm2 and saturate results. + + + VPSUBSB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F E8 /r + + AVX2 + + Subtract packed signed byte integers in ymm3/m256 from packed signed byte integers in ymm2 and saturate results. + + + VPSUBSW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F E9 /r + + AVX2 + + Subtract packed signed word integers in ymm3/m256 from packed signed word integers in ymm2 and saturate results. + + + VPSUBSB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG E8 /r + + AVX512VL + AVX512BW + + Subtract packed signed byte integers in xmm3/m128 from packed signed byte integers in xmm2 and saturate results and store in xmm1 using writemask k1. + + + VPSUBSB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG E8 /r + + AVX512VL + AVX512BW + + Subtract packed signed byte integers in ymm3/m256 from packed signed byte integers in ymm2 and saturate results and store in ymm1 using writemask k1. + + + VPSUBSB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG E8 /r + + AVX512BW + + Subtract packed signed byte integers in zmm3/m512 from packed signed byte integers in zmm2 and saturate results and store in zmm1 using writemask k1. + + + VPSUBSW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG E9 /r + + AVX512VL + AVX512BW + + Subtract packed signed word integers in xmm3/m128 from packed signed word integers in xmm2 and saturate results and store in xmm1 using writemask k1. + + + VPSUBSW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG E9 /r + + AVX512VL + AVX512BW + + Subtract packed signed word integers in ymm3/m256 from packed signed word integers in ymm2 and saturate results and store in ymm1 using writemask k1. + + + VPSUBSW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG E9 /r + + AVX512BW + + Subtract packed signed word integers in zmm3/m512 from packed signed word integers in zmm2 and saturate results and store in zmm1 using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PSUBUSB/PSUBUSW--Subtract Packed Unsigned Integers with Unsigned Saturation. + + PSUBUSB + xmm1,xmm2/m128 + 66 0F D8 /r + + SSE2 + + Subtract packed unsigned byte integers in xmm2/m128 from packed unsigned byte integers in xmm1 and saturate result. + + + PSUBUSW + xmm1,xmm2/m128 + 66 0F D9 /r + + SSE2 + + Subtract packed unsigned word integers in xmm2/m128 from packed unsigned word integers in xmm1 and saturate result. + + + VPSUBUSB + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F D8 /r + + AVX + + Subtract packed unsigned byte integers in xmm3/m128 from packed unsigned byte integers in xmm2 and saturate result. + + + VPSUBUSW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F D9 /r + + AVX + + Subtract packed unsigned word integers in xmm3/m128 from packed unsigned word integers in xmm2 and saturate result. + + + VPSUBUSB + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F D8 /r + + AVX2 + + Subtract packed unsigned byte integers in ymm3/m256 from packed unsigned byte integers in ymm2 and saturate result. + + + VPSUBUSW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F D9 /r + + AVX2 + + Subtract packed unsigned word integers in ymm3/m256 from packed unsigned word integers in ymm2 and saturate result. + + + VPSUBUSB + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG D8 /r + + AVX512VL + AVX512BW + + Subtract packed unsigned byte integers in xmm3/m128 from packed unsigned byte integers in xmm2, saturate results and store in xmm1 using writemask k1. + + + VPSUBUSB + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG D8 /r + + AVX512VL + AVX512BW + + Subtract packed unsigned byte integers in ymm3/m256 from packed unsigned byte integers in ymm2, saturate results and store in ymm1 using writemask k1. + + + VPSUBUSB + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG D8 /r + + AVX512BW + + Subtract packed unsigned byte integers in zmm3/m512 from packed unsigned byte integers in zmm2, saturate results and store in zmm1 using writemask k1. + + + VPSUBUSW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG D9 /r + + AVX512VL + AVX512BW + + Subtract packed unsigned word integers in xmm3/m128 from packed unsigned word integers in xmm2 and saturate results and store in xmm1 using writemask k1. + + + VPSUBUSW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG D9 /r + + AVX512VL + AVX512BW + + Subtract packed unsigned word integers in ymm3/m256 from packed unsigned word integers in ymm2, saturate results and store in ymm1 using writemask k1. + + + VPSUBUSW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG D9 /r + + AVX512BW + + Subtract packed unsigned word integers in zmm3/m512 from packed unsigned word integers in zmm2, saturate results and store in zmm1 using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPTESTNMB/W/D/Q--Logical NAND and Set. + + VPTESTNMB + k2 {k1},xmm2,xmm3/m128 + EVEX.NDS.128.F3.0F38.W0 26 /r + + AVX512VL + AVX512BW + + Bitwise NAND of packed byte integers in xmm2 and xmm3/m128 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMB + k2 {k1},ymm2,ymm3/m256 + EVEX.NDS.256.F3.0F38.W0 26 /r + + AVX512VL + AVX512BW + + Bitwise NAND of packed byte integers in ymm2 and ymm3/m256 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMB + k2 {k1},zmm2,zmm3/m512 + EVEX.NDS.512.F3.0F38.W0 26 /r + + AVX512F + AVX512BW + + Bitwise NAND of packed byte integers in zmm2 and zmm3/m512 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMW + k2 {k1},xmm2,xmm3/m128 + EVEX.NDS.128.F3.0F38.W1 26 /r + + AVX512VL + AVX512BW + + Bitwise NAND of packed word integers in xmm2 and xmm3/m128 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMW + k2 {k1},ymm2,ymm3/m256 + EVEX.NDS.256.F3.0F38.W1 26 /r + + AVX512VL + AVX512BW + + Bitwise NAND of packed word integers in ymm2 and ymm3/m256 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMW + k2 {k1},zmm2,zmm3/m512 + EVEX.NDS.512.F3.0F38.W1 26 /r + + AVX512F + AVX512BW + + Bitwise NAND of packed word integers in zmm2 and zmm3/m512 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMD + k2 {k1},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.F3.0F38.W0 27 /r + + AVX512VL + AVX512F + + Bitwise NAND of packed doubleword integers in xmm2 and xmm3/m128/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMD + k2 {k1},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.F3.0F38.W0 27 /r + + AVX512VL + AVX512F + + Bitwise NAND of packed doubleword integers in ymm2 and ymm3/m256/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMD + k2 {k1},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.F3.0F38.W0 27 /r + + AVX512F + + Bitwise NAND of packed doubleword integers in zmm2 and zmm3/m512/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMQ + k2 {k1},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.F3.0F38.W1 27 /r + + AVX512VL + AVX512F + + Bitwise NAND of packed quadword integers in xmm2 and xmm3/m128/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMQ + k2 {k1},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.F3.0F38.W1 27 /r + + AVX512VL + AVX512F + + Bitwise NAND of packed quadword integers in ymm2 and ymm3/m256/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTNMQ + k2 {k1},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.F3.0F38.W1 27 /r + + AVX512F + + Bitwise NAND of packed quadword integers in zmm2 and zmm3/m512/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ--Unpack High Data. + + PUNPCKHBW + xmm1,xmm2/m128 + 66 0F 68 /r + + SSE2 + + Interleave high-order bytes from xmm1 and xmm2/m128 into xmm1. + + + PUNPCKHWD + xmm1,xmm2/m128 + 66 0F 69 /r + + SSE2 + + Interleave high-order words from xmm1 and xmm2/m128 into xmm1. + + + PUNPCKHDQ + xmm1,xmm2/m128 + 66 0F 6A /r + + SSE2 + + Interleave high-order doublewords from xmm1 and xmm2/m128 into xmm1. + + + PUNPCKHQDQ + xmm1,xmm2/m128 + 66 0F 6D /r + + SSE2 + + Interleave high-order quadword from xmm1 and xmm2/m128 into xmm1 register. + + + VPUNPCKHBW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 68 /r + + AVX + + Interleave high-order bytes from xmm2 and xmm3/m128 into xmm1. + + + VPUNPCKHWD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 69 /r + + AVX + + Interleave high-order words from xmm2 and xmm3/m128 into xmm1. + + + VPUNPCKHDQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 6A /r + + AVX + + Interleave high-order doublewords from xmm2 and xmm3/m128 into xmm1. + + + VPUNPCKHQDQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 6D /r + + AVX + + Interleave high-order quadword from xmm2 and xmm3/m128 into xmm1 register. + + + VPUNPCKHBW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 68 /r + + AVX2 + + Interleave high-order bytes from ymm2 and ymm3/m256 into ymm1 register. + + + VPUNPCKHWD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 69 /r + + AVX2 + + Interleave high-order words from ymm2 and ymm3/m256 into ymm1 register. + + + VPUNPCKHDQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 6A /r + + AVX2 + + Interleave high-order doublewords from ymm2 and ymm3/m256 into ymm1 register. + + + VPUNPCKHQDQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 6D /r + + AVX2 + + Interleave high-order quadword from ymm2 and ymm3/m256 into ymm1 register. + + + VPUNPCKHBW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG 68 /r + + AVX512VL + AVX512BW + + Interleave high-order bytes from xmm2 and xmm3/m128 into xmm1 register using k1 write mask. + + + VPUNPCKHWD + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG 69 /r + + AVX512VL + AVX512BW + + Interleave high-order words from xmm2 and xmm3/m128 into xmm1 register using k1 write mask. + + + VPUNPCKHDQ + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 6A /r + + AVX512VL + AVX512F + + Interleave high-order doublewords from xmm2 and xmm3/m128/m32bcst into xmm1 register using k1 write mask. + + + VPUNPCKHQDQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 6D /r + + AVX512VL + AVX512F + + Interleave high-order quadword from xmm2 and xmm3/m128/m64bcst into xmm1 register using k1 write mask. + + + VPUNPCKHBW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG 68 /r + + AVX512VL + AVX512BW + + Interleave high-order bytes from ymm2 and ymm3/m256 into ymm1 register using k1 write mask. + + + VPUNPCKHWD + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG 69 /r + + AVX512VL + AVX512BW + + Interleave high-order words from ymm2 and ymm3/m256 into ymm1 register using k1 write mask. + + + VPUNPCKHDQ + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 6A /r + + AVX512VL + AVX512F + + Interleave high-order doublewords from ymm2 and ymm3/m256/m32bcst into ymm1 register using k1 write mask. + + + VPUNPCKHQDQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 6D /r + + AVX512VL + AVX512F + + Interleave high-order quadword from ymm2 and ymm3/m256/m64bcst into ymm1 register using k1 write mask. + + + VPUNPCKHBW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG 68/r + + AVX512BW + + Interleave high-order bytes from zmm2 and zmm3/m512 into zmm1 register. + + + VPUNPCKHWD + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG 69/r + + AVX512BW + + Interleave high-order words from zmm2 and zmm3/m512 into zmm1 register. + + + VPUNPCKHDQ + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 6A /r + + AVX512F + + Interleave high-order doublewords from zmm2 and zmm3/m512/m32bcst into zmm1 register using k1 write mask. + + + VPUNPCKHQDQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 6D /r + + AVX512F + + Interleave high-order quadword from zmm2 and zmm3/m512/m64bcst into zmm1 register using k1 write mask. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ--Unpack Low Data. + + PUNPCKLBW + xmm1,xmm2/m128 + 66 0F 60 /r + + SSE2 + + Interleave low-order bytes from xmm1 and xmm2/m128 into xmm1. + + + PUNPCKLWD + xmm1,xmm2/m128 + 66 0F 61 /r + + SSE2 + + Interleave low-order words from xmm1 and xmm2/m128 into xmm1. + + + PUNPCKLDQ + xmm1,xmm2/m128 + 66 0F 62 /r + + SSE2 + + Interleave low-order doublewords from xmm1 and xmm2/m128 into xmm1. + + + PUNPCKLQDQ + xmm1,xmm2/m128 + 66 0F 6C /r + + SSE2 + + Interleave low-order quadword from xmm1 and xmm2/m128 into xmm1 register. + + + VPUNPCKLBW + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 60 /r + + AVX + + Interleave low-order bytes from xmm2 and xmm3/m128 into xmm1. + + + VPUNPCKLWD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 61 /r + + AVX + + Interleave low-order words from xmm2 and xmm3/m128 into xmm1. + + + VPUNPCKLDQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 62 /r + + AVX + + Interleave low-order doublewords from xmm2 and xmm3/m128 into xmm1. + + + VPUNPCKLQDQ + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 6C /r + + AVX + + Interleave low-order quadword from xmm2 and xmm3/m128 into xmm1 register. + + + VPUNPCKLBW + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 60 /r + + AVX2 + + Interleave low-order bytes from ymm2 and ymm3/m256 into ymm1 register. + + + VPUNPCKLWD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 61 /r + + AVX2 + + Interleave low-order words from ymm2 and ymm3/m256 into ymm1 register. + + + VPUNPCKLDQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 62 /r + + AVX2 + + Interleave low-order doublewords from ymm2 and ymm3/m256 into ymm1 register. + + + VPUNPCKLQDQ + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 6C /r + + AVX2 + + Interleave low-order quadword from ymm2 and ymm3/m256 into ymm1 register. + + + VPUNPCKLBW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG 60 /r + + AVX512VL + AVX512BW + + Interleave low-order bytes from xmm2 and xmm3/m128 into xmm1 register subject to write mask k1. + + + VPUNPCKLWD + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F.WIG 61 /r + + AVX512VL + AVX512BW + + Interleave low-order words from xmm2 and xmm3/m128 into xmm1 register subject to write mask k1. + + + VPUNPCKLDQ + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 62 /r + + AVX512VL + AVX512F + + Interleave low-order doublewords from xmm2 and xmm3/m128/m32bcst into xmm1 register subject to write mask k1. + + + VPUNPCKLQDQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 6C /r + + AVX512VL + AVX512F + + Interleave low-order quadword from zmm2 and zmm3/m512/m64bcst into zmm1 register subject to write mask k1. + + + VPUNPCKLBW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG 60 /r + + AVX512VL + AVX512BW + + Interleave low-order bytes from ymm2 and ymm3/m256 into ymm1 register subject to write mask k1. + + + VPUNPCKLWD + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F.WIG 61 /r + + AVX512VL + AVX512BW + + Interleave low-order words from ymm2 and ymm3/m256 into ymm1 register subject to write mask k1. + + + VPUNPCKLDQ + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 62 /r + + AVX512VL + AVX512F + + Interleave low-order doublewords from ymm2 and ymm3/m256/m32bcst into ymm1 register subject to write mask k1. + + + VPUNPCKLQDQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 6C /r + + AVX512VL + AVX512F + + Interleave low-order quadword from ymm2 and ymm3/m256/m64bcst into ymm1 register subject to write mask k1. + + + VPUNPCKLBW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG 60/r + + AVX512BW + + Interleave low-order bytes from zmm2 and zmm3/m512 into zmm1 register subject to write mask k1. + + + VPUNPCKLWD + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F.WIG 61/r + + AVX512BW + + Interleave low-order words from zmm2 and zmm3/m512 into zmm1 register subject to write mask k1. + + + VPUNPCKLDQ + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 62 /r + + AVX512F + + Interleave low-order doublewords from zmm2 and zmm3/m512/m32bcst into zmm1 register subject to write mask k1. + + + VPUNPCKLQDQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 6C /r + + AVX512F + + Interleave low-order quadword from zmm2 and zmm3/m512/m64bcst into zmm1 register subject to write mask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2--Shuffle Packed Values at 128-bit Granularity. + + VSHUFF32X4 + ymm1{k1}{z},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.66.0F3A.W0 23 /r ib + + AVX512VL + AVX512F + + Shuffle 128-bit packed single-precision floating-point values selected by imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1. + + + VSHUFF32x4 + zmm1{k1}{z},zmm2,zmm3/m512/m32bcst,imm8 + EVEX.NDS.512.66.0F3A.W0 23 /r ib + + AVX512F + + Shuffle 128-bit packed single-precision floating-point values selected by imm8 from zmm2 and zmm3/m512/m32bcst and place results in zmm1 subject to writemask k1. + + + VSHUFF64X2 + ymm1{k1}{z},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F3A.W1 23 /r ib + + AVX512VL + AVX512F + + Shuffle 128-bit packed double-precision floating-point values selected by imm8 from ymm2 and ymm3/m256/m64bcst and place results in ymm1 subject to writemask k1. + + + VSHUFF64x2 + zmm1{k1}{z},zmm2,zmm3/m512/m64bcst,imm8 + EVEX.NDS.512.66.0F3A.W1 23 /r ib + + AVX512F + + Shuffle 128-bit packed double-precision floating-point values selected by imm8 from zmm2 and zmm3/m512/m64bcst and place results in zmm1 subject to writemask k1. + + + VSHUFI32X4 + ymm1{k1}{z},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.66.0F3A.W0 43 /r ib + + AVX512VL + AVX512F + + Shuffle 128-bit packed double-word values selected by imm8 from ymm2 and ymm3/m256/m32bcst and place results in ymm1 subject to writemask k1. + + + VSHUFI32x4 + zmm1{k1}{z},zmm2,zmm3/m512/m32bcst,imm8 + EVEX.NDS.512.66.0F3A.W0 43 /r ib + + AVX512F + + Shuffle 128-bit packed double-word values selected by imm8 from zmm2 and zmm3/m512/m32bcst and place results in zmm1 subject to writemask k1. + + + VSHUFI64X2 + ymm1{k1}{z},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F3A.W1 43 /r ib + + AVX512VL + AVX512F + + Shuffle 128-bit packed quad-word values selected by imm8 from ymm2 and ymm3/m256/m64bcst and place results in ymm1 subject to writemask k1. + + + VSHUFI64x2 + zmm1{k1}{z},zmm2,zmm3/m512/m64bcst,imm8 + EVEX.NDS.512.66.0F3A.W1 43 /r ib + + AVX512F + + Shuffle 128-bit packed quad-word values selected by imm8 from zmm2 and zmm3/m512/m64bcst and place results in zmm1 subject to writemask k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + SHUFPD--Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values. + + SHUFPD + xmm1,xmm2/m128,imm8 + 66 0F C6 /r ib + + SSE2 + + Shuffle two pairs of double-precision floating-point values from xmm1 and xmm2/m128 using imm8 to select from each pair, interleaved result is stored in xmm1. + + + VSHUFPD + xmm1,xmm2,xmm3/m128,imm8 + VEX.NDS.128.66.0F.WIG C6 /r ib + + AVX + + Shuffle two pairs of double-precision floating-point values from xmm2 and xmm3/m128 using imm8 to select from each pair, interleaved result is stored in xmm1. + + + VSHUFPD + ymm1,ymm2,ymm3/m256,imm8 + VEX.NDS.256.66.0F.WIG C6 /r ib + + AVX + + Shuffle four pairs of double-precision floating-point values from ymm2 and ymm3/m256 using imm8 to select from each pair, interleaved result is stored in xmm1. + + + VSHUFPD + xmm1{k1}{z},xmm2,xmm3/m128/m64bcst,imm8 + EVEX.NDS.128.66.0F.W1 C6 /r ib + + AVX512VL + AVX512F + + Shuffle two paris of double-precision floating-point values from xmm2 and xmm3/m128/m64bcst using imm8 to select from each pair. store interleaved results in xmm1 subject to writemask k1. + + + VSHUFPD + ymm1{k1}{z},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F.W1 C6 /r ib + + AVX512VL + AVX512F + + Shuffle four paris of double-precision floating-point values from ymm2 and ymm3/m256/m64bcst using imm8 to select from each pair. store interleaved results in ymm1 subject to writemask k1. + + + VSHUFPD + zmm1{k1}{z},zmm2,zmm3/m512/m64bcst,imm8 + EVEX.NDS.512.66.0F.W1 C6 /r ib + + AVX512F + + Shuffle eight paris of double-precision floating-point values from zmm2 and zmm3/m512/m64bcst using imm8 to select from each pair. store interleaved results in zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + SHUFPS--Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values. + + SHUFPS + xmm1,xmm3/m128,imm8 + 0F C6 /r ib + + SSE + + Select from quadruplet of single-precision floatingpoint values in xmm1 and xmm2/m128 using imm8, interleaved result pairs are stored in xmm1. + + + VSHUFPS + xmm1,xmm2,xmm3/m128,imm8 + VEX.NDS.128.0F.WIG C6 /r ib + + AVX + + Select from quadruplet of single-precision floatingpoint values in xmm1 and xmm2/m128 using imm8, interleaved result pairs are stored in xmm1. + + + VSHUFPS + ymm1,ymm2,ymm3/m256,imm8 + VEX.NDS.256.0F.WIG C6 /r ib + + AVX + + Select from quadruplet of single-precision floatingpoint values in ymm2 and ymm3/m256 using imm8, interleaved result pairs are stored in ymm1. + + + VSHUFPS + xmm1{k1}{z},xmm2,xmm3/m128/m32bcst,imm8 + EVEX.NDS.128.0F.W0 C6 /r ib + + AVX512VL + AVX512F + + Select from quadruplet of single-precision floatingpoint values in xmm1 and xmm2/m128 using imm8, interleaved result pairs are stored in xmm1, subject to writemask k1. + + + VSHUFPS + ymm1{k1}{z},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.0F.W0 C6 /r ib + + AVX512VL + AVX512F + + Select from quadruplet of single-precision floatingpoint values in ymm2 and ymm3/m256 using imm8, interleaved result pairs are stored in ymm1, subject to writemask k1. + + + VSHUFPS + zmm1{k1}{z},zmm2,zmm3/m512/m32bcst,imm8 + EVEX.NDS.512.0F.W0 C6 /r ib + + AVX512F + + Select from quadruplet of single-precision floatingpoint values in zmm2 and zmm3/m512 using imm8, interleaved result pairs are stored in zmm1, subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + SQRTPD--Square Root of Double-Precision Floating-Point Values. + + SQRTPD + xmm1,xmm2/m128 + 66 0F 51 /r + + SSE2 + + Computes Square Roots of the packed double-precision floating-point values in xmm2/m128 and stores the result in xmm1. + + + VSQRTPD + xmm1,xmm2/m128 + VEX.128.66.0F.WIG 51 /r + + AVX + + Computes Square Roots of the packed double-precision floating-point values in xmm2/m128 and stores the result in xmm1. + + + VSQRTPD + ymm1,ymm2/m256 + VEX.256.66.0F.WIG 51 /r + + AVX + + Computes Square Roots of the packed double-precision floating-point values in ymm2/m256 and stores the result in ymm1. + + + VSQRTPD + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.66.0F.W1 51 /r + + AVX512VL + AVX512F + + Computes Square Roots of the packed double-precision floating-point values in xmm2/m128/m64bcst and stores the result in xmm1 subject to writemask k1. + + + VSQRTPD + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.66.0F.W1 51 /r + + AVX512VL + AVX512F + + Computes Square Roots of the packed double-precision floating-point values in ymm2/m256/m64bcst and stores the result in ymm1 subject to writemask k1. + + + VSQRTPD + zmm1 {k1}{z},zmm2/m512/m64bcst{er} + EVEX.512.66.0F.W1 51 /r + + AVX512F + + Computes Square Roots of the packed double-precision floating-point values in zmm2/m512/m64bcst and stores the result in zmm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + SQRTPS--Square Root of Single-Precision Floating-Point Values. + + SQRTPS + xmm1,xmm2/m128 + 0F 51 /r + + SSE + + Computes Square Roots of the packed single-precision floating-point values in xmm2/m128 and stores the result in xmm1. + + + VSQRTPS + xmm1,xmm2/m128 + VEX.128.0F.WIG 51 /r + + AVX + + Computes Square Roots of the packed single-precision floating-point values in xmm2/m128 and stores the result in xmm1. + + + VSQRTPS + ymm1,ymm2/m256 + VEX.256.0F.WIG 51/r + + AVX + + Computes Square Roots of the packed single-precision floating-point values in ymm2/m256 and stores the result in ymm1. + + + VSQRTPS + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.0F.W0 51 /r + + AVX512VL + AVX512F + + Computes Square Roots of the packed single-precision floating-point values in xmm2/m128/m32bcst and stores the result in xmm1 subject to writemask k1. + + + VSQRTPS + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.0F.W0 51 /r + + AVX512VL + AVX512F + + Computes Square Roots of the packed single-precision floating-point values in ymm2/m256/m32bcst and stores the result in ymm1 subject to writemask k1. + + + VSQRTPS + zmm1 {k1}{z},zmm2/m512/m32bcst{er} + EVEX.512.0F.W0 51/r + + AVX512F + + Computes Square Roots of the packed single-precision floating-point values in zmm2/m512/m32bcst and stores the result in zmm1 subject to writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + SQRTSD--Compute Square Root of Scalar Double-Precision Floating-Point Value. + + SQRTSD + xmm1,xmm2/m64 + F2 0F 51/r + + SSE2 + + Computes square root of the low double-precision floatingpoint value in xmm2/m64 and stores the results in xmm1. + + + VSQRTSD + xmm1,xmm2,xmm3/m64 + VEX.NDS.128.F2.0F.WIG 51/r + + AVX + + Computes square root of the low double-precision floatingpoint value in xmm3/m64 and stores the results in xmm1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. + + + VSQRTSD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.NDS.LIG.F2.0F.W1 51/r + + AVX512F + + Computes square root of the low double-precision floatingpoint value in xmm3/m64 and stores the results in xmm1 under writemask k1. Also, upper double-precision floatingpoint value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + SQRTSS--Compute Square Root of Scalar Single-Precision Value. + + SQRTSS + xmm1,xmm2/m32 + F3 0F 51 /r + + SSE + + Computes square root of the low single-precision floating-point value in xmm2/m32 and stores the results in xmm1. + + + VSQRTSS + xmm1,xmm2,xmm3/m32 + VEX.NDS.128.F3.0F.WIG 51 /r + + AVX + + Computes square root of the low single-precision floating-point value in xmm3/m32 and stores the results in xmm1. Also, upper single-precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32]. + + + VSQRTSS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.NDS.LIG.F3.0F.W0 51 /r + + AVX512F + + Computes square root of the low single-precision floating-point value in xmm3/m32 and stores the results in xmm1 under writemask k1. Also, upper single-precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32]. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPTERNLOGD/VPTERNLOGQ--Bitwise Ternary Logic. + + VPTERNLOGD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst,imm8 + EVEX.DDS.128.66.0F3A.W0 25 /r ib + + AVX512VL + AVX512F + + Bitwise ternary logic taking xmm1, xmm2 and xmm3/m128/m32bcst as source operands and writing the result to xmm1 under writemask k1 with dword granularity. The immediate value determines the specific binary function being implemented. + + + VPTERNLOGD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.DDS.256.66.0F3A.W0 25 /r ib + + AVX512VL + AVX512F + + Bitwise ternary logic taking ymm1, ymm2 and ymm3/m256/m32bcst as source operands and writing the result to ymm1 under writemask k1 with dword granularity. The immediate value determines the specific binary function being implemented. + + + VPTERNLOGD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst,imm8 + EVEX.DDS.512.66.0F3A.W0 25 /r ib + + AVX512F + + Bitwise ternary logic taking zmm1, zmm2 and zmm3/m512/m32bcst as source operands and writing the result to zmm1 under writemask k1 with dword granularity. The immediate value determines the specific binary function being implemented. + + + VPTERNLOGQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst,imm8 + EVEX.DDS.128.66.0F3A.W1 25 /r ib + + AVX512VL + AVX512F + + Bitwise ternary logic taking xmm1, xmm2 and xmm3/m128/m64bcst as source operands and writing the result to xmm1 under writemask k1 with qword granularity. The immediate value determines the specific binary function being implemented. + + + VPTERNLOGQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.DDS.256.66.0F3A.W1 25 /r ib + + AVX512VL + AVX512F + + Bitwise ternary logic taking ymm1, ymm2 and ymm3/m256/m64bcst as source operands and writing the result to ymm1 under writemask k1 with qword granularity. The immediate value determines the specific binary function being implemented. + + + VPTERNLOGQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst,imm8 + EVEX.DDS.512.66.0F3A.W1 25 /r ib + + AVX512F + + Bitwise ternary logic taking zmm1, zmm2 and zmm3/m512/m64bcst as source operands and writing the result to zmm1 under writemask k1 with qword granularity. The immediate value determines the specific binary function being implemented. + + + ModRM:reg(r,w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ--Logical AND and Set Mask. + + VPTESTMB + k2 {k1},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W0 26 /r + + AVX512VL + AVX512BW + + Bitwise AND of packed byte integers in xmm2 and xmm3/m128 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMB + k2 {k1},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W0 26 /r + + AVX512VL + AVX512BW + + Bitwise AND of packed byte integers in ymm2 and ymm3/m256 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMB + k2 {k1},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W0 26 /r + + AVX512BW + + Bitwise AND of packed byte integers in zmm2 and zmm3/m512 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMW + k2 {k1},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W1 26 /r + + AVX512VL + AVX512BW + + Bitwise AND of packed word integers in xmm2 and xmm3/m128 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMW + k2 {k1},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W1 26 /r + + AVX512VL + AVX512BW + + Bitwise AND of packed word integers in ymm2 and ymm3/m256 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMW + k2 {k1},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W1 26 /r + + AVX512BW + + Bitwise AND of packed word integers in zmm2 and zmm3/m512 and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMD + k2 {k1},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 27 /r + + AVX512VL + AVX512F + + Bitwise AND of packed doubleword integers in xmm2 and xmm3/m128/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMD + k2 {k1},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 27 /r + + AVX512VL + AVX512F + + Bitwise AND of packed doubleword integers in ymm2 and ymm3/m256/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMD + k2 {k1},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 27 /r + + AVX512F + + Bitwise AND of packed doubleword integers in zmm2 and zmm3/m512/m32bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMQ + k2 {k1},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 27 /r + + AVX512VL + AVX512F + + Bitwise AND of packed quadword integers in xmm2 and xmm3/m128/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMQ + k2 {k1},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 27 /r + + AVX512VL + AVX512F + + Bitwise AND of packed quadword integers in ymm2 and ymm3/m256/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + VPTESTMQ + k2 {k1},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 27 /r + + AVX512F + + Bitwise AND of packed quadword integers in zmm2 and zmm3/m512/m64bcst and set mask k2 to reflect the zero/non-zero status of each element of the result, under writemask k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VPSRAVW/VPSRAVD/VPSRAVQ--Variable Bit Shift Right Arithmetic. + + VPSRAVD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F38.W0 46 /r + + AVX2 + + Shift doublewords in xmm2 right by amount specified in the corresponding element of xmm3/m128 while shifting in sign bits. + + + VPSRAVD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F38.W0 46 /r + + AVX2 + + Shift doublewords in ymm2 right by amount specified in the corresponding element of ymm3/m256 while shifting in sign bits. + + + VPSRAVW + xmm1 {k1}{z},xmm2,xmm3/m128 + EVEX.NDS.128.66.0F38.W1 11 /r + + AVX512VL + AVX512BW + + Shift words in xmm2 right by amount specified in the corresponding element of xmm3/m128 while shifting in sign bits using writemask k1. + + + VPSRAVW + ymm1 {k1}{z},ymm2,ymm3/m256 + EVEX.NDS.256.66.0F38.W1 11 /r + + AVX512VL + AVX512BW + + Shift words in ymm2 right by amount specified in the corresponding element of ymm3/m256 while shifting in sign bits using writemask k1. + + + VPSRAVW + zmm1 {k1}{z},zmm2,zmm3/m512 + EVEX.NDS.512.66.0F38.W1 11 /r + + AVX512BW + + Shift words in zmm2 right by amount specified in the corresponding element of zmm3/m512 while shifting in sign bits using writemask k1. + + + VPSRAVD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 46 /r + + AVX512VL + AVX512F + + Shift doublewords in xmm2 right by amount specified in the corresponding element of xmm3/m128/m32bcst while shifting in sign bits using writemask k1. + + + VPSRAVD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 46 /r + + AVX512VL + AVX512F + + Shift doublewords in ymm2 right by amount specified in the corresponding element of ymm3/m256/m32bcst while shifting in sign bits using writemask k1. + + + VPSRAVD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F38.W0 46 /r + + AVX512F + + Shift doublewords in zmm2 right by amount specified in the corresponding element of zmm3/m512/m32bcst while shifting in sign bits using writemask k1. + + + VPSRAVQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 46 /r + + AVX512VL + AVX512F + + Shift quadwords in xmm2 right by amount specified in the corresponding element of xmm3/m128/m64bcst while shifting in sign bits using writemask k1. + + + VPSRAVQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 46 /r + + AVX512VL + AVX512F + + Shift quadwords in ymm2 right by amount specified in the corresponding element of ymm3/m256/m64bcst while shifting in sign bits using writemask k1. + + + VPSRAVQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F38.W1 46 /r + + AVX512F + + Shift quadwords in zmm2 right by amount specified in the corresponding element of zmm3/m512/m64bcst while shifting in sign bits using writemask k1. + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + PXOR/PXORD/PXORQ--Exclusive Or. + + PXOR + xmm1,xmm2/m128 + 66 0F EF /r + + SSE2 + + Bitwise XOR of xmm2/m128 and xmm1. + + + VPXOR + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG EF /r + + AVX + + Bitwise XOR of xmm3/m128 and xmm2. + + + VPXOR + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG EF /r + + AVX2 + + Bitwise XOR of ymm3/m256 and ymm2. + + + VPXORD + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F.W0 EF /r + + AVX512VL + AVX512F + + Bitwise XOR of packed doubleword integers in xmm2 and xmm3/m128 using writemask k1. + + + VPXORD + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F.W0 EF /r + + AVX512VL + AVX512F + + Bitwise XOR of packed doubleword integers in ymm2 and ymm3/m256 using writemask k1. + + + VPXORD + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.66.0F.W0 EF /r + + AVX512F + + Bitwise XOR of packed doubleword integers in zmm2 and zmm3/m512/m32bcst using writemask k1. + + + VPXORQ + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 EF /r + + AVX512VL + AVX512F + + Bitwise XOR of packed quadword integers in xmm2 and xmm3/m128 using writemask k1. + + + VPXORQ + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 EF /r + + AVX512VL + AVX512F + + Bitwise XOR of packed quadword integers in ymm2 and ymm3/m256 using writemask k1. + + + VPXORQ + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 EF /r + + AVX512F + + Bitwise XOR of packed quadword integers in zmm2 and zmm3/m512/m64bcst using writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VRANGEPD--Range Restriction Calculation For Packed Pairs of Float64 Values. + + VRANGEPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst,imm8 + EVEX.NDS.128.66.0F3A.W1 50 /r ib + + AVX512VL + AVX512DQ + + Calculate two RANGE operation output value from 2 pairs of double-precision floating-point values in xmm2 and xmm3/m128/m32bcst, store the results to xmm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation. + + + VRANGEPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst,imm8 + EVEX.NDS.256.66.0F3A.W1 50 /r ib + + AVX512VL + AVX512DQ + + Calculate four RANGE operation output value from 4pairs of double-precision floating-point values in ymm2 and ymm3/m256/m32bcst, store the results to ymm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation. + + + VRANGEPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{sae},imm8 + EVEX.NDS.512.66.0F3A.W1 50 /r ib + + AVX512DQ + + Calculate eight RANGE operation output value from 8 pairs of double-precision floating-point values in zmm2 and zmm3/m512/m32bcst, store the results to zmm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + VRANGEPS--Range Restriction Calculation For Packed Pairs of Float32 Values. + + VRANGEPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst,imm8 + EVEX.NDS.128.66.0F3A.W0 50 /r ib + + AVX512VL + AVX512DQ + + Calculate four RANGE operation output value from 4 pairs of single-precision floating-point values in xmm2 and xmm3/m128/m32bcst, store the results to xmm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation. + + + VRANGEPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst,imm8 + EVEX.NDS.256.66.0F3A.W0 50 /r ib + + AVX512VL + AVX512DQ + + Calculate eight RANGE operation output value from 8 pairs of single-precision floating-point values in ymm2 and ymm3/m256/m32bcst, store the results to ymm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation. + + + VRANGEPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{sae},imm8 + EVEX.NDS.512.66.0F3A.W0 50 /r ib + + AVX512DQ + + Calculate 16 RANGE operation output value from 16 pairs of single-precision floating-point values in zmm2 and zmm3/m512/m32bcst, store the results to zmm1 under the writemask k1. Imm8 specifies the comparison and sign of the range operation. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + VRANGESD--Range Restriction Calculation From a pair of Scalar Float64 Values. + + VRANGESD + xmm1 {k1}{z},xmm2,xmm3/m64{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W1 51 /r + + AVX512DQ + + Calculate a RANGE operation output value from 2 doubleprecision floating-point values in xmm2 and xmm3/m64, store the output to xmm1 under writemask. Imm8 specifies the comparison and sign of the range operation. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + VRANGESS--Range Restriction Calculation From a Pair of Scalar Float32 Values. + + VRANGESS + xmm1 {k1}{z},xmm2,xmm3/m32{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W0 51 /r + + AVX512DQ + + Calculate a RANGE operation output value from 2 singleprecision floating-point values in xmm2 and xmm3/m32, store the output to xmm1 under writemask. Imm8 specifies the comparison and sign of the range operation. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VRCP14PD--Compute Approximate Reciprocals of Packed Float64 Values. + + VRCP14PD + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F38.W1 4C /r + + AVX512VL + AVX512F + + Computes the approximate reciprocals of the packed doubleprecision floating-point values in xmm2/m128/m64bcst and stores the results in xmm1. Under writemask. + + + VRCP14PD + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F38.W1 4C /r + + AVX512VL + AVX512F + + Computes the approximate reciprocals of the packed doubleprecision floating-point values in ymm2/m256/m64bcst and stores the results in ymm1. Under writemask. + + + VRCP14PD + zmm1 {k1}{z},zmm2/m512/m64bcst + EVEX.512.66.0F38.W1 4C /r + + AVX512F + + Computes the approximate reciprocals of the packed doubleprecision floating-point values in zmm2/m512/m64bcst and stores the results in zmm1. Under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VRCP14SD--Compute Approximate Reciprocal of Scalar Float64 Value. + + T1S + VRCP14SD xmm1 {k1}{z},xmm2,xmm3/m64 + EVEX.NDS.LIG.66.0F38.W1 4D /r + + AVX512F + + Computes the approximate reciprocal of the scalar doubleprecision floating-point value in xmm3/m64 and stores the result in xmm1 using writemask k1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VRCP14PS--Compute Approximate Reciprocals of Packed Float32 Values. + + VRCP14PS + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.66.0F38.W0 4C /r + + AVX512VL + AVX512F + + Computes the approximate reciprocals of the packed singleprecision floating-point values in xmm2/m128/m32bcst and stores the results in xmm1. Under writemask. + + + VRCP14PS + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.66.0F38.W0 4C /r + + AVX512VL + AVX512F + + Computes the approximate reciprocals of the packed singleprecision floating-point values in ymm2/m256/m32bcst and stores the results in ymm1. Under writemask. + + + VRCP14PS + zmm1 {k1}{z},zmm2/m512/m32bcst + EVEX.512.66.0F38.W0 4C /r + + AVX512F + + Computes the approximate reciprocals of the packed singleprecision floating-point values in zmm2/m512/m32bcst and stores the results in zmm1. Under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VRCP14SS--Compute Approximate Reciprocal of Scalar Float32 Value. + + VRCP14SS + xmm1 {k1}{z},xmm2,xmm3/m32 + EVEX.NDS.LIG.66.0F38.W0 4D /r + + AVX512F + + Computes the approximate reciprocal of the scalar singleprecision floating-point value in xmm3/m32 and stores the results in xmm1 using writemask k1. Also, upper doubleprecision floating-point value (bits[127:32]) from xmm2 is copied to xmm1[127:32]. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VREDUCEPD--Perform Reduction Transformation on Packed Float64 Values. + + VREDUCEPD + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.128.66.0F3A.W1 56 /r ib + + AVX512VL + AVX512DQ + + Perform reduction transformation on packed double-precision floating point values in xmm2/m128/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register under writemask k1. + + + VREDUCEPD + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.256.66.0F3A.W1 56 /r ib + + AVX512VL + AVX512DQ + + Perform reduction transformation on packed double-precision floating point values in ymm2/m256/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register under writemask k1. + + + VREDUCEPD + zmm1 {k1}{z},zmm2/m512/m64bcst{sae},imm8 + EVEX.512.66.0F3A.W1 56 /r ib + + AVX512DQ + + Perform reduction transformation on double-precision floating point values in zmm2/m512/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register under writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + VREDUCESD--Perform a Reduction Transformation on a Scalar Float64 Value. + + VREDUCESD + xmm1 {k1}{z},xmm2,xmm3/m64{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W1 57 /r + + AVX512DQ + + Perform a reduction transformation on a scalar double-precision floating point value in xmm3/m64 by subtracting a number of fraction bits specified by the imm8 field. Also, upper double precision floating-point value (bits[127:64]) from xmm2 are copied to xmm1[127:64]. Stores the result in xmm1 register. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VREDUCEPS--Perform Reduction Transformation on Packed Float32 Values. + + VREDUCEPS + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.128.66.0F3A.W0 56 /r ib + + AVX512VL + AVX512DQ + + Perform reduction transformation on packed single-precision floating point values in xmm2/m128/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register under writemask k1. + + + VREDUCEPS + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.256.66.0F3A.W0 56 /r ib + + AVX512VL + AVX512DQ + + Perform reduction transformation on packed single-precision floating point values in ymm2/m256/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register under writemask k1. + + + VREDUCEPS + zmm1 {k1}{z},zmm2/m512/m32bcst{sae},imm8 + EVEX.512.66.0F3A.W0 56 /r ib + + AVX512DQ + + Perform reduction transformation on packed single-precision floating point values in zmm2/m512/m32bcst by subtracting a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register under writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + VREDUCESS--Perform a Reduction Transformation on a Scalar Float32 Value. + + VREDUCESS + xmm1 {k1}{z},xmm2,xmm3/m32{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W0 57 /r /ib + + AVX512DQ + + Perform a reduction transformation on a scalar single-precision floating point value in xmm3/m32 by subtracting a number of fraction bits specified by the imm8 field. Also, upper single precision floating-point values (bits[127:32]) from xmm2 are copied to xmm1[127:32]. Stores the result in xmm1 register. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VRNDSCALEPD--Round Packed Float64 Values To Include A Given Number Of Fraction Bits. + + VRNDSCALEPD + xmm1 {k1}{z},xmm2/m128/m64bcst,imm8 + EVEX.128.66.0F3A.W1 09 /r ib + + AVX512VL + AVX512F + + Rounds packed double-precision floating point values in xmm2/m128/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register. Under writemask. + + + VRNDSCALEPD + ymm1 {k1}{z},ymm2/m256/m64bcst,imm8 + EVEX.256.66.0F3A.W1 09 /r ib + + AVX512VL + AVX512F + + Rounds packed double-precision floating point values in ymm2/m256/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register. Under writemask. + + + VRNDSCALEPD + zmm1 {k1}{z},zmm2/m512/m64bcst{sae},imm8 + EVEX.512.66.0F3A.W1 09 /r ib + + AVX512F + + Rounds packed double-precision floating-point values in zmm2/m512/m64bcst to a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register using writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + VRNDSCALESD--Round Scalar Float64 Value To Include A Given Number Of Fraction Bits. + + VRNDSCALESD + xmm1 {k1}{z},xmm2,xmm3/m64{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W1 0B /r ib + + AVX512F + + Rounds scalar double-precision floating-point value in xmm3/m64 to a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + Imm8 + + + + VRNDSCALEPS--Round Packed Float32 Values To Include A Given Number Of Fraction Bits. + + VRNDSCALEPS + xmm1 {k1}{z},xmm2/m128/m32bcst,imm8 + EVEX.128.66.0F3A.W0 08 /r ib + + AVX512VL + AVX512F + + Rounds packed single-precision floating point values in xmm2/m128/m32bcst to a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register. Under writemask. + + + VRNDSCALEPS + ymm1 {k1}{z},ymm2/m256/m32bcst,imm8 + EVEX.256.66.0F3A.W0 08 /r ib + + AVX512VL + AVX512F + + Rounds packed single-precision floating point values in ymm2/m256/m32bcst to a number of fraction bits specified by the imm8 field. Stores the result in ymm1 register. Under writemask. + + + VRNDSCALEPS + zmm1 {k1}{z},zmm2/m512/m32bcst{sae},imm8 + EVEX.512.66.0F3A.W0 08 /r ib + + AVX512F + + Rounds packed single-precision floating-point values in zmm2/m512/m32bcst to a number of fraction bits specified by the imm8 field. Stores the result in zmm1 register using writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + Imm8 + NA + + + + VRNDSCALESS--Round Scalar Float32 Value To Include A Given Number Of Fraction Bits. + + VRNDSCALESS + xmm1 {k1}{z},xmm2,xmm3/m32{sae},imm8 + EVEX.NDS.LIG.66.0F3A.W0 0A /r ib + + AVX512F + + Rounds scalar single-precision floating-point value in xmm3/m32 to a number of fraction bits specified by the imm8 field. Stores the result in xmm1 register under writemask. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VRSQRT14PD--Compute Approximate Reciprocals of Square Roots of Packed Float64 Values. + + VRSQRT14PD + xmm1 {k1}{z},xmm2/m128/m64bcst + EVEX.128.66.0F38.W1 4E /r + + AVX512VL + AVX512F + + Computes the approximate reciprocal square roots of the packed double-precision floating-point values in xmm2/m128/m64bcst and stores the results in xmm1. Under writemask. + + + VRSQRT14PD + ymm1 {k1}{z},ymm2/m256/m64bcst + EVEX.256.66.0F38.W1 4E /r + + AVX512VL + AVX512F + + Computes the approximate reciprocal square roots of the packed double-precision floating-point values in ymm2/m256/m64bcst and stores the results in ymm1. Under writemask. + + + VRSQRT14PD + zmm1 {k1}{z},zmm2/m512/m64bcst + EVEX.512.66.0F38.W1 4E /r + + AVX512F + + Computes the approximate reciprocal square roots of the packed double-precision floating-point values in zmm2/m512/m64bcst and stores the results in zmm1 under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VRSQRT14SD--Compute Approximate Reciprocal of Square Root of Scalar Float64 Value. + + VRSQRT14SD + xmm1 {k1}{z},xmm2,xmm3/m64 + EVEX.NDS.LIG.66.0F38.W1 4F /r + + AVX512F + + Computes the approximate reciprocal square root of the scalar double-precision floating-point value in xmm3/m64 and stores the result in the low quadword element of xmm1 using writemask k1. Bits[127:64] of xmm2 is copied to xmm1[127:64]. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VRSQRT14PS--Compute Approximate Reciprocals of Square Roots of Packed Float32 Values. + + VRSQRT14PS + xmm1 {k1}{z},xmm2/m128/m32bcst + EVEX.128.66.0F38.W0 4E /r + + AVX512VL + AVX512F + + Computes the approximate reciprocal square roots of the packed single-precision floating-point values in xmm2/m128/m32bcst and stores the results in xmm1. Under writemask. + + + VRSQRT14PS + ymm1 {k1}{z},ymm2/m256/m32bcst + EVEX.256.66.0F38.W0 4E /r + + AVX512VL + AVX512F + + Computes the approximate reciprocal square roots of the packed single-precision floating-point values in ymm2/m256/m32bcst and stores the results in ymm1. Under writemask. + + + VRSQRT14PS + zmm1 {k1}{z},zmm2/m512/m32bcst + EVEX.512.66.0F38.W0 4E /r + + AVX512F + + Computes the approximate reciprocal square roots of the packed single-precision floating-point values in zmm2/m512/m32bcst and stores the results in zmm1. Under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VRSQRT14SS--Compute Approximate Reciprocal of Square Root of Scalar Float32 Value. + + VRSQRT14SS + xmm1 {k1}{z},xmm2,xmm3/m32 + EVEX.NDS.LIG.66.0F38.W0 4F /r + + AVX512F + + Computes the approximate reciprocal square root of the scalar single-precision floating-point value in xmm3/m32 and stores the result in the low doubleword element of xmm1 using writemask k1. Bits[127:32] of xmm2 is copied to xmm1[127:32]. + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + + VSCALEFPD--Scale Packed Float64 Values With Float64 Values. + + VSCALEFPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F38.W1 2C /r + + AVX512VL + AVX512F + + Scale the packed double-precision floating-point values in xmm2 using values from xmm3/m128/m64bcst. Under writemask k1. + + + VSCALEFPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F38.W1 2C /r + + AVX512VL + AVX512F + + Scale the packed double-precision floating-point values in ymm2 using values from ymm3/m256/m64bcst. Under writemask k1. + + + VSCALEFPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F38.W1 2C /r + + AVX512F + + Scale the packed double-precision floating-point values in zmm2 using values from zmm3/m512/m64bcst. Under writemask k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VSCALEFSD--Scale Scalar Float64 Values With Float64 Values. + + VSCALEFSD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.NDS.LIG.66.0F38.W1 2D /r + + AVX512F + + Scale the scalar double-precision floating-point values in xmm2 using the value from xmm3/m64. Under writemask k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VSCALEFPS--Scale Packed Float32 Values With Float32 Values. + + VSCALEFPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.66.0F38.W0 2C /r + + AVX512VL + AVX512F + + Scale the packed single-precision floating-point values in xmm2 using values from xmm3/m128/m32bcst. Under writemask k1. + + + VSCALEFPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.66.0F38.W0 2C /r + + AVX512VL + AVX512F + + Scale the packed single-precision values in ymm2 using floating point values from ymm3/m256/m32bcst. Under writemask k1. + + + VSCALEFPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.66.0F38.W0 2C /r + + AVX512F + + Scale the packed single-precision floating-point values in zmm2 using floating-point values from zmm3/m512/m32bcst. Under writemask k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VSCALEFSS--Scale Scalar Float32 Value With Float32 Value. + + VSCALEFSS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.NDS.LIG.66.0F38.W0 2D /r + + AVX512F + + Scale the scalar single-precision floating-point value in xmm2 using floating-point value from xmm3/m32. Under writemask k1. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD--Scatter Packed Single, Packed Double with Signed Dword and Qword Indices. + + VSCATTERDPS + vm32x {k1},xmm1 + EVEX.128.66.0F38.W0 A2 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, scatter single-precision floating-point values to memory using writemask k1. + + + VSCATTERDPS + vm32y {k1},ymm1 + EVEX.256.66.0F38.W0 A2 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, scatter single-precision floating-point values to memory using writemask k1. + + + VSCATTERDPS + vm32z {k1},zmm1 + EVEX.512.66.0F38.W0 A2 /vsib + + AVX512F + + Using signed dword indices, scatter single-precision floating-point values to memory using writemask k1. + + + VSCATTERDPD + vm32x {k1},xmm1 + EVEX.128.66.0F38.W1 A2 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, scatter double-precision floating-point values to memory using writemask k1. + + + VSCATTERDPD + vm32x {k1},ymm1 + EVEX.256.66.0F38.W1 A2 /vsib + + AVX512VL + AVX512F + + Using signed dword indices, scatter double-precision floating-point values to memory using writemask k1. + + + VSCATTERDPD + vm32y {k1},zmm1 + EVEX.512.66.0F38.W1 A2 /vsib + + AVX512F + + Using signed dword indices, scatter double-precision floating-point values to memory using writemask k1. + + + VSCATTERQPS + vm64x {k1},xmm1 + EVEX.128.66.0F38.W0 A3 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, scatter single-precision floating-point values to memory using writemask k1. + + + VSCATTERQPS + vm64y {k1},xmm1 + EVEX.256.66.0F38.W0 A3 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, scatter single-precision floating-point values to memory using writemask k1. + + + VSCATTERQPS + vm64z {k1},ymm1 + EVEX.512.66.0F38.W0 A3 /vsib + + AVX512F + + Using signed qword indices, scatter single-precision floating-point values to memory using writemask k1. + + + VSCATTERQPD + vm64x {k1},xmm1 + EVEX.128.66.0F38.W1 A3 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, scatter double-precision floating-point values to memory using writemask k1. + + + VSCATTERQPD + vm64y {k1},ymm1 + EVEX.256.66.0F38.W1 A3 /vsib + + AVX512VL + AVX512F + + Using signed qword indices, scatter double-precision floating-point values to memory using writemask k1. + + + VSCATTERQPD + vm64z {k1},zmm1 + EVEX.512.66.0F38.W1 A3 /vsib + + AVX512F + + Using signed qword indices, scatter double-precision floating-point values to memory using writemask k1. + + + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + ModRM:reg(r) + NA + NA + + + + SUBPD--Subtract Packed Double-Precision Floating-Point Values. + + SUBPD + xmm1,xmm2/m128 + 66 0F 5C /r + + SSE2 + + Subtract packed double-precision floating-point values in xmm2/mem from xmm1 and store result in xmm1. + + + VSUBPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 5C /r + + AVX + + Subtract packed double-precision floating-point values in xmm3/mem from xmm2 and store result in xmm1. + + + VSUBPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 5C /r + + AVX + + Subtract packed double-precision floating-point values in ymm3/mem from ymm2 and store result in ymm1. + + + VSUBPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 5C /r + + AVX512VL + AVX512F + + Subtract packed double-precision floating-point values from xmm3/m128/m64bcst to xmm2 and store result in xmm1 with writemask k1. + + + VSUBPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 5C /r + + AVX512VL + AVX512F + + Subtract packed double-precision floating-point values from ymm3/m256/m64bcst to ymm2 and store result in ymm1 with writemask k1. + + + VSUBPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst{er} + EVEX.NDS.512.66.0F.W1 5C /r + + AVX512F + + Subtract packed double-precision floating-point values from zmm3/m512/m64bcst to zmm2 and store result in zmm1 with writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + SUBPS--Subtract Packed Single-Precision Floating-Point Values. + + SUBPS + xmm1,xmm2/m128 + 0F 5C /r + + SSE + + Subtract packed single-precision floating-point values in xmm2/mem from xmm1 and store result in xmm1. + + + VSUBPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 5C /r + + AVX + + Subtract packed single-precision floating-point values in xmm3/mem from xmm2 and stores result in xmm1. + + + VSUBPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F.WIG 5C /r + + AVX + + Subtract packed single-precision floating-point values in ymm3/mem from ymm2 and stores result in ymm1. + + + VSUBPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 5C /r + + AVX512VL + AVX512F + + Subtract packed single-precision floating-point values from xmm3/m128/m32bcst to xmm2 and stores result in xmm1 with writemask k1. + + + VSUBPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 5C /r + + AVX512VL + AVX512F + + Subtract packed single-precision floating-point values from ymm3/m256/m32bcst to ymm2 and stores result in ymm1 with writemask k1. + + + VSUBPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst{er} + EVEX.NDS.512.0F.W0 5C /r + + AVX512F + + Subtract packed single-precision floating-point values in zmm3/m512/m32bcst from zmm2 and stores result in zmm1 with writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + SUBSD--Subtract Scalar Double-Precision Floating-Point Value. + + SUBSD + xmm1,xmm2/m64 + F2 0F 5C /r + + SSE2 + + Subtract the low double-precision floating-point value in xmm2/m64 from xmm1 and store the result in xmm1. + + + VSUBSD + xmm1,xmm2,xmm3/m64 + VEX.NDS.128.F2.0F.WIG 5C /r + + AVX + + Subtract the low double-precision floating-point value in xmm3/m64 from xmm2 and store the result in xmm1. + + + VSUBSD + xmm1 {k1}{z},xmm2,xmm3/m64{er} + EVEX.NDS.LIG.F2.0F.W1 5C /r + + AVX512F + + Subtract the low double-precision floating-point value in xmm3/m64 from xmm2 and store the result in xmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + SUBSS--Subtract Scalar Single-Precision Floating-Point Value. + + SUBSS + xmm1,xmm2/m32 + F3 0F 5C /r + + SSE + + Subtract the low single-precision floating-point value in xmm2/m32 from xmm1 and store the result in xmm1. + + + VSUBSS + xmm1,xmm2,xmm3/m32 + VEX.NDS.128.F3.0F.WIG 5C /r + + AVX + + Subtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1. + + + VSUBSS + xmm1 {k1}{z},xmm2,xmm3/m32{er} + EVEX.NDS.LIG.F3.0F.W0 5C /r + + AVX512F + + Subtract the low single-precision floating-point value in xmm3/m32 from xmm2 and store the result in xmm1 under writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + UCOMISD--Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS. + + UCOMISD + xmm1,xmm2/m64 + 66 0F 2E /r + + SSE2 + + Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly. + + + VUCOMISD + xmm1,xmm2/m64 + VEX.128.66.0F.WIG 2E /r + + AVX + + Compare low double-precision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly. + + + VUCOMISD + xmm1,xmm2/m64{sae} + EVEX.LIG.66.0F.W1 2E /r + + AVX512F + + Compare low double-precision floating-point values in xmm1 and xmm2/m64 and set the EFLAGS flags accordingly. + + + ModRM:reg(r) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + UCOMISS--Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS. + + UCOMISS + xmm1,xmm2/m32 + 0F 2E /r + + SSE + + Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly. + + + VUCOMISS + xmm1,xmm2/m32 + VEX.128.0F.WIG 2E /r + + AVX + + Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly. + + + VUCOMISS + xmm1,xmm2/m32{sae} + EVEX.LIG.0F.W0 2E /r + + AVX512F + + Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly. + + + ModRM:reg(r) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + UNPCKHPD--Unpack and Interleave High Packed Double-Precision Floating-Point Values. + + UNPCKHPD + xmm1,xmm2/m128 + 66 0F 15 /r + + SSE2 + + Unpacks and Interleaves double-precision floating-point values from high quadwords of xmm1 and xmm2/m128. + + + VUNPCKHPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 15 /r + + AVX + + Unpacks and Interleaves double-precision floating-point values from high quadwords of xmm2 and xmm3/m128. + + + VUNPCKHPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 15 /r + + AVX + + Unpacks and Interleaves double-precision floating-point values from high quadwords of ymm2 and ymm3/m256. + + + VUNPCKHPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 15 /r + + AVX512VL + AVX512F + + Unpacks and Interleaves double precision floating-point values from high quadwords of xmm2 and xmm3/m128/m64bcst subject to writemask k1. + + + VUNPCKHPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 15 /r + + AVX512VL + AVX512F + + Unpacks and Interleaves double precision floating-point values from high quadwords of ymm2 and ymm3/m256/m64bcst subject to writemask k1. + + + VUNPCKHPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 15 /r + + AVX512F + + Unpacks and Interleaves double-precision floating-point values from high quadwords of zmm2 and zmm3/m512/m64bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + UNPCKHPS--Unpack and Interleave High Packed Single-Precision Floating-Point Values. + + UNPCKHPS + xmm1,xmm2/m128 + 0F 15 /r + + SSE + + Unpacks and Interleaves single-precision floating-point values from high quadwords of xmm1 and xmm2/m128. + + + VUNPCKHPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 15 /r + + AVX + + Unpacks and Interleaves single-precision floating-point values from high quadwords of xmm2 and xmm3/m128. + + + VUNPCKHPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F.WIG 15 /r + + AVX + + Unpacks and Interleaves single-precision floating-point values from high quadwords of ymm2 and ymm3/m256. + + + VUNPCKHPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 15 /r + + AVX512VL + AVX512F + + Unpacks and Interleaves single-precision floating-point values from high quadwords of xmm2 and xmm3/m128/m32bcst and write result to xmm1 subject to writemask k1. + + + VUNPCKHPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 15 /r + + AVX512VL + AVX512F + + Unpacks and Interleaves single-precision floating-point values from high quadwords of ymm2 and ymm3/m256/m32bcst and write result to ymm1 subject to writemask k1. + + + VUNPCKHPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.0F.W0 15 /r + + AVX512F + + Unpacks and Interleaves single-precision floating-point values from high quadwords of zmm2 and zmm3/m512/m32bcst and write result to zmm1 subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + UNPCKLPD--Unpack and Interleave Low Packed Double-Precision Floating-Point Values. + + UNPCKLPD + xmm1,xmm2/m128 + 66 0F 14 /r + + SSE2 + + Unpacks and Interleaves double-precision floating-point values from low quadwords of xmm1 and xmm2/m128. + + + VUNPCKLPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 14 /r + + AVX + + Unpacks and Interleaves double-precision floating-point values from low quadwords of xmm2 and xmm3/m128. + + + VUNPCKLPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 14 /r + + AVX + + Unpacks and Interleaves double-precision floating-point values from low quadwords of ymm2 and ymm3/m256. + + + VUNPCKLPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 14 /r + + AVX512VL + AVX512F + + Unpacks and Interleaves double precision floating-point values from low quadwords of xmm2 and xmm3/m128/m64bcst subject to write mask k1. + + + VUNPCKLPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 14 /r + + AVX512VL + AVX512F + + Unpacks and Interleaves double precision floating-point values from low quadwords of ymm2 and ymm3/m256/m64bcst subject to write mask k1. + + + VUNPCKLPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 14 /r + + AVX512F + + Unpacks and Interleaves double-precision floating-point values from low quadwords of zmm2 and zmm3/m512/m64bcst subject to write mask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + UNPCKLPS--Unpack and Interleave Low Packed Single-Precision Floating-Point Values. + + UNPCKLPS + xmm1,xmm2/m128 + 0F 14 /r + + SSE + + Unpacks and Interleaves single-precision floating-point values from low quadwords of xmm1 and xmm2/m128. + + + VUNPCKLPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 14 /r + + AVX + + Unpacks and Interleaves single-precision floating-point values from low quadwords of xmm2 and xmm3/m128. + + + ymm1,ymm2,ymm3/m256 + void + VEX.NDS.256.0F.WIG 14 /r VUNPCKLPS + + AVX + + Unpacks and Interleaves single-precision floating-point values from low quadwords of ymm2 and ymm3/m256. + + + VUNPCKLPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 14 /r + + AVX512VL + AVX512F + + Unpacks and Interleaves single-precision floating-point values from low quadwords of xmm2 and xmm3/mem and write result to xmm1 subject to write mask k1. + + + VUNPCKLPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 14 /r + + AVX512VL + AVX512F + + Unpacks and Interleaves single-precision floating-point values from low quadwords of ymm2 and ymm3/mem and write result to ymm1 subject to write mask k1. + + + VUNPCKLPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.0F.W0 14 /r + + AVX512F + + Unpacks and Interleaves single-precision floating-point values from low quadwords of zmm2 and zmm3/m512/m32bcst and write result to zmm1 subject to write mask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + XORPD--Bitwise Logical XOR of Packed Double Precision Floating-Point Values. + + XORPD + xmm1,xmm2/m128 + 66 0F 57/r + + SSE2 + + Return the bitwise logical XOR of packed doubleprecision floating-point values in xmm1 and xmm2/mem. + + + VXORPD + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.66.0F.WIG 57 /r + + AVX + + Return the bitwise logical XOR of packed doubleprecision floating-point values in xmm2 and xmm3/mem. + + + VXORPD + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.66.0F.WIG 57 /r + + AVX + + Return the bitwise logical XOR of packed doubleprecision floating-point values in ymm2 and ymm3/mem. + + + VXORPD + xmm1 {k1}{z},xmm2,xmm3/m128/m64bcst + EVEX.NDS.128.66.0F.W1 57 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical XOR of packed doubleprecision floating-point values in xmm2 and xmm3/m128/m64bcst subject to writemask k1. + + + VXORPD + ymm1 {k1}{z},ymm2,ymm3/m256/m64bcst + EVEX.NDS.256.66.0F.W1 57 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical XOR of packed doubleprecision floating-point values in ymm2 and ymm3/m256/m64bcst subject to writemask k1. + + + VXORPD + zmm1 {k1}{z},zmm2,zmm3/m512/m64bcst + EVEX.NDS.512.66.0F.W1 57 /r + + AVX512DQ + + Return the bitwise logical XOR of packed doubleprecision floating-point values in zmm2 and zmm3/m512/m64bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv(r) + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + XORPS--Bitwise Logical XOR of Packed Single Precision Floating-Point Values. + + XORPS + xmm1,xmm2/m128 + 0F 57 /r + + SSE + + Return the bitwise logical XOR of packed singleprecision floating-point values in xmm1 and xmm2/mem. + + + VXORPS + xmm1,xmm2,xmm3/m128 + VEX.NDS.128.0F.WIG 57 /r + + AVX + + Return the bitwise logical XOR of packed singleprecision floating-point values in xmm2 and xmm3/mem. + + + VXORPS + ymm1,ymm2,ymm3/m256 + VEX.NDS.256.0F.WIG 57 /r + + AVX + + Return the bitwise logical XOR of packed singleprecision floating-point values in ymm2 and ymm3/mem. + + + VXORPS + xmm1 {k1}{z},xmm2,xmm3/m128/m32bcst + EVEX.NDS.128.0F.W0 57 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical XOR of packed singleprecision floating-point values in xmm2 and xmm3/m128/m32bcst subject to writemask k1. + + + VXORPS + ymm1 {k1}{z},ymm2,ymm3/m256/m32bcst + EVEX.NDS.256.0F.W0 57 /r + + AVX512VL + AVX512DQ + + Return the bitwise logical XOR of packed singleprecision floating-point values in ymm2 and ymm3/m256/m32bcst subject to writemask k1. + + + VXORPS + zmm1 {k1}{z},zmm2,zmm3/m512/m32bcst + EVEX.NDS.512.0F.W0 57 /r + + AVX512DQ + + Return the bitwise logical XOR of packed singleprecision floating-point values in zmm2 and zmm3/m512/m32bcst subject to writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + ModRM:reg(w) + VEX.vvvv + ModRM:r/m(r) + NA + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + KADDW/KADDB/KADDQ/KADDD--ADD Two Masks. + + KADDW + k1,k2,k3 + VEX.L1.0F.W0 4A /r + + AVX512DQ + + Add 16 bits masks in k2 and k3 and place result in k1. + + + KADDB + k1,k2,k3 + VEX.L1.66.0F.W0 4A /r + + AVX512DQ + + Add 8 bits masks in k2 and k3 and place result in k1. + + + KADDQ + k1,k2,k3 + VEX.L1.0F.W1 4A /r + + AVX512BW + + Add 64 bits masks in k2 and k3 and place result in k1. + + + KADDD + k1,k2,k3 + VEX.L1.66.0F.W1 4A /r + + AVX512BW + + Add 32 bits masks in k2 and k3 and place result in k1. + + + ModRM:reg(w) + VEX.1vvv(r) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + + + + KANDW/KANDB/KANDQ/KANDD--Bitwise Logical AND Masks. + + KANDW + k1,k2,k3 + VEX.NDS.L1.0F.W0 41 /r + + AVX512F + + Bitwise AND 16 bits masks k2 and k3 and place result in k1. + + + KANDB + k1,k2,k3 + VEX.L1.66.0F.W0 41 /r + + AVX512DQ + + Bitwise AND 8 bits masks k2 and k3 and place result in k1. + + + KANDQ + k1,k2,k3 + VEX.L1.0F.W1 41 /r + + AVX512BW + + Bitwise AND 64 bits masks k2 and k3 and place result in k1. + + + KANDD + k1,k2,k3 + VEX.L1.66.0F.W1 41 /r + + AVX512BW + + Bitwise AND 32 bits masks k2 and k3 and place result in k1. + + + ModRM:reg(w) + VEX.1vvv(r) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + + + + KANDNW/KANDNB/KANDNQ/KANDND--Bitwise Logical AND NOT Masks. + + KANDNW + k1,k2,k3 + VEX.NDS.L1.0F.W0 42 /r + + AVX512F + + Bitwise AND NOT 16 bits masks k2 and k3 and place result in k1. + + + KANDNB + k1,k2,k3 + VEX.L1.66.0F.W0 42 /r + + AVX512DQ + + Bitwise AND NOT 8 bits masks k1 and k2 and place result in k1. + + + KANDNQ + k1,k2,k3 + VEX.L1.0F.W1 42 /r + + AVX512BW + + Bitwise AND NOT 64 bits masks k2 and k3 and place result in k1. + + + KANDND + k1,k2,k3 + VEX.L1.66.0F.W1 42 /r + + AVX512BW + + Bitwise AND NOT 32 bits masks k2 and k3 and place result in k1. + + + ModRM:reg(w) + VEX.1vvv(r) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + + + + KMOVW/KMOVB/KMOVQ/KMOVD--Move from and to Mask Registers. + + KMOVW + k1,k2/m16 + VEX.L0.0F.W0 90 /r + + AVX512F + + Move 16 bits mask from k2/m16 and store the result in k1. + + + KMOVB + k1,k2/m8 + VEX.L0.66.0F.W0 90 /r + + AVX512DQ + + Move 8 bits mask from k2/m8 and store the result in k1. + + + KMOVQ + k1,k2/m64 + VEX.L0.0F.W1 90 /r + + AVX512BW + + Move 64 bits mask from k2/m64 and store the result in k1. + + + KMOVD + k1,k2/m32 + VEX.L0.66.0F.W1 90 /r + + AVX512BW + + Move 32 bits mask from k2/m32 and store the result in k1. + + + KMOVW + m16,k1 + VEX.L0.0F.W0 91 /r + + AVX512F + + Move 16 bits mask from k1 and store the result in m16. + + + KMOVB + m8,k1 + VEX.L0.66.0F.W0 91 /r + + AVX512DQ + + Move 8 bits mask from k1 and store the result in m8. + + + KMOVQ + m64,k1 + VEX.L0.0F.W1 91 /r + + AVX512BW + + Move 64 bits mask from k1 and store the result in m64. + + + KMOVD + m32,k1 + VEX.L0.66.0F.W1 91 /r + + AVX512BW + + Move 32 bits mask from k1 and store the result in m32. + + + KMOVW + k1,r32 + VEX.L0.0F.W0 92 /r + + AVX512F + + Move 16 bits mask from r32 to k1. + + + KMOVB + k1,r32 + VEX.L0.66.0F.W0 92 /r + + AVX512DQ + + Move 8 bits mask from r32 to k1. + + + KMOVQ + k1,r64 + VEX.L0.F2.0F.W1 92 /r + + AVX512BW + + Move 64 bits mask from r64 to k1. + + + KMOVD + k1,r32 + VEX.L0.F2.0F.W0 92 /r + + AVX512BW + + Move 32 bits mask from r32 to k1. + + + KMOVW + r32,k1 + VEX.L0.0F.W0 93 /r + + AVX512F + + Move 16 bits mask from k1 to r32. + + + KMOVB + r32,k1 + VEX.L0.66.0F.W0 93 /r + + AVX512DQ + + Move 8 bits mask from k1 to r32. + + + KMOVQ + r64,k1 + VEX.L0.F2.0F.W1 93 /r + + AVX512BW + + Move 64 bits mask from k1 to r64. + + + KMOVD + r32,k1 + VEX.L0.F2.0F.W0 93 /r + + AVX512BW + + Move 32 bits mask from k1 to r32. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + ModRM:r/m(w, ModRM:[7:6] must not be 11b) + ModRM:reg(r) + NA + NA + + + ModRM:reg(w) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + NA + + + + KUNPCKBW/KUNPCKWD/KUNPCKDQ--Unpack for Mask Registers. + + KUNPCKBW + k1,k2,k3 + VEX.NDS.L1.66.0F.W0 4B /r + + AVX512F + + Unpack and interleave 8 bits masks in k2 and k3 and write word result in k1. + + + KUNPCKWD + k1,k2,k3 + VEX.NDS.L1.0F.W0 4B /r + + AVX512BW + + Unpack and interleave 16 bits in k2 and k3 and write doubleword result in k1. + + + KUNPCKDQ + k1,k2,k3 + VEX.NDS.L1.0F.W1 4B /r + + AVX512BW + + Unpack and interleave 32 bits masks in k2 and k3 and write quadword result in k1. + + + ModRM:reg(w) + VEX.1vvv(r) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + + + + KNOTW/KNOTB/KNOTQ/KNOTD--NOT Mask Register. + + KNOTW + k1,k2 + VEX.L0.0F.W0 44 /r + + AVX512F + + Bitwise NOT of 16 bits mask k2. + + + KNOTB + k1,k2 + VEX.L0.66.0F.W0 44 /r + + AVX512DQ + + Bitwise NOT of 8 bits mask k2. + + + KNOTQ + k1,k2 + VEX.L0.0F.W1 44 /r + + AVX512BW + + Bitwise NOT of 64 bits mask k2. + + + KNOTD + k1,k2 + VEX.L0.66.0F.W1 44 /r + + AVX512BW + + Bitwise NOT of 32 bits mask k2. + + + ModRM:reg(w) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + NA + + + + KORW/KORB/KORQ/KORD--Bitwise Logical OR Masks. + + KORW + k1,k2,k3 + VEX.NDS.L1.0F.W0 45 /r + + AVX512F + + Bitwise OR 16 bits masks k2 and k3 and place result in k1. + + + KORB + k1,k2,k3 + VEX.L1.66.0F.W0 45 /r + + AVX512DQ + + Bitwise OR 8 bits masks k2 and k3 and place result in k1. + + + KORQ + k1,k2,k3 + VEX.L1.0F.W1 45 /r + + AVX512BW + + Bitwise OR 64 bits masks k2 and k3 and place result in k1. + + + KORD + k1,k2,k3 + VEX.L1.66.0F.W1 45 /r + + AVX512BW + + Bitwise OR 32 bits masks k2 and k3 and place result in k1. + + + ModRM:reg(w) + VEX.1vvv(r) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + + + + KORTESTW/KORTESTB/KORTESTQ/KORTESTD--OR Masks And Set Flags. + + KORTESTW + k1,k2 + VEX.L0.0F.W0 98 /r + + AVX512F + + Bitwise OR 16 bits masks k1 and k2 and update ZF and CF accordingly. + + + KORTESTB + k1,k2 + VEX.L0.66.0F.W0 98 /r + + AVX512DQ + + Bitwise OR 8 bits masks k1 and k2 and update ZF and CF accordingly. + + + KORTESTQ + k1,k2 + VEX.L0.0F.W1 98 /r + + AVX512BW + + Bitwise OR 64 bits masks k1 and k2 and update ZF and CF accordingly. + + + KORTESTD + k1,k2 + VEX.L0.66.0F.W1 98 /r + + AVX512BW + + Bitwise OR 32 bits masks k1 and k2 and update ZF and CF accordingly. + + + ModRM:reg(w) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + NA + + + + KSHIFTLW/KSHIFTLB/KSHIFTLQ/KSHIFTLD--Shift Left Mask Registers. + + KSHIFTLW + k1,k2,imm8 + VEX.L0.66.0F3A.W1 32 /r + + AVX512F + + Shift left 16 bits in k2 by immediate and write result in k1. + + + KSHIFTLB + k1,k2,imm8 + VEX.L0.66.0F3A.W0 32 /r + + AVX512DQ + + Shift left 8 bits in k2 by immediate and write result in k1. + + + KSHIFTLQ + k1,k2,imm8 + VEX.L0.66.0F3A.W1 33 /r + + AVX512BW + + Shift left 64 bits in k2 by immediate and write result in k1. + + + KSHIFTLD + k1,k2,imm8 + VEX.L0.66.0F3A.W0 33 /r + + AVX512BW + + Shift left 32 bits in k2 by immediate and write result in k1. + + + ModRM:reg(w) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + Imm8 + NA + + + + KSHIFTRW/KSHIFTRB/KSHIFTRQ/KSHIFTRD--Shift Right Mask Registers. + + KSHIFTRW + k1,k2,imm8 + VEX.L0.66.0F3A.W1 30 /r + + AVX512F + + Shift right 16 bits in k2 by immediate and write result in k1. + + + KSHIFTRB + k1,k2,imm8 + VEX.L0.66.0F3A.W0 30 /r + + AVX512DQ + + Shift right 8 bits in k2 by immediate and write result in k1. + + + KSHIFTRQ + k1,k2,imm8 + VEX.L0.66.0F3A.W1 31 /r + + AVX512BW + + Shift right 64 bits in k2 by immediate and write result in k1. + + + KSHIFTRD + k1,k2,imm8 + VEX.L0.66.0F3A.W0 31 /r + + AVX512BW + + Shift right 32 bits in k2 by immediate and write result in k1. + + + ModRM:reg(w) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + Imm8 + NA + + + + KXNORW/KXNORB/KXNORQ/KXNORD--Bitwise Logical XNOR Masks. + + KXNORW + k1,k2,k3 + VEX.NDS.L1.0F.W0 46 /r + + AVX512F + + Bitwise XNOR 16 bits masks k2 and k3 and place result in k1. + + + KXNORB + k1,k2,k3 + VEX.L1.66.0F.W0 46 /r + + AVX512DQ + + Bitwise XNOR 8 bits masks k2 and k3 and place result in k1. + + + KXNORQ + k1,k2,k3 + VEX.L1.0F.W1 46 /r + + AVX512BW + + Bitwise XNOR 64 bits masks k2 and k3 and place result in k1. + + + KXNORD + k1,k2,k3 + VEX.L1.66.0F.W1 46 /r + + AVX512BW + + Bitwise XNOR 32 bits masks k2 and k3 and place result in k1. + + + ModRM:reg(w) + VEX.1vvv(r) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + + + + KTESTW/KTESTB/KTESTQ/KTESTD--Packed Bit Test Masks and Set Flags. + + RR + KTESTW k1,k2 + VEX.L0.0F.W0 99 /r + + AVX512DQ + + Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask register sources. + + + RR + KTESTB k1,k2 + VEX.L0.66.0F.W0 99 /r + + AVX512DQ + + Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask register sources. + + + RR + KTESTQ k1,k2 + VEX.L0.0F.W1 99 /r + + AVX512BW + + Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask register sources. + + + RR + KTESTD k1,k2 + VEX.L0.66.0F.W1 99 /r + + AVX512BW + + Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask register sources. + + + ModRM:reg(r) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + NA + + + + KXORW/KXORB/KXORQ/KXORD--Bitwise Logical XOR Masks. + + KXORW + k1,k2,k3 + VEX.NDS.L1.0F.W0 47 /r + + AVX512F + + Bitwise XOR 16 bits masks k2 and k3 and place result in k1. + + + KXORB + k1,k2,k3 + VEX.L1.66.0F.W0 47 /r + + AVX512DQ + + Bitwise XOR 8 bits masks k2 and k3 and place result in k1. + + + KXORQ + k1,k2,k3 + VEX.L1.0F.W1 47 /r + + AVX512BW + + Bitwise XOR 64 bits masks k2 and k3 and place result in k1. + + + KXORD + k1,k2,k3 + VEX.L1.66.0F.W1 47 /r + + AVX512BW + + Bitwise XOR 32 bits masks k2 and k3 and place result in k1. + + + ModRM:reg(w) + VEX.1vvv(r) + ModRM:r/m(r, ModRM:[7:6] must be 11b) + NA + + + + VEXP2PD--Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error. + + VEXP2PD + zmm1 {k1}{z},zmm2/m512/m64bcst {sae} + EVEX.512.66.0F38.W1 C8 /r + + AVX512ER + + Computes approximations to the exponential 2^x (with less than 2^-23 of maximum relative error) of the packed doubleprecision floating-point values from zmm2/m512/m64bcst and stores the floating-point result in zmm1with writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + + VEXP2PS--Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error. + + VEXP2PS + zmm1 {k1}{z},zmm2/m512/m32bcst {sae} + EVEX.512.66.0F38.W0 C8 /r + + AVX512ER + + Computes approximations to the exponential 2^x (with less than 2^-23 of maximum relative error) of the packed singleprecision floating-point values from zmm2/m512/m32bcst and stores the floating-point result in zmm1with writemask k1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + + VRCP28PD--Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error. + + VRCP28PD + zmm1 {k1}{z},zmm2/m512/m64bcst {sae} + EVEX.512.66.0F38.W1 CA /r + + AVX512ER + + Computes the approximate reciprocals ( < 2^-28 relative error) of the packed double-precision floating-point values in zmm2/m512/m64bcst and stores the results in zmm1. Under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VRCP28SD--Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error. + + VRCP28SD + xmm1 {k1}{z},xmm2,xmm3/m64 {sae} + EVEX.NDS.LIG.66.0F38.W1 CB /r + + AVX512ER + + Computes the approximate reciprocal ( < 2^-28 relative error) of the scalar double-precision floating-point value in xmm3/m64 and stores the results in xmm1. Under writemask. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VRCP28PS--Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error. + + VRCP28PS + zmm1 {k1}{z},zmm2/m512/m32bcst {sae} + EVEX.512.66.0F38.W0 CA /r + + AVX512ER + + Computes the approximate reciprocals ( < 2^-28 relative error) of the packed single-precision floating-point values in zmm2/m512/m32bcst and stores the results in zmm1. Under writemask. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VRCP28SS--Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error. + + VRCP28SS + xmm1 {k1}{z},xmm2,xmm3/m32 {sae} + EVEX.NDS.LIG.66.0F38.W0 CB /r + + AVX512ER + + Computes the approximate reciprocal ( < 2^-28 relative error) of the scalar single-precision floating-point value in xmm3/m32 and stores the results in xmm1. Under writemask. Also, upper 3 single-precision floating-point values (bits[127:32]) from xmm2 is copied to xmm1[127:32]. + + + ModRM:reg(w) + EVEX.vvvv + ModRM:r/m(r) + NA + + + + VRSQRT28PD--Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error. + + VRSQRT28PD + zmm1 {k1}{z},zmm2/m512/m64bcst {sae} + EVEX.512.66.0F38.W1 CC /r + + AVX512ER + + Computes approximations to the Reciprocal square root (<2^28 relative error) of the packed double-precision floating-point values from zmm2/m512/m64bcst and stores result in zmm1with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VRSQRT28SD--Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error. + + VRSQRT28SD + xmm1 {k1}{z},xmm2,xmm3/m64 {sae} + EVEX.NDS.LIG.66.0F38.W1 CD /r + + AVX512ER + + Computes approximate reciprocal square root (<2^-28 relative error) of the scalar double-precision floating-point value from xmm3/m64 and stores result in xmm1with writemask k1. Also, upper double-precision floating-point value (bits[127:64]) from xmm2 is copied to xmm1[127:64]. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VRSQRT28PS--Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error. + + VRSQRT28PS + zmm1 {k1}{z},zmm2/m512/m32bcst {sae} + EVEX.512.66.0F38.W0 CC /r + + AVX512ER + + Computes approximations to the Reciprocal square root (<2^-28 relative error) of the packed single-precision floating-point values from zmm2/m512/m32bcst and stores result in zmm1with writemask k1. + + + ModRM:reg(w) + ModRM:r/m(r) + NA + NA + + + + VRSQRT28SS--Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error. + + VRSQRT28SS + xmm1 {k1}{z},xmm2,xmm3/m32 {sae} + EVEX.NDS.LIG.66.0F38.W0 CD /r + + AVX512ER + + Computes approximate reciprocal square root (<2^-28 relative error) of the scalar single-precision floating-point value from xmm3/m32 and stores result in xmm1with writemask k1. Also, upper 3 single-precision floating-point value (bits[127:32]) from xmm2 is copied to xmm1[127:32]. + + + ModRM:reg(w) + EVEX.vvvv(r) + ModRM:r/m(r) + NA + + + + VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD--Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint. + + VGATHERPF0DPS + vm32z {k1} + EVEX.512.66.0F38.W0 C6 /1 /vsib + + AVX512PF + + Using signed dword indices, prefetch sparse byte memory locations containing single-precision data using opmask k1 and T0 hint. + + + VGATHERPF0QPS + vm64z {k1} + EVEX.512.66.0F38.W0 C7 /1 /vsib + + AVX512PF + + Using signed qword indices, prefetch sparse byte memory locations containing single-precision data using opmask k1 and T0 hint. + + + VGATHERPF0DPD + vm32y {k1} + EVEX.512.66.0F38.W1 C6 /1 /vsib + + AVX512PF + + Using signed dword indices, prefetch sparse byte memory locations containing double-precision data using opmask k1 and T0 hint. + + + VGATHERPF0QPD + vm64z {k1} + EVEX.512.66.0F38.W1 C7 /1 /vsib + + AVX512PF + + Using signed qword indices, prefetch sparse byte memory locations containing double-precision data using opmask k1 and T0 hint. + + + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + NA + NA + NA + + + + VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD--Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint. + + VGATHERPF1DPS + vm32z {k1} + EVEX.512.66.0F38.W0 C6 /2 /vsib + + AVX512PF + + Using signed dword indices, prefetch sparse byte memory locations containing single-precision data using opmask k1 and T1 hint. + + + VGATHERPF1QPS + vm64z {k1} + EVEX.512.66.0F38.W0 C7 /2 /vsib + + AVX512PF + + Using signed qword indices, prefetch sparse byte memory locations containing single-precision data using opmask k1 and T1 hint. + + + VGATHERPF1DPD + vm32y {k1} + EVEX.512.66.0F38.W1 C6 /2 /vsib + + AVX512PF + + Using signed dword indices, prefetch sparse byte memory locations containing double-precision data using opmask k1 and T1 hint. + + + VGATHERPF1QPD + vm64z {k1} + EVEX.512.66.0F38.W1 C7 /2 /vsib + + AVX512PF + + Using signed qword indices, prefetch sparse byte memory locations containing double-precision data using opmask k1 and T1 hint. + + + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + NA + NA + NA + + + + VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD--Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write. + + VSCATTERPF0DPS + vm32z {k1} + EVEX.512.66.0F38.W0 C6 /5 /vsib + + AVX512PF + + Using signed dword indices, prefetch sparse byte memory locations containing single-precision data using writemask k1 and T0 hint with intent to write. + + + VSCATTERPF0QPS + vm64z {k1} + EVEX.512.66.0F38.W0 C7 /5 /vsib + + AVX512PF + + Using signed qword indices, prefetch sparse byte memory locations containing single-precision data using writemask k1 and T0 hint with intent to write. + + + VSCATTERPF0DPD + vm32y {k1} + EVEX.512.66.0F38.W1 C6 /5 /vsib + + AVX512PF + + Using signed dword indices, prefetch sparse byte memory locations containing double-precision data using writemask k1 and T0 hint with intent to write. + + + VSCATTERPF0QPD + vm64z {k1} + EVEX.512.66.0F38.W1 C7 /5 /vsib + + AVX512PF + + Using signed qword indices, prefetch sparse byte memory locations containing double-precision data using writemask k1 and T0 hint with intent to write. + + + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + NA + NA + NA + + + + VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD--Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write. + + VSCATTERPF1DPS + vm32z {k1} + EVEX.512.66.0F38.W0 C6 /6 /vsib + + AVX512PF + + Using signed dword indices, prefetch sparse byte memory locations containing single-precision data using writemask k1 and T1 hint with intent to write. + + + VSCATTERPF1QPS + vm64z {k1} + EVEX.512.66.0F38.W0 C7 /6 /vsib + + AVX512PF + + Using signed qword indices, prefetch sparse byte memory locations containing single-precision data using writemask k1 and T1 hint with intent to write. + + + VSCATTERPF1DPD + vm32y {k1} + EVEX.512.66.0F38.W1 C6 /6 /vsib + + AVX512PF + + Using signed dword indices, prefetch sparse byte memory locations containing double-precision data using writemask k1 and T1 hint with intent to write. + + + VSCATTERPF1QPD + vm64z {k1} + EVEX.512.66.0F38.W1 C7 /6 /vsib + + AVX512PF + + Using signed qword indices, prefetch sparse byte memory locations containing double-precision data using writemask k1 and T1 hint with intent to write. + + + BaseReg(R): VSIB:base,VectorReg(R): VSIB:index + NA + NA + NA + + + + SHA1RNDS4--Perform Four Rounds of SHA1 Operation. + + SHA1RNDS4 + xmm1,xmm2/m128,imm8 + 0F 3A CC /r ib + + SHA + + Performs four rounds of SHA1 operation operating on SHA1 state (A,B,C,D) from xmm1, with a pre-computed sum of the next 4 round message dwords and state variable E from xmm2/m128. The immediate byte controls logic functions and round constants. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Imm8 + NA + + + + SHA1NEXTE--Calculate SHA1 State Variable E after Four Rounds. + + SHA1NEXTE + xmm1,xmm2/m128 + 0F 38 C8 /r + + SHA + + Calculates SHA1 state variable E after four rounds of operation from the current SHA1 state variable A in xmm1. The calculated value of the SHA1 state variable E is added to the scheduled dwords in xmm2/m128, and stored with some of the scheduled dwords in xmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + + SHA1MSG1--Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords. + + SHA1MSG1 + xmm1,xmm2/m128 + 0F 38 C9 /r + + SHA + + Performs an intermediate calculation for the next four SHA1 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + + SHA1MSG2--Perform a Final Calculation for the Next Four SHA1 Message Dwords. + + SHA1MSG2 + xmm1,xmm2/m128 + 0F 38 CA /r + + SHA + + Performs the final calculation for the next four SHA1 message dwords using intermediate results from xmm1 and the previous message dwords from xmm2/m128, storing the result in xmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + + SHA256RNDS2--Perform Two Rounds of SHA256 Operation. + + SHA256RNDS2 + xmm1,xmm2/m128,<XMM0> + 0F 38 CB /r + + SHA + + Perform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from xmm1, an initial SHA256 state (A,B,E,F) from xmm2/m128, and a pre-computed sum of the next 2 round message dwords and the corresponding round constants from the implicit operand XMM0, storing the updated SHA256 state (A,B,E,F) result in xmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + Implicit XMM0(r) + NA + + + + SHA256MSG1--Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords. + + SHA256MSG1 + xmm1,xmm2/m128 + 0F 38 CC /r + + SHA + + Performs an intermediate calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + + SHA256MSG2--Perform a Final Calculation for the Next Four SHA256 Message Dwords. + + SHA256MSG2 + xmm1,xmm2/m128 + 0F 38 CD /r + + SHA + + Performs the final calculation for the next four SHA256 message dwords using previous message dwords from xmm1 and xmm2/m128, storing the result in xmm1. + + + ModRM:reg(r,w) + ModRM:r/m(r) + NA + NA + + + + PREFETCHWT1--Prefetch Vector Data Into Caches with Intent to Write and T1 Hint. + + PREFETCHWT1 + m8 + 0F 0D /2 + + PREFETCHWT1 + + Move data from m8 closer to the processor using T1 hint with intent to write. + + + ModRM:r/m(r) + NA + NA + NA + + + + CLWB--Cache Line Write Back (THIS IS AN EXAMPLE). + + CLWB + m8 + 66 0F AE /6 + + CLWB + + Writes back modified cache line containing m8, and may retain the line in cache hierarchy in non-modified state. + + + ModRM:r/m(w) + NA + NA + NA + + + NA + NA + NA + NA + + + + CLWB--Cache Line Write Back. + + CLWB + m8 + 66 0F AE /6 + + CLWB + + Writes back modified cache line containing m8, and may retain the line in cache hierarchy in non-modified state. + + + ModRM:r/m(w) + NA + NA + NA + + + + PCOMMIT--Persistent Commit. + + PCOMMIT + void + 66 0F AE F8 + + PCOMMIT + + Commits stores to persistent memory. + + + NA + NA + NA + NA + + + \ No newline at end of file