mykola/Parsable-Instructions
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Commit graph

  • 157a6cc9a2 add todo master mykola2312 2024-08-14 03:50:54 +03:00
  • 81671b4652 implement C table generator mykola2312 2024-08-14 01:08:37 +03:00
  • 1de12a1f82 final steps to the lookup table generator mykola2312 2024-08-13 21:30:03 +03:00
  • 5e8ddc2c32 add traits to instructions for decoder table mykola2312 2024-08-13 21:02:59 +03:00
  • dbec45533b begin working on EVEX parsing mykola2312 2024-08-13 20:22:57 +03:00
  • ea4f1d7308 fix typo in evex.l field mykola2312 2024-08-13 20:21:45 +03:00
  • ce12de6fc3 implement VEX parser mykola2312 2024-08-13 18:10:37 +03:00
  • db68712b3e fix typo mykola2312 2024-08-13 16:28:52 +03:00
  • c6ee87c4c0 add OOP boilerplate to ease VEX/EVEX parsing logic mykola2312 2024-08-13 16:01:05 +03:00
  • 5e8df2bd51 generate dump list of VEX and EVEX instructions mykola2312 2024-08-13 15:36:03 +03:00
  • 5b739f6054 add branching and instruction types for future VEX parser mykola2312 2024-08-01 04:38:09 +03:00
  • a681a53ff3 now I can definitely tell if instruction has ModRM byte or no mykola2312 2024-08-01 02:37:08 +03:00
  • 5998950f23 begin implementing intel opcode syntax parser mykola2312 2024-08-01 02:24:43 +03:00
  • 24c290e29e fix typo mykola2312 2024-08-01 00:33:32 +03:00
  • 954e5cc96a update on plan mykola2312 2024-08-01 00:33:01 +03:00
  • e8ae5937f8 update on vex mykola2312 2024-07-31 23:29:08 +03:00
  • 0f8e380dac skip even more 16 bit crap mykola2312 2024-07-29 00:46:58 +03:00
  • ac909fc71f add some notes mykola2312 2024-07-27 21:23:18 +03:00
  • 095d90776e add another 16 bit real mode filter mykola2312 2024-07-25 03:53:45 +03:00
  • 9a7c47b03e update readme mykola2312 2024-07-25 03:42:04 +03:00
  • 467331c693 strip rel16 since we're not going to encounter real mode in running processes on Linux or FreeBSD mykola2312 2024-07-25 03:40:06 +03:00
  • f81b7f524e fix regex mykola2312 2024-07-25 03:01:19 +03:00
  • 8b9742ca42 implement opcode parsing mykola2312 2024-07-25 01:29:02 +03:00
  • 0310704f2b begin working on script to generate C files for my future disassembler mykola2312 2024-07-25 00:35:46 +03:00
  • 81c506ffb5 Update README.md Mahdi Safsafi 2017-03-02 10:58:35 +01:00
  • 8c0d3f17e1 Merge pull request #1 from mquigley/patch-1 Mahdi Safsafi 2016-10-05 09:06:56 +01:00
  • 61b8854649 Fix mismatch of operand encoding for PREFETCHW mquigley 2016-10-04 19:38:10 -07:00
  • 244d17dadc Update README.md Mahdi Safsafi 2016-03-30 03:31:09 +02:00
  • 8cb15e5226 Update README.md Mahdi Safsafi 2016-03-27 23:15:38 +02:00
  • 2297196c9b Update README.md Mahdi Safsafi 2016-03-27 04:24:00 +02:00
  • c56122daaf Update README.md Mahdi Safsafi 2016-03-27 03:28:21 +02:00
  • 39f277e465 Added latest instructions found in Intel doc #319433-024(FEBRUARY 2016). Renamed AVX512.xml to AVX512_r22 (OCTOBER 2014). Mahdi Safsafi 2016-03-27 03:20:11 +02:00
  • 9bd0f37091 Fix bug in AVX512.xml. Mahdi Safsafi 2016-03-26 22:35:58 +01:00
  • 540c9d5f8e Fix some minor bugs found in AZ.xml. Mahdi Safsafi 2016-03-26 22:18:46 +01:00
  • 99db987520 Update README.md Mahdi Safsafi 2015-09-03 18:38:24 +02:00
  • 393aac9800 Added AMD (3DNow!,SSE5 and XOP)Instructions. XML Refactoring. Mahdi Safsafi 2015-09-03 18:29:55 +02:00
  • e56d77147c Include project link Mahdi Safsafi 2015-09-01 15:49:29 +02:00
  • 6504d7b007 First Commit. Mahdi Safsafi 2015-09-01 15:28:20 +02:00
  • a73eca5531 Update README.md Mahdi Safsafi 2015-09-01 15:27:16 +02:00
  • 4551c1013c Initial commit Mahdi Safsafi 2015-09-01 15:08:45 +02:00