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merge Parsable-Instructions into this project for integrity. rtdisasm needs lookup tables of instruction opcodes

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mykola2312 2024-08-14 17:24:34 +03:00
parent 585d940ece
commit b0e89a263c
15 changed files with 77133 additions and 7 deletions
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11
Makefile
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@ -8,13 +8,13 @@ CC = gcc
AS = as AS = as
AR = ar AR = ar
LD = ld LD = ld
GZIP = gzip PYTHON = python
CFLAGS = -Wall -I$(INC_DIR) CFLAGS = -Wall -I$(INC_DIR)
ASFLAGS = ASFLAGS =
LDFLAGS = -z noexecstack -lcap LDFLAGS = -z noexecstack -lcap
RTDISASM_SRC = rtdisasm.c RTDISASM_SRC = rtdisasm.c
RTDISASM_OBJ := $(addprefix $(OBJ_DIR)/,$(patsubst %.s,%.o,$(patsubst %.c,%.o,$(RTDISASM_SRC)))) $(OBJ_DIR)/rtdisasm_table.o RTDISASM_OBJ := $(addprefix $(OBJ_DIR)/,$(patsubst %.s,%.o,$(patsubst %.c,%.o,$(RTDISASM_SRC))))
RTDISASM_SRC := $(addprefix $(SRC_DIR)/,$(RTDISASM_SRC)) RTDISASM_SRC := $(addprefix $(SRC_DIR)/,$(RTDISASM_SRC))
RTDISASM_DEPS = rtdisasm.h rtdisasm_table.h RTDISASM_DEPS = rtdisasm.h rtdisasm_table.h
RTDISASM_DEPS := $(addprefix $(INC_DIR)/,$(RTDISASM_DEPS)) RTDISASM_DEPS := $(addprefix $(INC_DIR)/,$(RTDISASM_DEPS))
@ -38,15 +38,12 @@ DUMMY_TARGET_SRC := $(addprefix $(SRC_DIR)/,$(DUMMY_TARGET_SRC))
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.c $(OBJ_DIR)/%.o: $(SRC_DIR)/%.c
$(CC) $(CFLAGS) -c -o $@ $< $(CC) $(CFLAGS) -c -o $@ $<
# compressed C files
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cgz
$(GZIP) -d -c $< | $(CC) -x c $(CFLAGS) -c -o $@ -
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.s $(OBJ_DIR)/%.o: $(SRC_DIR)/%.s
$(AS) $(ASFLAGS) -o $@ $< $(AS) $(ASFLAGS) -o $@ $<
rtdisasm: $(RTDISASM_OBJ) $(RTDISASM_DEPS) rtdisasm: $(RTDISASM_OBJ) $(RTDISASM_DEPS)
$(AR) -crs $(BIN_DIR)/librtdisasm.a $(RTDISASM_OBJ) $(PYTHON) genc.py | $(CC) -x c $(CFLAGS) -c -o $(OBJ_DIR)/rtdisasm_table.o -
$(AR) -crs $(BIN_DIR)/librtdisasm.a $(RTDISASM_OBJ) $(OBJ_DIR)/rtdisasm_table.o
rtdisasm_test: $(RTDISASM_TEST_OBJ) $(RTDISASM_TEST_DEPS) rtdisasm_test: $(RTDISASM_TEST_OBJ) $(RTDISASM_TEST_DEPS)
$(CC) $(LDFLAGS) $(LIB_DIR)/librtdisasm.a -o $(BIN_DIR)/$@ $(RTDISASM_TEST_OBJ) $(CC) $(LDFLAGS) $(LIB_DIR)/librtdisasm.a -o $(BIN_DIR)/$@ $(RTDISASM_TEST_OBJ)

245
genc.py Normal file
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@ -0,0 +1,245 @@
import re
import xml.etree.ElementTree as ET
from enum import Enum
class InstructionType(Enum):
STANDARD = 0
VEX = 1
EVEX = 2
def __str__(self):
if self == InstructionType.STANDARD: return "std"
elif self == InstructionType.VEX: return "vex"
elif self == InstructionType.EVEX: return "evex"
def value(self):
if self == InstructionType.STANDARD: return 0
elif self == InstructionType.VEX: return 1
elif self == InstructionType.EVEX: return 2
class Instruction:
def __init__(self, ins):
self._opc = ins.find("opc").text
self.x32m = ins.attrib["x32m"]
self.x64m = ins.attrib["x64m"]
self.mnemonic = ins.find("mnem").text
self.bytes = None
def get_type(self):
pass
def has_rex(self):
return False
def has_digit(self):
return False
def has_modrm(self):
return False
def has_imm(self):
return False
def has_value(self):
return False
def has_opreg(self):
return False
def __str__(self):
return f"<{self.get_type()}> {self.mnemonic} bytes {self.bytes} rex {self.has_rex()} digit {self.has_digit()} modrm {self.has_modrm()} imm {self.has_imm()} value {self.has_value()} opreg {self.has_opreg()}"
class InstructionCommon:
REX_REGEX = re.compile("^REX\\.(.)")
BYTES_REGEX = re.compile("([0-9A-F][0-9A-F])")
DIGIT_REGEX = re.compile("\\/(\\d)")
MODRM_REGEX = re.compile("\\/r")
IMM_REGEX = re.compile("i(.)")
VALUE_REGEX = re.compile("c(.)")
OPREG_REGEX = re.compile("r(.)")
class StandardInstruction(Instruction):
def __init__(self, ins):
super().__init__(ins)
rex = InstructionCommon.REX_REGEX.search(self._opc)
bytes = InstructionCommon.BYTES_REGEX.findall(self._opc)
digit = InstructionCommon.DIGIT_REGEX.search(self._opc)
modrm = InstructionCommon.MODRM_REGEX.search(self._opc)
imm = InstructionCommon.IMM_REGEX.search(self._opc)
value = InstructionCommon.VALUE_REGEX.search(self._opc)
opreg = InstructionCommon.OPREG_REGEX.search(self._opc)
self.bytes = bytes
self.rex = None
self.digit = None
self.modrm = False
self.imm = None
self.value = None
self.opreg = None
if rex: self.rex = rex.group(1)
if digit: self.digit = int(digit.group(1))
if modrm: self.modrm = True
if imm: self.imm = imm.group(1)
if value: self.value = value.group(1)
if opreg: self.opreg = opreg.group(1)
def get_type(self):
return InstructionType.STANDARD
def has_rex(self):
return self.rex is not None
def has_digit(self):
return self.digit is not None
def has_modrm(self):
return self.modrm or (self.digit is not None)
def has_imm(self):
return self.imm is not None
def has_value(self):
return self.value is not None
def has_opreg(self):
return self.opreg is not None
class VEXInstruction(Instruction):
def __init__(self, ins):
super().__init__(ins)
# fix string because intel employees keep bashing keyboard with random keys
self._opc = re.sub(r"\. ", ".", self._opc)
parts = self._opc.split(" ")
(vex, opc) = (parts[0], "".join(parts[1:]))
vex_parts = vex.split(".")
self.lig = False
if "128" in vex_parts or "L0" in vex_parts or "LZ" in vex_parts:
self.l = 128
elif "256" in vex_parts or "L1" in vex_parts:
self.l = 256
elif "LIG" in vex_parts:
self.l = 0
self.lig = True
else: raise RuntimeError("VEX.L is unknown!")
self.wig = False
if "W0" in vex_parts: self.w = False
elif "W1" in vex_parts: self.w = True
elif "WIG" in vex_parts:
self.wig = True
self.w = False
else: self.w = False # just default it to False, it's not a big deal
self.bytes = InstructionCommon.BYTES_REGEX.findall(opc)
modrm = InstructionCommon.MODRM_REGEX.search(opc)
imm = InstructionCommon.IMM_REGEX.search(opc)
self.modrm = True if modrm else False
self.imm = imm.group(1) if imm else None
def get_type(self):
return InstructionType.VEX
def has_modrm(self):
return self.modrm
def has_imm(self):
return self.imm is not None
class EVEXInstruction(Instruction):
def __init__(self, ins):
super().__init__(ins)
# fix string because intel employees keep bashing keyboard with random keys
self._opc = re.sub(r"\. ", ".", self._opc)
parts = self._opc.split(" ")
(evex, opc) = (parts[0], "".join(parts[1:]))
evex_parts = evex.split(".")
print(evex, opc)
self.lig = False
if "128" in evex_parts: self.l = 128
elif "256" in evex_parts: self.l = 256
elif "512" in evex_parts: self.l = 512
elif "LIG" in evex_parts or "LLIG" in evex_parts:
self.l = 0
self.lig = True
else: raise RuntimeError("EVEX.L and EVEX.LIG is unknown!")
self.wig = False
if "W0" in evex_parts: self.w = False
elif "W1" in evex_parts: self.w = True
elif "WIG" in evex_parts:
self.w = False
self.wig = True
else: self.w = False
self.bytes = InstructionCommon.BYTES_REGEX.findall(opc)
modrm = InstructionCommon.MODRM_REGEX.search(opc)
imm = InstructionCommon.IMM_REGEX.search(opc)
self.modrm = True if modrm else False
self.imm = imm.group(1) if imm else None
def get_type(self):
return InstructionType.EVEX
def has_modrm(self):
return self.modrm
def has_imm(self):
return self.imm is not None
def parse_instruction(ins):
opc = ins.find("opc").text
if "EVEX" in opc: return EVEXInstruction(ins)
elif "VEX" in opc: return VEXInstruction(ins)
else: return StandardInstruction(ins)
class InstructionGroup:
def __init__(self, common):
self.brief = common.find("brief").text
self.instructions = [parse_instruction(ins) for ins in common.iter("ins")]
def parse_file(path):
tree = ET.parse(path)
root = tree.getroot()
groups = [InstructionGroup(common) for common in root.iter("common")]
return groups
# TODO: instead of gzipping pipe directly C code into GCC
# FIXME: instruction_t has no actual rex, imm, value values
def generate_table(groups):
table_len = 0
# header
print("#include \"rtdisasm_table.h\"\n")
print("const instruction_t rtdisasm_table[] = {")
# entries
for group in groups:
for i in group.instructions:
opcode = ",".join(["0x{}".format(byte) for byte in i.bytes])
opcode_len = len(i.bytes)
print("\t{{ .info = {{ .type = {}, .has_rex = {}, .has_digit = {}, .has_modrm = {}, .has_imm = {}, .has_value = {}, .has_opreg = {} }}, .opcode_len = {}, .opcode = {{ {} }} }},".format(
i.get_type().value(), int(i.has_rex()), int(i.has_digit()), int(i.has_modrm()), int(i.has_imm()), int(i.has_value()), int(i.has_opreg()), opcode_len, opcode
))
table_len += 1
# footer
print("}};\n\nconst unsigned rtdisasm_table_len = {};".format(table_len))
if __name__ == "__main__":
groups = parse_file("xml/raw/x86/Intel/AZ.xml")
#groups.extend(parse_file("xml/raw/x86/Intel/AVX512_r22.xml"))
#groups.extend(parse_file("xml/raw/x86/Intel/AVX512_r24.xml"))
generate_table(groups)

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src/rtdisasm_table.cgz
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xml/LICENSE Normal file
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@ -0,0 +1,22 @@
The MIT License (MIT)
Copyright (c) 2015 Mahdi Safsafi
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

210
xml/raw/x86/AMD/3DNow.xml Normal file
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@ -0,0 +1,210 @@
<?xml version="1.0" encoding="ASCII"?>
<!DOCTYPE instrs SYSTEM "3DNow_Rules.dtd">
<!-- Copyright (c) 2015 Mahdi Safsafi
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
-->
<!-- https://github.com/MahdiSafsafi/Parsable-Instructions -->
<!--
This XML file includes all instructions found in :
3DNow! Technology Manual 21928G/0-March 2000 document.
-->
<instrs version="1.00">
<common>
<brief>FEMMS</brief>
<ins>
<mnem>FEMMS</mnem>
<args>void</args>
<opc>0F 0E</opc>
<dscrp>Faster Enter/Exit of the MMX or floating-point state.</dscrp>
</ins>
</common>
<common>
<brief>PAVGUSB</brief>
<ins>
<mnem>PAVGUSB</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r BF</opc>
<dscrp>Average of unsigned packed 8-bit values.</dscrp>
</ins>
</common>
<common>
<brief>PF2ID</brief>
<ins>
<mnem>PF2ID</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r 1D</opc>
<dscrp>Converts packed floating-point operand to packed 32-bit integer.</dscrp>
</ins>
</common>
<common>
<brief>PFACC</brief>
<ins>
<mnem>PFACC</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r AE</opc>
<dscrp>Floating-point accumulate.</dscrp>
</ins>
</common>
<common>
<brief>PFADD</brief>
<ins>
<mnem>PFADD</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r 9E</opc>
<dscrp>Packed, floating-point addition.</dscrp>
</ins>
</common>
<common>
<brief>PFCMPEQ</brief>
<ins>
<mnem>PFCMPEQ</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r B0</opc>
<dscrp>Packed floating-point comparison, equal to.</dscrp>
</ins>
</common>
<common>
<brief>PFCMPGE</brief>
<ins>
<mnem>PFCMPGE</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r 90</opc>
<dscrp>Packed floating-point comparison, greater than or equal to.</dscrp>
</ins>
</common>
<common>
<brief>PFCMPGT</brief>
<ins>
<mnem>PFCMPGT</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r A0</opc>
<dscrp>Packed floating-point comparison, greater than.</dscrp>
</ins>
</common>
<common>
<brief>PFMAX</brief>
<ins>
<mnem>PFMAX</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r A4</opc>
<dscrp>Packed floating-point maximum.</dscrp>
</ins>
</common>
<common>
<brief>PFMIN</brief>
<ins>
<mnem>PFMIN</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r 94</opc>
<dscrp>Packed floating-point minimum.</dscrp>
</ins>
</common>
<common>
<brief>PFMUL</brief>
<ins>
<mnem>PFMUL</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r B4</opc>
<dscrp>Packed floating-point multiplication.</dscrp>
</ins>
</common>
<common>
<brief>PFRCP</brief>
<ins>
<mnem>PFRCP</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r 96</opc>
<dscrp>Floating-point reciprocal approximation.</dscrp>
</ins>
</common>
<common>
<brief>PFRCPIT1</brief>
<ins>
<mnem>PFRCPIT1</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r A6</opc>
<dscrp>Packed floating-point reciprocal, first iteration step.</dscrp>
</ins>
</common>
<common>
<brief>PFRCPIT2</brief>
<ins>
<mnem>PFRCPIT2</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r B6</opc>
<dscrp>Packed floating-point reciprocal/reciprocal square root, second iteration step.</dscrp>
</ins>
</common>
<common>
<brief>PFRSQIT1</brief>
<ins>
<mnem>PFRSQIT1</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r A7</opc>
<dscrp>Packed floating-point reciprocal square root, first iteration step.</dscrp>
</ins>
</common>
<common>
<brief>PFRSQRT</brief>
<ins>
<mnem>PFRSQRT</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r 97</opc>
<dscrp>Floating-point reciprocal square root approximation.</dscrp>
</ins>
</common>
<common>
<brief>PFSUB</brief>
<ins>
<mnem>PFSUB</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r 9A</opc>
<dscrp>Packed floating-point subtraction.</dscrp>
</ins>
</common>
<common>
<brief>PFSUBR</brief>
<ins>
<mnem>PFSUBR</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r AA</opc>
<dscrp>Packed floating-point reverse subtraction.</dscrp>
</ins>
</common>
<common>
<brief>PI2FD</brief>
<ins>
<mnem>PI2FD</mnem>
<args>mmreg1,mmreg2/mem64</args>
<opc>0F 0F /r 0D</opc>
<dscrp>Packed 32-bit integer to floating-point conversion.</dscrp>
</ins>
</common>
<common>
<brief>PREFETCHW</brief>
<ins>
<mnem>PREFETCHW</mnem>
<args>mem8</args>
<opc>0F 0D</opc>
<dscrp>Prefetch processor cache line into L1 data cache (Dcache).</dscrp>
</ins>
</common>
</instrs>

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<?xml version="1.0" encoding="ASCII"?>
<!-- 3DNow rules -->
<!ELEMENT instrs (common+)>
<!ELEMENT common (brief,ins)>
<!ELEMENT ins (mnem,args,opc,dscrp)>
<!ELEMENT brief (#PCDATA)>
<!ELEMENT mnem (#PCDATA)>
<!ELEMENT args (#PCDATA)>
<!ELEMENT opc (#PCDATA)>
<!ELEMENT dscrp (#PCDATA)>
<!ATTLIST instrs version CDATA #REQUIRED>

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<?xml version="1.0" encoding="ASCII"?>
<!-- XOP Rules -->
<!ELEMENT instrs (common+)>
<!ELEMENT common (brief,dscrp,ins+)>
<!ELEMENT ins (mnem,args,opc)>
<!ELEMENT brief (#PCDATA)>
<!ELEMENT dscrp (#PCDATA)>
<!ELEMENT mnem (#PCDATA)>
<!ELEMENT args (#PCDATA)>
<!ELEMENT opc (#PCDATA)>
<!ATTLIST instrs version CDATA #REQUIRED>

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<?xml version="1.0" encoding="ASCII"?>
<!DOCTYPE instrs SYSTEM "XOP_Rules.dtd">
<!-- Copyright (c) 2015 Mahdi Safsafi
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
-->
<!-- https://github.com/MahdiSafsafi/Parsable-Instructions -->
<!--
This XML file includes all instructions found in :
AMD64 Architecture Programmers Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions Pub No 43479 Rev 3.04 Date November 2009 document.
-->
<instrs version="1.00">
<common>
<brief>VFMADDPD--Multiply and Add Packed Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFMADDPD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 69 /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDPD</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 69 /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDPD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 69 /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDPD</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 69 /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMADDPS--Multiply and Add Packed Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFMADDPS</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 68 /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDPS</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 68 /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDPS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 68 /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDPS</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 68 /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMADDSD--Multiply and Add Scalar Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFMADDSD</mnem>
<args>xmm1,xmm2,xmm3/mem64,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 6B /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDSD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem64</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 6B /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMADDSS--Multiply and Add Scalar Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFMADDSS</mnem>
<args>xmm1,xmm2,xmm3/mem32,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 6A /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDSS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem32</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 6A /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMADDSUBPD--Multiply with Alternating Add/Subtract of Packed Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFMADDSUBPD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 5D /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDSUBPD</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 5D /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDSUBPD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 5D /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDSUBPD</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 5D /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMADDSUBPS--Multiply with Alternating Add/Subtract of Packed Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFMADDSUBPS</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 5C /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDSUBPS</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 5C /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDSUBPS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 5C /r /is4</opc>
</ins>
<ins>
<mnem>VFMADDSUBPS</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 5C /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMSUBADDPD--Multiply with Alternating Subtract/Add of Packed Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFMSUBADDPD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 5F /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBADDPD</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 5F /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBADDPD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 5F /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBADDPD</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 5F /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMSUBADDPS--Multiply with Alternating Subtract/Add of Packed Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFMSUBADDPS</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 5E /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBADDPS</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 5E /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBADDPS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 5E /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBADDPS</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 5E /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMSUBPD--Multiply and Subtract Packed Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFMSUBPD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 6D /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBPD</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 6D /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBPD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 6D /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBPD</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 6D /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMSUBPS--Multiply and Subtract Packed Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFMSUBPS</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 6C /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBPS</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 6C /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBPS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 6C /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBPS</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 6C /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMSUBSD--Multiply and Subtract Scalar Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFMSUBSD</mnem>
<args>xmm1,xmm2,xmm3/mem64,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 6F /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBSD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem64</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 6F /r /is4</opc>
</ins>
</common>
<common>
<brief>VFMSUBSS--Multiply and Subtract Scalar Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFMSUBSS</mnem>
<args>xmm1,xmm2,xmm3/mem32,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 6E /r /is4</opc>
</ins>
<ins>
<mnem>VFMSUBSS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem32</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 6E /r /is4</opc>
</ins>
</common>
<common>
<brief>VFNMADDPD--Negative Multiply and Add Packed Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFNMADDPD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 79 /r /is4</opc>
</ins>
<ins>
<mnem>VFNMADDPD</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 79 /r /is4</opc>
</ins>
<ins>
<mnem>VFNMADDPD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 79 /r /is4</opc>
</ins>
<ins>
<mnem>VFNMADDPD</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 79 /r /is4</opc>
</ins>
</common>
<common>
<brief>VFNMADDPS--Negative Multiply and Add Packed Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFNMADDPS</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 78 /r /is4</opc>
</ins>
<ins>
<mnem>VFNMADDPS</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 78 /r /is4</opc>
</ins>
<ins>
<mnem>VFNMADDPS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 78 /r /is4</opc>
</ins>
<ins>
<mnem>VFNMADDPS</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 78 /r /is4</opc>
</ins>
</common>
<common>
<brief>VFNMADDSD--Negative Multiply and Add Scalar Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFNMADDSD</mnem>
<args>xmm1,xmm2,xmm3/mem64,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 7B /r /is4</opc>
</ins>
<ins>
<mnem>VFNMADDSD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem64</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 7B /r /is4</opc>
</ins>
</common>
<common>
<brief>VFNMADDSS--Negative Multiply and Add Scalar Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFNMADDSS</mnem>
<args>xmm1,xmm2,xmm3/mem32,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 7A /r /is4</opc>
</ins>
<ins>
<mnem>VFNMADDSS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem32</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 7A /r /is4</opc>
</ins>
</common>
<common>
<brief>VFNMSUBPD--Negative Multiply and Subtract Packed Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFNMSUBPD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 7D /r /is4</opc>
</ins>
<ins>
<mnem>VFNMSUBPD</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 7D /r /is4</opc>
</ins>
<ins>
<mnem>VFNMSUBPD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 7D /r /is4</opc>
</ins>
<ins>
<mnem>VFNMSUBPD</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 7D /r /is4</opc>
</ins>
</common>
<common>
<brief>VFNMSUBPS--Negative Multiply and Subtract Packed Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFNMSUBPS</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 7C /r /is4</opc>
</ins>
<ins>
<mnem>VFNMSUBPS</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.66 7C /r /is4</opc>
</ins>
<ins>
<mnem>VFNMSUBPS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 7C /r /is4</opc>
</ins>
<ins>
<mnem>VFNMSUBPS</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.66 7C /r /is4</opc>
</ins>
</common>
<common>
<brief>VFNMSUBSD--Negative Multiply and Subtract Scalar Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFNMSUBSD</mnem>
<args>xmm1,xmm2,xmm3/mem64,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 7F /r /is4</opc>
</ins>
<ins>
<mnem>VFNMSUBSD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem64</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 7F /r /is4</opc>
</ins>
</common>
<common>
<brief>VFNMSUBSS--Negative Multiply and Subtract Scalar Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFNMSUBSS</mnem>
<args>xmm1,xmm2,xmm3/mem32,xmm4</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.66 7E /r /is4</opc>
</ins>
<ins>
<mnem>VFNMSUBSS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem32</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.66 7E /r /is4</opc>
</ins>
</common>
<common>
<brief>VFRCZPD--Extract Fraction Packed Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFRCZPD</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA 81 /r</opc>
</ins>
<ins>
<mnem>VFRCZPD</mnem>
<args>ymm1,ymm2/mem256</args>
<opc>XOP.mmmmm9.W0.1111.L1.NA 81 /r</opc>
</ins>
</common>
<common>
<brief>VFRCZPS--Extract Fraction Packed Single-Precision Floating-Point.</brief>
<ins>
<mnem>VFRCZPS</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA 80 /r</opc>
</ins>
<ins>
<mnem>VFRCZPS</mnem>
<args>ymm1,ymm2/mem256</args>
<opc>XOP.mmmmm9.W0.1111.L1.NA 80 /r</opc>
</ins>
</common>
<common>
<brief>VFRCZSD--Extract Fraction Scalar Double-Precision Floating-Point.</brief>
<ins>
<mnem>VFRCZSD</mnem>
<args>xmm1,xmm2/mem64</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA 83 /r</opc>
</ins>
</common>
<common>
<brief>VFRCZSS--Extract Fraction Scalar Single-Precision Floating Point.</brief>
<ins>
<mnem>VFRCZSS</mnem>
<args>xmm1,xmm2/mem32</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA 82 /r</opc>
</ins>
</common>
<common>
<brief>VPCMOV--Vector Conditional Moves.</brief>
<ins>
<mnem>VPCMOV</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA A2 /r imm[7:4]</opc>
</ins>
<ins>
<mnem>VPCMOV</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4</args>
<opc>XOP.mmmmm8.W0.ysrc1.L1.NA A2 /r imm[7:4]</opc>
</ins>
<ins>
<mnem>VPCMOV</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>XOP.mmmmm8.W1.xsrc1.L0.NA A2 /r imm[7:4]</opc>
</ins>
<ins>
<mnem>VPCMOV</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256</args>
<opc>XOP.mmmmm8.W1.ysrc1.L1.NA A2 /r imm[7:4]</opc>
</ins>
</common>
<common>
<brief>VPCOMB--Compare Vector Signed Bytes.</brief>
<ins>
<mnem>VPCOMB</mnem>
<args>xmm1,xmm2,xmm3/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA CC /r /imm8</opc>
</ins>
</common>
<common>
<brief>VPCOMD--Compare Vector Signed Doublewords.</brief>
<ins>
<mnem>VPCOMD</mnem>
<args>xmm1,xmm2,xmm3/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA CE /r /imm8</opc>
</ins>
</common>
<common>
<brief>VPCOMQ--Compare Vector Signed Quadwords.</brief>
<ins>
<mnem>VPCOMQ</mnem>
<args>xmm1,xmm2,xmm3/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA CF /r imm8</opc>
</ins>
</common>
<common>
<brief>VPCOMUB--Compare Vector Unsigned Bytes.</brief>
<ins>
<mnem>VPCOMUB</mnem>
<args>xmm1,xmm2,xmm3/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA EC /r imm8</opc>
</ins>
</common>
<common>
<brief>VPCOMUD--Compare Vector Unsigned Doublewords.</brief>
<ins>
<mnem>VPCOMUD</mnem>
<args>xmm1,xmm2,xmm3/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA EE /r imm8</opc>
</ins>
</common>
<common>
<brief>VPCOMUQ--Compare Vector Unsigned Quadwords.</brief>
<ins>
<mnem>VPCOMUQ</mnem>
<args>xmm1,xmm2,xmm3/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA EF /r imm8</opc>
</ins>
</common>
<common>
<brief>VPCOMUW--Compare Vector Unsigned Words.</brief>
<ins>
<mnem>VPCOMUW</mnem>
<args>xmm1,xmm2,xmm3/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA ED /r imm8</opc>
</ins>
</common>
<common>
<brief>VPCOMW--Compare Vector Signed Words.</brief>
<ins>
<mnem>VPCOMW</mnem>
<args>xmm1,xmm2,xmm3/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA CD /r imm8</opc>
</ins>
</common>
<common>
<brief>VPERMIL2PD--Permute Two-Source Double-Precision Floating- Point Values.</brief>
<ins>
<mnem>VPERMIL2PD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4,imm8</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.NA 49 /r imm8</opc>
</ins>
<ins>
<mnem>VPERMIL2PD</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128,imm8</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.NA 49 /r imm8</opc>
</ins>
<ins>
<mnem>VPERMIL2PD</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4,imm8</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.NA 49 /r imm8</opc>
</ins>
<ins>
<mnem>VPERMIL2PD</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256,imm8</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.NA 49 /r imm8</opc>
</ins>
</common>
<common>
<brief>VPERMIL2PS--Permute Two-Source Single-Precision Floating-Point Values.</brief>
<ins>
<mnem>VPERMIL2PS</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4,imm8</args>
<opc>VEX3.mmmmm3.W0.xsrc1.L0.NA 48 /r imm8</opc>
</ins>
<ins>
<mnem>VPERMIL2PS</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128,imm8</args>
<opc>VEX3.mmmmm3.W1.xsrc1.L0.NA 48 /r imm8</opc>
</ins>
<ins>
<mnem>VPERMIL2PS</mnem>
<args>ymm1,ymm2,ymm3/mem256,ymm4,imm8</args>
<opc>VEX3.mmmmm3.W0.ysrc1.L1.NA 48 /r imm8</opc>
</ins>
<ins>
<mnem>VPERMIL2PS</mnem>
<args>ymm1,ymm2,ymm3,ymm4/mem256,imm8</args>
<opc>VEX3.mmmmm3.W1.ysrc1.L1.NA 48 /r imm8</opc>
</ins>
</common>
<common>
<brief>VPHADDBD--Packed Horizontal Add Signed Byte to Signed Doubleword.</brief>
<ins>
<mnem>VPHADDBD</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA C2 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDBQ--Packed Horizontal Add Signed Byte to Signed Quadword.</brief>
<ins>
<mnem>VPHADDBQ</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA C3 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDBW--Packed Horizontal Add Signed Byte to Signed Word.</brief>
<ins>
<mnem>VPHADDBW</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA C1 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDDQ--Packed Horizontal Add Signed Doubleword to Signed Quadword.</brief>
<ins>
<mnem>VPHADDDQ</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA CB /r</opc>
</ins>
</common>
<common>
<brief>VPHADDUBD--Packed Horizontal Add Unsigned Byte to Doubleword.</brief>
<ins>
<mnem>VPHADDUBD</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA D2 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDUBQ--Packed Horizontal Add Unsigned Byte to Quadword.</brief>
<ins>
<mnem>VPHADDUBQ</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA D3 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDUBW--Packed Horizontal Add Unsigned Byte to Word.</brief>
<ins>
<mnem>VPHADDUBWD</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA D1 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDUDQ--Packed Horizontal Add Unsigned Doubleword to Quadword.</brief>
<ins>
<mnem>VPHADDUDQ</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA DB /r</opc>
</ins>
</common>
<common>
<brief>VPHADDUWDPacked--Horizontal Add Unsigned Word to Doubleword.</brief>
<ins>
<mnem>VPHADDUWD</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA D6 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDUWQ--Packed Horizontal Add Unsigned Word to Quadword.</brief>
<ins>
<mnem>VPHADDUWQ</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA D7 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDWD--Packed Horizontal Add Signed Word to Signed Doubleword.</brief>
<ins>
<mnem>VPHADDWD</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA C6 /r</opc>
</ins>
</common>
<common>
<brief>VPHADDWQ--Packed Horizontal Add Signed Word to Signed Quadword.</brief>
<ins>
<mnem>VPHADDWQ</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA C7 /r</opc>
</ins>
</common>
<common>
<brief>VPHSUBBW--Packed Horizontal Subtract Signed Byte to Signed Word.</brief>
<ins>
<mnem>VPHSUBBW</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA E1 /r</opc>
</ins>
</common>
<common>
<brief>VPHSUBDQ--Packed Horizontal Subtract Signed Doubleword to Signed Quadword.</brief>
<ins>
<mnem>VPHSUBDQ</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA E3 /r</opc>
</ins>
</common>
<common>
<brief>VPHSUBWD--Packed Horizontal Subtract Signed Word to Signed Doubleword.</brief>
<ins>
<mnem>VPHSUBWD</mnem>
<args>xmm1,xmm2/mem128</args>
<opc>XOP.mmmmm9.W0.1111.L0.NA E2 /r</opc>
</ins>
</common>
<common>
<brief>VPMACSDD--Packed Multiply Accumulate Signed Doubleword to Signed Doubleword.</brief>
<ins>
<mnem>VPMACSDD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 9E /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMACSDQH--Packed Multiply Accumulate Signed High Doubleword to Signed Quadword.</brief>
<ins>
<mnem>VPMACSDQH</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 9F /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMACSDQL--Packed Multiply Accumulate Signed Low Doubleword to Signed Quadword.</brief>
<ins>
<mnem>VPMACSDQL</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 97 /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMACSSDD--Packed Multiply Accumulate Signed Doubleword to Signed Doubleword with Saturation.</brief>
<ins>
<mnem>VPMACSSDD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 8E /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMACSSDQH--Packed Multiply Accumulate Signed High Doubleword to Signed Quadword with.</brief>
<ins>
<mnem>VPMACSSDQH</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 8F /r is4</opc>
</ins>
</common>
<common>
<brief>VPMACSSDQL--Packed Multiply Accumulate Signed Low Doubleword to Signed Quadword with.</brief>
<ins>
<mnem>PMACSSDQL</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 87 /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMACSSWD--Packed Multiply Accumulate Signed Word to Signed Doubleword with Saturation.</brief>
<ins>
<mnem>VPMACSSWD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 86 /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMACSSWW--Packed Multiply Accumulate Signed Word to Signed Word with Saturation.</brief>
<ins>
<mnem>PMACSSWW</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 85 /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMACSWD--Packed Multiply Accumulate Signed Word to Signed Doubleword.</brief>
<ins>
<mnem>VPMACSWD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 96 /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMACSWW--Packed Multiply Accumulate Signed Word to Signed Word.</brief>
<ins>
<mnem>VPMACSWW</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA 95 /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMADCSSWD--Packed Multiply, Add and Accumulate Signed Word to Signed Doubleword with Saturation.</brief>
<ins>
<mnem>VPMADCSSWD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA A6 /r /is4</opc>
</ins>
</common>
<common>
<brief>VPMADCSWD--Packed Multiply Add and Accumulate Signed Word to Signed Doubleword.</brief>
<ins>
<mnem>PMADCSWD</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA B6 /r /is4</opc>
</ins>
</common>
<common>
<brief>VPPERM--Packed Permute Bytes.</brief>
<ins>
<mnem>VPPERM</mnem>
<args>xmm1,xmm2,xmm3,xmm4/mem128</args>
<opc>XOP.mmmmm8.W1.xsrc1.L0.NA A3 /r is4</opc>
</ins>
<ins>
<mnem>VPPERM</mnem>
<args>xmm1,xmm2,xmm3/mem128,xmm4</args>
<opc>XOP.mmmmm8.W0.xsrc1.L0.NA A3 /r is4</opc>
</ins>
</common>
<common>
<brief>VPROTB--Packed Rotate Bytes.</brief>
<ins>
<mnem>VPROTB</mnem>
<args>xmm1,xmm2/mem128,xmm8</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 90 /r</opc>
</ins>
<ins>
<mnem>VPROTB</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 90 /r</opc>
</ins>
<ins>
<mnem>VPROTB</mnem>
<args>xmm1,xmm2/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.1111.L0.NA C0 /r /ib</opc>
</ins>
</common>
<common>
<brief>VPROTD--Packed Rotate Doublewords.</brief>
<ins>
<mnem>VPROTD</mnem>
<args>xmm1,xmm2/mem128,xmm3</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 92 /r</opc>
</ins>
<ins>
<mnem>VPROTD</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 92 /r</opc>
</ins>
<ins>
<mnem>VPROTD</mnem>
<args>xmm1,xmm2/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.1111.L0.NA C2 /ib</opc>
</ins>
</common>
<common>
<brief>VPROTQ--Packed Rotate Quadwords.</brief>
<ins>
<mnem>VPROTQ</mnem>
<args>xmm1,xmm2/mem128,xmm3</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 93 /r</opc>
</ins>
<ins>
<mnem>VPROTQ</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 93 /r</opc>
</ins>
<ins>
<mnem>VPROTQ</mnem>
<args>xmm1,xmm2/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.1111.L0.NA C3 /ib</opc>
</ins>
</common>
<common>
<brief>VPROTW--Packed Rotate Words.</brief>
<ins>
<mnem>VPROTW</mnem>
<args>xmm1,xmm2/mem128,xmm3</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 91 /r</opc>
</ins>
<ins>
<mnem>VPROTW</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 91 /r</opc>
</ins>
<ins>
<mnem>VPROTW</mnem>
<args>xmm1,xmm2/mem128,imm8</args>
<opc>XOP.mmmmm8.W0.1111.L0.NA C1 /r /ib</opc>
</ins>
</common>
<common>
<brief>VPSHAB--Packed Shift Arithmetic Bytes.</brief>
<ins>
<mnem>VPSHAB</mnem>
<args>xmm1,xmm2/mem128,xmm3</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 98 /r</opc>
</ins>
<ins>
<mnem>VPSHAB</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 98 /r</opc>
</ins>
</common>
<common>
<brief>VPSHAD--Packed Shift Arithmetic Doublewords.</brief>
<ins>
<mnem>VPSHAD</mnem>
<args>xmm1,xmm2/mem128,xmm3</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 9A /r</opc>
</ins>
<ins>
<mnem>VPSHAD</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 9A /r</opc>
</ins>
</common>
<common>
<brief>VPSHAQ--Packed Shift Arithmetic Quadwords.</brief>
<ins>
<mnem>VPSHAQ</mnem>
<args>xmm1,xmm2/mem128,xmm3</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 9B /r</opc>
</ins>
<ins>
<mnem>VPSHAQ</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 9B /r</opc>
</ins>
</common>
<common>
<brief>VPSHAW--Packed Shift Arithmetic Words.</brief>
<ins>
<mnem>VPSHAW</mnem>
<args>xmm1,xmm2/mem128,xmm3</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 99 /r</opc>
</ins>
<ins>
<mnem>VPSHAW</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 99 /r</opc>
</ins>
</common>
<common>
<brief>VPSHLB--Packed Shift Logical Bytes.</brief>
<ins>
<mnem>VPSHLB</mnem>
<args>xmm1,xmm2/mem128,xmm3</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 94 /r</opc>
</ins>
<ins>
<mnem>VPSHLB</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 94 /r</opc>
</ins>
</common>
<common>
<brief>VPSHLD--Packed Shift Logical Doublewords.</brief>
<ins>
<mnem>VPSHLD</mnem>
<args>xmm1,xmm3/mem128,xmm2</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 96 /r</opc>
</ins>
<ins>
<mnem>VPSHLD</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 96 /r</opc>
</ins>
</common>
<common>
<brief>VPSHLQ--Packed Shift Logical Quadwords.</brief>
<ins>
<mnem>VPSHLQ</mnem>
<args>xmm1,xmm3/mem128,xmm2</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 97 /r</opc>
</ins>
<ins>
<mnem>VPSHLQ</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 97 /r</opc>
</ins>
</common>
<common>
<brief>VPSHLW--Packed Shift Logical Words.</brief>
<ins>
<mnem>VPSHLW</mnem>
<args>xmm1,xmm3/mem128,xmm2</args>
<opc>XOP.mmmmm9.W0.xcnt.L0.NA 95 /r</opc>
</ins>
<ins>
<mnem>VPSHLW</mnem>
<args>xmm1,xmm2,xmm3/mem128</args>
<opc>XOP.mmmmm9.W1.xsrc.L0.NA 95 /r</opc>
</ins>
</common>
</instrs>

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xml/raw/x86/AMD/XOP_Rules.dtd Normal file
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<?xml version="1.0" encoding="ASCII"?>
<!-- XOP Rules -->
<!ELEMENT instrs (common+)>
<!ELEMENT common (brief,ins+)>
<!ELEMENT ins (mnem,args,opc)>
<!ELEMENT brief (#PCDATA)>
<!ELEMENT mnem (#PCDATA)>
<!ELEMENT args (#PCDATA)>
<!ELEMENT opc (#PCDATA)>
<!ATTLIST instrs version CDATA #REQUIRED>

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xml/raw/x86/Intel/AVX512_Rules.dtd Normal file
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<?xml version="1.0" encoding="ASCII"?>
<!-- AZ Rules -->
<!--
https://github.com/MahdiSafsafi/Parsable-Instructions
-->
<!-- XML data must be validated.
If XML validation failed ,you probably have a corrupted data !
-->
<!ELEMENT instrs (common+)>
<!ELEMENT common (brief,ins+,oprndenc*)>
<!-- cpuid and dscrp elements are optional. -->
<!ELEMENT ins (mnem,args,opc,cpuid*,dscrp*)>
<!-- If cpuid tag found , flag tag must exists. -->
<!ELEMENT cpuid (flag+)>
<!-- If oprndenc tag found , all oprndX must exists. -->
<!ELEMENT oprndenc (oprnd1,oprnd2,oprnd3,oprnd4)>
<!ELEMENT brief (#PCDATA)>
<!ELEMENT mnem (#PCDATA)>
<!ELEMENT args (#PCDATA)>
<!ELEMENT opc (#PCDATA)>
<!ELEMENT flag (#PCDATA)>
<!ELEMENT dscrp (#PCDATA)>
<!ELEMENT oprnd1 (#PCDATA)>
<!ELEMENT oprnd2 (#PCDATA)>
<!ELEMENT oprnd3 (#PCDATA)>
<!ELEMENT oprnd4 (#PCDATA)>
<!-- version attribute must be specified !-->
<!ATTLIST instrs version CDATA #REQUIRED>
<!ATTLIST ins x32m CDATA "V"> <!-- x32m default to Valid if not specified.-->
<!ATTLIST ins x64m CDATA "V"> <!-- x64m default to Valid if not specified.-->
<!ATTLIST opc openc CDATA "">
<!ATTLIST oprndenc openc CDATA #REQUIRED>

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xml/raw/x86/Intel/AVX512_r22.xml Normal file
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xml/raw/x86/Intel/AVX512_r24.xml Normal file
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22780
xml/raw/x86/Intel/AZ.xml Normal file
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xml/raw/x86/Intel/AZ_Rules.dtd Normal file
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<?xml version="1.0" encoding="ASCII"?>
<!-- AZ Rules -->
<!--
https://github.com/MahdiSafsafi/Parsable-Instructions
-->
<!-- XML data must be validated.
If XML validation failed ,you probably have a corrupted data !
-->
<!ELEMENT instrs (common+)>
<!ELEMENT common (brief,ins+,oprndenc*)>
<!-- cpuid and dscrp elements are optional. -->
<!ELEMENT ins (mnem,args,opc,cpuid*,dscrp*)>
<!-- If cpuid tag found , flag tag must exists. -->
<!ELEMENT cpuid (flag+)>
<!-- If oprndenc tag found , all oprndX must exists. -->
<!ELEMENT oprndenc (oprnd1,oprnd2,oprnd3,oprnd4)>
<!ELEMENT brief (#PCDATA)>
<!ELEMENT mnem (#PCDATA)>
<!ELEMENT args (#PCDATA)>
<!ELEMENT opc (#PCDATA)>
<!ELEMENT flag (#PCDATA)>
<!ELEMENT dscrp (#PCDATA)>
<!ELEMENT oprnd1 (#PCDATA)>
<!ELEMENT oprnd2 (#PCDATA)>
<!ELEMENT oprnd3 (#PCDATA)>
<!ELEMENT oprnd4 (#PCDATA)>
<!-- version attribute must be specified !-->
<!ATTLIST instrs version CDATA #REQUIRED>
<!ATTLIST ins x32m CDATA "V"> <!-- x32m default to Valid if not specified.-->
<!ATTLIST ins x64m CDATA "V"> <!-- x64m default to Valid if not specified.-->
<!ATTLIST opc openc CDATA "">
<!ATTLIST oprndenc openc CDATA #REQUIRED>