forked from Lainports/opnsense-ports
39 lines
1.2 KiB
C++
39 lines
1.2 KiB
C++
--- src/external/atomic_queue/defs.h.orig 2020-07-23 22:01:34 UTC
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+++ src/external/atomic_queue/defs.h
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@@ -6,11 +6,15 @@
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#include <atomic>
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+#if defined(__FreeBSD__) || defined(__DragonFly__)
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+#include <machine/param.h> // for CACHE_LINE_SIZE
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+#endif
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+
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#if defined(__x86_64__) || defined(_M_X64) || \
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defined(__i386__) || defined(_M_IX86)
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#include <emmintrin.h>
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namespace atomic_queue {
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-constexpr int CACHE_LINE_SIZE = 64;
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+//constexpr int CACHE_LINE_SIZE = 64;
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static inline void spin_loop_pause() noexcept {
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_mm_pause();
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}
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@@ -18,7 +22,7 @@ static inline void spin_loop_pause() noexcept {
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#elif defined(__arm__) || defined(__aarch64__)
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// TODO: These need to be verified as I do not have access to ARM platform.
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namespace atomic_queue {
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-constexpr int CACHE_LINE_SIZE = 64;
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+//constexpr int CACHE_LINE_SIZE = 64;
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static inline void spin_loop_pause() noexcept {
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#if (defined(__ARM_ARCH_6K__) || \
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defined(__ARM_ARCH_6Z__) || \
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@@ -37,6 +41,10 @@ static inline void spin_loop_pause() noexcept {
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#endif
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}
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} // namespace atomic_queue
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+#elif defined(__powerpc__)
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+static inline void spin_loop_pause() noexcept {
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+ asm volatile("ori 0,0,0" ::: "memory");
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+}
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#else
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#error "Unknown CPU architecture."
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#endif
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