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rewrite core.S

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mykola2312 2022-04-21 05:21:27 +03:00
parent 8d068607ac
commit a909eba31c
1 changed files with 55 additions and 18 deletions
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73
core.S
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@ -1,25 +1,62 @@
.syntax unified .syntax unified
.cpu cortex-m4 .cpu cortex-m4
.fpu softvfp
.thumb .thumb
.global vtable .global _estack
.global reset_handler
.type vtable, %object .equ SCR, 0xE000E000
vtable: .equ STCSR, SCR+0x10
.word _estack .equ STRVR, SCR+0x14
.word reset_handler .equ STCVR, SCR+0x18
.size vtable, .-vtable .equ STCR, SCR+0x20
.type reset_handler, %function ivt:
reset_handler: .word _estack
LDR r0, =_estack .word int0_reset
MOV sp, r0
LDR r7, =0xDEADBEEF int0_reset:
MOVS r0, #0 ldr r0, =_estack
main_loop: mov sp, r0
ADDS r0, r0, #1
B main_loop bl main
.size reset_handler, .-reset_handler
ldr r7, =0xDEADBEEF
mov r0, #0
reset_loop:
add r0, r0, #1
b reset_loop
.equ CLOCK_1MS, 180000
# r0 - delay
systick_wait:
push {lr}
ldr r1, =CLOCK_1MS
mul r0, r0, r1
ldr r1, =STCVR
str r0, [r1]
mov r0, #0b101
ldr r1, =STCSR
str r0, [r1]
systick_loop:
ldr r0, [r1]
ands r0, #0b10000
beq systick_loop
pop {lr}
bx lr
main:
mov r0, #9000
bl systick_wait
ldr r6, =0xAABBCCDD
dbg_loop: b dbg_loop
mov r0, #9000
bl systick_wait
bx lr