finished project outline, added two walkthrough sections, included local copies of some sources

2024-11-30 08:11:08 +05:00 · 2024-11-30 08:11:08 +05:00 · d4d925fd79
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+++ b/README.md
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 # wirecat

-fuck your phone - PDA based on OrangePi 5 Plus
+fuck your phone - PDA based on OrangePi 5 Plus
+
+## quick FAQ & overview
+
+>what the fuck is this?
+
+wirecat is a project i thought about for a long time - building your own portable device with all the functionality you need, tailored to your specific needs, and of course - the one that looks cool.
+
+> why wirecat?
+
+just a cool name. also, the amount of interface ports on opi5+ is sure impressive for a SBC, so it's kinda fitting.
+
+> why FreeBSD?
+
+the only OS i could find that would satisfy my needs of running properly on this piece of hardware and not being a piece of dead shit. none of the linux distros would do, since unfortunately as of 11/2024 there is not a single systemd-free distro that works properly. trust me, i've tried several(void, alpine, artix, gentoo, etc.)
+
+> what kind of functionality does it have?
+
+it is a fully capable ARM computer running a UNIX-compliant system - the only limit is your schizo level. but in short - it can do everything what a smartphone/laptop can do, taking desktop functionality as granted - connect and utilize cellular network, work with RFID/NFC devices, even used as an electronic recon system(if you have an SDR)! sounds cool, doesn't it?
+
+> SDR? what is that?
+
+software-defined radio. an auxillary device that can be used to discover the electromagnetic(radio) spectrum around it, receive or transmit on certain radio frequency with certain types of modulation, depending on your SDR specs. for my own i used RTL-SDRv3, since it's cheap and i've had it for years. a reasonable choice for beginners in RF field, though better alternatives exist as of now, but those have a higher price tag(HackRF One, for example).
+
+> specs?
+
+OrangePi 5 Plus:
+- CPU: octa-core Rockchip RK3588 64-bit ARM processor(aarch64, 4x Cortex-A55 + 4x Cortex-A72, upo to 2.4GHz)
+- RAM: dual-channel 16GB LPDDR4X*
+- GPU: Mali-610 ARM
+- storage: 1x NVME M.2 MSI Spectrum Z390 SSD 240GB(system), 1x eMMC 256GB(secondary storage)
+- wireless: 1x RTL8862BE(PCIE+USB) wireless network adapter(Wi-Fi 6/BT 5 capable), 1x Sierra Wireless AIrprime EM7455 M.2 key cellular/GPS module with USB adapter
+- ethernet: 2x Realtek 2.5Gbps Ethernet adapters
+battery: 
+- cells: 6x Samsung INR18650-35E 18650 batteries, 3500mAh
+- BMS: chinkshit 22,5W BMS, QuickCharge 3.0/4.0, 2x USB, 1x microUSB, 1x USB-C, 1x USB-C(charge only)
+auxillary:
+- cellular: Sierra Wireless Airprime EM7455, GSM/LTE/GPS, 1x SIM card slot, 3x U.FL male antenna connector
+- RFID/NFC: RFID-RC522 module
+- display: 5" FHD HDMI touchscreen display(many options, acquisition in progress)
+- keyboard: mini-keyboard, wireless capable(many options, acquisition in progress)
+software:
+- operating system: FreeBSD 14.1-RELEASE aarch64
+- video drivers: Panfrost/drm-510
+
+## walkthrough(WIP)
+
+walkthrough on how to assemble your own variation of wirecat is divided into following sections:
+1. hardware assembly
+2. OS installation
+3. software installation(WIP)
+4. chassis assembly(WIP)
+
+full list of parts and tools needed for building will be in the end of this document
+
+### hardware assembly
+
+BATTERY ASSEMBLY
+
+hardware required:
+- 6x battery cells
+- BMS board
+- wiring(i recommend 16AWG)
+- 18650 battery slots(any kind, just make sure they are connected in parallel)
+tools required:
+- soldering iron
+- wire stripper/knife
+- multimeter
+- isolation tape
+- two-side duct tape(optional)
+
+step-by-step:
+
+0. prepare the wiring, measure the length and strip the ends for soldering
+1. connect the 18650 battery slots in parallel so you have a single 6-piece battery block
+2. solder the positive and negative terminals according to their respective locations on the BMS board(marked by B+ and B- accordingly)
+3. check connections with multimeter, then properly isolate the terminals with isolation nape or in any other suitable way(thermal glue, epoxy, etc.)
+4. OPTIONAL: use two-way duct tape to secure the BMS board on the top/side of the battery block
+5. this BMS plate has a thermal resistor, place it right on one of the battery cells and secure with tape
+6. insert the battery cells
+7. put the battery assembly to charge
+
+congrats! the battery block is ready!
+
+ORANGEPI 5 PLUS
+
+hardware required:
+- OrangePi 5 Plus
+- eMMC chip
+- cooler/radiator kit
+- M.2 SSD
+tools required:
+- screwdriver
+
+>>note: i know 99% of people can manage this without any instructions, but anyway
+step-by-step:
+
+0. prepare all your stuff, watch out for small components getting lost!
+1. unpack the M.2 SSD, install it just like any other one in the back M.2 2280 slot
+2. unpack the eMMC, install into the designated slot
+3. unpack the coller/radiator kit, remove the back cover to expose the thermal sticky pads, install to their respective places
+
+probably the easiest part, nonetheless - way to go!
+
+RFID/NFC MODULE WIRING(WIP)
+
+### OS installation
+
+depending on your OS, instructions may not be suitable for your system of choice. only FreeBSd installation will be covered here. known other operating systems with some level of Orange Pi 5 Plus support:
+- Orange Pi OS(full, vendor-provided)
+- Armbian(partial)
+- BredOS(full)
+- Armtix(barely)
+
+tools required:
+- flashing/burning software(dd/Rufus/balenaEtcher/etc.)
+- SD card
+
+PART 1 - UEFI INSTALLATION VIA JUMPER OS
+
+0. prepare your tools
+1. pick any OS image you want, vendor-provided ones are a good option
+2. flash the image onto an SD card
+3. insert the SD card and boot up Orange Pi 5 Plus
+4. once logged in, follow [guide in this repo](https://github.com/edk2-porting/edk2-rk3588) to install UEFI firmware [local copy of guide and UEFI image](./local/UEFI)
+
+now you should have a working UEFI installed, after rebooting the I/O status light will blink blue instead of green
+
+PART 2 - FREEBSD INSTALLATION
+
+tools required:
+- flashing/burning software(dd/Rufus/balenaEtcher/etc.)
+- SD card or USB flash drive
+
+0. prepare your tools, download the OS image from [here](https://download.freebsd.org/releases/ISO-IMAGES/14.1/FreeBSD-14.1-RELEASE-arm64-aarch64-memstick.img)
+1. flash the image onto the storage device
+2. insert the storage device into the SD card slot/USB port
+3. power on the OrangePi 5 Plus, enter the BIOS
+4. select the storage medium and boot
+5. FreeBSD installation here is not really any different from any other platform, pretty intuitive as well, nonetheless i will leave [this guide](https://docs.freebsd.org/en/books/handbook/bsdinstall/) here [(local copy)](./local/freebsd/bsdinstall.html)
+
+NOTE: as of 11/2024, the current version of FreeBSD 14.1-RELEASE does not come with the drivers for wireless card, so for network connectivity you will need to use either an Ethernet cable or USB tethering via your smartphone until then
+
+congratulations, now you should have a working FreeBSD installation running!
+
+### software installation(WIP)
+
+### chassis assembly(WIP)
+
+## list of parts and tools(WIP)
+
+PARTS
+
+- OrangePi 5 Plus 16GB kit(32GB version is available for purchase as of 11/2024) - i recommend the option with the cooling/radiator kit, wireless card and 265GB eMMC card
+- M.2 2280 SSD
+- RFID-RC522 module
+- Sierra Wireless Airprime EM7455 module with USB adapter
+- RTL-SDRv3 software-defined radio
+- 5" FHD HDMI touchscreen display
+- 6x 18650 batteries - you can alter the battery assembly design to your needs, i just went full blast on this one
+- 3x 2-piece parallel 18650 battery slots - you can get whatever combination you want, according to your battery aseembly configuration
+- 16AWG wiring - you will probably need like 20cm of it at most, suit yourself :3
+- signal wires - can find those almost anywhere
+- HDMI cable
+- USB-C cable
+
+TOOLS
+- soldering iron and soldering neccessities(flux, solder, cleaning kit, etc.)
+- screwdriver
+- wire stripper
+- isolation tape
+- two-way duct tape(optional)
--- a/local/UEFI/edk2-rk3588-master/.github/workflows/build.yml
+++ b/local/UEFI/edk2-rk3588-master/.github/workflows/build.yml
@ -0,0 +1,106 @@
+name: Build
+on:
+  push:
+    paths-ignore:
+      - '**.md'
+    branches:
+      - master
+  pull_request:
+    paths-ignore:
+      - '**.md'
+    branches:
+      - master
+  workflow_call:
+    inputs:
+      build-configs:
+        type: string
+        required: true
+  workflow_dispatch:
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        PLATFORM:
+          - rock-5b
+          - rock-5a
+          - rock-5-itx
+          - orangepi-5
+          - orangepi-5plus
+          - indiedroid-nova
+          - fydetab-duo
+          - roc-rk3588s-pc
+          - itx-3588j
+          - aio-3588q
+          - station-m3
+          - r58x
+          - r58-mini
+          - edge2
+          - nanopi-r6c
+          - nanopi-r6s
+          - nanopc-t6
+          - blade3
+          - h88k
+        CONFIGURATION: ${{ fromJSON(format('[{0}]', inputs.build-configs || '"Debug"')) }}
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          submodules: recursive
+
+      - name: Install dependencies
+        shell: bash
+        run: |
+          sudo apt-get update && \
+          sudo apt-get install -y \
+          acpica-tools \
+          binutils-aarch64-linux-gnu \
+          build-essential \
+          device-tree-compiler \
+          gettext \
+          git \
+          gcc-aarch64-linux-gnu \
+          libc6-dev-arm64-cross \
+          python3 \
+          python3-pyelftools
+
+      - name: Get version tag
+        id: get_version_tag
+        shell: bash
+        run: echo "version=$(git describe --tags --always)" >> $GITHUB_OUTPUT
+
+      - name: Set up Secure Boot default keys
+        run: |
+          mkdir keys
+          # We don't really need a usable PK, so just generate a public key for it and discard the private key
+          openssl req -new -x509 -newkey rsa:2048 -subj "/CN=Rockchip Platform Key/" -keyout /dev/null -outform DER -out keys/pk.cer -days 7300 -nodes -sha256
+          curl -L https://go.microsoft.com/fwlink/?LinkId=321185 -o keys/ms_kek.cer
+          curl -L https://go.microsoft.com/fwlink/?linkid=321192 -o keys/ms_db1.cer
+          curl -L https://go.microsoft.com/fwlink/?linkid=321194 -o keys/ms_db2.cer
+          curl -L https://uefi.org/sites/default/files/resources/dbxupdate_arm64.bin -o keys/arm64_dbx.bin
+
+      - name: Build platform
+        shell: bash
+        run: |
+          export EDK2_SECUREBOOT_FLAGS=" \
+              -D DEFAULT_KEYS=TRUE \
+              -D PK_DEFAULT_FILE=keys/pk.cer \
+              -D KEK_DEFAULT_FILE1=keys/ms_kek.cer \
+              -D DB_DEFAULT_FILE1=keys/ms_db1.cer \
+              -D DB_DEFAULT_FILE2=keys/ms_db2.cer \
+              -D DBX_DEFAULT_FILE1=keys/arm64_dbx.bin \
+              -D SECURE_BOOT_ENABLE=TRUE"
+
+          export EDK2_BUILD_FLAGS=" \
+              ${EDK2_SECUREBOOT_FLAGS}"
+
+          ./build.sh --device ${{matrix.PLATFORM}} --release ${{matrix.CONFIGURATION}} --edk2-flags "${EDK2_BUILD_FLAGS}"
+          mv RK3588_NOR_FLASH.img ${{matrix.PLATFORM}}_UEFI_${{matrix.CONFIGURATION}}_${{steps.get_version_tag.outputs.version}}.img
+
+      - name: Upload artifact
+        uses: actions/upload-artifact@v4
+        with:
+          name: ${{matrix.PLATFORM}} UEFI ${{matrix.CONFIGURATION}} image
+          path: ./*.img
+          if-no-files-found: error
--- a/local/UEFI/edk2-rk3588-master/.github/workflows/nightly.yml
+++ b/local/UEFI/edk2-rk3588-master/.github/workflows/nightly.yml
@ -0,0 +1,41 @@
+name: Nightly
+run-name: Nightly build
+on:
+  schedule:
+    - cron: "0 0 * * *"
+
+jobs:
+  prepare:
+    runs-on: ubuntu-latest
+    permissions:
+      actions: write
+    steps:
+      - name: Delete previous cancelled runs
+        uses: Mattraks/delete-workflow-runs@v2
+        with:
+          retain_days: 0
+          keep_minimum_runs: 0
+          delete_workflow_pattern: ${{ github.workflow }}
+          delete_run_by_conclusion_pattern: cancelled
+
+      - name: Check for new commits
+        id: check-new-commits
+        uses: adriangl/check-new-commits-action@v1
+        with:
+          seconds: 86400 # One day in seconds
+          branch: 'master'
+
+      - name: Cancel action if no new commits
+        if: ${{ steps.check-new-commits.outputs.has-new-commits != 'true' }}
+        uses: andymckay/cancel-action@0.3
+
+      - name: Wait for cancellation
+        if: ${{ steps.check-new-commits.outputs.has-new-commits != 'true' }}
+        shell: bash
+        run: while true; do echo "Waiting for job to be cancelled"; sleep 5; done
+
+  build_for_nightly:
+    needs: prepare
+    uses: ./.github/workflows/build.yml
+    with:
+      build-configs: '"Debug", "Release"'
--- a/local/UEFI/edk2-rk3588-master/.github/workflows/release.yml
+++ b/local/UEFI/edk2-rk3588-master/.github/workflows/release.yml
@ -0,0 +1,28 @@
+name: Release
+on:
+  push:
+    tags:
+      - '*'
+
+jobs:
+  build_for_release:
+    uses: ./.github/workflows/build.yml
+    with:
+      build-configs: '"Debug", "Release"'
+
+  release:
+    runs-on: ubuntu-latest
+    needs: build_for_release
+    permissions:
+      contents: write
+    steps:
+      - name: Download all workflow run artifacts
+        uses: actions/download-artifact@v4
+
+      - name: Create release
+        uses: softprops/action-gh-release@v2
+        with:
+          draft: true
+          prerelease: false
+          files: "*/*Release*.img"
+          fail_on_unmatched_files: true
--- a/local/UEFI/edk2-rk3588-master/.gitignore
+++ b/local/UEFI/edk2-rk3588-master/.gitignore
@ -0,0 +1,13 @@
+boot-*.img
+uefi-*.img
+uefi-*.img.gz
+workspace
+*.dll
+ramdisk
+.cache
+.vscode
+*.dts
+*.swp
+*.rej
+*.orig
+*_FLASH.img
--- a/local/UEFI/edk2-rk3588-master/.gitmodules
+++ b/local/UEFI/edk2-rk3588-master/.gitmodules
@ -0,0 +1,16 @@
+[submodule "edk2"]
+	path = edk2
+	url = https://github.com/tianocore/edk2.git
+[submodule "edk2-non-osi"]
+	path = edk2-non-osi
+	url = https://github.com/tianocore/edk2-non-osi.git
+[submodule "edk2-platforms"]
+	path = edk2-platforms
+	url = https://github.com/tianocore/edk2-platforms.git
+[submodule "misc/rkbin"]
+	path = misc/rkbin
+	url = https://github.com/rockchip-linux/rkbin.git
+[submodule "arm-trusted-firmware"]
+	path = arm-trusted-firmware
+	url = https://github.com/worproject/arm-trusted-firmware
+	branch = rk3588
--- a/local/UEFI/edk2-rk3588-master/README.md
+++ b/local/UEFI/edk2-rk3588-master/README.md
@ -0,0 +1,376 @@
+# EDK2 UEFI firmware for Rockchip RK3588 platforms
+This repository contains an UEFI firmware implementation based on EDK2 for various RK3588 boards.
+
+# Supported platforms
+- [Radxa ROCK 5B](https://radxa.com/products/rock5/5b/)
+- [Radxa ROCK 5A](https://radxa.com/products/rock5/5a/)
+- [Radxa ROCK 5 ITX](https://radxa.com/products/rock5/5itx/)
+- [Orange Pi 5](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5.html)
+- [Orange Pi 5 Plus](http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-5-plus.html)
+- [ameriDroid Indiedroid Nova](https://indiedroid.us)
+- [Fydetab Duo](https://fydetabduo.com/)
+- [Firefly AIO-3588Q](https://en.t-firefly.com/product/industry/aio3588q)
+- [Firefly ITX-3588J](https://en.t-firefly.com/product/industry/itx3588j)
+- [Firefly ROC-RK3588S-PC](https://en.t-firefly.com/product/industry/rocrk3588spc)
+- [StationPC Station M3](https://www.stationpc.com/product/stationm3)
+- [Mekotronics R58X](https://www.mekotronics.com/h-pd-75.html)
+- [Mekotronics R58 Mini](https://www.mekotronics.com/h-pd-76.html)
+- [Khadas Edge2](https://www.khadas.com/edge2)
+- [Mixtile Blade 3](https://www.mixtile.com/blade-3)
+- [FriendlyELEC NanoPC T6](https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6)
+- [FriendlyELEC NanoPi R6C](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6C)
+- [FriendlyELEC NanoPi R6S](https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R6S)
+- [Hinlink H88K](http://www.hinlink.com)
+
+# Supported OSes
+## In ACPI mode
+| OS | Version | Tested/supported hardware | Notes |
+| --- | --- | --- | --- |
+| Windows | 11 | [Status](https://github.com/worproject/Rockchip-Windows-Drivers#hardware-support-status) ||
+| NetBSD | 10 | Display, UART, USB, PCIe (incl. NVME), SATA, eMMC, GMAC Ethernet ||
+| VMware ESXi Arm Fling | >= 1.12 | Display, USB | * PCIe devices will hang at boot, need to disable in settings or leave the ports empty.<br>* GMAC Ethernet gets detected but does not work. |
+| Linux | tested Ubuntu 22.04, kernel 5.15.0-75-generic | Display, UART, USB, PCIe (incl. NVME & Ethernet), SATA | For full hardware functionality, use a kernel with RK3588 support and switch to Device Tree mode. |
+
+> [!NOTE]
+> ACPI support is only being developed and tested against Windows. There are no plans to further improve functionality for other OSes. Consider using Device Tree instead (where applicable, for instance Linux).
+
+## In Device Tree mode
+| OS | Version | Tested/supported hardware | Notes |
+| --- | --- | --- | --- |
+| Rockchip SDK Linux | 5.10 legacy, tested with [Armbian rk3588-live-iso](https://github.com/amazingfate/rk3588-live-iso) | Platform-dependent, most peripherals work. | If using a different kernel, see [Device Tree configuration](#device-tree-configuration). |
+
+# Supported peripherals in UEFI
+
+> [!NOTE]
+> Applicable to all platforms unless otherwise noted.
+>
+> Only devices relevant to the firmware itself (not OS) are listed below.
+
+| Device | Status | Notes |
+| --- | --- | --- |
+| USB 3 / 2.0 / 1.1                  | 🟢 Working     | Host-mode only, USB 3 devices connected to a Type-C port only work in one orientation. |
+| PCIe 3.0 (RK3588)                  | 🟢 Working     | No bifurcation support |
+| PCIe 2.1                           | 🟢 Working     | |
+| SATA                               | 🟢 Working     | |
+| SD/eMMC                            | 🟢 Working     | |
+| HDMI output                        | 🟡 Partial     | Single display with mode limited at 1080p 60 Hz |
+| DisplayPort output (USB-C)         | 🟡 Partial     | Mode fixed at 1080p 60 Hz, only works in one orientation of the Type-C port. Some displays may not work regardless. |
+| eDP output                         | 🟡 Partial     | Disabled, requires manual configuration depending on the platform and panel. |
+| DSI output                         | 🟢 Working     | Only enabled on Fydetab Duo. Requires manual configuration depending on the platform and panel. |
+| GMAC Ethernet                      | 🔴 Not working | Only brought-up for OS usage |
+| Realtek PCIe Ethernet              | 🟢 Working     | Some platforms don't have MAC addresses set, networking may not work in that case. |
+| UART                               | 🟢 Working     | UART2 console available at 1500000 baud rate |
+| GPIO                               | 🟡 Partial     | Only read, write and alt function supported |
+| I2C                                | 🟢 Working     | |
+| SPI                                | 🟢 Working     | |
+| PWM                                | 🟢 Working     | |
+| SPI NOR Flash                      | 🟢 Working     | |
+| HYM8563 real-time clock            | 🟢 Working     | |
+| RNG                                | 🟢 Working     | |
+| Cooling fan                        | 🟢 Working     | Supported on most platforms. Fan connector where present, otherwise available at the GPIO header for 3-pin PWM fans (do *not* connect 2-pin fans there!):<br>* Orange Pi 5: `GPIO4_B2`<br>* Indiedroid Nova: `GPIO4_B4` |
+| Status LED                         | 🟢 Working     | |
+| Voltage regulators (RK806, RK860)  | 🟢 Working     | |
+| FUSB302 USB Type-C Controller      | 🔴 Not working | Required for PD negotiation and connector orientation switching |
+
+# Getting started
+## 1. Requirements
+* One of the [supported devices](#supported-platforms).
+* Storage for the firmware: SPI NOR flash (included with some devices), SD card or eMMC.
+* Quality power supply that can provide at least 15 W. Depending on the peripherals you use, more may be needed.
+
+  Note: on Mixtile Blade 3, a fixed voltage *higher than* 5V must be supplied. The board cannot power any external peripherals if the input voltage is just 5V. USB-PD negotiation is not supported by firmware.
+* HDMI or DisplayPort (USB-C) screen capable of at least 1080p 60Hz.
+* Optionally, if display is not available or for debugging purposes, an UART adapter capable of 1500000 baud rate (e.g. USB CH340, CP2104).
+
+## 2. Download the firmware image
+The latest version can be obtained from <https://github.com/edk2-porting/edk2-rk3588/releases>.
+
+If your platform is not yet supported, using an image meant for another device is **not** recommended. Although they are generally similar, voltage setup can happen to be different and you may risk damaging the board. External peripherals are unlikely to work either.
+
+## 3. Flash the firmware
+UEFI can be flashed to either a SPI NOR flash, SD card or eMMC module:
+* For removable SD or eMMC (easiest), you can simply use balenaEtcher, RPi Imager or dd.
+* For SPI NOR or soldered eMMC, instructions can be found at: <https://wiki.radxa.com/Rock5/install/spi>.
+
+  In short, you can flash the image from Linux booted on the device or by using RKDevTool on another computer. The latter requires entering Maskrom mode on the device. The way to do this slightly varies across platforms, refer to your vendor documentation.
+
+**Warning:** these operations will erase data on the storage device. Make a backup first!
+
+If you wish to have both UEFI and an OS on the same SD or eMMC device: flash UEFI first, then create any additional partitions without touching the first, reserved one. Steps for updating the firmware in this case can be found [here](#updating-the-firmware).
+
+Note: Using SPI NOR (if present) is recommeded, as it leaves the other storage options free for other purposes. Additionally, SD/eMMC will limit the firmware's ability to access its own storage (variable store) when an OS is running. This feature is mostly used by OS installers to create the boot menu options, it is not mandatory.
+
+## 4. Connect peripherals and power on the device
+If the flashing process has been done correctly, you should see the status LED blinking (if present), and shortly after, the platform's boot logo with a progress bar at the bottom on the connected display.
+
+At this stage, you can press <kbd>Esc</kbd> to enter the firmware setup, <kbd>F1</kbd> to launch the UEFI Shell, or, provided you also have an UEFI bootloader/app on a storage device, you can let the system automatically run that, which is the default behavior if no action is taken.
+
+Check the [Supported OSes](#supported-oses) and [Supported peripherals in UEFI](#supported-peripherals-in-uefi) sections to see what's currently possible with this firmware.
+
+Also check the configuration options described below, some of which may need to be changed depending on the OS used.
+
+If you experience any issues, please see the [Troubleshooting](#troubleshooting) section.
+
+# Configuration settings
+The UEFI provides a few configuration options, like CPU frequency, PCIe/SATA selection for an M.2 port, fan control, etc. These can be viewed and changed using the UI configuration menu (under `Device Manager` -> `Rockchip Platform Configuration`).
+
+Configuration through the user interface is fairly straightforward and help/navigation information is provided around the menus.
+
+## Tips
+* CPU clocks are set to 816 MHz (boot default) on platforms without a cooling fan included. If you have adequate cooling, go to the configuration menu -> `CPU Performance` and set all Cluster Presets to `Maximum`.
+
+## Device Tree configuration
+For rich Linux support, it is recommended to enable Device Tree mode. You can do so by going to the configuration menu -> `ACPI / Device Tree` and setting `Config Table Mode` to `Device Tree`.
+
+By default, the firmware installs a [DTB compatible with (most) Rockchip SDK Linux 5.10 legacy kernel variants](https://github.com/edk2-porting/edk2-rk3588/tree/master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree).
+
+### Custom Device Tree Blob (DTB) override and overlays
+It is also possible to provide a custom DTB and overlays. To enable this, go to the configuration menu -> `ACPI / Device Tree` and set `Support DTB override & overlays` to `Enabled`.
+
+The firmware will now look for overrides in the partition of a selected boot option / OS loader. In most cases this will be the first FAT32 EFI System Partition.
+
+* The base DTB must be located at `\dtb\base\<PLATFORM-DT-NAME>.dtb`.
+
+* The overlays can be placed in:
+  * `\dtb\overlays` - will be applied first, regardless of the platform.
+  * `\dtb\overlays\<PLATFORM-DT-NAME>` - will be applied only to the specified platform.
+
+  and must have the `.dtbo` extension.
+
+The paths above are relative to the root of the file system. That is, the `dtb` directory must not be placed in a sub-directory.
+
+`<PLATFORM-DT-NAME>` can be:
+| Name                                    | Platform                      |
+| --------------------------------------- | ----------------------------- |
+| `rk3588-rock-5b`                        | ROCK 5B                       |
+| `rk3588s-rock-5a`                       | ROCK 5A                       |
+| `rk3588-rock-5-itx`                     | ROCK 5 ITX                    |
+| `rk3588s-orangepi-5`                    | Orange Pi 5                   |
+| `rk3588-orangepi-5-plus`                | Orange Pi 5 Plus              |
+| `rk3588s-9tripod-linux`                 | Indiedroid Nova               |
+| `rk3588s-fydetab-duo`                   | Fydetab Duo                   |
+| `rk3588-firefly-aio-3588q`              | Firefly AIO-3588Q             |
+| `itx-3588j`                             | Firefly ITX-3588J             |
+| `roc-rk3588s-pc`                        | ROC-RK3588S-PC / Station M3   |
+| `rk3588-blueberry-edge-v12-linux`       | R58X (v1.2)                   |
+| `rk3588-blueberry-minipc-linux`         | R58 Mini                      |
+| `rk3588s-khadas-edge2`                  | Edge2                         |
+| `rk3588-blade3-v101-linux`              | Blade 3                       |
+| `rk3588-nanopc-t6`                      | NanoPC T6                     |
+| `rk3588s-nanopi-r6c`                    | NanoPi R6C                    |
+| `rk3588s-nanopi-r6s`                    | NanoPi R6S                    |
+| `rk3588-hinlink-h88k`                   | H88K                          |
+
+In the absence of a custom base DTB override, the overlays are applied on top of the firmware-provided DTB.
+
+The firmware applies some fix-ups to its own DTB depending on the user settings (e.g. PCIe/SATA/USB selection, making SATA overlays redundant). These fix-ups are not applied to a custom base DTB - overlays must be used instead.
+
+If the application of an overlay fails (e.g. due to it being invalid in regard to the base DTB), all overlays are discarded, including those that got applied up to that point.
+
+If the custom base DTB is invalid, the firmware-provided one will be passed to the OS instead.
+
+This entire process is logged to the [serial console](#advanced-troubleshooting). There's currently no other way to see potential errors.
+
+# Updating the firmware
+If the storage is only used for UEFI and nothing else, simply download the latest image and flash it as described in the [Getting started](#getting-started) section.
+
+If it is also used by an OS and has additional partitions, only part of the image needs to be applied. This can be done with the `dd` tool:
+```bash
+dd if=FIRMWARE.img of=DESTINATION bs=512 skip=64 seek=64 conv=notrunc
+```
+
+`FIRMWARE.img` is the firmware image for your platform. E.g. `edge2_UEFI_Release_v0.8.img`.
+
+`DESTINATION` is the destination storage that you wish to update the firmware on. E.g. `/dev/sdb`.
+
+Here we skip the GPT and copy the firmware starting at offset 0x8000 (`64` blocks * `512` bytes block size) until its end. See [Flash layout](#flash-layout) for more details.
+
+# Troubleshooting
+
+> [!IMPORTANT]
+> First of all, make sure your device can only possibly load the UEFI firmware and nothing else.
+>
+> **U-Boot must not present on either SPI NOR, SD or eMMC, otherwise it could take precedence and cause hidden issues.**
+
+Below you can find some basic debugging information. If none of this helps, please see the [Advanced troubleshooting](#advanced-troubleshooting) section.
+
+## Meaning of the Status LED
+If your device has an activity LED, the firmware will blink it in different patterns to indicate the current system status.
+
+1. Immediately after power on, the LED should start pulsing quickly. This indicates that the firmware is initializing.
+
+2. After initialization (usually takes less than 5 seconds), the LED will switch to a short pulsing every 2 seconds or so. This indicates that the firmware is ready and waiting for user action or the countdown to boot automatically. The display output should also be enabled at this point.
+
+3. When the firmware boots an OS and is about to exit, the LED will stop blinking.
+
+If the LED:
+* does not light up after power on, this means the firmware has not managed to load up at all.
+* gets stuck in either on or off state after blinking a few times and never recovers, something went wrong and the firmware has crashed or frozen.
+
+  Note that it is only expected to stop as described at point 3) above.
+
+## Common issues
+### Nothing shows up on the screen
+Make sure you've flashed the firmware correctly and that it is the version designed for your device. In most cases this is the culprit.
+
+Assuming the firmware loads fine:
+* The display must support a resolution of at least 1080p at 60 Hz.
+* If you're using HDMI and the system has two ports, only one will work. Try both.
+* If you're using USB-C to DisplayPort, only one orientation of the USB-C connector will work. Check both.
+
+If you are not able to get any display output, the only way to interact with UEFI is via the [serial console](#advanced-troubleshooting).
+
+### Configuration settings do not get saved
+This has been observed in cases where U-Boot was still present on another boot device (SD, eMMC or SPI NOR).  This is not a supported scenario. The solution is to unplug or erase devices that may have other firmware on them.
+
+What's happening:
+1. Board loads U-Boot from a storage device that has higher priority (let's say eMMC).
+2. That U-Boot image in turn loads UEFI and its settings from another device with lower priority (let's say SD).
+3. UEFI cannot accurately determine to which device it belongs. The parameter used to verify this points to eMMC (U-Boot), while UEFI actually got loaded from SD.
+4. Consequently, UEFI mistakenly saves the user settings to eMMC. On reboot, U-Boot loads UEFI and the original/unchanged settings from SD and the cycle repeats.
+
+### USB 3 devices do not work
+* Try a different port.
+* If you're using USB-C, 3.0 devices will only work in one orientation of the connector. Check both.
+* Make sure the power supply and cable are good.
+
+### Networking does not work
+* Only Realtek PCIe and USB controllers are supported. Native Gigabit provided by RK3588 isn't.
+
+* Some boards with Realtek NICs do not have a MAC address set at factory and will show-up as being all zeros in UEFI, possibly preventing the adapter from obtaining an IP address.
+
+  You can easily fix this by writing the MAC address manually:
+
+  1. Boot into Linux and open up a terminal. The commands below apply to Armbian with legacy kernel.
+
+  2. Install the headers for your kernel version:
+      ```bash
+      sudo apt install -y linux-headers-legacy-rk35xx
+      ```
+
+  3. Clone Realtek PGTool and build the driver:
+      ```bash
+      git clone https://github.com/redchenjs/rtnicpg
+      cd rtnicpg
+      make
+      ```
+
+  4. Unload all Realtek modules and load the driver built above:
+      ```bash
+      sudo rmmod pgdrv
+      sudo ./pgload.sh
+      ```
+      Note: make sure there aren't any remaining Realtek modules loaded after this, except for the new `pgdrv`.<br> If you have `r8125` built-in, you might have to reboot with `initcall_blacklist=rtl8125_init_module` as a kernel parameter (in Grub).
+
+   5. Burn a MAC address into the eFuses:
+
+      For only one NIC:
+      ```bash
+      sudo ./rtnicpg-aarch64-linux-gnu /efuse /nodeid 00E04C001234
+      ```
+      For two or more:
+      ```bash
+      sudo ./rtnicpg-aarch64-linux-gnu /efuse /# 1 /nodeid 00E04C001234
+      sudo ./rtnicpg-aarch64-linux-gnu /efuse /# 2 /nodeid 00E04C001235
+      ```
+      `00E04C001234` is an example address. You can generate random and unique ones using: <https://www.macvendorlookup.com/mac-address-generator>
+
+  **Note:** the number of eFuses is limited, thus MAC addresses can only be changed a few times.
+
+## Advanced troubleshooting
+The firmware will log detailed information to the serial console when using a debug version. See the [release notes](https://github.com/edk2-porting/edk2-rk3588/releases) for details on how to obtain this version.
+
+1. The debug image needs to be flashed in place of the existing one.
+
+2. Connect the **UART2** RX, TX and GND pins on your device (check vendor documentation) to the UART adapter on your other computer.
+
+3. Open up a serial terminal (`PuTTY` on Windows, `stty` on Linux) set to 1500000 baud rate and 8n1 (default).
+
+4. Power on the device.
+
+You should be able to see many debug messages being printed to the console. If that's not the case, double check the connections (swap RX/TX), make sure the adapter is functional and configured correctly.
+
+The logs should give an insight of what's going on. If you need help analyzing them, feel free to open an issue ticket.
+
+# Reporting issues
+You can open issues related to UEFI at <https://github.com/edk2-porting/edk2-rk3588/issues>.
+
+Please include as many details as possible: expected behavior, what actually happens, steps to reproduce, [serial logs](#advanced-troubleshooting), etc.
+
+Also check the existing issues in case yours might be already reported.
+
+# Building
+The firmware can only be built on Linux currently. For Windows use WSL.
+
+1. Install required packages:
+
+   For Ubuntu/Debian:
+   ```bash
+   sudo apt install git gcc g++ build-essential gcc-aarch64-linux-gnu acpica-tools python3-pyelftools uuid-dev python-is-python3 device-tree-compiler
+   ```
+   For Arch Linux:
+   ```bash
+   sudo pacman -Syu
+   sudo pacman -S git base-devel gcc dtc aarch64-linux-gnu-binutils aarch64-linux-gnu-gcc aarch64-linux-gnu-glibc python python-pyelftools iasl --needed
+   ```
+
+2. Clone the repository:
+   ```bash
+   git clone https://github.com/edk2-porting/edk2-rk3588.git --recursive
+   cd edk2-rk3588
+   ```
+
+3. Build UEFI (ROCK 5B for example, check [list of platform configs](https://github.com/edk2-porting/edk2-rk3588/tree/master/configs)):
+   ```bash
+   ./build.sh --device rock-5b --release Release # (or Debug)
+   ```
+
+If you get build errors, it is very likely that you're still missing some dependencies. The list of packages above is not complete and depending on the distro you may need to install additional ones. In most cases, looking up the error messages on the internet will point you at the right packages.
+
+# Notes
+
+## Flash layout
+| Address    | Size       | Desc                  | File                   |
+| ---------- | ---------- | --------------------- | ---------------------- |
+| 0x00000000 | 0x00004400 | GPT Table             | rk3588_spi_nor_gpt.img |
+| 0x00008000 |            | IDBlock               | idblock.bin            |
+| 0x00100000 | 0x00500000 | BL33_AP_UEFI FV       | ${DEVICE}_EFI.itb      |
+| 0x007C0000 | 0x00010000 | NV_VARIABLE_STORE     |                        |
+| 0x007D0000 | 0x00010000 | NV_FTW_WORKING        |                        |
+| 0x007E0000 | 0x00010000 | NV_FTW_SPARE          |                        |
+
+The variable store is not included in the flash image, in order to prevent overwriting it and to maintain the user settings across updates.
+
+The firmware expects these exact offsets, do not change them.
+
+## Memory Map
+| Address    | Size       | Desc                  | File                |
+| ---------- | ---------  | --------------------- | ------------------- |
+| 0x00040000 |            | ATF                   | bl31_0x00040000.bin |
+| 0x000f0000 |            | ATF                   | bl31_0x000f0000.bin |
+| 0x00200000 | 0x00500000 | UEFI FV               | BL33_AP_UEFI.Fv     |
+| 0x007C0000 | 0x00010000 | NV_VARIABLE_STORE     |                     |
+| 0x007D0000 | 0x00010000 | NV_FTW_WORKING        |                     |
+| 0x007E0000 | 0x00010000 | NV_FTW_SPARE          |                     |
+| 0x08400000 |            | OP-TEE                | bl32.bin            |
+| 0xff100000 |            | ATF (PMU_MEM)         | bl31_0xff100000.bin |
+
+## Licenses
+Most of the UEFI code is licensed under the default EDK2 license, which is [BSD-2-Clause-Patent](https://github.com/tianocore/edk2/blob/master/License.txt).
+
+Some non-critical components have been ported from Rockchip's U-Boot fork and are licensed as **GPL-2.0-or-later**:
+* UsbDpPhy
+* DwDpLib
+
+The files in `edk2-rockchip-non-osi` are licensed as **GPL-2.0-only**.
+
+The license for some of the blobs in the `misc/rkbin/` directory can be found at: <https://github.com/rockchip-linux/rkbin/blob/master/LICENSE>. Note that it also contains binaries built from open-source projects such as U-Boot (SPL), Arm Trusted Firmware and OP-TEE, having a different license.
+
+## Community
+* Hack w/ Rockchip Telegram: <https://t.me/UEFIonRockchip>
+* Windows on R Discord: <https://discord.gg/vjHwptUCa3>
+
+## Credits & alternatives
+This firmware is based on Rockchip's initial efforts at <https://gitlab.com/rk3588_linux/rk/uefi-monorepo>.
+
+For RK356x, check out the Quartz64-UEFI project at https://github.com/jaredmcneill/quartz64_uefi, from which we also reused some code.
--- a/local/UEFI/edk2-rk3588-master/build.sh
+++ b/local/UEFI/edk2-rk3588-master/build.sh
@ -0,0 +1,252 @@
+#!/bin/bash
+
+function _help(){
+    echo
+    echo "Build EDK2 for Rockchip RK3588 platforms."
+    echo
+    echo "Usage: build.sh [options]"
+    echo
+    echo "Options:"
+    echo "  -d, --device DEV            Build for DEV, or 'all'."
+    echo "  -r, --release MODE          Release mode for building, default is 'DEBUG', 'RELEASE' alternatively."
+    echo "  -t, --toolchain TOOLCHAIN   Set toolchain, default is 'GCC'."
+    echo "  --open-tfa ENABLE           Use open-source TF-A submodule. Default: ${OPEN_TFA}"
+    echo "  -C, --clean                 Clean workspace and output."
+    echo "  -D, --distclean             Clean up all files that are not in repo."
+    echo "  --tfa-flags \"FLAGS\"         Flags appended to open TF-A build process."
+    echo "  --edk2-flags \"FLAGS\"        Flags appended to the EDK2 build process."
+    echo "  -h, --help                  Show this help."
+    echo
+    exit "${1}"
+}
+
+function _error() { echo "${@}" >&2; exit 1; }
+
+function _build_idblock() {
+    echo " => Building idblock.bin"
+    pushd ${WORKSPACE}
+
+    FLASHFILES="FlashHead.bin FlashData.bin FlashBoot.bin"
+    rm -f rk35*_spl_loader_*.bin idblock.bin rk35*_ddr_*.bin rk35*_usbplug*.bin UsbHead.bin ${FLASHFILES}
+
+    DDRBIN_RKBIN=$(grep '^FlashData' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
+    SPL_RKBIN=$(grep '^FlashBoot' ${ROOTDIR}/misc/rkbin/RKBOOT/${MINIALL_INI} | cut -d = -f 2-)
+
+    DDRBIN="${ROOTDIR}/misc/rkbin/${DDRBIN_RKBIN}"
+
+    #
+    # SPL v1.13 has broken SD card support!
+    # Use v1.12 instead.
+    #
+    # SPL="${ROOTDIR}/misc/rkbin/${SPL_RKBIN}"
+    SPL="${ROOTDIR}/misc/rk3588_spl_v1.12.bin"
+
+    # Create idblock.bin
+    ${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -n rk3588 -T rksd -d ${DDRBIN}:${SPL} idblock.bin
+
+    popd
+    echo " => idblock.bin build done"
+}
+
+function _build_fit() {
+    echo " => Building FIT"
+    pushd ${WORKSPACE}
+
+    BL31_RKBIN=$(grep '^PATH=.*_bl31_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
+    BL32_RKBIN=$(grep '^PATH=.*_bl32_' ${ROOTDIR}/misc/rkbin/RKTRUST/${TRUST_INI} | cut -d = -f 2-)
+
+    BL31="${ROOTDIR}/misc/rkbin/${BL31_RKBIN}"
+    BL32="${ROOTDIR}/misc/rkbin/${BL32_RKBIN}"
+
+    if [ ${OPEN_TFA} == 1 ]; then
+        BL31="${ROOTDIR}/arm-trusted-firmware/build/${TFA_PLAT}/${RELEASE_TYPE,,}/bl31/bl31.elf"
+    fi
+
+    rm -f bl31_0x*.bin ${WORKSPACE}/BL33_AP_UEFI.Fv ${SOC_L}_${DEVICE}_EFI.its
+
+    ${ROOTDIR}/misc/extractbl31.py ${BL31}
+    if [ ! -f bl31_0x000f0000.bin ]; then
+        # Not used but FIT expects it.
+        touch bl31_0x000f0000.bin
+    fi
+
+    cp ${BL32} ${WORKSPACE}/bl32.bin
+    cp ${ROOTDIR}/misc/${SOC_L}_spl.dtb ${WORKSPACE}/${DEVICE}.dtb
+    cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/BL33_AP_UEFI.Fv ${WORKSPACE}/
+    cat ${ROOTDIR}/misc/uefi_${SOC_L}.its | sed "s,@DEVICE@,${DEVICE},g" > ${SOC_L}_${DEVICE}_EFI.its
+    ${ROOTDIR}/misc/tools/${MACHINE_TYPE}/mkimage -f ${SOC_L}_${DEVICE}_EFI.its -E ${DEVICE}_EFI.itb
+
+    popd
+    echo " => FIT build done"
+}
+
+function _pack_image() {
+    _build_idblock
+    _build_fit
+
+    echo " => Building 8MB NOR FLASH IMAGE"
+    cp ${WORKSPACE}/Build/${PLATFORM_NAME}/${RELEASE_TYPE}_${TOOLCHAIN}/FV/NOR_FLASH_IMAGE.fd ${WORKSPACE}/RK3588_NOR_FLASH.img
+
+    # GPT at 0x0, size:0x4400
+    dd if=${ROOTDIR}/misc/rk3588_spi_nor_gpt.img of=${WORKSPACE}/RK3588_NOR_FLASH.img
+    # idblock at 0x8000
+    dd if=${WORKSPACE}/idblock.bin of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=32
+    # FIT Image at 0x100000
+    dd if=${WORKSPACE}/${DEVICE}_EFI.itb of=${WORKSPACE}/RK3588_NOR_FLASH.img bs=1K seek=1024
+    cp ${WORKSPACE}/RK3588_NOR_FLASH.img ${ROOTDIR}/
+}
+
+function _build(){
+    local DEVICE="${1}"; shift
+
+    #
+    # Grab platform parameters
+    #
+    if [ -f "configs/${DEVICE}.conf" ]
+    then source "configs/${DEVICE}.conf"
+    else _error "Device configuration not found"
+    fi
+    if [ -f "configs/${SOC}.conf" ]
+    then source "configs/${SOC}.conf"
+    else _error "SoC configuration not found"
+    fi
+    typeset -l SOC_L="$SOC"
+
+    rm -f "${OUTDIR}/RK35*_NOR_FLASH.img"
+
+    #
+    # Build TF-A
+    #
+    if [ ${OPEN_TFA} == 1 ]; then
+        pushd arm-trusted-firmware
+
+        if [ ${RELEASE_TYPE} == "DEBUG" ]; then
+            DEBUG=1
+        else
+            DEBUG=0
+        fi
+
+        make PLAT=${TFA_PLAT} DEBUG=${DEBUG} all ${TFA_FLAGS}
+
+        popd
+    fi
+
+    #
+    # Build EDK2
+    #
+    [ -d "${WORKSPACE}/Conf" ] || mkdir -p "${WORKSPACE}/Conf"
+
+    export GCC_AARCH64_PREFIX="${CROSS_COMPILE}"
+    export CLANG38_AARCH64_PREFIX="${CROSS_COMPILE}"
+    export PACKAGES_PATH="${ROOTDIR}/edk2:${ROOTDIR}/edk2-platforms:${ROOTDIR}/edk2-rockchip:${ROOTDIR}/edk2-rockchip-non-osi:${ROOTDIR}/edk2-non-osi:${ROOTDIR}"
+
+    make -C "${ROOTDIR}/edk2/BaseTools"
+    source "${ROOTDIR}/edk2/edksetup.sh"
+
+    build \
+        -s \
+        -n 0 \
+        -a AARCH64 \
+        -t "${TOOLCHAIN}" \
+        -p "${ROOTDIR}/${DSC_FILE}" \
+        -b "${RELEASE_TYPE}" \
+        -D FIRMWARE_VER="${GIT_COMMIT}" \
+        ${EDK2_FLAGS}
+
+    #
+    # Compile final image
+    #
+    _pack_image
+
+    echo "Build done: RK3588_NOR_FLASH.img"
+}
+
+function _clean() { rm --one-file-system --recursive --force "${OUTDIR}"/workspace "${OUTDIR}"/RK3588_*.img; }
+function _distclean() { if [ -d .git ]; then git clean -xdf; else _clean; fi; }
+
+#
+# Default variables
+#
+typeset -l DEVICE
+typeset -u RELEASE_TYPE
+DEVICE=""
+RELEASE_TYPE=DEBUG
+TOOLCHAIN=GCC
+OPEN_TFA=1
+TFA_FLAGS=""
+EDK2_FLAGS=""
+CLEAN=false
+DISTCLEAN=false
+OUTDIR="${PWD}"
+
+#
+# Get options
+#
+OPTS=$(getopt -o "d:r:t:CDh" -l "device:,release:,toolchain:,open-tfa:,tfa-flags:,edk2-flags:,clean,distclean,help" -n build.sh -- "${@}") || _help $?
+eval set -- "${OPTS}"
+while true; do
+    case "${1}" in
+        -d|--device) DEVICE="${2}"; shift 2 ;;
+        -r|--release) RELEASE_TYPE="${2}"; shift 2 ;;
+        -t|--toolchain) TOOLCHAIN="${2}"; shift 2 ;;
+        --open-tfa) OPEN_TFA="${2}"; shift 2 ;;
+        --tfa-flags) TFA_FLAGS="${2}"; shift 2 ;;
+        --edk2-flags) EDK2_FLAGS="${2}"; shift 2 ;;
+        -C|--clean) CLEAN=true; shift ;;
+        -D|--distclean) DISTCLEAN=true; shift ;;
+        -h|--help) _help 0; shift ;;
+        --) shift; break ;;
+        *) break ;;
+    esac
+done
+if [[ -n "${@}" ]]; then
+    echo "Invalid additional arguments '${@}'"
+    _help 1
+fi
+
+if "${DISTCLEAN}"; then _distclean; exit "$?"; fi
+if "${CLEAN}"; then _clean; exit "$?"; fi
+
+[ -z "${DEVICE}" ] && _help 1
+[ -f "configs/${DEVICE}.conf" ] || [ "${DEVICE}" == "all" ] || _error "Device configuration not found"
+
+#
+# Get machine architecture
+#
+MACHINE_TYPE=$(uname -m)
+
+# Fix-up possible differences in reported arch
+if [ ${MACHINE_TYPE} == 'arm64' ]; then
+    MACHINE_TYPE='aarch64'
+elif [ ${MACHINE_TYPE} == 'amd64' ]; then
+    MACHINE_TYPE='x86_64'
+fi
+
+if [ ${MACHINE_TYPE} != 'aarch64' ]; then
+    export CROSS_COMPILE="${CROSS_COMPILE:-aarch64-linux-gnu-}"
+fi
+
+GIT_COMMIT="$(git describe --tags --always)" || GIT_COMMIT="unknown"
+
+export WORKSPACE="${OUTDIR}/workspace"
+[ -d "${WORKSPACE}" ] || mkdir "${WORKSPACE}"
+
+ROOTDIR="$(realpath "$(dirname "$0")")"
+cd "${ROOTDIR}" || exit 1
+
+# Exit on first error
+set -e
+
+if [ "${DEVICE}" == "all" ]
+then
+    for i in configs/*.conf; do
+        DEV="$(basename "$i" .conf)"
+        if [ "${DEV}" != "RK3588" ]
+        then
+            echo "Building ${DEV}"
+            _build "${DEV}"
+        fi
+    done
+else
+    _build "${DEVICE}"
+fi
--- a/local/UEFI/edk2-rk3588-master/configs/RK3588.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/RK3588.conf
@ -0,0 +1,3 @@
+MINIALL_INI=RK3588MINIALL.ini
+TRUST_INI=RK3588TRUST.ini
+TFA_PLAT=rk3588_reference_pmic
--- a/local/UEFI/edk2-rk3588-master/configs/aio-3588q.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/aio-3588q.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc
+PLATFORM_NAME=AIO-3588Q
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/blade3.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/blade3.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Mixtile/Blade3/Blade3.dsc
+PLATFORM_NAME=Blade3
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/edge2.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/edge2.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Khadas/Edge2/Edge2.dsc
+PLATFORM_NAME=Edge2
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/fydetab-duo.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/fydetab-duo.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/FydeInnovations/FydetabDuo/FydetabDuo.dsc
+PLATFORM_NAME=FydetabDuo
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/h88k.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/h88k.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Hinlink/H88K/H88K.dsc
+PLATFORM_NAME=H88K
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/indiedroid-nova.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/indiedroid-nova.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
+PLATFORM_NAME=IndiedroidNova
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/itx-3588j.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/itx-3588j.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc
+PLATFORM_NAME=ITX-3588J
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/nanopc-t6.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/nanopc-t6.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
+PLATFORM_NAME=NanoPC-T6
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/nanopi-r6c.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/nanopi-r6c.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.dsc
+PLATFORM_NAME=NanoPi-R6C
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/nanopi-r6s.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/nanopi-r6s.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/FriendlyElec/NanoPi-R6S/NanoPi-R6S.dsc
+PLATFORM_NAME=NanoPi-R6S
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/orangepi-5.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/orangepi-5.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/OrangePi/OrangePi5/OrangePi5.dsc
+PLATFORM_NAME=OrangePi5
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/orangepi-5plus.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/orangepi-5plus.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/OrangePi/OrangePi5Plus/OrangePi5Plus.dsc
+PLATFORM_NAME=OrangePi5Plus
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/r58-mini.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/r58-mini.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Mekotronics/R58-Mini/R58-Mini.dsc
+PLATFORM_NAME=R58-Mini
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/r58x.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/r58x.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Mekotronics/R58X/R58X.dsc
+PLATFORM_NAME=R58X
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/roc-rk3588s-pc.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/roc-rk3588s-pc.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc
+PLATFORM_NAME=ROC-RK3588S-PC
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/rock-5-itx.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/rock-5-itx.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5ITX/ROCK5ITX.dsc
+PLATFORM_NAME=ROCK5ITX
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/rock-5a.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/rock-5a.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5A/ROCK5A.dsc
+PLATFORM_NAME=ROCK5A
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/rock-5b.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/rock-5b.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5B/ROCK5B.dsc
+PLATFORM_NAME=ROCK5B
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/rock-5bplus.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/rock-5bplus.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/Radxa/ROCK5BPlus/ROCK5BPlus.dsc
+PLATFORM_NAME=ROCK5BPlus
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/configs/station-m3.conf
+++ b/local/UEFI/edk2-rk3588-master/configs/station-m3.conf
@ -0,0 +1,3 @@
+DSC_FILE=edk2-rockchip/Platform/StationPC/StationM3/StationM3.dsc
+PLATFORM_NAME=StationM3
+SOC=RK3588
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/README.md
@ -0,0 +1,20 @@
+# Rockchip Platform Device Trees
+## Sources
+* <https://github.com/armbian/linux-rockchip/tree/f3fb30ac9de06b41fb621d17bc53603f1f48ac90/arch/arm64/boot/dts/rockchip>
+  * Updated to `rk-6.1-rkr1` branch, currently called `vendor` branch in armbian/build
+
+* roc-rk3588s-pc: <https://gitlab.com/firefly-linux/kernel/-/tree/b8646da2122f45a2c02082d949427b80d2e89b1f/arch/arm64/boot/dts/rockchip>
+
+* itx-3588j: <https://gitlab.com/firefly-linux/kernel/-/tree/e14c28295dd7ee8f807899e9b0b7da5f79742e4f/arch/arm64/boot/dts/rockchip>
+  (note: in the dtb given here, the builtin bootargs in the source above were commented out
+   before building. Not sure if that was a necessary step - SS)
+
+* rk3588-firefly-aio-3588q: <https://gitlab.com/firefly-linux/kernel/-/tree/fa0e053fd911339b825407cb6d4b167fad7cdc49/arch/arm64/boot/dts/rockchip>
+
+* rk3588-rock-5b-plus: <https://github.com/radxa/kernel/blob/3b95df6d8bf567857b69e5266f1cb0651a6cfb3e/arch/arm64/boot/dts/rockchip/>
+
+* rk3588s-fydetab-duo: <https://github.com/Linux-for-Fydetab-Duo/linux-rockchip/tree/14294048d2a0deb7f38c890329aded87038d3299/arch/arm64/boot/dts/rockchip>
+  (note: dtb taken from the `noble` branch which is based on the rockchip 6.1 rkr3 bsp kernel)
+
+## License
+SPDX-License-Identifier: GPL-2.0-only
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/itx-3588j.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/itx-3588j.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blade3-v101-linux.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blade3-v101-linux.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blueberry-edge-v12-linux.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blueberry-edge-v12-linux.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blueberry-minipc-linux.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-blueberry-minipc-linux.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-hinlink-h88k.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-hinlink-h88k.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-nanopc-t6.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-nanopc-t6.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-orangepi-5-plus.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-orangepi-5-plus.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5-itx.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5-itx.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5b-plus.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5b-plus.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5b.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588-rock-5b.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-9tripod-linux.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-9tripod-linux.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-fydetab-duo.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-fydetab-duo.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-khadas-edge2.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-khadas-edge2.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6c.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6c.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6s.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6s.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-orangepi-5.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-orangepi-5.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-rock-5a.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/rk3588s-rock-5a.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/roc-rk3588s-pc.dtb
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip-non-osi/Platform/Rockchip/DeviceTree/roc-rk3588s-pc.dtb
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.bmp
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.bmp
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.c
@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.idf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/Logo.idf
@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/Drivers/LogoDxe/LogoDxe.inf
@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/AcpiTables.inf
@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/AcpiTables/Dsdt.asl
@ -0,0 +1,53 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C7"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI4"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PA7
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    // include ("Gmac.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+
+    Scope (I2C7) {
+      include ("Es8388.asl")
+    }
+  }
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.Modules.fdf.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.Modules.fdf.inc
@ -0,0 +1,18 @@
+## @file
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+    SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-9tripod-linux.dtb
+  }
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/IndiedroidNova.dsc
@ -0,0 +1,116 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = IndiedroidNova
+  PLATFORM_VENDOR                = Ameridroid
+  PLATFORM_GUID                  = 247fa541-ba0c-478e-ba76-4e00450f7f11
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
+
+  # No status LED on this platform.
+  DEFINE RK_STATUS_LED_ENABLE = FALSE
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  #
+  # RK3588S-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"Indiedroid Nova"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"ameriDroid"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"Indiedroid"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://indiedroid.us"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588s-9tripod-linux"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x7 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_MAX)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
+
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
+  #
+  # On-Board fan output
+  #
+  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.c
@ -0,0 +1,296 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  /* No GMAC here */
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
+    break;
+  case 1:
+    break;
+  case 2:
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
+    break;
+  case 3:
+    break;
+  case 4:
+    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3
+    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
+    break;
+  case 5:
+    GpioPinSetFunction(3, GPIO_PIN_PC7, 9); //i2c5_scl_m0
+    GpioPinSetFunction(3, GPIO_PIN_PD0, 9); //i2c5_sda_m0
+    break;
+  case 6:
+    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
+    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+
+  /* Set GPIO4 PA5 output high to enable USB-C VBUS */
+  GpioPinWrite (4, GPIO_PIN_PA5, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PA5, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  /* Set reset to gpio output mode */
+  if(Segment == PCIE_SEGMENT_PCIE20L2) { // RTL8111
+    GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  /* nothing to power on */
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+    GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
+  }
+}
+
+PWM_DATA pwm_data = {
+  .ControllerID = PWM_CONTROLLER2,
+  .ChannelID = PWM_CHANNEL3,
+  .PeriodNs = 4000000,
+  .DutyNs = 4000000,
+  .Polarity = FALSE,
+}; // PWM2_CH3
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+  GpioPinSetFunction (4, GPIO_PIN_PB4, 0xB); // PWM11_IR_M1
+  RkPwmSetConfig (&pwm_data);
+  RkPwmEnable (&pwm_data);
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+  pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
+  RkPwmSetConfig (&pwm_data);
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  // No controllable LEDs on this platform
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  // No controllable LEDs on this platform
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+  GpioPinSetFunction(4, GPIO_PIN_PA7, 0); //jdet
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Ameridroid/IndiedroidNova/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@ -0,0 +1,35 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc
@ -0,0 +1,18 @@
+## @file
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+    SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-firefly-aio-3588q.dtb
+  }
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc
@ -0,0 +1,31 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = AIO-3588Q
+  PLATFORM_VENDOR                = Firefly
+  PLATFORM_GUID                  = 400f8259-7664-47df-b375-8ba262e4867e
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+  #
+  # Platform based on AIO-3588Q board
+  #
+!include Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AIO-3588Q.dsc.inc
@ -0,0 +1,134 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = Platform/Firefly/AIO-3588Q/AIO-3588Q.Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  #
+  # PCA9555 GPIO extender support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_PCA9555_ENABLE = TRUE
+
+  #
+  # RK3588-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"AIO-3588Q"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"AIO"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/core/icore3588q"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"aio-3588q"
+
+  # I2C
+  # i2c0: pc9202@3c, rk8602@42, rk8603@43
+  # i2c1: rk8602@42 (npu)
+  # i2c3: es8388@11, XC7160b@1b, gc2053b@37, gc2093b@7e
+  # i2c6: pca9555@20, pca9555@21, fusb302@22, hym8563@51
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{           0x42,  0x43,  0x42,  0x11,  0x51, 0x20,  0x21,  0x22  }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{               0x0,   0x0,   0x1,   0x3,   0x6,  0x6,   0x6,   0x6   }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{     0x0,  0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+  gRockchipTokenSpaceGuid.PcdPca9555Address|0x21
+  gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 }
+
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x47
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x4f
+
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
+  #
+  # On-Board fan output
+  #
+  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
+
+  # Hack to enable use of PCA9555 during PCIe initialization.
+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <LibraryClasses>
+      RockchipPlatformLib|Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
+  }
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/AcpiTables.inf
@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/AcpiTables/Dsdt.asl
@ -0,0 +1,55 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C3"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PC4
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac0.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
+
+    Scope (I2C3) {
+      include ("Es8388.asl")
+    }
+  }
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.c
@ -0,0 +1,460 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Pca9555.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+EFI_STATUS
+EFIAPI
+GetPca9555Protocol (
+  IN OUT PCA95XX_PROTOCOL        **Pca95xxProtocl
+  )
+{
+  EFI_HANDLE          *HandleBuffer;
+  EFI_STATUS           Status;
+  UINTN                HandleCount;
+
+  /* Locate Handles of all PCA95XX_PROTOCOL producers */
+  Status = gBS->LocateHandleBuffer (ByProtocol,
+                  &gPca95xxProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__));
+    return Status;
+  }
+
+  DEBUG ((DEBUG_INFO,
+          "%a: got %d PCA95XX_PROTOCOLs\n",
+          __FUNCTION__,
+          HandleCount));
+
+  /*
+   * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute
+   * the consumer is not obliged to call CloseProtocol.
+   */
+  Status = gBS->OpenProtocol (HandleBuffer[0],
+                  &gPca95xxProtocolGuid,
+                  (VOID **)Pca95xxProtocl,
+                  HandleBuffer[0],
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+
+  return Status;
+}
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_RXD2, GMAC0_RXD3
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; // GMAC0_RXCLK, GMAC0_TXD2, GMAC0_TXD3, GMAC0_TXCLK
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100; // GMAC0_TXD0, GMAC0_TXD1
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111; // GMAC0_TXEN, GMAC0_RXD0, GMAC0_RXD1
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; // GMAC0_RXDV_CRS, GMAC0_MCLKINOUT
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011; // GMAC0_MDC, GMAC0_MDIO
+
+      /* phy0 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT);
+      break;
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (3, GPIO_PIN_PC7, !Enable);
+      break;
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); // I2C0_SCL_M2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); // I2C0_SDA_M2
+    break;
+  case 1:
+    GpioPinSetFunction(0, GPIO_PIN_PD4, 9); // I2C1_SCL_M2
+    GpioPinSetFunction(0, GPIO_PIN_PD5, 9); // I2C1_SDA_M2
+    break;
+  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); // I2C3_SCL_M0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); // I2C3_SDA_M0
+    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); // I2C6_SCL_M0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); // I2C6_SDA_M0
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  /* On Firefly AIO-3588Q this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "UsbPortPowerEnable failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* USB-C */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_0
+    );
+
+    gBS->Stall(1200000);
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    /* other USB stuff */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      5, /* vcc5v0_host */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      4, /* vcc_hub_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      6, /* vcc_hub3_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      7, /* vcc5v0_host3 */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT); // PCIE30X4_PERSTN_M1
+    GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT); // vcc3v3_pcie30
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    GpioPinSetDirection (1, GPIO_PIN_PB4, GPIO_PIN_OUTPUT);
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinWrite (4, GPIO_PIN_PC6, Enable); // vcc3v3_pcie30
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+
+  switch (Segment) {
+  case PCIE_SEGMENT_PCIE30X4:
+    GpioPinWrite (4, GPIO_PIN_PB6, !Enable); // PCIE30X4_PERSTN_M1
+    break;
+  case PCIE_SEGMENT_PCIE20L0:
+    GpioPinWrite (1, GPIO_PIN_PB4, !Enable);
+    break;
+  case PCIE_SEGMENT_PCIE20L1:
+    break;
+  case PCIE_SEGMENT_PCIE20L2:
+    Status = GetPca9555Protocol(&Pca95xxProtocol);
+    if (EFI_ERROR(Status)) {
+      DEBUG ((DEBUG_ERROR, "PciePeReset(L2) failed to get PCA9555! (%d)\n", Status));
+    } else {
+      Pca95xxProtocol->GpioProtocol.Set(
+        &Pca95xxProtocol->GpioProtocol,
+        14, /* PCA_IO1_6 */
+        Enable ? GPIO_MODE_OUTPUT_0 : GPIO_MODE_OUTPUT_1
+      );
+    }
+    break;
+  }
+}
+
+PWM_DATA pwm_data = {
+  .ControllerID = PWM_CONTROLLER3,
+  .ChannelID = PWM_CHANNEL3,
+  .PeriodNs = 50000,
+  .DutyNs = 50000,
+  .Polarity = FALSE,
+}; // PWM15
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+  GpioPinSetFunction (1, GPIO_PIN_PC6, 0xB); // PWM15_IR_M2
+  RkPwmSetConfig (&pwm_data);
+  RkPwmEnable (&pwm_data);
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+  pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
+  RkPwmSetConfig (&pwm_data);
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PB2, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PB2, Enable);
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT); // headphone enable
+  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
+  GpioPinSetFunction (1, GPIO_PIN_PC4, 0); // headphone detect
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@ -0,0 +1,38 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/AIO-3588Q/Library/RockchipPlatformLib/RockchipPlatformLibPcaDepex.inf
@ -0,0 +1,42 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
+
+# Hack to enable use of PCA9555 during PCIe initialization.
+[Depex]
+  gPca95xxProtocolGuid
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.bmp
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.bmp
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.c
@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.idf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/Logo.idf
@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/LogoDxe.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/Drivers/LogoDxe/LogoDxe.inf
@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+  
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/AcpiTables/Dsdt.asl
@ -0,0 +1,41 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac0.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    include ("Usb3Host2.asl")
+  }
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc
@ -0,0 +1,19 @@
+## @file
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+    SECTION RAW = Platform/Rockchip/DeviceTree/itx-3588j.dtb
+  }
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc
@ -0,0 +1,34 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ITX-3588J
+  PLATFORM_VENDOR                = Firefly
+  PLATFORM_GUID                  = db88a604-ec99-4d39-84d4-af4fa5b5e757
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+  #
+  # Platform based on ITX-3588J board
+  #
+!include Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc
+
+  
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/ITX-3588J.dsc.inc
@ -0,0 +1,120 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Shimrra Shai <shimmyshai00@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = Platform/Firefly/ITX-3588J/ITX-3588J.Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+  
+  #
+  # PCA9555 GPIO extender support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_PCA9555_ENABLE = TRUE
+
+  #
+  # RK3588-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"ITX-3588J"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"ITX"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/industry/itx3588j"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"itx-3588j"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x21, 0x22 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6, 0x6, 0x6 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+  gRockchipTokenSpaceGuid.PcdPca9555Address|0x21
+  gRockchipTokenSpaceGuid.PcdPca9555Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_SATA)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x2, 0x3 }
+  
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac0TxDelay|0x45
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x42
+
+  #
+  # On-Board fan output
+  #
+  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  Platform/Firefly/ITX-3588J/AcpiTables/AcpiTables.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
+  
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.c
@ -0,0 +1,511 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Pca9555.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+EFI_STATUS
+EFIAPI
+GetPca9555Protocol (
+  IN OUT PCA95XX_PROTOCOL        **Pca95xxProtocl
+  )
+{
+  EFI_HANDLE          *HandleBuffer;
+  EFI_STATUS           Status;
+  UINTN                HandleCount;
+  UINTN                Index;
+
+  /* Locate Handles of all PCA95XX_PROTOCOL producers */
+  Status = gBS->LocateHandleBuffer (ByProtocol,
+                  &gPca95xxProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: Unable to locate handles\n", __FUNCTION__));
+    return Status;
+  }
+  
+  DEBUG ((DEBUG_INFO, 
+          "%a: got %d PCA95XX_PROTOCOLs\n", 
+          __FUNCTION__, 
+          HandleCount));
+  
+  /*
+   * Open Pca95xxProtocl. With EFI_OPEN_PROTOCOL_GET_PROTOCOL attribute
+   * the consumer is not obliged to call CloseProtocol.
+   */
+  Status = gBS->OpenProtocol (HandleBuffer[0],
+                  &gPca95xxProtocolGuid,
+                  (VOID **)Pca95xxProtocl,
+                  HandleBuffer[0],
+                  NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+                    
+  return Status;
+}
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 0:
+      /* gmac0 iomux */
+      BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO2C_IOMUX_SEL_L = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO4C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+      BUS_IOC->GPIO4C_IOMUX_SEL_H = (0x00FFUL << 16) | 0x0011;
+
+      /* phy0 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PC7, GPIO_PIN_OUTPUT);
+      break;
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111; /* GMAC1_MCLKINOUT, GMAC1_TXEN, GMAC1_TXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111; /* GMAC1_RXD3, GMAC1_RXD2, GMAC1_TXD3, GMAC1_TXD2 */
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011; /* GMAC1_TXD0, GMAC1_RXDV_CRS, GMAC1_RXD1 */
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011; /* GMAC1_RXD0, GMAC1_RXCLK, GMAC1_TXCLK */
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100; /* GMAC1_MDIO, GMAC1_MDC */
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 0:
+      /* phy0 reset */
+      GpioPinWrite (3, GPIO_PIN_PC7, !Enable);
+      break;
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    /* io mux M2 */
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x0F00UL << 16) | 0x0300;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x00F0UL << 16) | 0x0030;
+    break;
+  case 1:
+    /* io mux */
+    //BUS_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0990;
+    //PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0880;
+    break;
+  case 2:
+    /* io mux */
+    BUS_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0B_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  case 3:
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  case 6:
+    /* io mux M0 */
+    BUS_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x9000;
+    BUS_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0009;
+    PMU2_IOC->GPIO0C_IOMUX_SEL_H = (0xF000UL << 16) | 0x8000;
+    PMU2_IOC->GPIO0D_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  
+  /* On Firefly ITX-3588J this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* USB-C */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_0
+    );
+    
+    gBS->Stall(1200000);
+    
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      12, /* vbus5v0_typec_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );    
+
+    /* other USB stuff */    
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      5, /* vcc5v0_host */
+      GPIO_MODE_OUTPUT_1
+    );
+
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      4, /* vcc_hub_reset */
+      GPIO_MODE_OUTPUT_1
+    );
+    
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      6, /* vcc_hub3_reset */
+      GPIO_MODE_OUTPUT_1
+    );  
+    
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      7, /* vcc5v0_host3 */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    /* reset */
+    GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+    /* vcc3v3_pcie30 */
+    GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    /* vcc3v3_pcie30 */
+    GpioPinWrite (2, GPIO_PIN_PC5, Enable);
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE30X4) {
+    GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
+  }
+}
+
+PWM_DATA pwm_data = {
+  .ControllerID = PWM_CONTROLLER2,
+  .ChannelID = PWM_CHANNEL3,
+  .PeriodNs = 50000,
+  .DutyNs = 50000,
+  .Polarity = TRUE,
+}; // PWM2_CH3
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      11, /* vcc_fan_pwr_en */
+      GPIO_MODE_OUTPUT_1
+    );
+  }
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    /* (SS) NB: (TBA?) It doesn't *appear* we can regulate the fan speed,
+     *      only power up/down, but I could be wrong
+     */
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      11, /* vcc_fan_pwr_en */
+      (Percentage > 0) ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
+    );
+  }
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  /* Activate power LED only */
+  GpioPinWrite (1, GPIO_PIN_PB3, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PB3, GPIO_PIN_OUTPUT);
+  
+#if 0
+  /* Red off, Green for status, Blue for power */
+  GpioPinWrite (3, GPIO_PIN_PB2, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+  GpioPinWrite (3, GPIO_PIN_PC0, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+  GpioPinWrite (1, GPIO_PIN_PD5, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
+#endif
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  /* (SS) does not seem to work and causes errors on I2C complaining
+   * about something being too high
+   */
+#if 0
+  EFI_STATUS Status = EFI_SUCCESS;
+  PCA95XX_PROTOCOL *Pca95xxProtocol;
+  
+  /* On Firefly ITX-3588J this is controlled via the PCA9555. */
+  Status = GetPca9555Protocol(&Pca95xxProtocol);
+  if (EFI_ERROR(Status)) {
+    DEBUG ((DEBUG_ERROR, "Failed to get PCA9555! (%d)\n", Status));
+  } else {
+    Pca95xxProtocol->GpioProtocol.Set(
+      &Pca95xxProtocol->GpioProtocol,
+      3, /* user_led */
+      Enable ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0
+    );
+  }
+#endif
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ITX-3588J/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@ -0,0 +1,38 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Protocols]
+  gPca95xxProtocolGuid
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/AcpiTables/Dsdt.asl
@ -0,0 +1,53 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+#define BOARD_AUDIO_CODEC_HID "ESSX8388"
+#define BOARD_CODEC_I2C "\\_SB.I2C3"
+#define BOARD_CODEC_I2C_ADDR 0x11
+#define BOARD_CODEC_GPIO "\\_SB.GPI1"
+#define BOARD_CODEC_GPIO_PIN GPIO_PIN_PA6
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host2.asl")
+
+    Scope (I2C3) {
+      include ("Es8388.asl")
+    }
+  }
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.c
@ -0,0 +1,368 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Library/PWMLib.h>
+#include <Soc.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+ // RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (0, GPIO_PIN_PD3, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (0, GPIO_PIN_PD3, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
+    break;
+  case 1:
+    break;
+  case 2:
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
+    break;
+  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
+    break;
+  case 4:
+    GpioPinSetFunction(1, GPIO_PIN_PA3, 9); //i2c4_scl_m3 
+    GpioPinSetFunction(1, GPIO_PIN_PA2, 9); //i2c4_sda_m3
+    break;
+  case 5:
+    break;
+  case 6:
+    GpioPinSetFunction(4, GPIO_PIN_PB1, 9); //i2c6_scl_m3
+    GpioPinSetFunction(4, GPIO_PIN_PB0, 9); //i2c6_sda_m3
+    break;
+  case 7:
+    GpioPinSetFunction(1, GPIO_PIN_PD0, 9); //i2c7_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PD1, 9); //i2c7_sda_m0
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+
+  /* Enable USB-C VBUS */
+  GpioPinWrite (1, GPIO_PIN_PB1, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PB1, GPIO_PIN_OUTPUT);
+
+  //
+  // Power cycle vcc5v0_host as some USB 3.0 devices won't enumerate
+  // during boot otherwise.
+  //
+  GpioPinSetDirection (1, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+  GpioPinWrite (1, GPIO_PIN_PB6, FALSE);
+  gBS->Stall (1200000);
+  GpioPinWrite (1, GPIO_PIN_PB6, TRUE);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  if(Segment == PCIE_SEGMENT_PCIE20L2) { // M.2 M Key
+    /* reset */
+    GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
+    /* vcc3v3_pcie20 */
+    GpioPinSetDirection (1, GPIO_PIN_PD7, GPIO_PIN_OUTPUT);
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+    /* vcc3v3_pcie20 */
+    GpioPinWrite (1, GPIO_PIN_PD7, Enable);
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  if(Segment == PCIE_SEGMENT_PCIE20L2) {
+    GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
+  }
+}
+
+PWM_DATA pwm_data = {
+  .ControllerID = PWM_CONTROLLER2,
+  .ChannelID = PWM_CHANNEL3,
+  .PeriodNs = 50000,
+  .DutyNs = 50000,
+  .Polarity = TRUE,
+}; // PWM2_CH3
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+  GpioPinSetFunction (3, GPIO_PIN_PD5, 0xB); // PWM11_IR_M3
+  RkPwmSetConfig (&pwm_data);
+  RkPwmEnable (&pwm_data);
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+  pwm_data.DutyNs = pwm_data.PeriodNs * Percentage / 100;
+  RkPwmSetConfig (&pwm_data);
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  /* Red off, Green for status, Blue for power */
+  GpioPinWrite (3, GPIO_PIN_PB2, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PB2, GPIO_PIN_OUTPUT);
+  GpioPinWrite (3, GPIO_PIN_PC0, FALSE);
+  GpioPinSetDirection (3, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+  GpioPinWrite (1, GPIO_PIN_PD5, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PD5, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  GpioPinWrite (3, GPIO_PIN_PC0, Enable);
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  GpioPinSetFunction(1, GPIO_PIN_PA6, 0); //jdet
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@ -0,0 +1,35 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+  PWMLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.Modules.fdf.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.Modules.fdf.inc
@ -0,0 +1,18 @@
+## @file
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+    SECTION RAW = Platform/Rockchip/DeviceTree/roc-rk3588s-pc.dtb
+  }
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc
@ -0,0 +1,45 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ROC-RK3588S-PC
+  PLATFORM_VENDOR                = Firefly
+  PLATFORM_GUID                  = d6741299-c347-4115-9f1a-1207fdf16ab0
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+  #
+  # Platform based on ROC-RK3588S-PC board
+  #
+!include Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"ROC-RK3588S-PC"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"Firefly"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"ROC"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://en.t-firefly.com/product/industry/rocrk3588spc"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"roc-rk3588s-pc"
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.dsc.inc
@ -0,0 +1,107 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = Platform/Firefly/ROC-RK3588S-PC/ROC-RK3588S-PC.Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  #
+  # RK3588S-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588SPlatform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|Platform/Firefly/ROC-RK3588S-PC/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdBoardName|"ROC-RK3588S-PC"
+  gRockchipTokenSpaceGuid.PcdBoardVendorName|"Firefly"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51, 0x11 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x2, 0x3 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE, FALSE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x2
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_USB3)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
+
+  #
+  # GMAC
+  #
+  gRK3588TokenSpaceGuid.PcdGmac1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdGmac1TxDelay|0x43
+
+  #
+  # On-Board fan output
+  #
+  gRK3588TokenSpaceGuid.PcdHasOnBoardFanOutput|TRUE
+
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  Platform/Firefly/ROC-RK3588S-PC/AcpiTables/AcpiTables.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.bmp
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.bmp
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.c
@ -0,0 +1,144 @@
+/** @file
+  Logo DXE Driver, install Edkii Platform Logo protocol.
+
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/HiiDatabase.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/HiiImageEx.h>
+#include <Protocol/PlatformLogo.h>
+#include <Protocol/HiiPackageList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+
+typedef struct {
+  EFI_IMAGE_ID                          ImageId;
+  EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE Attribute;
+  INTN                                  OffsetX;
+  INTN                                  OffsetY;
+} LOGO_ENTRY;
+
+STATIC EFI_HII_IMAGE_EX_PROTOCOL *mHiiImageEx;
+STATIC EFI_HII_HANDLE            mHiiHandle;
+STATIC LOGO_ENTRY                mLogos[] = {
+  {
+    IMAGE_TOKEN (IMG_LOGO),
+    EdkiiPlatformLogoDisplayAttributeCenter,
+    0,
+    0
+  }
+};
+
+/**
+  Load a platform logo image and return its data and attributes.
+
+  @param This              The pointer to this protocol instance.
+  @param Instance          The visible image instance is found.
+  @param Image             Points to the image.
+  @param Attribute         The display attributes of the image returned.
+  @param OffsetX           The X offset of the image regarding the Attribute.
+  @param OffsetY           The Y offset of the image regarding the Attribute.
+
+  @retval EFI_SUCCESS      The image was fetched successfully.
+  @retval EFI_NOT_FOUND    The specified image could not be found.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+GetImage (
+  IN     EDKII_PLATFORM_LOGO_PROTOCOL          *This,
+  IN OUT UINT32                                *Instance,
+     OUT EFI_IMAGE_INPUT                       *Image,
+     OUT EDKII_PLATFORM_LOGO_DISPLAY_ATTRIBUTE *Attribute,
+     OUT INTN                                  *OffsetX,
+     OUT INTN                                  *OffsetY
+  )
+{
+  UINT32 Current;
+
+  if (Instance == NULL || Image == NULL ||
+      Attribute == NULL || OffsetX == NULL || OffsetY == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  Current = *Instance;
+  if (Current >= ARRAY_SIZE (mLogos)) {
+    return EFI_NOT_FOUND;
+  }
+
+  (*Instance)++;
+  *Attribute = mLogos[Current].Attribute;
+  *OffsetX   = mLogos[Current].OffsetX;
+  *OffsetY   = mLogos[Current].OffsetY;
+
+  return mHiiImageEx->GetImageEx (mHiiImageEx, mHiiHandle,
+                        mLogos[Current].ImageId, Image);
+}
+
+STATIC EDKII_PLATFORM_LOGO_PROTOCOL mPlatformLogo = {
+  GetImage
+};
+
+/**
+  Entrypoint of this module.
+
+  This function is the entrypoint of this module. It installs the Edkii
+  Platform Logo protocol.
+
+  @param  ImageHandle       The firmware allocated handle for the EFI image.
+  @param  SystemTable       A pointer to the EFI System Table.
+
+  @retval EFI_SUCCESS       The entry point is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeLogo (
+  IN EFI_HANDLE               ImageHandle,
+  IN EFI_SYSTEM_TABLE         *SystemTable
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_HII_PACKAGE_LIST_HEADER *PackageList;
+  EFI_HII_DATABASE_PROTOCOL   *HiiDatabase;
+  EFI_HANDLE                  Handle;
+
+  Status = gBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL,
+                  (VOID **) &HiiDatabase);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = gBS->LocateProtocol (&gEfiHiiImageExProtocolGuid, NULL,
+                  (VOID **) &mHiiImageEx);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Retrieve HII package list from ImageHandle
+  //
+  Status = gBS->OpenProtocol (ImageHandle, &gEfiHiiPackageListProtocolGuid,
+                  (VOID **) &PackageList, ImageHandle, NULL,
+                  EFI_OPEN_PROTOCOL_GET_PROTOCOL);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR,
+      "HII Image Package with logo not found in PE/COFF resource section\n"));
+    return Status;
+  }
+
+  //
+  // Publish HII package list to HII Database.
+  //
+  Status = HiiDatabase->NewPackageList (HiiDatabase, PackageList, NULL,
+                          &mHiiHandle);
+  if (!EFI_ERROR (Status)) {
+    Handle = NULL;
+    Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+                    &gEdkiiPlatformLogoProtocolGuid, &mPlatformLogo, NULL);
+  }
+  return Status;
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.idf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/Logo.idf
@ -0,0 +1,10 @@
+// @file
+// Platform Logo image definition file.
+//
+// Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+// Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+
+#image IMG_LOGO Logo.bmp
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/LogoDxe.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/Drivers/LogoDxe/LogoDxe.inf
@ -0,0 +1,48 @@
+## @file
+#  The default logo bitmap picture shown on setup screen.
+#
+#  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>
+#  Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = LogoDxe
+  FILE_GUID                      = 4b55f0bc-8b1a-11ec-bd4b-f42a7dcb925d
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = InitializeLogo
+#
+#  This flag specifies whether HII resource section is generated into PE image.
+#
+  UEFI_HII_RESOURCE_SECTION      = TRUE
+
+[Sources]
+  Logo.bmp
+  Logo.c
+  Logo.idf
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  DebugLib
+
+[Protocols]
+  gEfiHiiDatabaseProtocolGuid        ## CONSUMES
+  gEfiHiiImageExProtocolGuid         ## CONSUMES
+  gEfiHiiPackageListProtocolGuid     ## PRODUCES CONSUMES
+  gEdkiiPlatformLogoProtocolGuid     ## PRODUCES
+
+[Depex]
+  gEfiHiiDatabaseProtocolGuid AND
+  gEfiHiiImageExProtocolGuid
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/AcpiTables.inf
@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/AcpiTables/Dsdt.asl
@ -0,0 +1,44 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+#define BOARD_I2S0_TPLG "i2s-jack"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588  ", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    // include ("Gmac.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    // include ("Spi.asl")
+
+    include ("I2s.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+    // include ("Usb3Host2.asl")
+  }
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.c
@ -0,0 +1,354 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdhci0 iomux (eMMC socket) */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON78,
+             (((0x3 << 12) | (0x3f << 6)) << 16) | (0x0 << 12) | (0x3f << 6));
+#define FSPI_M1
+#if defined(FSPI_M0)
+   /*FSPI M0*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = ((0xF << 0) << 16) | (2 << 0); //FSPI_CLK_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x2222); //FSPI_D0_M0,FSPI_D1_M0,FSPI_D2_M0,FSPI_D3_M0
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = ((0xF << 8) << 16) | (0x2 << 8); //FSPI_CS0N_M0
+#elif defined(FSPI_M1)
+  /*FSPI M1*/
+  BUS_IOC->GPIO2A_IOMUX_SEL_H = (0xFF00UL << 16) | (0x3300); //FSPI_D0_M1,FSPI_D1_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_L = (0xF0FFUL << 16) | (0x3033); //FSPI_D2_M1,FSPI_D3_M1,FSPI_CLK_M1
+  BUS_IOC->GPIO2B_IOMUX_SEL_H = (0xF << 16) | (0x3); //FSPI_CS0N_M1
+#else
+  /*FSPI M2*/
+  BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x5555); //[FSPI_D0_M2-FSPI_D3_M2]
+  BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0UL << 16) | (0x50); //FSPI_CLK_M2
+  BUS_IOC->GPIO3C_IOMUX_SEL_H = (0xF << 16) | (0x2); //FSPI_CS0_M2
+#endif
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  /* No GMAC here */
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
+    break;
+  case 1:
+    break;
+  case 2:
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
+    break;
+  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  /* Set GPIO4 PB0 (USB_HOST_PWREN) output high to power USB ports */
+  GpioPinWrite (4, GPIO_PIN_PB0, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PB0, GPIO_PIN_OUTPUT);
+
+  /* Set GPIO4 PC6 output high to power the 4G/LTE module */
+  GpioPinWrite (4, GPIO_PIN_PC6, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PC6, GPIO_PIN_OUTPUT);
+
+  /* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */
+  GpioPinWrite (1, GPIO_PIN_PD2, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT);
+
+  // DEBUG((DEBUG_INFO, "Trying to enable on-board LED1\n"));
+  // GpioPinWrite (2, GPIO_PIN_PC0, TRUE);
+  // GpioPinSetDirection (2, GPIO_PIN_PC0, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  switch(Segment) {
+    case PCIE_SEGMENT_PCIE30X4:
+      GpioPinSetDirection (4, GPIO_PIN_PB6, GPIO_PIN_OUTPUT);
+      GpioPinSetDirection (2, GPIO_PIN_PC5, GPIO_PIN_OUTPUT);
+      break;
+    case PCIE_SEGMENT_PCIE20L0: // rtl8152b
+      GpioPinSetDirection (4, GPIO_PIN_PB3, GPIO_PIN_OUTPUT);
+      break;
+    case PCIE_SEGMENT_PCIE20L1: // m.2 a+e key
+      GpioPinSetDirection (4, GPIO_PIN_PC2, GPIO_PIN_OUTPUT);
+      GpioPinSetDirection (4, GPIO_PIN_PA2, GPIO_PIN_OUTPUT);
+      break;
+    case PCIE_SEGMENT_PCIE20L2: //rtl8152b
+      GpioPinSetDirection (4, GPIO_PIN_PA4, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  /* output high to enable power */
+
+  switch(Segment) {
+    case PCIE_SEGMENT_PCIE30X4:
+      GpioPinWrite (2, GPIO_PIN_PC5, Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L0:
+      break;
+    case PCIE_SEGMENT_PCIE20L1:
+      GpioPinWrite (4, GPIO_PIN_PC2, Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L2:
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  switch(Segment) {
+    case PCIE_SEGMENT_PCIE30X4:
+      GpioPinWrite (4, GPIO_PIN_PB6, !Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L0:
+      GpioPinWrite (4, GPIO_PIN_PB3, !Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L1:
+      GpioPinWrite (4, GPIO_PIN_PA2, !Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L2:
+      GpioPinWrite (4, GPIO_PIN_PA4, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  /* Status indicator */
+  GpioPinWrite (2, GPIO_PIN_PB7, FALSE);
+  GpioPinSetDirection (2, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  GpioPinWrite (2, GPIO_PIN_PB7, Enable);
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+  GpioPinSetFunction(1, GPIO_PIN_PC4, 0); //jdet
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@ -0,0 +1,34 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.Modules.fdf.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.Modules.fdf.inc
@ -0,0 +1,18 @@
+## @file
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+    SECTION RAW = Platform/Rockchip/DeviceTree/rk3588-nanopc-t6.dtb
+  }
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPC-T6/NanoPC-T6.dsc
@ -0,0 +1,116 @@
+## @file
+#
+#  Copyright (c) 2014-2018, Linaro Limited. All rights reserved.
+#  Copyright (c) 2023, Molly Sophia <mollysophia379@gmail.com>
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = NanoPC-T6
+  PLATFORM_VENDOR                = FriendlyElec
+  PLATFORM_GUID                  = e5022309-24e1-46e0-9d40-dcbc7293e609
+  PLATFORM_VERSION               = 0.2
+  DSC_SPECIFICATION              = 0x00010019
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  VENDOR_DIRECTORY               = Platform/$(PLATFORM_VENDOR)
+  PLATFORM_DIRECTORY             = $(VENDOR_DIRECTORY)/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = Silicon/Rockchip/RK3588/RK3588.fdf
+  RK_PLATFORM_FVMAIN_MODULES     = $(PLATFORM_DIRECTORY)/$(PLATFORM_NAME).Modules.fdf.inc
+
+  #
+  # HYM8563 RTC support
+  # I2C location configured by PCDs below.
+  #
+  DEFINE RK_RTC8563_ENABLE = TRUE
+
+  #
+  # RK3588-based platform
+  #
+!include Silicon/Rockchip/RK3588/RK3588Platform.dsc.inc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+[LibraryClasses.common]
+  RockchipPlatformLib|$(PLATFORM_DIRECTORY)/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
+#
+################################################################################
+
+[PcdsFixedAtBuild.common]
+  # SMBIOS platform config
+  gRockchipTokenSpaceGuid.PcdPlatformName|"NanoPC T6"
+  gRockchipTokenSpaceGuid.PcdPlatformVendorName|"FriendlyElec"
+  gRockchipTokenSpaceGuid.PcdFamilyName|"NanoPi 6"
+  gRockchipTokenSpaceGuid.PcdProductUrl|"https://wiki.friendlyelec.com/wiki/index.php/NanoPC-T6"
+  gRockchipTokenSpaceGuid.PcdDeviceTreeName|"rk3588-nanopc-t6"
+
+  # I2C
+  gRockchipTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x42, 0x43, 0x51 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x6 }
+  gRockchipTokenSpaceGuid.PcdI2cSlaveBusesRuntimeSupport|{ FALSE, FALSE, TRUE }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorAddresses|{ 0x42, 0x43 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorBuses|{ 0x0, 0x0 }
+  gRockchipTokenSpaceGuid.PcdRk860xRegulatorTags|{ $(SCMI_CLK_CPUB01), $(SCMI_CLK_CPUB23) }
+  gPcf8563RealTimeClockLibTokenSpaceGuid.PcdI2cSlaveAddress|0x51
+  gRockchipTokenSpaceGuid.PcdRtc8563Bus|0x6
+
+  #
+  # CPU Performance default values
+  #
+  gRK3588TokenSpaceGuid.PcdCPULClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB01ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+  gRK3588TokenSpaceGuid.PcdCPUB23ClusterClockPresetDefault|$(CPU_PERF_CLUSTER_CLOCK_PRESET_BOOTDEFAULT)
+
+  #
+  # PCIe/SATA/USB Combo PIPE PHY support flags and default values
+  # NanoPC T6 has two 2.5 GBE wired to the first two PCIE2 ports, while the third one is wired to m.2 a+e key
+  #
+  gRK3588TokenSpaceGuid.PcdComboPhy0Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy1Switchable|FALSE
+  gRK3588TokenSpaceGuid.PcdComboPhy2Switchable|TRUE
+  gRK3588TokenSpaceGuid.PcdComboPhy0ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy1ModeDefault|$(COMBO_PHY_MODE_PCIE)
+  gRK3588TokenSpaceGuid.PcdComboPhy2ModeDefault|$(COMBO_PHY_MODE_PCIE)
+
+  #
+  # USB/DP Combo PHY support flags and default values
+  #
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy0Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdUsbDpPhy1Supported|TRUE
+  gRK3588TokenSpaceGuid.PcdDp0LaneMux|{ 0x2, 0x3 }
+  gRK3588TokenSpaceGuid.PcdDp1LaneMux|{ 0x0 }
+
+  #
+  # I2S
+  #
+  gRK3588TokenSpaceGuid.PcdI2S0Supported|TRUE
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform.
+#
+################################################################################
+[Components.common]
+  # ACPI Support
+  $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # Splash screen logo
+  $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/AcpiTables.inf
@ -0,0 +1,58 @@
+#/** @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+#  Copyright (c) Microsoft Corporation. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+  RK_COMMON_ACPI_DIR             = Silicon/Rockchip/RK3588/AcpiTables
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = AARCH64
+#
+
+[Sources]
+  Dsdt.asl
+  $(RK_COMMON_ACPI_DIR)/Madt.aslc
+  $(RK_COMMON_ACPI_DIR)/Fadt.aslc
+  $(RK_COMMON_ACPI_DIR)/Gtdt.aslc
+  $(RK_COMMON_ACPI_DIR)/Spcr.aslc
+  $(RK_COMMON_ACPI_DIR)/Mcfg.aslc
+  $(RK_COMMON_ACPI_DIR)/Dbg2.aslc
+  $(RK_COMMON_ACPI_DIR)/Pptt.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Rockchip/RockchipPkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+  gRK3588TokenSpaceGuid.PcdI2S0Supported
+  gRK3588TokenSpaceGuid.PcdI2S1Supported
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxBase
+  gRockchipTokenSpaceGuid.PcdRkMtlMailBoxSize
+  gRockchipTokenSpaceGuid.PcdRkSdmmcCardDetectBroken
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/AcpiTables/Dsdt.asl
@ -0,0 +1,39 @@
+/** @file
+ *
+ *  Differentiated System Definition Table (DSDT)
+ *
+ *  Copyright (c) 2020, Pete Batard <pete@akeo.ie>
+ *  Copyright (c) 2018-2020, Andrey Warkentin <andrey.warkentin@gmail.com>
+ *  Copyright (c) Microsoft Corporation. All rights reserved.
+ *  Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ *  SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include "AcpiTables.h"
+
+DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RKCP  ", "RK3588S", 2)
+{
+  Scope (\_SB_)
+  {
+    include ("DsdtCommon.asl")
+
+    include ("Cpu.asl")
+
+    include ("Pcie.asl")
+    include ("Sata.asl")
+    include ("Emmc.asl")
+    include ("Sdhc.asl")
+    include ("Dma.asl")
+    include ("Gmac1.asl")
+    include ("Gpio.asl")
+    include ("I2c.asl")
+    include ("Uart.asl")
+    //include ("Spi.asl")
+
+    include ("Usb2Host.asl")
+    include ("Usb3Host0.asl")
+    include ("Usb3Host1.asl")
+  }
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.c
@ -0,0 +1,342 @@
+/** @file
+*
+*  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+*
+*  SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+#include <Base.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/RK806.h>
+#include <Library/Rk3588Pcie.h>
+#include <Soc.h>
+
+static struct regulator_init_data rk806_init_data[] = {
+  /* Master PMIC */
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK4, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK5, 850000),
+  //RK8XX_VOLTAGE_INIT(MASTER_BUCK6, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK7, 2000000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK8, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_BUCK10, 1800000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO1, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO2, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO3, 750000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO4, 850000),
+  RK8XX_VOLTAGE_INIT(MASTER_NLDO5, 750000),
+
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO1, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO2, 1800000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO3, 1200000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO4, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO5, 3300000),
+  RK8XX_VOLTAGE_INIT(MASTER_PLDO6, 1800000),
+  /* No dual PMICs on this platform */
+};
+
+VOID
+EFIAPI
+SdmmcIoMux (
+  VOID
+  )
+{
+  /* sdmmc0 iomux (microSD socket) */
+  BUS_IOC->GPIO4D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //SDMMC_D0,SDMMC_D1,SDMMC_D2,SDMMC_D3
+  BUS_IOC->GPIO4D_IOMUX_SEL_H = (0x00FFUL << 16) | (0x0011); //SDMMC_CLK,SDMMC_CMD
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x000FUL << 16) | (0x0001); //SDMMC_DET
+}
+
+VOID
+EFIAPI
+SdhciEmmcIoMux (
+  VOID
+  )
+{
+  /* sdhci0 iomux (eMMC socket) */
+  BUS_IOC->GPIO2A_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_CMD,EMMC_CLKOUT,EMMC_DATASTROBE,EMMC_RSTN
+  BUS_IOC->GPIO2D_IOMUX_SEL_L = (0xFFFFUL << 16) | (0x1111); //EMMC_D0,EMMC_D1,EMMC_D2,EMMC_D3
+  BUS_IOC->GPIO2D_IOMUX_SEL_H = (0xFFFFUL << 16) | (0x1111); //EMMC_D4,EMMC_D5,EMMC_D6,EMMC_D7
+}
+
+#define NS_CRU_BASE         0xFD7C0000
+#define CRU_CLKSEL_CON59    0x03EC
+#define CRU_CLKSEL_CON78    0x0438
+
+VOID
+EFIAPI
+Rk806SpiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  //BUS_IOC->GPIO1A_IOMUX_SEL_H = (0xFFFFUL << 16) | 0x8888;
+  //BUS_IOC->GPIO1B_IOMUX_SEL_L = (0x000FUL << 16) | 0x0008;
+  PMU1_IOC->GPIO0A_IOMUX_SEL_H = (0x0FF0UL << 16) | 0x0110;
+  PMU1_IOC->GPIO0B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+  MmioWrite32(NS_CRU_BASE + CRU_CLKSEL_CON59, (0x00C0UL << 16) | 0x0080);
+}
+
+VOID
+EFIAPI
+Rk806Configure (
+  VOID
+  )
+{
+  UINTN RegCfgIndex;
+
+  RK806Init();
+
+  for (RegCfgIndex = 0; RegCfgIndex < ARRAY_SIZE(rk806_init_data); RegCfgIndex++)
+    RK806RegulatorInit(rk806_init_data[RegCfgIndex]);
+}
+
+VOID
+EFIAPI
+SetCPULittleVoltage (
+  IN UINT32 Microvolts
+  )
+{
+  struct regulator_init_data Rk806CpuLittleSupply =
+        RK8XX_VOLTAGE_INIT(MASTER_BUCK2, Microvolts);
+
+  RK806RegulatorInit(Rk806CpuLittleSupply);
+}
+
+VOID
+EFIAPI
+NorFspiIomux (
+  VOID
+  )
+{
+  /* io mux */
+  /* Do not override, set by earlier boot stages. */
+}
+
+VOID
+EFIAPI
+GmacIomux (
+  IN UINT32 Id
+  )
+{
+  switch (Id) {
+    case 1:
+      /* gmac1 iomux */
+      BUS_IOC->GPIO3B_IOMUX_SEL_H = (0x0FFFUL << 16) | 0x0111;
+      BUS_IOC->GPIO3A_IOMUX_SEL_L = (0xFFFFUL << 16) | 0x1111;
+      BUS_IOC->GPIO3B_IOMUX_SEL_L = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3A_IOMUX_SEL_H = (0xF0FFUL << 16) | 0x1011;
+      BUS_IOC->GPIO3C_IOMUX_SEL_L = (0xFF00UL << 16) | 0x1100;
+
+      /* phy1 reset */
+      GpioPinSetDirection (3, GPIO_PIN_PB7, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+GmacIoPhyReset (
+  UINT32   Id,
+  BOOLEAN  Enable
+  )
+{
+  switch (Id) {
+    case 1:
+      /* phy1 reset */
+      GpioPinWrite (3, GPIO_PIN_PB7, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+NorFspiEnableClock (
+  UINT32 *CruBase
+  )
+{
+  UINTN BaseAddr = (UINTN) CruBase;
+
+  MmioWrite32(BaseAddr + 0x087C, 0x0E000000);
+}
+
+VOID
+EFIAPI
+I2cIomux (
+   UINT32 id
+  )
+{
+  switch (id) {
+  case 0:
+    GpioPinSetFunction(0, GPIO_PIN_PD1, 3); //i2c0_scl_m2
+    GpioPinSetFunction(0, GPIO_PIN_PD2, 3); //i2c0_sda_m2
+    break;
+  case 1:
+    break;
+  case 2:
+    GpioPinSetFunction(0, GPIO_PIN_PB7, 9); //i2c2_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC0, 9); //i2c2_sda_m0
+    break;
+  case 3:
+    GpioPinSetFunction(1, GPIO_PIN_PC1, 9); //i2c3_scl_m0
+    GpioPinSetFunction(1, GPIO_PIN_PC0, 9); //i2c3_sda_m0
+    break;
+  case 4:
+    break;
+  case 5:
+    break;
+  case 6:
+    GpioPinSetFunction(0, GPIO_PIN_PD0, 9); //i2c6_scl_m0
+    GpioPinSetFunction(0, GPIO_PIN_PC7, 9); //i2c6_sda_m0
+    break;
+  case 7:
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+EFIAPI
+UsbPortPowerEnable (
+  VOID
+  )
+{
+  DEBUG((DEBUG_INFO, "UsbPortPowerEnable called\n"));
+  /* Set GPIO4 PB5 (USB_HOST_PWREN) output high to power USB ports */
+  GpioPinWrite (4, GPIO_PIN_PB5, TRUE);
+  GpioPinSetDirection (4, GPIO_PIN_PB5, GPIO_PIN_OUTPUT);
+
+  /* Set GPIO1 PD2 (TYPEC5V_PWREN) output high to power the type-c port */
+  GpioPinWrite (1, GPIO_PIN_PD2, TRUE);
+  GpioPinSetDirection (1, GPIO_PIN_PD2, GPIO_PIN_OUTPUT);
+
+  // DEBUG((DEBUG_INFO, "Trying to enable on-board LED WAN\n"));
+  // GpioPinWrite (1, GPIO_PIN_PC2, TRUE);
+  // GpioPinSetDirection (1, GPIO_PIN_PC2, GPIO_PIN_OUTPUT);
+
+  // DEBUG((DEBUG_INFO, "Trying to enable on-board LED LAN\n"));
+  // GpioPinWrite (1, GPIO_PIN_PC3, TRUE);
+  // GpioPinSetDirection (1, GPIO_PIN_PC3, GPIO_PIN_OUTPUT);
+
+  // DEBUG((DEBUG_INFO, "Trying to enable on-board LED1\n"));
+  // GpioPinWrite (1, GPIO_PIN_PC4, TRUE);
+  // GpioPinSetDirection (1, GPIO_PIN_PC4, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+Usb2PhyResume (
+  VOID
+  )
+{
+  MmioWrite32(0xfd5d0008, 0x20000000);
+  MmioWrite32(0xfd5d4008, 0x20000000);
+  MmioWrite32(0xfd5d8008, 0x20000000);
+  MmioWrite32(0xfd5dc008, 0x20000000);
+  MmioWrite32(0xfd7f0a10, 0x07000700);
+  MmioWrite32(0xfd7f0a10, 0x07000000);
+}
+
+VOID
+EFIAPI
+PcieIoInit (
+  UINT32 Segment
+  )
+{
+  /* Set reset and power IO to gpio output mode */
+  switch(Segment) {
+    case PCIE_SEGMENT_PCIE20L1: // RTL8152BG
+      // GPIO1_A7_u - PCIE20x1_1_PERSTn_M2
+      GpioPinSetDirection (1, GPIO_PIN_PA7, GPIO_PIN_OUTPUT);
+      break;
+    case PCIE_SEGMENT_PCIE20L2: // M.2 SSD
+      // GPIO3_D1_d - PCIE20X1_2_PERSTN_M0
+      GpioPinSetDirection (3, GPIO_PIN_PD1, GPIO_PIN_OUTPUT);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+PciePowerEn (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  /* nothing to power on */
+}
+
+VOID
+EFIAPI
+PciePeReset (
+  UINT32 Segment,
+  BOOLEAN Enable
+  )
+{
+  switch(Segment) {
+    case PCIE_SEGMENT_PCIE20L1:
+      GpioPinWrite (1, GPIO_PIN_PA7, !Enable);
+      break;
+    case PCIE_SEGMENT_PCIE20L2:
+      GpioPinWrite (3, GPIO_PIN_PD1, !Enable);
+      break;
+    default:
+      break;
+  }
+}
+
+VOID
+EFIAPI
+PwmFanIoSetup (
+  VOID
+  )
+{
+}
+
+VOID
+EFIAPI
+PwmFanSetSpeed (
+  IN UINT32 Percentage
+  )
+{
+}
+
+VOID
+EFIAPI
+PlatformInitLeds (
+  VOID
+  )
+{
+  /* Status indicator */
+  GpioPinWrite (1, GPIO_PIN_PC1, FALSE);
+  GpioPinSetDirection (1, GPIO_PIN_PC1, GPIO_PIN_OUTPUT);
+}
+
+VOID
+EFIAPI
+PlatformSetStatusLed (
+  IN BOOLEAN Enable
+  )
+{
+  GpioPinWrite (1, GPIO_PIN_PC1, Enable);
+}
+
+VOID
+EFIAPI
+PlatformEarlyInit (
+  VOID
+  )
+{
+  // Configure various things specific to this platform
+}
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.inf
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/Library/RockchipPlatformLib/RockchipPlatformLib.inf
@ -0,0 +1,34 @@
+#
+#  Copyright (c) 2021, Rockchip Limited. All rights reserved.
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[Defines]
+  INF_VERSION                    = 0x00010019
+  BASE_NAME                      = RockchipPlatformLib
+  FILE_GUID                      = 5178fa86-2fec-11ec-95b4-f42a7dcb925d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = RockchipPlatformLib
+  RKPLATLIB_COMMON_DIR           = Silicon/Rockchip/RK3588/Library/RockchipPlatformLibCommon
+
+[Packages]
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  Silicon/Rockchip/RK3588/RK3588.dec
+  Silicon/Rockchip/RockchipPkg.dec
+
+[LibraryClasses]
+  ArmLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  SerialPortLib
+  CruLib
+  GpioLib
+
+[Sources.common]
+  RockchipPlatformLib.c
+  $(RKPLATLIB_COMMON_DIR)/RK3588CruLib.c
--- a/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.Modules.fdf.inc
+++ b/local/UEFI/edk2-rk3588-master/edk2-rockchip/Platform/FriendlyElec/NanoPi-R6C/NanoPi-R6C.Modules.fdf.inc
@ -0,0 +1,19 @@
+## @file
+#
+#  Copyright (c) 2023, Mario Bălănică <mariobalanica02@gmail.com>
+#  Copyright (c) 2023, Sergey Tyuryukanov <s199p.wa1k9r@gmail.com>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+  # ACPI Support
+  INF RuleOverride = ACPITABLE $(PLATFORM_DIRECTORY)/AcpiTables/AcpiTables.inf
+
+  # Device Tree Support
+  FILE FREEFORM = gDtPlatformDefaultDtbFileGuid {
+    SECTION RAW = Platform/Rockchip/DeviceTree/rk3588s-nanopi-r6c.dtb
+  }
+
+  # Splash screen logo
+  INF $(VENDOR_DIRECTORY)/Drivers/LogoDxe/LogoDxe.inf
--- a/Show more
+++ b/Show more