96 lines
3.4 KiB
Markdown
96 lines
3.4 KiB
Markdown
# Fork
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Project to parse and embed instruction info into ```rtdisasm``` component of [blackjack](https://github.com/mykola2312/blackjack)
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# Parsable-Instructions
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List of all instructions found in *Intel* and *AMD* documentations, listed into ***XML files*** for easy parsing.
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Each instruction in the XML file contains:
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* Instruction mnemonic.
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* Instruction arguments.
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* Instruction opcode.
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* Instruction opcode encoding.
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* Instruction 64 bit mode support.
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* Instruction 32 bit mode support.
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* Instruction CPUID flags.
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* Instruction operands encoding.
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* Instruction description.
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***NOTE***: Some fields listed above may not exists in other instructions.
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For each **XML file** there is a **DTD file** associated which is used to ensure that the XML file follows the same rules for all XML files.
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## XML files
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- **raw.x86.Intel.AZ.xml**: Contains all instructions found in “Intel® 64 and IA-32 Architectures Software Developer Manuals volume 2”.
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- **\*raw.x86.Intel.AVX512_r22.xml**: Contains all instructions found in “Intel® Architecture Instruction Set Extensions Programming Reference 319433-022”.
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- **raw.x86.Intel.AVX512_r24.xml**: Contains all instructions found in “Intel® Architecture Instruction Set Extensions Programming Reference 319433-024”.
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- **raw.x86.AMD.3DNow.xml**: Contains all instructions found in "AMD 3DNow! Technology Manual".
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- **raw.x86.AMD.SSE5.xml**: Contains all instructions found in "AMD 128-Bit SSE5 Instruction Set".
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- **raw.x86.AMD.XOP.xml**: Contains all instructions found in "AMD64 Architecture Programmers Manual Volume 6: 128-Bit and 256-Bit XOP and FMA4 Instructions".
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\* means deprecated.
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## KEY TO ABBREVIATIONS
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- **x32m** = 32-bit mode support.
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- **x64m** = 64-bit mode support.
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- **mnem** = Instruction Mnemonic.
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- **args** = Instruction Arguments.
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- **opc** = Opcodes.
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- **openc** = Operand Encoding name.
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- **dscrp** = Description.
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- **oprndenc** = Instruction Operand Encoding.
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- **oprnd1** = Operand 1.
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- **oprnd2** = Operand 2.
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- **oprnd3** = Operand 3.
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- **oprnd4** = Operand 4.
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***NOTE:*** FOR THE REST OF KEYS YOU SHOULD REFER TO INTEL/AMD DOCUMENTATIONS!
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## Example
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Here's a simple example of ADDPD instruction.
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```
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<common>
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<brief>ADDPD--Add Packed Double-Precision Floating-Point Values.</brief>
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<ins x32m="V" x64m="V">
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<mnem>ADDPD</mnem>
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<args>xmm1,xmm2/m128</args>
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<opc openc="RM">66 0F 58 /r</opc>
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<cpuid>
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<flag>SSE2</flag>
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</cpuid>
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<dscrp>Add packed double-precision floating-point values from xmm2/m128 to xmm1.</dscrp>
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</ins>
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<ins x32m="V" x64m="V">
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<mnem>VADDPD</mnem>
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<args>xmm1,xmm2,xmm3/m128</args>
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<opc openc="RVM">VEX.NDS.128.66.0F.WIG 58 /r</opc>
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<cpuid>
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<flag>AVX</flag>
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</cpuid>
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<dscrp>Add packed double-precision floating-point values from xmm3/mem to xmm2 and stores result in xmm1.</dscrp>
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</ins>
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<ins x32m="V" x64m="V">
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<mnem>VADDPD</mnem>
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<args>ymm1,ymm2,ymm3/m256</args>
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<opc openc="RVM">VEX.NDS.256.66.0F.WIG 58 /r</opc>
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<cpuid>
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<flag>AVX</flag>
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</cpuid>
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<dscrp>Add packed double-precision floating-point values from ymm3/mem to ymm2 and stores result in ymm1.</dscrp>
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</ins>
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<oprndenc openc="RM">
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<oprnd1>ModRM:reg(r,w)</oprnd1>
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<oprnd2>ModRM:r/m(r)</oprnd2>
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<oprnd3>NA</oprnd3>
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<oprnd4>NA</oprnd4>
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</oprndenc>
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<oprndenc openc="RVM">
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<oprnd1>ModRM:reg(w)</oprnd1>
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<oprnd2>VEX.vvvv(r)</oprnd2>
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<oprnd3>ModRM:r/m(r)</oprnd3>
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<oprnd4>NA</oprnd4>
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</oprndenc>
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</common>
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```
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