mykola2312
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157a6cc9a2
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add todo
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2024-08-14 03:50:54 +03:00 |
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mykola2312
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81671b4652
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implement C table generator
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2024-08-14 01:08:37 +03:00 |
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mykola2312
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1de12a1f82
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final steps to the lookup table generator
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2024-08-13 21:30:03 +03:00 |
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mykola2312
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5e8ddc2c32
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add traits to instructions for decoder table
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2024-08-13 21:02:59 +03:00 |
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mykola2312
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dbec45533b
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begin working on EVEX parsing
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2024-08-13 20:22:57 +03:00 |
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mykola2312
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ea4f1d7308
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fix typo in evex.l field
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2024-08-13 20:21:45 +03:00 |
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mykola2312
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ce12de6fc3
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implement VEX parser
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2024-08-13 18:10:37 +03:00 |
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mykola2312
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db68712b3e
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fix typo
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2024-08-13 16:28:52 +03:00 |
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mykola2312
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c6ee87c4c0
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add OOP boilerplate to ease VEX/EVEX parsing logic
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2024-08-13 16:01:05 +03:00 |
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mykola2312
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5e8df2bd51
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generate dump list of VEX and EVEX instructions
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2024-08-13 15:36:03 +03:00 |
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mykola2312
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5b739f6054
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add branching and instruction types for future VEX parser
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2024-08-01 04:38:09 +03:00 |
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mykola2312
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a681a53ff3
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now I can definitely tell if instruction has ModRM byte or no
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2024-08-01 02:37:08 +03:00 |
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mykola2312
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5998950f23
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begin implementing intel opcode syntax parser
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2024-08-01 02:24:43 +03:00 |
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mykola2312
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24c290e29e
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fix typo
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2024-08-01 00:33:32 +03:00 |
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mykola2312
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954e5cc96a
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update on plan
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2024-08-01 00:33:01 +03:00 |
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mykola2312
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e8ae5937f8
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update on vex
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2024-07-31 23:29:08 +03:00 |
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mykola2312
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0f8e380dac
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skip even more 16 bit crap
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2024-07-29 00:46:58 +03:00 |
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mykola2312
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ac909fc71f
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add some notes
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2024-07-27 21:23:18 +03:00 |
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mykola2312
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095d90776e
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add another 16 bit real mode filter
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2024-07-25 03:53:45 +03:00 |
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mykola2312
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9a7c47b03e
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update readme
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2024-07-25 03:42:04 +03:00 |
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mykola2312
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467331c693
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strip rel16 since we're not going to encounter real mode in running processes on Linux or FreeBSD
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2024-07-25 03:40:06 +03:00 |
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mykola2312
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f81b7f524e
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fix regex
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2024-07-25 03:01:19 +03:00 |
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mykola2312
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8b9742ca42
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implement opcode parsing
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2024-07-25 01:29:02 +03:00 |
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mykola2312
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0310704f2b
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begin working on script to generate C files for my future disassembler
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2024-07-25 00:35:46 +03:00 |
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Mahdi Safsafi
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81c506ffb5
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Update README.md
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2017-03-02 10:58:35 +01:00 |
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Mahdi Safsafi
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8c0d3f17e1
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Merge pull request #1 from mquigley/patch-1
Fix mismatch of operand encoding for PREFETCHW
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2016-10-05 09:06:56 +01:00 |
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mquigley
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61b8854649
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Fix mismatch of operand encoding for PREFETCHW
The Intel manual actually has this error too, but it does not match up.
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2016-10-04 19:38:10 -07:00 |
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Mahdi Safsafi
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244d17dadc
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Update README.md
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2016-03-30 03:31:09 +02:00 |
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Mahdi Safsafi
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8cb15e5226
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Update README.md
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2016-03-27 23:15:38 +02:00 |
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Mahdi Safsafi
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2297196c9b
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Update README.md
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2016-03-27 04:24:00 +02:00 |
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Mahdi Safsafi
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c56122daaf
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Update README.md
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2016-03-27 03:28:21 +02:00 |
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Mahdi Safsafi
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39f277e465
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Added latest instructions found in Intel doc #319433-024(FEBRUARY 2016).
Renamed AVX512.xml to AVX512_r22 (OCTOBER 2014).
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2016-03-27 03:20:11 +02:00 |
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Mahdi Safsafi
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9bd0f37091
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Fix bug in AVX512.xml.
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2016-03-26 22:35:58 +01:00 |
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Mahdi Safsafi
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540c9d5f8e
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Fix some minor bugs found in AZ.xml.
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2016-03-26 22:18:46 +01:00 |
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Mahdi Safsafi
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99db987520
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Update README.md
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2015-09-03 18:38:24 +02:00 |
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Mahdi Safsafi
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393aac9800
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Added AMD (3DNow!,SSE5 and XOP)Instructions.
XML Refactoring.
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2015-09-03 18:30:00 +02:00 |
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Mahdi Safsafi
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e56d77147c
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Include project link
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2015-09-01 15:49:29 +02:00 |
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Mahdi Safsafi
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6504d7b007
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First Commit.
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2015-09-01 15:28:38 +02:00 |
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Mahdi Safsafi
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a73eca5531
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Update README.md
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2015-09-01 15:27:16 +02:00 |
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Mahdi Safsafi
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4551c1013c
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Initial commit
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2015-09-01 15:08:45 +02:00 |
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